2 * drivers/char/watchdog/pnx4008_wdt.c
4 * Watchdog driver for PNX4008 board
6 * Authors: Dmitry Chigirev <source@mvista.com>,
7 * Vitaly Wool <vitalywool@gmail.com>
8 * Based on sa1100 driver,
9 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
11 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
22 #include <linux/miscdevice.h>
23 #include <linux/watchdog.h>
24 #include <linux/init.h>
25 #include <linux/bitops.h>
26 #include <linux/ioport.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/spinlock.h>
32 #include <asm/hardware.h>
33 #include <asm/uaccess.h>
36 #define MODULE_NAME "PNX4008-WDT: "
38 /* WatchDog Timer - Chapter 23 Page 207 */
40 #define DEFAULT_HEARTBEAT 19
41 #define MAX_HEARTBEAT 60
43 /* Watchdog timer register set definition */
44 #define WDTIM_INT(p) ((p) + 0x0)
45 #define WDTIM_CTRL(p) ((p) + 0x4)
46 #define WDTIM_COUNTER(p) ((p) + 0x8)
47 #define WDTIM_MCTRL(p) ((p) + 0xC)
48 #define WDTIM_MATCH0(p) ((p) + 0x10)
49 #define WDTIM_EMR(p) ((p) + 0x14)
50 #define WDTIM_PULSE(p) ((p) + 0x18)
51 #define WDTIM_RES(p) ((p) + 0x1C)
53 /* WDTIM_INT bit definitions */
56 /* WDTIM_CTRL bit definitions */
58 #define RESET_COUNT (1<<1)
59 #define DEBUG_EN (1<<2)
61 /* WDTIM_MCTRL bit definitions */
64 #define RESET_COUNT0 (1<<2)
65 #define STOP_COUNT0 (1<<2)
68 #define RESFRC1 (1<<5)
69 #define RESFRC2 (1<<6)
71 /* WDTIM_EMR bit definitions */
73 #define MATCH_OUTPUT_HIGH (2<<4) /*a MATCH_CTRL setting */
75 /* WDTIM_RES bit definitions */
76 #define WDOG_RESET 1 /* read only */
78 #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
80 static int nowayout
= WATCHDOG_NOWAYOUT
;
81 static int heartbeat
= DEFAULT_HEARTBEAT
;
83 static spinlock_t io_lock
;
84 static unsigned long wdt_status
;
86 #define WDT_OK_TO_CLOSE 1
87 #define WDT_REGION_INITED 2
88 #define WDT_DEVICE_INITED 3
90 static unsigned long boot_status
;
92 static struct resource
*wdt_mem
;
93 static void __iomem
*wdt_base
;
96 static void wdt_enable(void)
101 clk_set_rate(wdt_clk
, 1);
103 /* stop counter, initiate counter reset */
104 __raw_writel(RESET_COUNT
, WDTIM_CTRL(wdt_base
));
105 /*wait for reset to complete. 100% guarantee event */
106 while (__raw_readl(WDTIM_COUNTER(wdt_base
)))
108 /* internal and external reset, stop after that */
109 __raw_writel(M_RES2
| STOP_COUNT0
| RESET_COUNT0
,
110 WDTIM_MCTRL(wdt_base
));
111 /* configure match output */
112 __raw_writel(MATCH_OUTPUT_HIGH
, WDTIM_EMR(wdt_base
));
113 /* clear interrupt, just in case */
114 __raw_writel(MATCH_INT
, WDTIM_INT(wdt_base
));
115 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
116 __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base
));
117 __raw_writel(heartbeat
* WDOG_COUNTER_RATE
, WDTIM_MATCH0(wdt_base
));
118 /*enable counter, stop when debugger active */
119 __raw_writel(COUNT_ENAB
| DEBUG_EN
, WDTIM_CTRL(wdt_base
));
121 spin_unlock(&io_lock
);
124 static void wdt_disable(void)
128 __raw_writel(0, WDTIM_CTRL(wdt_base
)); /*stop counter */
130 clk_set_rate(wdt_clk
, 0);
132 spin_unlock(&io_lock
);
135 static int pnx4008_wdt_open(struct inode
*inode
, struct file
*file
)
137 if (test_and_set_bit(WDT_IN_USE
, &wdt_status
))
140 clear_bit(WDT_OK_TO_CLOSE
, &wdt_status
);
144 return nonseekable_open(inode
, file
);
148 pnx4008_wdt_write(struct file
*file
, const char *data
, size_t len
,
155 clear_bit(WDT_OK_TO_CLOSE
, &wdt_status
);
157 for (i
= 0; i
!= len
; i
++) {
160 if (get_user(c
, data
+ i
))
163 set_bit(WDT_OK_TO_CLOSE
, &wdt_status
);
172 static struct watchdog_info ident
= {
173 .options
= WDIOF_CARDRESET
| WDIOF_MAGICCLOSE
|
174 WDIOF_SETTIMEOUT
| WDIOF_KEEPALIVEPING
,
175 .identity
= "PNX4008 Watchdog",
179 pnx4008_wdt_ioctl(struct inode
*inode
, struct file
*file
, unsigned int cmd
,
186 case WDIOC_GETSUPPORT
:
187 ret
= copy_to_user((struct watchdog_info
*)arg
, &ident
,
188 sizeof(ident
)) ? -EFAULT
: 0;
191 case WDIOC_GETSTATUS
:
192 ret
= put_user(0, (int *)arg
);
195 case WDIOC_GETBOOTSTATUS
:
196 ret
= put_user(boot_status
, (int *)arg
);
199 case WDIOC_SETTIMEOUT
:
200 ret
= get_user(time
, (int *)arg
);
204 if (time
<= 0 || time
> MAX_HEARTBEAT
) {
213 case WDIOC_GETTIMEOUT
:
214 ret
= put_user(heartbeat
, (int *)arg
);
217 case WDIOC_KEEPALIVE
:
225 static int pnx4008_wdt_release(struct inode
*inode
, struct file
*file
)
227 if (!test_bit(WDT_OK_TO_CLOSE
, &wdt_status
))
228 printk(KERN_WARNING
"WATCHDOG: Device closed unexpectdly\n");
231 clear_bit(WDT_IN_USE
, &wdt_status
);
232 clear_bit(WDT_OK_TO_CLOSE
, &wdt_status
);
237 static const struct file_operations pnx4008_wdt_fops
= {
238 .owner
= THIS_MODULE
,
240 .write
= pnx4008_wdt_write
,
241 .ioctl
= pnx4008_wdt_ioctl
,
242 .open
= pnx4008_wdt_open
,
243 .release
= pnx4008_wdt_release
,
246 static struct miscdevice pnx4008_wdt_miscdev
= {
247 .minor
= WATCHDOG_MINOR
,
249 .fops
= &pnx4008_wdt_fops
,
252 static int pnx4008_wdt_probe(struct platform_device
*pdev
)
255 struct resource
*res
;
257 spin_lock_init(&io_lock
);
259 if (heartbeat
< 1 || heartbeat
> MAX_HEARTBEAT
)
260 heartbeat
= DEFAULT_HEARTBEAT
;
262 printk(KERN_INFO MODULE_NAME
263 "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat
);
265 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
267 printk(KERN_INFO MODULE_NAME
268 "failed to get memory region resouce\n");
272 size
= res
->end
- res
->start
+ 1;
273 wdt_mem
= request_mem_region(res
->start
, size
, pdev
->name
);
275 if (wdt_mem
== NULL
) {
276 printk(KERN_INFO MODULE_NAME
"failed to get memory region\n");
279 wdt_base
= (void __iomem
*)IO_ADDRESS(res
->start
);
281 wdt_clk
= clk_get(&pdev
->dev
, "wdt_ck");
282 if (IS_ERR(wdt_clk
)) {
283 ret
= PTR_ERR(wdt_clk
);
284 release_resource(wdt_mem
);
288 clk_set_rate(wdt_clk
, 1);
290 ret
= misc_register(&pnx4008_wdt_miscdev
);
292 printk(KERN_ERR MODULE_NAME
"cannot register misc device\n");
293 release_resource(wdt_mem
);
295 clk_set_rate(wdt_clk
, 0);
297 boot_status
= (__raw_readl(WDTIM_RES(wdt_base
)) & WDOG_RESET
) ?
299 wdt_disable(); /*disable for now */
300 set_bit(WDT_DEVICE_INITED
, &wdt_status
);
307 static int pnx4008_wdt_remove(struct platform_device
*pdev
)
309 misc_deregister(&pnx4008_wdt_miscdev
);
311 clk_set_rate(wdt_clk
, 0);
316 release_resource(wdt_mem
);
323 static struct platform_driver platform_wdt_driver
= {
327 .probe
= pnx4008_wdt_probe
,
328 .remove
= pnx4008_wdt_remove
,
331 static int __init
pnx4008_wdt_init(void)
333 return platform_driver_register(&platform_wdt_driver
);
336 static void __exit
pnx4008_wdt_exit(void)
338 return platform_driver_unregister(&platform_wdt_driver
);
341 module_init(pnx4008_wdt_init
);
342 module_exit(pnx4008_wdt_exit
);
344 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
345 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
347 module_param(heartbeat
, int, 0);
348 MODULE_PARM_DESC(heartbeat
,
349 "Watchdog heartbeat period in seconds from 1 to "
350 __MODULE_STRING(MAX_HEARTBEAT
) ", default "
351 __MODULE_STRING(DEFAULT_HEARTBEAT
));
353 module_param(nowayout
, int, 0);
354 MODULE_PARM_DESC(nowayout
,
355 "Set to 1 to keep watchdog running after device release");
357 MODULE_LICENSE("GPL");
358 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR
);