drivers/video/geode/video_gx.c

   1 /*
   2  * Geode GX video processor device.
   3  *
   4  *   Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *   Portions from AMD's original 2.4 driver:
   7  *     Copyright (C) 2004 Advanced Micro Devices, Inc.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify it
  10  *   under the terms of the GNU General Public License as published by the
  11  *   Free Software Foundation; either version 2 of the License, or (at your
  12  *   option) any later version.
  13  */
  14 #include <linux/fb.h>
  15 #include <linux/delay.h>
  16 #include <asm/io.h>
  17 #include <asm/delay.h>
  18 #include <asm/msr.h>
  19 #include <asm/geode.h>
  20
  21 #include "geodefb.h"
  22 #include "video_gx.h"
  23 #include "gxfb.h"
  24
  25
  26 /*
  27  * Tables of register settings for various DOTCLKs.
  28  */
  29 struct gx_pll_entry {
  30         long pixclock; /* ps */
  31         u32 sys_rstpll_bits;
  32         u32 dotpll_value;
  33 };
  34
  35 #define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
  36 #define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
  37 #define PREDIV2  ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
  38
  39 static const struct gx_pll_entry gx_pll_table_48MHz[] = {
  40         { 40123, POSTDIV3,          0x00000BF2 },       /*  24.9230 */
  41         { 39721, 0,                 0x00000037 },       /*  25.1750 */
  42         { 35308, POSTDIV3|PREMULT2, 0x00000B1A },       /*  28.3220 */
  43         { 31746, POSTDIV3,          0x000002D2 },       /*  31.5000 */
  44         { 27777, POSTDIV3|PREMULT2, 0x00000FE2 },       /*  36.0000 */
  45         { 26666, POSTDIV3,          0x0000057A },       /*  37.5000 */
  46         { 25000, POSTDIV3,          0x0000030A },       /*  40.0000 */
  47         { 22271, 0,                 0x00000063 },       /*  44.9000 */
  48         { 20202, 0,                 0x0000054B },       /*  49.5000 */
  49         { 20000, 0,                 0x0000026E },       /*  50.0000 */
  50         { 19860, PREMULT2,          0x00000037 },       /*  50.3500 */
  51         { 18518, POSTDIV3|PREMULT2, 0x00000B0D },       /*  54.0000 */
  52         { 17777, 0,                 0x00000577 },       /*  56.2500 */
  53         { 17733, 0,                 0x000007F7 },       /*  56.3916 */
  54         { 17653, 0,                 0x0000057B },       /*  56.6444 */
  55         { 16949, PREMULT2,          0x00000707 },       /*  59.0000 */
  56         { 15873, POSTDIV3|PREMULT2, 0x00000B39 },       /*  63.0000 */
  57         { 15384, POSTDIV3|PREMULT2, 0x00000B45 },       /*  65.0000 */
  58         { 14814, POSTDIV3|PREMULT2, 0x00000FC1 },       /*  67.5000 */
  59         { 14124, POSTDIV3,          0x00000561 },       /*  70.8000 */
  60         { 13888, POSTDIV3,          0x000007E1 },       /*  72.0000 */
  61         { 13426, PREMULT2,          0x00000F4A },       /*  74.4810 */
  62         { 13333, 0,                 0x00000052 },       /*  75.0000 */
  63         { 12698, 0,                 0x00000056 },       /*  78.7500 */
  64         { 12500, POSTDIV3|PREMULT2, 0x00000709 },       /*  80.0000 */
  65         { 11135, PREMULT2,          0x00000262 },       /*  89.8000 */
  66         { 10582, 0,                 0x000002D2 },       /*  94.5000 */
  67         { 10101, PREMULT2,          0x00000B4A },       /*  99.0000 */
  68         { 10000, PREMULT2,          0x00000036 },       /* 100.0000 */
  69         {  9259, 0,                 0x000007E2 },       /* 108.0000 */
  70         {  8888, 0,                 0x000007F6 },       /* 112.5000 */
  71         {  7692, POSTDIV3|PREMULT2, 0x00000FB0 },       /* 130.0000 */
  72         {  7407, POSTDIV3|PREMULT2, 0x00000B50 },       /* 135.0000 */
  73         {  6349, 0,                 0x00000055 },       /* 157.5000 */
  74         {  6172, 0,                 0x000009C1 },       /* 162.0000 */
  75         {  5787, PREMULT2,          0x0000002D },       /* 172.798  */
  76         {  5698, 0,                 0x000002C1 },       /* 175.5000 */
  77         {  5291, 0,                 0x000002D1 },       /* 189.0000 */
  78         {  4938, 0,                 0x00000551 },       /* 202.5000 */
  79         {  4357, 0,                 0x0000057D },       /* 229.5000 */
  80 };
  81
  82 static const struct gx_pll_entry gx_pll_table_14MHz[] = {
  83         { 39721, 0, 0x00000037 },       /*  25.1750 */
  84         { 35308, 0, 0x00000B7B },       /*  28.3220 */
  85         { 31746, 0, 0x000004D3 },       /*  31.5000 */
  86         { 27777, 0, 0x00000BE3 },       /*  36.0000 */
  87         { 26666, 0, 0x0000074F },       /*  37.5000 */
  88         { 25000, 0, 0x0000050B },       /*  40.0000 */
  89         { 22271, 0, 0x00000063 },       /*  44.9000 */
  90         { 20202, 0, 0x0000054B },       /*  49.5000 */
  91         { 20000, 0, 0x0000026E },       /*  50.0000 */
  92         { 19860, 0, 0x000007C3 },       /*  50.3500 */
  93         { 18518, 0, 0x000007E3 },       /*  54.0000 */
  94         { 17777, 0, 0x00000577 },       /*  56.2500 */
  95         { 17733, 0, 0x000002FB },       /*  56.3916 */
  96         { 17653, 0, 0x0000057B },       /*  56.6444 */
  97         { 16949, 0, 0x0000058B },       /*  59.0000 */
  98         { 15873, 0, 0x0000095E },       /*  63.0000 */
  99         { 15384, 0, 0x0000096A },       /*  65.0000 */
 100         { 14814, 0, 0x00000BC2 },       /*  67.5000 */
 101         { 14124, 0, 0x0000098A },       /*  70.8000 */
 102         { 13888, 0, 0x00000BE2 },       /*  72.0000 */
 103         { 13333, 0, 0x00000052 },       /*  75.0000 */
 104         { 12698, 0, 0x00000056 },       /*  78.7500 */
 105         { 12500, 0, 0x0000050A },       /*  80.0000 */
 106         { 11135, 0, 0x0000078E },       /*  89.8000 */
 107         { 10582, 0, 0x000002D2 },       /*  94.5000 */
 108         { 10101, 0, 0x000011F6 },       /*  99.0000 */
 109         { 10000, 0, 0x0000054E },       /* 100.0000 */
 110         {  9259, 0, 0x000007E2 },       /* 108.0000 */
 111         {  8888, 0, 0x000002FA },       /* 112.5000 */
 112         {  7692, 0, 0x00000BB1 },       /* 130.0000 */
 113         {  7407, 0, 0x00000975 },       /* 135.0000 */
 114         {  6349, 0, 0x00000055 },       /* 157.5000 */
 115         {  6172, 0, 0x000009C1 },       /* 162.0000 */
 116         {  5698, 0, 0x000002C1 },       /* 175.5000 */
 117         {  5291, 0, 0x00000539 },       /* 189.0000 */
 118         {  4938, 0, 0x00000551 },       /* 202.5000 */
 119         {  4357, 0, 0x0000057D },       /* 229.5000 */
 120 };
 121
 122 static void gx_set_dclk_frequency(struct fb_info *info)
 123 {
 124         const struct gx_pll_entry *pll_table;
 125         int pll_table_len;
 126         int i, best_i;
 127         long min, diff;
 128         u64 dotpll, sys_rstpll;
 129         int timeout = 1000;
 130
 131         /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
 132         if (cpu_data(0).x86_mask == 1) {
 133                 pll_table = gx_pll_table_14MHz;
 134                 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
 135         } else {
 136                 pll_table = gx_pll_table_48MHz;
 137                 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
 138         }
 139
 140         /* Search the table for the closest pixclock. */
 141         best_i = 0;
 142         min = abs(pll_table[0].pixclock - info->var.pixclock);
 143         for (i = 1; i < pll_table_len; i++) {
 144                 diff = abs(pll_table[i].pixclock - info->var.pixclock);
 145                 if (diff < min) {
 146                         min = diff;
 147                         best_i = i;
 148                 }
 149         }
 150
 151         rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
 152         rdmsrl(MSR_GLCP_DOTPLL, dotpll);
 153
 154         /* Program new M, N and P. */
 155         dotpll &= 0x00000000ffffffffull;
 156         dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
 157         dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
 158         dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
 159
 160         wrmsrl(MSR_GLCP_DOTPLL, dotpll);
 161
 162         /* Program dividers. */
 163         sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
 164                          | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
 165                          | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
 166         sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
 167
 168         wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
 169
 170         /* Clear reset bit to start PLL. */
 171         dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
 172         wrmsrl(MSR_GLCP_DOTPLL, dotpll);
 173
 174         /* Wait for LOCK bit. */
 175         do {
 176                 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
 177         } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
 178 }
 179
 180 static void
 181 gx_configure_tft(struct fb_info *info)
 182 {
 183         struct geodefb_par *par = info->par;
 184         unsigned long val;
 185         unsigned long fp;
 186
 187         /* Set up the DF pad select MSR */
 188
 189         rdmsrl(MSR_GX_MSR_PADSEL, val);
 190         val &= ~GX_VP_PAD_SELECT_MASK;
 191         val |= GX_VP_PAD_SELECT_TFT;
 192         wrmsrl(MSR_GX_MSR_PADSEL, val);
 193
 194         /* Turn off the panel */
 195
 196         fp = read_fp(par, GX_FP_PM);
 197         fp &= ~GX_FP_PM_P;
 198         write_fp(par, GX_FP_PM, fp);
 199
 200         /* Set timing 1 */
 201
 202         fp = read_fp(par, GX_FP_PT1);
 203         fp &= GX_FP_PT1_VSIZE_MASK;
 204         fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
 205         write_fp(par, GX_FP_PT1, fp);
 206
 207         /* Timing 2 */
 208         /* Set bits that are always on for TFT */
 209
 210         fp = 0x0F100000;
 211
 212         /* Configure sync polarity */
 213
 214         if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
 215                 fp |= GX_FP_PT2_VSP;
 216
 217         if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
 218                 fp |= GX_FP_PT2_HSP;
 219
 220         write_fp(par, GX_FP_PT2, fp);
 221
 222         /*  Set the dither control */
 223         write_fp(par, GX_FP_DFC, 0x70);
 224
 225         /* Enable the FP data and power (in case the BIOS didn't) */
 226
 227         fp = read_vp(par, GX_DCFG);
 228         fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
 229         write_vp(par, GX_DCFG, fp);
 230
 231         /* Unblank the panel */
 232
 233         fp = read_fp(par, GX_FP_PM);
 234         fp |= GX_FP_PM_P;
 235         write_fp(par, GX_FP_PM, fp);
 236 }
 237
 238 static void gx_configure_display(struct fb_info *info)
 239 {
 240         struct geodefb_par *par = info->par;
 241         u32 dcfg, misc;
 242
 243         /* Write the display configuration */
 244         dcfg = read_vp(par, GX_DCFG);
 245
 246         /* Disable hsync and vsync */
 247         dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
 248         write_vp(par, GX_DCFG, dcfg);
 249
 250         /* Clear bits from existing mode. */
 251         dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
 252                   | GX_DCFG_CRT_HSYNC_POL   | GX_DCFG_CRT_VSYNC_POL
 253                   | GX_DCFG_VSYNC_EN        | GX_DCFG_HSYNC_EN);
 254
 255         /* Set default sync skew.  */
 256         dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
 257
 258         /* Enable hsync and vsync. */
 259         dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
 260
 261         misc = read_vp(par, GX_MISC);
 262
 263         /* Disable gamma correction */
 264         misc |= GX_MISC_GAM_EN;
 265
 266         if (par->enable_crt) {
 267
 268                 /* Power up the CRT DACs */
 269                 misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
 270                 write_vp(par, GX_MISC, misc);
 271
 272                 /* Only change the sync polarities if we are running
 273                  * in CRT mode.  The FP polarities will be handled in
 274                  * gxfb_configure_tft */
 275                 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
 276                         dcfg |= GX_DCFG_CRT_HSYNC_POL;
 277                 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
 278                         dcfg |= GX_DCFG_CRT_VSYNC_POL;
 279         } else {
 280                 /* Power down the CRT DACs if in FP mode */
 281                 misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
 282                 write_vp(par, GX_MISC, misc);
 283         }
 284
 285         /* Enable the display logic */
 286         /* Set up the DACS to blank normally */
 287
 288         dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
 289
 290         /* Enable the external DAC VREF? */
 291
 292         write_vp(par, GX_DCFG, dcfg);
 293
 294         /* Set up the flat panel (if it is enabled) */
 295
 296         if (par->enable_crt == 0)
 297                 gx_configure_tft(info);
 298 }
 299
 300 static int gx_blank_display(struct fb_info *info, int blank_mode)
 301 {
 302         struct geodefb_par *par = info->par;
 303         u32 dcfg, fp_pm;
 304         int blank, hsync, vsync;
 305
 306         /* CRT power saving modes. */
 307         switch (blank_mode) {
 308         case FB_BLANK_UNBLANK:
 309                 blank = 0; hsync = 1; vsync = 1;
 310                 break;
 311         case FB_BLANK_NORMAL:
 312                 blank = 1; hsync = 1; vsync = 1;
 313                 break;
 314         case FB_BLANK_VSYNC_SUSPEND:
 315                 blank = 1; hsync = 1; vsync = 0;
 316                 break;
 317         case FB_BLANK_HSYNC_SUSPEND:
 318                 blank = 1; hsync = 0; vsync = 1;
 319                 break;
 320         case FB_BLANK_POWERDOWN:
 321                 blank = 1; hsync = 0; vsync = 0;
 322                 break;
 323         default:
 324                 return -EINVAL;
 325         }
 326         dcfg = read_vp(par, GX_DCFG);
 327         dcfg &= ~(GX_DCFG_DAC_BL_EN
 328                   | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
 329         if (!blank)
 330                 dcfg |= GX_DCFG_DAC_BL_EN;
 331         if (hsync)
 332                 dcfg |= GX_DCFG_HSYNC_EN;
 333         if (vsync)
 334                 dcfg |= GX_DCFG_VSYNC_EN;
 335         write_vp(par, GX_DCFG, dcfg);
 336
 337         /* Power on/off flat panel. */
 338
 339         if (par->enable_crt == 0) {
 340                 fp_pm = read_fp(par, GX_FP_PM);
 341                 if (blank_mode == FB_BLANK_POWERDOWN)
 342                         fp_pm &= ~GX_FP_PM_P;
 343                 else
 344                         fp_pm |= GX_FP_PM_P;
 345                 write_fp(par, GX_FP_PM, fp_pm);
 346         }
 347
 348         return 0;
 349 }
 350
 351 struct geode_vid_ops gx_vid_ops = {
 352         .set_dclk          = gx_set_dclk_frequency,
 353         .configure_display = gx_configure_display,
 354         .blank_display     = gx_blank_display,
 355 };