include/asm-m68knommu/commproc.h

   1
   2 /*
   3  * 68360 Communication Processor Module.
   4  * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
   5  * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
   6  *
   7  * This file contains structures and information for the communication
   8  * processor channels.  Some CPM control and status is available
   9  * through the 68360 internal memory map.  See include/asm/360_immap.h for details.
  10  * This file is not a complete map of all of the 360 QUICC's capabilities
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM_360__
  18 #define __CPM_360__
  19
  20 #include <linux/config.h>
  21
  22 /* CPM Command register masks: */
  23 #define CPM_CR_RST      ((ushort)0x8000)
  24 #define CPM_CR_OPCODE   ((ushort)0x0f00)
  25 #define CPM_CR_CHAN     ((ushort)0x00f0)
  26 #define CPM_CR_FLG      ((ushort)0x0001)
  27
  28 /* CPM Command set (opcodes): */
  29 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  30 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  31 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  32 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  33 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  34 #define CPM_CR_GRSTOP_TX        ((ushort)0x0005)
  35 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  36 #define CPM_CR_CLOSE_RXBD       ((ushort)0x0007)
  37 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  38 #define CPM_CR_GCI_TIMEOUT      ((ushort)0x0009)
  39 #define CPM_CR_GCI_ABORT        ((ushort)0x000a)
  40 #define CPM_CR_RESET_BCS        ((ushort)0x000a)
  41
  42 /* CPM Channel numbers. */
  43 #define CPM_CR_CH_SCC1  ((ushort)0x0000)
  44 #define CPM_CR_CH_SCC2  ((ushort)0x0004)
  45 #define CPM_CR_CH_SPI   ((ushort)0x0005)        /* SPI / Timers */
  46 #define CPM_CR_CH_TMR   ((ushort)0x0005)
  47 #define CPM_CR_CH_SCC3  ((ushort)0x0008)
  48 #define CPM_CR_CH_SMC1  ((ushort)0x0009)        /* SMC1 / IDMA1 */
  49 #define CPM_CR_CH_IDMA1 ((ushort)0x0009)
  50 #define CPM_CR_CH_SCC4  ((ushort)0x000c)
  51 #define CPM_CR_CH_SMC2  ((ushort)0x000d)        /* SMC2 / IDMA2 */
  52 #define CPM_CR_CH_IDMA2 ((ushort)0x000d)
  53
  54
  55 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  56
  57 #if 1 /* mleslie: I dinna think we have any such restrictions on
  58        * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
  59
  60 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  61  * being) used for microcode.  There is an area that can only be used
  62  * as data ram for buffer descriptors, which is all we use right now.
  63  * Currently the first 512 and last 256 bytes are used for microcode.
  64  */
  65 /* mleslie: The uCquicc board is using no extra microcode in DPRAM */
  66 #define CPM_DATAONLY_BASE       ((uint)0x0000)
  67 #define CPM_DATAONLY_SIZE       ((uint)0x0800)
  68 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  69
  70 #endif
  71
  72
  73 /* Export the base address of the communication processor registers
  74  * and dual port ram. */
  75 /* extern       cpm360_t        *cpmp; */               /* Pointer to comm processor */
  76 extern QUICC *pquicc;
  77 uint         m360_cpm_dpalloc(uint size);
  78 /* void         *m360_cpm_hostalloc(uint size); */
  79 void          m360_cpm_setbrg(uint brg, uint rate);
  80
  81 #if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h  */
  82 /* Buffer descriptors used by many of the CPM protocols. */
  83 typedef struct cpm_buf_desc {
  84         ushort  cbd_sc;         /* Status and Control */
  85         ushort  cbd_datlen;     /* Data length in buffer */
  86         uint    cbd_bufaddr;    /* Buffer address in host memory */
  87 } cbd_t;
  88 #endif
  89
  90
  91 /* rx bd status/control bits */
  92 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
  93 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor in table */
  94 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
  95 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame OR control char */
  96
  97 #define BD_SC_FIRST     ((ushort)0x0400)        /* 1st buffer in an HDLC frame */
  98 #define BD_SC_ADDR      ((ushort)0x0400)        /* 1st byte is a multidrop address */
  99
 100 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 101 #define BD_SC_ID        ((ushort)0x0100)        /* Received too many idles */
 102
 103 #define BD_SC_AM        ((ushort)0x0080)        /* Multidrop address match */
 104 #define BD_SC_DE        ((ushort)0x0080)        /* DPLL Error (HDLC) */
 105
 106 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 107 #define BD_SC_LG        ((ushort)0x0020)        /* Frame length violation (HDLC) */
 108
 109 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 110 #define BD_SC_NO        ((ushort)0x0010)        /* Nonoctet aligned frame (HDLC) */
 111
 112 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 113 #define BD_SC_AB        ((ushort)0x0008)        /* Received abort Sequence (HDLC) */
 114
 115 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 116 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
 117
 118 /* tx bd status/control bits (as differ from rx bd) */
 119 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
 120 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 121 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 122 #define BD_SC_UN        ((ushort)0x0002)        /* Underrun */
 123
 124
 125
 126
 127 /* Parameter RAM offsets. */
 128
 129
 130
 131 /* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
 132  * In 2.0, we use a more structured C struct map of DPRAM, and so
 133  * instead, we need only a parameter ram `slot'  */
 134
 135 #define PRSLOT_SCC1     0
 136 #define PRSLOT_SCC2     1
 137 #define PRSLOT_SCC3     2
 138 #define PRSLOT_SMC1     2
 139 #define PRSLOT_SCC4     3
 140 #define PRSLOT_SMC2     3
 141
 142
 143 /* #define PROFF_SCC1   ((uint)0x0000) */
 144 /* #define PROFF_SCC2   ((uint)0x0100) */
 145 /* #define PROFF_SCC3   ((uint)0x0200) */
 146 /* #define PROFF_SMC1   ((uint)0x0280) */
 147 /* #define PROFF_SCC4   ((uint)0x0300) */
 148 /* #define PROFF_SMC2   ((uint)0x0380) */
 149
 150
 151 /* Define enough so I can at least use the serial port as a UART.
 152  * The MBX uses SMC1 as the host serial port.
 153  */
 154 typedef struct smc_uart {
 155         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 156         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 157         u_char  smc_rfcr;       /* Rx function code */
 158         u_char  smc_tfcr;       /* Tx function code */
 159         ushort  smc_mrblr;      /* Max receive buffer length */
 160         uint    smc_rstate;     /* Internal */
 161         uint    smc_idp;        /* Internal */
 162         ushort  smc_rbptr;      /* Internal */
 163         ushort  smc_ibc;        /* Internal */
 164         uint    smc_rxtmp;      /* Internal */
 165         uint    smc_tstate;     /* Internal */
 166         uint    smc_tdp;        /* Internal */
 167         ushort  smc_tbptr;      /* Internal */
 168         ushort  smc_tbc;        /* Internal */
 169         uint    smc_txtmp;      /* Internal */
 170         ushort  smc_maxidl;     /* Maximum idle characters */
 171         ushort  smc_tmpidl;     /* Temporary idle counter */
 172         ushort  smc_brklen;     /* Last received break length */
 173         ushort  smc_brkec;      /* rcv'd break condition counter */
 174         ushort  smc_brkcr;      /* xmt break count register */
 175         ushort  smc_rmask;      /* Temporary bit mask */
 176 } smc_uart_t;
 177
 178 /* Function code bits.
 179 */
 180 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 181
 182 /* SMC uart mode register.
 183 */
 184 #define SMCMR_REN       ((ushort)0x0001)
 185 #define SMCMR_TEN       ((ushort)0x0002)
 186 #define SMCMR_DM        ((ushort)0x000c)
 187 #define SMCMR_SM_GCI    ((ushort)0x0000)
 188 #define SMCMR_SM_UART   ((ushort)0x0020)
 189 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 190 #define SMCMR_SM_MASK   ((ushort)0x0030)
 191 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 192 #define SMCMR_REVD      SMCMR_PM_EVEN
 193 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 194 #define SMCMR_BS        SMCMR_PEN
 195 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 196 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 197 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 198
 199 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 200  * it can only receive or transmit.  The parameter ram values for
 201  * each direction are either unique or properly overlap, so we can
 202  * include them in one structure.
 203  */
 204 typedef struct smc_centronics {
 205         ushort  scent_rbase;
 206         ushort  scent_tbase;
 207         u_char  scent_cfcr;
 208         u_char  scent_smask;
 209         ushort  scent_mrblr;
 210         uint    scent_rstate;
 211         uint    scent_r_ptr;
 212         ushort  scent_rbptr;
 213         ushort  scent_r_cnt;
 214         uint    scent_rtemp;
 215         uint    scent_tstate;
 216         uint    scent_t_ptr;
 217         ushort  scent_tbptr;
 218         ushort  scent_t_cnt;
 219         uint    scent_ttemp;
 220         ushort  scent_max_sl;
 221         ushort  scent_sl_cnt;
 222         ushort  scent_character1;
 223         ushort  scent_character2;
 224         ushort  scent_character3;
 225         ushort  scent_character4;
 226         ushort  scent_character5;
 227         ushort  scent_character6;
 228         ushort  scent_character7;
 229         ushort  scent_character8;
 230         ushort  scent_rccm;
 231         ushort  scent_rccr;
 232 } smc_cent_t;
 233
 234 /* Centronics Status Mask Register.
 235 */
 236 #define SMC_CENT_F      ((u_char)0x08)
 237 #define SMC_CENT_PE     ((u_char)0x04)
 238 #define SMC_CENT_S      ((u_char)0x02)
 239
 240 /* SMC Event and Mask register.
 241 */
 242 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 243 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 244 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 245 #define SMCM_BSY        ((unsigned char)0x04)
 246 #define SMCM_TX         ((unsigned char)0x02)
 247 #define SMCM_RX         ((unsigned char)0x01)
 248
 249 /* Baud rate generators.
 250 */
 251 #define CPM_BRG_RST             ((uint)0x00020000)
 252 #define CPM_BRG_EN              ((uint)0x00010000)
 253 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 254 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 255 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 256 #define CPM_BRG_ATB             ((uint)0x00002000)
 257 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 258 #define CPM_BRG_DIV16           ((uint)0x00000001)
 259
 260 /* SCCs.
 261 */
 262 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 263 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 264 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 265 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 266 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 267 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 268 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 269 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 270 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 271 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 272 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 273 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 274 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 275 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 276 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 277 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 278 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 279 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 280 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 281 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 282
 283 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 284 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 285 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 286 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 287 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 288 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 289 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 290 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 291 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 292 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 293 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 294 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 295 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 296 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 297 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 298 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 299 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 300 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 301 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 302 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 303 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 304 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 305 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 306 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 307 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 308 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 309 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 310 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 311 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 312 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 313 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 314 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 315 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 316 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 317 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 318 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 319 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 320 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 321 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 322 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 323 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 324 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 325 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 326 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 327 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 328 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 329 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 330 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 331 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 332 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 333 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 334 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 335 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 336 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 337 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 338 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 339 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 340 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 341
 342 #define SCC_TODR_TOD            ((ushort)0x8000)
 343
 344 /* SCC Event and Mask register.
 345 */
 346 #define SCCM_TXE        ((unsigned char)0x10)
 347 #define SCCM_BSY        ((unsigned char)0x04)
 348 #define SCCM_TX         ((unsigned char)0x02)
 349 #define SCCM_RX         ((unsigned char)0x01)
 350
 351 typedef struct scc_param {
 352         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 353         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 354         u_char  scc_rfcr;       /* Rx function code */
 355         u_char  scc_tfcr;       /* Tx function code */
 356         ushort  scc_mrblr;      /* Max receive buffer length */
 357         uint    scc_rstate;     /* Internal */
 358         uint    scc_idp;        /* Internal */
 359         ushort  scc_rbptr;      /* Internal */
 360         ushort  scc_ibc;        /* Internal */
 361         uint    scc_rxtmp;      /* Internal */
 362         uint    scc_tstate;     /* Internal */
 363         uint    scc_tdp;        /* Internal */
 364         ushort  scc_tbptr;      /* Internal */
 365         ushort  scc_tbc;        /* Internal */
 366         uint    scc_txtmp;      /* Internal */
 367         uint    scc_rcrc;       /* Internal */
 368         uint    scc_tcrc;       /* Internal */
 369 } sccp_t;
 370
 371
 372 /* Function code bits.
 373  */
 374 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 375 #define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
 376
 377 /* CPM Ethernet through SCC1.
 378  */
 379 typedef struct scc_enet {
 380         sccp_t  sen_genscc;
 381         uint    sen_cpres;      /* Preset CRC */
 382         uint    sen_cmask;      /* Constant mask for CRC */
 383         uint    sen_crcec;      /* CRC Error counter */
 384         uint    sen_alec;       /* alignment error counter */
 385         uint    sen_disfc;      /* discard frame counter */
 386         ushort  sen_pads;       /* Tx short frame pad character */
 387         ushort  sen_retlim;     /* Retry limit threshold */
 388         ushort  sen_retcnt;     /* Retry limit counter */
 389         ushort  sen_maxflr;     /* maximum frame length register */
 390         ushort  sen_minflr;     /* minimum frame length register */
 391         ushort  sen_maxd1;      /* maximum DMA1 length */
 392         ushort  sen_maxd2;      /* maximum DMA2 length */
 393         ushort  sen_maxd;       /* Rx max DMA */
 394         ushort  sen_dmacnt;     /* Rx DMA counter */
 395         ushort  sen_maxb;       /* Max BD byte count */
 396         ushort  sen_gaddr1;     /* Group address filter */
 397         ushort  sen_gaddr2;
 398         ushort  sen_gaddr3;
 399         ushort  sen_gaddr4;
 400         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 401         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 402         uint    sen_tbuf0rba;   /* Internal */
 403         uint    sen_tbuf0crc;   /* Internal */
 404         ushort  sen_tbuf0bcnt;  /* Internal */
 405         ushort  sen_paddrh;     /* physical address (MSB) */
 406         ushort  sen_paddrm;
 407         ushort  sen_paddrl;     /* physical address (LSB) */
 408         ushort  sen_pper;       /* persistence */
 409         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 410         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 411         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 412         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 413         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 414         uint    sen_tbuf1rba;   /* Internal */
 415         uint    sen_tbuf1crc;   /* Internal */
 416         ushort  sen_tbuf1bcnt;  /* Internal */
 417         ushort  sen_txlen;      /* Tx Frame length counter */
 418         ushort  sen_iaddr1;     /* Individual address filter */
 419         ushort  sen_iaddr2;
 420         ushort  sen_iaddr3;
 421         ushort  sen_iaddr4;
 422         ushort  sen_boffcnt;    /* Backoff counter */
 423
 424         /* NOTE: Some versions of the manual have the following items
 425          * incorrectly documented.  Below is the proper order.
 426          */
 427         ushort  sen_taddrh;     /* temp address (MSB) */
 428         ushort  sen_taddrm;
 429         ushort  sen_taddrl;     /* temp address (LSB) */
 430 } scc_enet_t;
 431
 432
 433
 434 #if defined (CONFIG_UCQUICC)
 435 /* uCquicc has the following signals connected to Ethernet:
 436  *  68360    - lxt905
 437  * PA0/RXD1  - rxd
 438  * PA1/TXD1  - txd
 439  * PA8/CLK1  - tclk
 440  * PA9/CLK2  - rclk
 441  * PC0/!RTS1 - t_en
 442  * PC1/!CTS1 - col
 443  * PC5/!CD1  - cd
 444  */
 445 #define PA_ENET_RXD     PA_RXD1
 446 #define PA_ENET_TXD     PA_TXD1
 447 #define PA_ENET_TCLK    PA_CLK1
 448 #define PA_ENET_RCLK    PA_CLK2
 449 #define PC_ENET_TENA    PC_RTS1
 450 #define PC_ENET_CLSN    PC_CTS1
 451 #define PC_ENET_RENA    PC_CD1
 452
 453 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 454  * SCC1.
 455  */
 456 #define SICR_ENET_MASK  ((uint)0x000000ff)
 457 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 458
 459 #endif /* config_ucquicc */
 460
 461
 462 #ifdef MBX
 463 /* Bits in parallel I/O port registers that have to be set/cleared
 464  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
 465  * to the MBX860 board.  Any two of the four available clocks could be
 466  * used, and the MPC860 cookbook manual has an example using different
 467  * clock pins.
 468  */
 469 #define PA_ENET_RXD     ((ushort)0x0001)
 470 #define PA_ENET_TXD     ((ushort)0x0002)
 471 #define PA_ENET_TCLK    ((ushort)0x0200)
 472 #define PA_ENET_RCLK    ((ushort)0x0800)
 473 #define PC_ENET_TENA    ((ushort)0x0001)
 474 #define PC_ENET_CLSN    ((ushort)0x0010)
 475 #define PC_ENET_RENA    ((ushort)0x0020)
 476
 477 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 478  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 479  */
 480 #define SICR_ENET_MASK  ((uint)0x000000ff)
 481 #define SICR_ENET_CLKRT ((uint)0x0000003d)
 482 #endif
 483
 484 #ifdef CONFIG_RPXLITE
 485 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
 486  * this may be unique to the RPX-Lite configuration.
 487  * Note TENA is on Port B.
 488  */
 489 #define PA_ENET_RXD     ((ushort)0x0004)
 490 #define PA_ENET_TXD     ((ushort)0x0008)
 491 #define PA_ENET_TCLK    ((ushort)0x0200)
 492 #define PA_ENET_RCLK    ((ushort)0x0800)
 493 #define PB_ENET_TENA    ((uint)0x00002000)
 494 #define PC_ENET_CLSN    ((ushort)0x0040)
 495 #define PC_ENET_RENA    ((ushort)0x0080)
 496
 497 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 498 #define SICR_ENET_CLKRT ((uint)0x00003d00)
 499 #endif
 500
 501 #ifdef CONFIG_BSEIP
 502 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
 503  * This is unique to the BSE ip-Engine board.
 504  */
 505 #define PA_ENET_RXD     ((ushort)0x0004)
 506 #define PA_ENET_TXD     ((ushort)0x0008)
 507 #define PA_ENET_TCLK    ((ushort)0x0100)
 508 #define PA_ENET_RCLK    ((ushort)0x0200)
 509 #define PB_ENET_TENA    ((uint)0x00002000)
 510 #define PC_ENET_CLSN    ((ushort)0x0040)
 511 #define PC_ENET_RENA    ((ushort)0x0080)
 512
 513 /* BSE uses port B and C bits for PHY control also.
 514 */
 515 #define PB_BSE_POWERUP  ((uint)0x00000004)
 516 #define PB_BSE_FDXDIS   ((uint)0x00008000)
 517 #define PC_BSE_LOOPBACK ((ushort)0x0800)
 518
 519 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 520 #define SICR_ENET_CLKRT ((uint)0x00002c00)
 521 #endif
 522
 523 #ifdef CONFIG_RPXCLASSIC
 524 /* Bits in parallel I/O port registers that have to be set/cleared
 525  * to configure the pins for SCC1 use.
 526  */
 527 #define PA_ENET_RXD     ((ushort)0x0001)
 528 #define PA_ENET_TXD     ((ushort)0x0002)
 529 #define PA_ENET_TCLK    ((ushort)0x0200)
 530 #define PA_ENET_RCLK    ((ushort)0x0800)
 531 #define PB_ENET_TENA    ((uint)0x00001000)
 532 #define PC_ENET_CLSN    ((ushort)0x0010)
 533 #define PC_ENET_RENA    ((ushort)0x0020)
 534
 535 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 536  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 537  */
 538 #define SICR_ENET_MASK  ((uint)0x000000ff)
 539 #define SICR_ENET_CLKRT ((uint)0x0000003d)
 540 #endif
 541
 542 /* SCC Event register as used by Ethernet.
 543 */
 544 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 545 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 546 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 547 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 548 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 549 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 550
 551 /* SCC Mode Register (PMSR) as used by Ethernet.
 552 */
 553 #define SCC_PMSR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 554 #define SCC_PMSR_FC     ((ushort)0x4000)        /* Force collision */
 555 #define SCC_PMSR_RSH    ((ushort)0x2000)        /* Receive short frames */
 556 #define SCC_PMSR_IAM    ((ushort)0x1000)        /* Check individual hash */
 557 #define SCC_PMSR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 558 #define SCC_PMSR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 559 #define SCC_PMSR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 560 #define SCC_PMSR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 561 #define SCC_PMSR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 562 #define SCC_PMSR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 563 #define SCC_PMSR_LCW    ((ushort)0x0010)        /* Late collision window */
 564 #define SCC_PMSR_NIB22  ((ushort)0x000a)        /* Start frame search */
 565 #define SCC_PMSR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 566
 567 /* Buffer descriptor control/status used by Ethernet receive.
 568 */
 569 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 570 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
 571 #define BD_ENET_RX_INTR         ((ushort)0x1000)
 572 #define BD_ENET_RX_LAST         ((ushort)0x0800)
 573 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
 574 #define BD_ENET_RX_MISS         ((ushort)0x0100)
 575 #define BD_ENET_RX_LG           ((ushort)0x0020)
 576 #define BD_ENET_RX_NO           ((ushort)0x0010)
 577 #define BD_ENET_RX_SH           ((ushort)0x0008)
 578 #define BD_ENET_RX_CR           ((ushort)0x0004)
 579 #define BD_ENET_RX_OV           ((ushort)0x0002)
 580 #define BD_ENET_RX_CL           ((ushort)0x0001)
 581 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
 582
 583 /* Buffer descriptor control/status used by Ethernet transmit.
 584 */
 585 #define BD_ENET_TX_READY        ((ushort)0x8000)
 586 #define BD_ENET_TX_PAD          ((ushort)0x4000)
 587 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
 588 #define BD_ENET_TX_INTR         ((ushort)0x1000)
 589 #define BD_ENET_TX_LAST         ((ushort)0x0800)
 590 #define BD_ENET_TX_TC           ((ushort)0x0400)
 591 #define BD_ENET_TX_DEF          ((ushort)0x0200)
 592 #define BD_ENET_TX_HB           ((ushort)0x0100)
 593 #define BD_ENET_TX_LC           ((ushort)0x0080)
 594 #define BD_ENET_TX_RL           ((ushort)0x0040)
 595 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
 596 #define BD_ENET_TX_UN           ((ushort)0x0002)
 597 #define BD_ENET_TX_CSL          ((ushort)0x0001)
 598 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 599
 600 /* SCC as UART
 601 */
 602 typedef struct scc_uart {
 603         sccp_t  scc_genscc;
 604         uint    scc_res1;       /* Reserved */
 605         uint    scc_res2;       /* Reserved */
 606         ushort  scc_maxidl;     /* Maximum idle chars */
 607         ushort  scc_idlc;       /* temp idle counter */
 608         ushort  scc_brkcr;      /* Break count register */
 609         ushort  scc_parec;      /* receive parity error counter */
 610         ushort  scc_frmec;      /* receive framing error counter */
 611         ushort  scc_nosec;      /* receive noise counter */
 612         ushort  scc_brkec;      /* receive break condition counter */
 613         ushort  scc_brkln;      /* last received break length */
 614         ushort  scc_uaddr1;     /* UART address character 1 */
 615         ushort  scc_uaddr2;     /* UART address character 2 */
 616         ushort  scc_rtemp;      /* Temp storage */
 617         ushort  scc_toseq;      /* Transmit out of sequence char */
 618         ushort  scc_char1;      /* control character 1 */
 619         ushort  scc_char2;      /* control character 2 */
 620         ushort  scc_char3;      /* control character 3 */
 621         ushort  scc_char4;      /* control character 4 */
 622         ushort  scc_char5;      /* control character 5 */
 623         ushort  scc_char6;      /* control character 6 */
 624         ushort  scc_char7;      /* control character 7 */
 625         ushort  scc_char8;      /* control character 8 */
 626         ushort  scc_rccm;       /* receive control character mask */
 627         ushort  scc_rccr;       /* receive control character register */
 628         ushort  scc_rlbc;       /* receive last break character */
 629 } scc_uart_t;
 630
 631 /* SCC Event and Mask registers when it is used as a UART.
 632 */
 633 #define UART_SCCM_GLR           ((ushort)0x1000)
 634 #define UART_SCCM_GLT           ((ushort)0x0800)
 635 #define UART_SCCM_AB            ((ushort)0x0200)
 636 #define UART_SCCM_IDL           ((ushort)0x0100)
 637 #define UART_SCCM_GRA           ((ushort)0x0080)
 638 #define UART_SCCM_BRKE          ((ushort)0x0040)
 639 #define UART_SCCM_BRKS          ((ushort)0x0020)
 640 #define UART_SCCM_CCR           ((ushort)0x0008)
 641 #define UART_SCCM_BSY           ((ushort)0x0004)
 642 #define UART_SCCM_TX            ((ushort)0x0002)
 643 #define UART_SCCM_RX            ((ushort)0x0001)
 644
 645 /* The SCC PMSR when used as a UART.
 646 */
 647 #define SCU_PMSR_FLC            ((ushort)0x8000)
 648 #define SCU_PMSR_SL             ((ushort)0x4000)
 649 #define SCU_PMSR_CL             ((ushort)0x3000)
 650 #define SCU_PMSR_UM             ((ushort)0x0c00)
 651 #define SCU_PMSR_FRZ            ((ushort)0x0200)
 652 #define SCU_PMSR_RZS            ((ushort)0x0100)
 653 #define SCU_PMSR_SYN            ((ushort)0x0080)
 654 #define SCU_PMSR_DRT            ((ushort)0x0040)
 655 #define SCU_PMSR_PEN            ((ushort)0x0010)
 656 #define SCU_PMSR_RPM            ((ushort)0x000c)
 657 #define SCU_PMSR_REVP           ((ushort)0x0008)
 658 #define SCU_PMSR_TPM            ((ushort)0x0003)
 659 #define SCU_PMSR_TEVP           ((ushort)0x0003)
 660
 661 /* CPM Transparent mode SCC.
 662  */
 663 typedef struct scc_trans {
 664         sccp_t  st_genscc;
 665         uint    st_cpres;       /* Preset CRC */
 666         uint    st_cmask;       /* Constant mask for CRC */
 667 } scc_trans_t;
 668
 669 #define BD_SCC_TX_LAST          ((ushort)0x0800)
 670
 671
 672
 673 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 674  * channels or devices.  All of these are presented to the PPC core
 675  * as a single interrupt.  The CPM interrupt handler dispatches its
 676  * own handlers, in a similar fashion to the PPC core handler.  We
 677  * use the table as defined in the manuals (i.e. no special high
 678  * priority and SCC1 == SCCa, etc...).
 679  */
 680 /* #define CPMVEC_NR            32 */
 681 /* #define      CPMVEC_PIO_PC15         ((ushort)0x1f) */
 682 /* #define      CPMVEC_SCC1             ((ushort)0x1e) */
 683 /* #define      CPMVEC_SCC2             ((ushort)0x1d) */
 684 /* #define      CPMVEC_SCC3             ((ushort)0x1c) */
 685 /* #define      CPMVEC_SCC4             ((ushort)0x1b) */
 686 /* #define      CPMVEC_PIO_PC14         ((ushort)0x1a) */
 687 /* #define      CPMVEC_TIMER1           ((ushort)0x19) */
 688 /* #define      CPMVEC_PIO_PC13         ((ushort)0x18) */
 689 /* #define      CPMVEC_PIO_PC12         ((ushort)0x17) */
 690 /* #define      CPMVEC_SDMA_CB_ERR      ((ushort)0x16) */
 691 /* #define CPMVEC_IDMA1         ((ushort)0x15) */
 692 /* #define CPMVEC_IDMA2         ((ushort)0x14) */
 693 /* #define CPMVEC_TIMER2                ((ushort)0x12) */
 694 /* #define CPMVEC_RISCTIMER     ((ushort)0x11) */
 695 /* #define CPMVEC_I2C           ((ushort)0x10) */
 696 /* #define      CPMVEC_PIO_PC11         ((ushort)0x0f) */
 697 /* #define      CPMVEC_PIO_PC10         ((ushort)0x0e) */
 698 /* #define CPMVEC_TIMER3                ((ushort)0x0c) */
 699 /* #define      CPMVEC_PIO_PC9          ((ushort)0x0b) */
 700 /* #define      CPMVEC_PIO_PC8          ((ushort)0x0a) */
 701 /* #define      CPMVEC_PIO_PC7          ((ushort)0x09) */
 702 /* #define CPMVEC_TIMER4                ((ushort)0x07) */
 703 /* #define      CPMVEC_PIO_PC6          ((ushort)0x06) */
 704 /* #define      CPMVEC_SPI              ((ushort)0x05) */
 705 /* #define      CPMVEC_SMC1             ((ushort)0x04) */
 706 /* #define      CPMVEC_SMC2             ((ushort)0x03) */
 707 /* #define      CPMVEC_PIO_PC5          ((ushort)0x02) */
 708 /* #define      CPMVEC_PIO_PC4          ((ushort)0x01) */
 709 /* #define      CPMVEC_ERROR            ((ushort)0x00) */
 710
 711 extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
 712
 713 /* CPM interrupt configuration vector.
 714 */
 715 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 716 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 717 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 718 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 719 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
 720 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 721 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 722 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 723 #endif /* __CPM_360__ */