| blob | 4b090f3142e0d6c74cde9f0e595b9272d18cec20 |
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
10 *
11 * Some useful macros for MIPS assembler code
12 *
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
16 */
17 #ifndef __ASM_ASM_H
18 #define __ASM_ASM_H
20 #include <linux/config.h>
21 #include <asm/sgidefs.h>
23 #ifndef CAT
24 #ifdef __STDC__
25 #define __CAT(str1,str2) str1##str2
26 #else
28 #endif
29 #define CAT(str1,str2) __CAT(str1,str2)
30 #endif
32 /*
33 * PIC specific declarations
34 * Not used for the kernel but here seems to be the right place.
35 */
36 #ifdef __PIC__
37 #define CPRESTORE(register) \
38 .cprestore register
39 #define CPADD(register) \
40 .cpadd register
41 #define CPLOAD(register) \
42 .cpload register
43 #else
44 #define CPRESTORE(register)
45 #define CPADD(register)
46 #define CPLOAD(register)
47 #endif
49 /*
50 * LEAF - declare leaf routine
51 */
52 #define LEAF(symbol) \
53 .globl symbol; \
54 .align 2; \
55 .type symbol,@function; \
56 .ent symbol,0; \
57 symbol: .frame sp,0,ra
59 /*
60 * NESTED - declare nested routine entry point
61 */
62 #define NESTED(symbol, framesize, rpc) \
63 .globl symbol; \
64 .align 2; \
65 .type symbol,@function; \
66 .ent symbol,0; \
67 symbol: .frame sp, framesize, rpc
69 /*
70 * END - mark end of function
71 */
72 #define END(function) \
73 .end function; \
74 .size function,.-function
76 /*
77 * EXPORT - export definition of symbol
78 */
79 #define EXPORT(symbol) \
80 .globl symbol; \
81 symbol:
83 /*
84 * FEXPORT - export definition of a function symbol
85 */
86 #define FEXPORT(symbol) \
87 .globl symbol; \
88 .type symbol,@function; \
89 symbol:
91 /*
92 * ABS - export absolute symbol
93 */
94 #define ABS(symbol,value) \
95 .globl symbol; \
96 symbol = value
98 #define PANIC(msg) \
99 .set push; \
100 .set reorder; \
101 PTR_LA a0,8f; \
102 jal panic; \
103 9: b 9b; \
104 .set pop; \
105 TEXT(msg)
107 /*
108 * Print formatted string
109 */
110 #ifdef CONFIG_PRINTK
111 #define PRINT(string) \
112 .set push; \
113 .set reorder; \
114 PTR_LA a0,8f; \
115 jal printk; \
116 .set pop; \
117 TEXT(string)
118 #else
119 #define PRINT(string)
120 #endif
122 #define TEXT(msg) \
123 .pushsection .data; \
124 8: .asciiz msg; \
125 .popsection;
127 /*
128 * Build text tables
129 */
130 #define TTABLE(string) \
131 .pushsection .text; \
132 .word 1f; \
133 .popsection \
134 .pushsection .data; \
135 1: .asciiz string; \
136 .popsection
138 /*
139 * MIPS IV pref instruction.
140 * Use with .set noreorder only!
141 *
142 * MIPS IV implementations are free to treat this as a nop. The R5000
143 * is one of them. So we should have an option not to use this instruction.
144 */
145 #ifdef CONFIG_CPU_HAS_PREFETCH
147 #define PREF(hint,addr) \
148 .set push; \
149 .set mips4; \
150 pref hint,addr; \
151 .set pop
153 #define PREFX(hint,addr) \
154 .set push; \
155 .set mips4; \
156 prefx hint,addr; \
157 .set pop
161 #define PREF(hint,addr)
162 #define PREFX(hint,addr)
166 /*
167 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
168 */
169 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
170 #define MOVN(rd,rs,rt) \
171 .set push; \
172 .set reorder; \
173 beqz rt,9f; \
174 move rd,rs; \
175 .set pop; \
176 9:
177 #define MOVZ(rd,rs,rt) \
178 .set push; \
179 .set reorder; \
180 bnez rt,9f; \
181 move rd,rs; \
182 .set pop; \
183 9:
185 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
186 #define MOVN(rd,rs,rt) \
187 .set push; \
188 .set noreorder; \
189 bnezl rt,9f; \
190 move rd,rs; \
191 .set pop; \
192 9:
193 #define MOVZ(rd,rs,rt) \
194 .set push; \
195 .set noreorder; \
196 beqzl rt,9f; \
197 move rd,rs; \
198 .set pop; \
199 9:
201 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
202 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
203 #define MOVN(rd,rs,rt) \
204 movn rd,rs,rt
205 #define MOVZ(rd,rs,rt) \
206 movz rd,rs,rt
209 /*
210 * Stack alignment
211 */
212 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
213 #define ALSZ 7
214 #define ALMASK ~7
215 #endif
216 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
217 #define ALSZ 15
218 #define ALMASK ~15
219 #endif
221 /*
222 * Macros to handle different pointer/register sizes for 32/64-bit code
223 */
225 /*
226 * Size of a register
227 */
228 #ifdef __mips64
229 #define SZREG 8
230 #else
231 #define SZREG 4
232 #endif
234 /*
235 * Use the following macros in assemblercode to load/store registers,
236 * pointers etc.
237 */
238 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
239 #define REG_S sw
240 #define REG_L lw
241 #define REG_SUBU subu
242 #define REG_ADDU addu
243 #endif
244 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
245 #define REG_S sd
246 #define REG_L ld
247 #define REG_SUBU dsubu
248 #define REG_ADDU daddu
249 #endif
251 /*
252 * How to add/sub/load/store/shift C int variables.
253 */
254 #if (_MIPS_SZINT == 32)
255 #define INT_ADD add
256 #define INT_ADDU addu
257 #define INT_ADDI addi
258 #define INT_ADDIU addiu
259 #define INT_SUB sub
260 #define INT_SUBU subu
261 #define INT_L lw
262 #define INT_S sw
263 #define INT_SLL sll
264 #define INT_SLLV sllv
265 #define INT_SRL srl
266 #define INT_SRLV srlv
267 #define INT_SRA sra
268 #define INT_SRAV srav
269 #endif
271 #if (_MIPS_SZINT == 64)
272 #define INT_ADD dadd
273 #define INT_ADDU daddu
274 #define INT_ADDI daddi
275 #define INT_ADDIU daddiu
276 #define INT_SUB dsub
277 #define INT_SUBU dsubu
278 #define INT_L ld
279 #define INT_S sd
280 #define INT_SLL dsll
281 #define INT_SLLV dsllv
282 #define INT_SRL dsrl
283 #define INT_SRLV dsrlv
284 #define INT_SRA dsra
285 #define INT_SRAV dsrav
286 #endif
288 /*
289 * How to add/sub/load/store/shift C long variables.
290 */
291 #if (_MIPS_SZLONG == 32)
292 #define LONG_ADD add
293 #define LONG_ADDU addu
294 #define LONG_ADDI addi
295 #define LONG_ADDIU addiu
296 #define LONG_SUB sub
297 #define LONG_SUBU subu
298 #define LONG_L lw
299 #define LONG_S sw
300 #define LONG_SLL sll
301 #define LONG_SLLV sllv
302 #define LONG_SRL srl
303 #define LONG_SRLV srlv
304 #define LONG_SRA sra
305 #define LONG_SRAV srav
307 #define LONG .word
308 #define LONGSIZE 4
309 #define LONGMASK 3
310 #define LONGLOG 2
311 #endif
313 #if (_MIPS_SZLONG == 64)
314 #define LONG_ADD dadd
315 #define LONG_ADDU daddu
316 #define LONG_ADDI daddi
317 #define LONG_ADDIU daddiu
318 #define LONG_SUB dsub
319 #define LONG_SUBU dsubu
320 #define LONG_L ld
321 #define LONG_S sd
322 #define LONG_SLL dsll
323 #define LONG_SLLV dsllv
324 #define LONG_SRL dsrl
325 #define LONG_SRLV dsrlv
326 #define LONG_SRA dsra
327 #define LONG_SRAV dsrav
329 #define LONG .dword
330 #define LONGSIZE 8
331 #define LONGMASK 7
332 #define LONGLOG 3
333 #endif
335 /*
336 * How to add/sub/load/store/shift pointers.
337 */
338 #if (_MIPS_SZPTR == 32)
339 #define PTR_ADD add
340 #define PTR_ADDU addu
341 #define PTR_ADDI addi
342 #define PTR_ADDIU addiu
343 #define PTR_SUB sub
344 #define PTR_SUBU subu
345 #define PTR_L lw
346 #define PTR_S sw
347 #define PTR_LA la
348 #define PTR_SLL sll
349 #define PTR_SLLV sllv
350 #define PTR_SRL srl
351 #define PTR_SRLV srlv
352 #define PTR_SRA sra
353 #define PTR_SRAV srav
355 #define PTR_SCALESHIFT 2
357 #define PTR .word
358 #define PTRSIZE 4
359 #define PTRLOG 2
360 #endif
362 #if (_MIPS_SZPTR == 64)
363 #define PTR_ADD dadd
364 #define PTR_ADDU daddu
365 #define PTR_ADDI daddi
366 #define PTR_ADDIU daddiu
367 #define PTR_SUB dsub
368 #define PTR_SUBU dsubu
369 #define PTR_L ld
370 #define PTR_S sd
371 #define PTR_LA dla
372 #define PTR_SLL dsll
373 #define PTR_SLLV dsllv
374 #define PTR_SRL dsrl
375 #define PTR_SRLV dsrlv
376 #define PTR_SRA dsra
377 #define PTR_SRAV dsrav
379 #define PTR_SCALESHIFT 3
381 #define PTR .dword
382 #define PTRSIZE 8
383 #define PTRLOG 3
384 #endif
386 /*
387 * Some cp0 registers were extended to 64bit for MIPS III.
388 */
389 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
390 #define MFC0 mfc0
391 #define MTC0 mtc0
392 #endif
393 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
394 #define MFC0 dmfc0
395 #define MTC0 dmtc0
396 #endif
398 #define SSNOP sll zero,zero,1