include/asm-sparc64/pgtable.h

   1 /* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
   2  * pgtable.h: SpitFire page table operations.
   3  *
   4  * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #ifndef _SPARC64_PGTABLE_H
   9 #define _SPARC64_PGTABLE_H
  10
  11 /* This file contains the functions and defines necessary to modify and use
  12  * the SpitFire page tables.
  13  */
  14
  15 #include <asm-generic/pgtable-nopud.h>
  16
  17 #include <linux/config.h>
  18 #include <linux/compiler.h>
  19 #include <asm/types.h>
  20 #include <asm/spitfire.h>
  21 #include <asm/asi.h>
  22 #include <asm/system.h>
  23 #include <asm/page.h>
  24 #include <asm/processor.h>
  25 #include <asm/const.h>
  26
  27 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
  28  * The page copy blockops can use 0x2000000 to 0x4000000.
  29  * The TSB is mapped in the 0x4000000 to 0x6000000 range.
  30  * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
  31  * The vmalloc area spans 0x100000000 to 0x200000000.
  32  * Since modules need to be in the lowest 32-bits of the address space,
  33  * we place them right before the OBP area from 0x10000000 to 0xf0000000.
  34  * There is a single static kernel PMD which maps from 0x0 to address
  35  * 0x400000000.
  36  */
  37 #define TLBTEMP_BASE            _AC(0x0000000002000000,UL)
  38 #define TSBMAP_BASE             _AC(0x0000000004000000,UL)
  39 #define MODULES_VADDR           _AC(0x0000000010000000,UL)
  40 #define MODULES_LEN             _AC(0x00000000e0000000,UL)
  41 #define MODULES_END             _AC(0x00000000f0000000,UL)
  42 #define LOW_OBP_ADDRESS         _AC(0x00000000f0000000,UL)
  43 #define HI_OBP_ADDRESS          _AC(0x0000000100000000,UL)
  44 #define VMALLOC_START           _AC(0x0000000100000000,UL)
  45 #define VMALLOC_END             _AC(0x0000000200000000,UL)
  46
  47 /* XXX All of this needs to be rethought so we can take advantage
  48  * XXX cheetah's full 64-bit virtual address space, ie. no more hole
  49  * XXX in the middle like on spitfire. -DaveM
  50  */
  51 /*
  52  * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
  53  * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
  54  * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
  55  * table is a single page long). The next higher PMD_BITS determine pmd#
  56  * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
  57  * since the pmd entries are 4 bytes, and each pmd page is a single page
  58  * long). Finally, the higher few bits determine pgde#.
  59  */
  60
  61 /* PMD_SHIFT determines the size of the area a second-level page
  62  * table can map
  63  */
  64 #define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-3))
  65 #define PMD_SIZE        (_AC(1,UL) << PMD_SHIFT)
  66 #define PMD_MASK        (~(PMD_SIZE-1))
  67 #define PMD_BITS        (PAGE_SHIFT - 2)
  68
  69 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  70 #define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
  71 #define PGDIR_SIZE      (_AC(1,UL) << PGDIR_SHIFT)
  72 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  73 #define PGDIR_BITS      (PAGE_SHIFT - 2)
  74
  75 #ifndef __ASSEMBLY__
  76
  77 #include <linux/sched.h>
  78
  79 /* Entries per page directory level. */
  80 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-3))
  81 #define PTRS_PER_PMD    (1UL << PMD_BITS)
  82 #define PTRS_PER_PGD    (1UL << PGDIR_BITS)
  83
  84 /* Kernel has a separate 44bit address space. */
  85 #define FIRST_USER_ADDRESS      0
  86
  87 #define pte_ERROR(e)    __builtin_trap()
  88 #define pmd_ERROR(e)    __builtin_trap()
  89 #define pgd_ERROR(e)    __builtin_trap()
  90
  91 #endif /* !(__ASSEMBLY__) */
  92
  93 /* PTE bits which are the same in SUN4U and SUN4V format.  */
  94 #define _PAGE_VALID       _AC(0x8000000000000000,UL) /* Valid TTE            */
  95 #define _PAGE_R           _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
  96
  97 /* SUN4U pte bits... */
  98 #define _PAGE_SZ4MB_4U    _AC(0x6000000000000000,UL) /* 4MB Page             */
  99 #define _PAGE_SZ512K_4U   _AC(0x4000000000000000,UL) /* 512K Page            */
 100 #define _PAGE_SZ64K_4U    _AC(0x2000000000000000,UL) /* 64K Page             */
 101 #define _PAGE_SZ8K_4U     _AC(0x0000000000000000,UL) /* 8K Page              */
 102 #define _PAGE_NFO_4U      _AC(0x1000000000000000,UL) /* No Fault Only        */
 103 #define _PAGE_IE_4U       _AC(0x0800000000000000,UL) /* Invert Endianness    */
 104 #define _PAGE_SOFT2_4U    _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
 105 #define _PAGE_RES1_4U     _AC(0x0002000000000000,UL) /* Reserved             */
 106 #define _PAGE_SZ32MB_4U   _AC(0x0001000000000000,UL) /* (Panther) 32MB page  */
 107 #define _PAGE_SZ256MB_4U  _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
 108 #define _PAGE_SN_4U       _AC(0x0000800000000000,UL) /* (Cheetah) Snoop      */
 109 #define _PAGE_RES2_4U     _AC(0x0000780000000000,UL) /* Reserved             */
 110 #define _PAGE_PADDR_4U    _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13]  */
 111 #define _PAGE_SOFT_4U     _AC(0x0000000000001F80,UL) /* Software bits:       */
 112 #define _PAGE_EXEC_4U     _AC(0x0000000000001000,UL) /* Executable SW bit    */
 113 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty)     */
 114 #define _PAGE_FILE_4U     _AC(0x0000000000000800,UL) /* Pagecache page       */
 115 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd)     */
 116 #define _PAGE_READ_4U     _AC(0x0000000000000200,UL) /* Readable SW Bit      */
 117 #define _PAGE_WRITE_4U    _AC(0x0000000000000100,UL) /* Writable SW Bit      */
 118 #define _PAGE_PRESENT_4U  _AC(0x0000000000000080,UL) /* Present              */
 119 #define _PAGE_L_4U        _AC(0x0000000000000040,UL) /* Locked TTE           */
 120 #define _PAGE_CP_4U       _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
 121 #define _PAGE_CV_4U       _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
 122 #define _PAGE_E_4U        _AC(0x0000000000000008,UL) /* side-Effect          */
 123 #define _PAGE_P_4U        _AC(0x0000000000000004,UL) /* Privileged Page      */
 124 #define _PAGE_W_4U        _AC(0x0000000000000002,UL) /* Writable             */
 125
 126 /* SUN4V pte bits... */
 127 #define _PAGE_NFO_4V      _AC(0x4000000000000000,UL) /* No Fault Only        */
 128 #define _PAGE_SOFT2_4V    _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
 129 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty)     */
 130 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd)     */
 131 #define _PAGE_READ_4V     _AC(0x0800000000000000,UL) /* Readable SW Bit      */
 132 #define _PAGE_WRITE_4V    _AC(0x0400000000000000,UL) /* Writable SW Bit      */
 133 #define _PAGE_PADDR_4V    _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13]         */
 134 #define _PAGE_IE_4V       _AC(0x0000000000001000,UL) /* Invert Endianness    */
 135 #define _PAGE_E_4V        _AC(0x0000000000000800,UL) /* side-Effect          */
 136 #define _PAGE_CP_4V       _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
 137 #define _PAGE_CV_4V       _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
 138 #define _PAGE_P_4V        _AC(0x0000000000000100,UL) /* Privileged Page      */
 139 #define _PAGE_EXEC_4V     _AC(0x0000000000000080,UL) /* Executable Page      */
 140 #define _PAGE_W_4V        _AC(0x0000000000000040,UL) /* Writable             */
 141 #define _PAGE_SOFT_4V     _AC(0x0000000000000030,UL) /* Software bits        */
 142 #define _PAGE_FILE_4V     _AC(0x0000000000000020,UL) /* Pagecache page       */
 143 #define _PAGE_PRESENT_4V  _AC(0x0000000000000010,UL) /* Present              */
 144 #define _PAGE_RESV_4V     _AC(0x0000000000000008,UL) /* Reserved             */
 145 #define _PAGE_SZ16GB_4V   _AC(0x0000000000000007,UL) /* 16GB Page            */
 146 #define _PAGE_SZ2GB_4V    _AC(0x0000000000000006,UL) /* 2GB Page             */
 147 #define _PAGE_SZ256MB_4V  _AC(0x0000000000000005,UL) /* 256MB Page           */
 148 #define _PAGE_SZ32MB_4V   _AC(0x0000000000000004,UL) /* 32MB Page            */
 149 #define _PAGE_SZ4MB_4V    _AC(0x0000000000000003,UL) /* 4MB Page             */
 150 #define _PAGE_SZ512K_4V   _AC(0x0000000000000002,UL) /* 512K Page            */
 151 #define _PAGE_SZ64K_4V    _AC(0x0000000000000001,UL) /* 64K Page             */
 152 #define _PAGE_SZ8K_4V     _AC(0x0000000000000000,UL) /* 8K Page              */
 153
 154 #if PAGE_SHIFT == 13
 155 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
 156 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
 157 #elif PAGE_SHIFT == 16
 158 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
 159 #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
 160 #elif PAGE_SHIFT == 19
 161 #define _PAGE_SZBITS_4U _PAGE_SZ512K_4U
 162 #define _PAGE_SZBITS_4V _PAGE_SZ512K_4V
 163 #elif PAGE_SHIFT == 22
 164 #define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U
 165 #define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V
 166 #else
 167 #error Wrong PAGE_SHIFT specified
 168 #endif
 169
 170 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
 171 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
 172 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
 173 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
 174 #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
 175 #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
 176 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 177 #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
 178 #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
 179 #endif
 180
 181 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
 182 #define __P000  __pgprot(0)
 183 #define __P001  __pgprot(0)
 184 #define __P010  __pgprot(0)
 185 #define __P011  __pgprot(0)
 186 #define __P100  __pgprot(0)
 187 #define __P101  __pgprot(0)
 188 #define __P110  __pgprot(0)
 189 #define __P111  __pgprot(0)
 190
 191 #define __S000  __pgprot(0)
 192 #define __S001  __pgprot(0)
 193 #define __S010  __pgprot(0)
 194 #define __S011  __pgprot(0)
 195 #define __S100  __pgprot(0)
 196 #define __S101  __pgprot(0)
 197 #define __S110  __pgprot(0)
 198 #define __S111  __pgprot(0)
 199
 200 #ifndef __ASSEMBLY__
 201
 202 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
 203
 204 extern unsigned long pte_sz_bits(unsigned long size);
 205
 206 extern pgprot_t PAGE_KERNEL;
 207 extern pgprot_t PAGE_KERNEL_LOCKED;
 208 extern pgprot_t PAGE_COPY;
 209 extern pgprot_t PAGE_SHARED;
 210
 211 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
 212 extern unsigned long _PAGE_IE;
 213 extern unsigned long _PAGE_E;
 214 extern unsigned long _PAGE_CACHE;
 215
 216 extern unsigned long pg_iobits;
 217 extern unsigned long _PAGE_ALL_SZ_BITS;
 218 extern unsigned long _PAGE_SZBITS;
 219
 220 extern struct page *mem_map_zero;
 221 #define ZERO_PAGE(vaddr)        (mem_map_zero)
 222
 223 /* PFNs are real physical page numbers.  However, mem_map only begins to record
 224  * per-page information starting at pfn_base.  This is to handle systems where
 225  * the first physical page in the machine is at some huge physical address,
 226  * such as 4GB.   This is common on a partitioned E10000, for example.
 227  */
 228 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 229 {
 230         unsigned long paddr = pfn << PAGE_SHIFT;
 231         unsigned long sz_bits;
 232
 233         sz_bits = 0UL;
 234         if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
 235                 __asm__ __volatile__(
 236                 "\n661: sethi           %uhi(%1), %0\n"
 237                 "       sllx            %0, 32, %0\n"
 238                 "       .section        .sun4v_2insn_patch, \"ax\"\n"
 239                 "       .word           661b\n"
 240                 "       mov             %2, %0\n"
 241                 "       nop\n"
 242                 "       .previous\n"
 243                 : "=r" (sz_bits)
 244                 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
 245         }
 246         return __pte(paddr | sz_bits | pgprot_val(prot));
 247 }
 248 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 249
 250 /* This one can be done with two shifts.  */
 251 static inline unsigned long pte_pfn(pte_t pte)
 252 {
 253         unsigned long ret;
 254
 255         __asm__ __volatile__(
 256         "\n661: sllx            %1, %2, %0\n"
 257         "       srlx            %0, %3, %0\n"
 258         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 259         "       .word           661b\n"
 260         "       sllx            %1, %4, %0\n"
 261         "       srlx            %0, %5, %0\n"
 262         "       .previous\n"
 263         : "=r" (ret)
 264         : "r" (pte_val(pte)),
 265           "i" (21), "i" (21 + PAGE_SHIFT),
 266           "i" (8), "i" (8 + PAGE_SHIFT));
 267
 268         return ret;
 269 }
 270 #define pte_page(x) pfn_to_page(pte_pfn(x))
 271
 272 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
 273 {
 274         unsigned long mask, tmp;
 275
 276         /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
 277          * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
 278          *
 279          * Even if we use negation tricks the result is still a 6
 280          * instruction sequence, so don't try to play fancy and just
 281          * do the most straightforward implementation.
 282          *
 283          * Note: We encode this into 3 sun4v 2-insn patch sequences.
 284          */
 285
 286         __asm__ __volatile__(
 287         "\n661: sethi           %%uhi(%2), %1\n"
 288         "       sethi           %%hi(%2), %0\n"
 289         "\n662: or              %1, %%ulo(%2), %1\n"
 290         "       or              %0, %%lo(%2), %0\n"
 291         "\n663: sllx            %1, 32, %1\n"
 292         "       or              %0, %1, %0\n"
 293         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 294         "       .word           661b\n"
 295         "       sethi           %%uhi(%3), %1\n"
 296         "       sethi           %%hi(%3), %0\n"
 297         "       .word           662b\n"
 298         "       or              %1, %%ulo(%3), %1\n"
 299         "       or              %0, %%lo(%3), %0\n"
 300         "       .word           663b\n"
 301         "       sllx            %1, 32, %1\n"
 302         "       or              %0, %1, %0\n"
 303         "       .previous\n"
 304         : "=r" (mask), "=r" (tmp)
 305         : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
 306                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
 307                _PAGE_SZBITS_4U),
 308           "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
 309                _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
 310                _PAGE_SZBITS_4V));
 311
 312         return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
 313 }
 314
 315 static inline pte_t pgoff_to_pte(unsigned long off)
 316 {
 317         off <<= PAGE_SHIFT;
 318
 319         __asm__ __volatile__(
 320         "\n661: or              %0, %2, %0\n"
 321         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 322         "       .word           661b\n"
 323         "       or              %0, %3, %0\n"
 324         "       .previous\n"
 325         : "=r" (off)
 326         : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 327
 328         return __pte(off);
 329 }
 330
 331 static inline pgprot_t pgprot_noncached(pgprot_t prot)
 332 {
 333         unsigned long val = pgprot_val(prot);
 334
 335         __asm__ __volatile__(
 336         "\n661: andn            %0, %2, %0\n"
 337         "       or              %0, %3, %0\n"
 338         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 339         "       .word           661b\n"
 340         "       andn            %0, %4, %0\n"
 341         "       or              %0, %3, %0\n"
 342         "       .previous\n"
 343         : "=r" (val)
 344         : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
 345                      "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
 346
 347         return __pgprot(val);
 348 }
 349 /* Various pieces of code check for platform support by ifdef testing
 350  * on "pgprot_noncached".  That's broken and should be fixed, but for
 351  * now...
 352  */
 353 #define pgprot_noncached pgprot_noncached
 354
 355 #ifdef CONFIG_HUGETLB_PAGE
 356 static inline pte_t pte_mkhuge(pte_t pte)
 357 {
 358         unsigned long mask;
 359
 360         __asm__ __volatile__(
 361         "\n661: sethi           %%uhi(%1), %0\n"
 362         "       sllx            %0, 32, %0\n"
 363         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 364         "       .word           661b\n"
 365         "       mov             %2, %0\n"
 366         "       nop\n"
 367         "       .previous\n"
 368         : "=r" (mask)
 369         : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
 370
 371         return __pte(pte_val(pte) | mask);
 372 }
 373 #endif
 374
 375 static inline pte_t pte_mkdirty(pte_t pte)
 376 {
 377         unsigned long val = pte_val(pte), tmp;
 378
 379         __asm__ __volatile__(
 380         "\n661: or              %0, %3, %0\n"
 381         "       nop\n"
 382         "\n662: nop\n"
 383         "       nop\n"
 384         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 385         "       .word           661b\n"
 386         "       sethi           %%uhi(%4), %1\n"
 387         "       sllx            %1, 32, %1\n"
 388         "       .word           662b\n"
 389         "       or              %1, %%lo(%4), %1\n"
 390         "       or              %0, %1, %0\n"
 391         "       .previous\n"
 392         : "=r" (val), "=r" (tmp)
 393         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 394           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 395
 396         return __pte(val);
 397 }
 398
 399 static inline pte_t pte_mkclean(pte_t pte)
 400 {
 401         unsigned long val = pte_val(pte), tmp;
 402
 403         __asm__ __volatile__(
 404         "\n661: andn            %0, %3, %0\n"
 405         "       nop\n"
 406         "\n662: nop\n"
 407         "       nop\n"
 408         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 409         "       .word           661b\n"
 410         "       sethi           %%uhi(%4), %1\n"
 411         "       sllx            %1, 32, %1\n"
 412         "       .word           662b\n"
 413         "       or              %1, %%lo(%4), %1\n"
 414         "       andn            %0, %1, %0\n"
 415         "       .previous\n"
 416         : "=r" (val), "=r" (tmp)
 417         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 418           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 419
 420         return __pte(val);
 421 }
 422
 423 static inline pte_t pte_mkwrite(pte_t pte)
 424 {
 425         unsigned long val = pte_val(pte), mask;
 426
 427         __asm__ __volatile__(
 428         "\n661: mov             %1, %0\n"
 429         "       nop\n"
 430         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 431         "       .word           661b\n"
 432         "       sethi           %%uhi(%2), %0\n"
 433         "       sllx            %0, 32, %0\n"
 434         "       .previous\n"
 435         : "=r" (mask)
 436         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 437
 438         return __pte(val | mask);
 439 }
 440
 441 static inline pte_t pte_wrprotect(pte_t pte)
 442 {
 443         unsigned long val = pte_val(pte), tmp;
 444
 445         __asm__ __volatile__(
 446         "\n661: andn            %0, %3, %0\n"
 447         "       nop\n"
 448         "\n662: nop\n"
 449         "       nop\n"
 450         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 451         "       .word           661b\n"
 452         "       sethi           %%uhi(%4), %1\n"
 453         "       sllx            %1, 32, %1\n"
 454         "       .word           662b\n"
 455         "       or              %1, %%lo(%4), %1\n"
 456         "       andn            %0, %1, %0\n"
 457         "       .previous\n"
 458         : "=r" (val), "=r" (tmp)
 459         : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
 460           "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
 461
 462         return __pte(val);
 463 }
 464
 465 static inline pte_t pte_mkold(pte_t pte)
 466 {
 467         unsigned long mask;
 468
 469         __asm__ __volatile__(
 470         "\n661: mov             %1, %0\n"
 471         "       nop\n"
 472         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 473         "       .word           661b\n"
 474         "       sethi           %%uhi(%2), %0\n"
 475         "       sllx            %0, 32, %0\n"
 476         "       .previous\n"
 477         : "=r" (mask)
 478         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 479
 480         mask |= _PAGE_R;
 481
 482         return __pte(pte_val(pte) & ~mask);
 483 }
 484
 485 static inline pte_t pte_mkyoung(pte_t pte)
 486 {
 487         unsigned long mask;
 488
 489         __asm__ __volatile__(
 490         "\n661: mov             %1, %0\n"
 491         "       nop\n"
 492         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 493         "       .word           661b\n"
 494         "       sethi           %%uhi(%2), %0\n"
 495         "       sllx            %0, 32, %0\n"
 496         "       .previous\n"
 497         : "=r" (mask)
 498         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 499
 500         mask |= _PAGE_R;
 501
 502         return __pte(pte_val(pte) | mask);
 503 }
 504
 505 static inline unsigned long pte_young(pte_t pte)
 506 {
 507         unsigned long mask;
 508
 509         __asm__ __volatile__(
 510         "\n661: mov             %1, %0\n"
 511         "       nop\n"
 512         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 513         "       .word           661b\n"
 514         "       sethi           %%uhi(%2), %0\n"
 515         "       sllx            %0, 32, %0\n"
 516         "       .previous\n"
 517         : "=r" (mask)
 518         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 519
 520         return (pte_val(pte) & mask);
 521 }
 522
 523 static inline unsigned long pte_dirty(pte_t pte)
 524 {
 525         unsigned long mask;
 526
 527         __asm__ __volatile__(
 528         "\n661: mov             %1, %0\n"
 529         "       nop\n"
 530         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 531         "       .word           661b\n"
 532         "       sethi           %%uhi(%2), %0\n"
 533         "       sllx            %0, 32, %0\n"
 534         "       .previous\n"
 535         : "=r" (mask)
 536         : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
 537
 538         return (pte_val(pte) & mask);
 539 }
 540
 541 static inline unsigned long pte_write(pte_t pte)
 542 {
 543         unsigned long mask;
 544
 545         __asm__ __volatile__(
 546         "\n661: mov             %1, %0\n"
 547         "       nop\n"
 548         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 549         "       .word           661b\n"
 550         "       sethi           %%uhi(%2), %0\n"
 551         "       sllx            %0, 32, %0\n"
 552         "       .previous\n"
 553         : "=r" (mask)
 554         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 555
 556         return (pte_val(pte) & mask);
 557 }
 558
 559 static inline unsigned long pte_exec(pte_t pte)
 560 {
 561         unsigned long mask;
 562
 563         __asm__ __volatile__(
 564         "\n661: sethi           %%hi(%1), %0\n"
 565         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 566         "       .word           661b\n"
 567         "       mov             %2, %0\n"
 568         "       .previous\n"
 569         : "=r" (mask)
 570         : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
 571
 572         return (pte_val(pte) & mask);
 573 }
 574
 575 static inline unsigned long pte_read(pte_t pte)
 576 {
 577         unsigned long mask;
 578
 579         __asm__ __volatile__(
 580         "\n661: mov             %1, %0\n"
 581         "       nop\n"
 582         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 583         "       .word           661b\n"
 584         "       sethi           %%uhi(%2), %0\n"
 585         "       sllx            %0, 32, %0\n"
 586         "       .previous\n"
 587         : "=r" (mask)
 588         : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V));
 589
 590         return (pte_val(pte) & mask);
 591 }
 592
 593 static inline unsigned long pte_file(pte_t pte)
 594 {
 595         unsigned long val = pte_val(pte);
 596
 597         __asm__ __volatile__(
 598         "\n661: and             %0, %2, %0\n"
 599         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 600         "       .word           661b\n"
 601         "       and             %0, %3, %0\n"
 602         "       .previous\n"
 603         : "=r" (val)
 604         : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 605
 606         return val;
 607 }
 608
 609 static inline unsigned long pte_present(pte_t pte)
 610 {
 611         unsigned long val = pte_val(pte);
 612
 613         __asm__ __volatile__(
 614         "\n661: and             %0, %2, %0\n"
 615         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 616         "       .word           661b\n"
 617         "       and             %0, %3, %0\n"
 618         "       .previous\n"
 619         : "=r" (val)
 620         : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
 621
 622         return val;
 623 }
 624
 625 #define pmd_set(pmdp, ptep)     \
 626         (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
 627 #define pud_set(pudp, pmdp)     \
 628         (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
 629 #define __pmd_page(pmd)         \
 630         ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
 631 #define pmd_page(pmd)                   virt_to_page((void *)__pmd_page(pmd))
 632 #define pud_page(pud)           \
 633         ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
 634 #define pmd_none(pmd)                   (!pmd_val(pmd))
 635 #define pmd_bad(pmd)                    (0)
 636 #define pmd_present(pmd)                (pmd_val(pmd) != 0U)
 637 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0U)
 638 #define pud_none(pud)                   (!pud_val(pud))
 639 #define pud_bad(pud)                    (0)
 640 #define pud_present(pud)                (pud_val(pud) != 0U)
 641 #define pud_clear(pudp)                 (pud_val(*(pudp)) = 0U)
 642
 643 /* Same in both SUN4V and SUN4U.  */
 644 #define pte_none(pte)                   (!pte_val(pte))
 645
 646 /* to find an entry in a page-table-directory. */
 647 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 648 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 649
 650 /* to find an entry in a kernel page-table-directory */
 651 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 652
 653 /* Find an entry in the second-level page table.. */
 654 #define pmd_offset(pudp, address)       \
 655         ((pmd_t *) pud_page(*(pudp)) + \
 656          (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
 657
 658 /* Find an entry in the third-level page table.. */
 659 #define pte_index(dir, address) \
 660         ((pte_t *) __pmd_page(*(dir)) + \
 661          ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 662 #define pte_offset_kernel               pte_index
 663 #define pte_offset_map                  pte_index
 664 #define pte_offset_map_nested           pte_index
 665 #define pte_unmap(pte)                  do { } while (0)
 666 #define pte_unmap_nested(pte)           do { } while (0)
 667
 668 /* Actual page table PTE updates.  */
 669 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
 670
 671 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
 672 {
 673         pte_t orig = *ptep;
 674
 675         *ptep = pte;
 676
 677         /* It is more efficient to let flush_tlb_kernel_range()
 678          * handle init_mm tlb flushes.
 679          *
 680          * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
 681          *             and SUN4V pte layout, so this inline test is fine.
 682          */
 683         if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
 684                 tlb_batch_add(mm, addr, ptep, orig);
 685 }
 686
 687 #define pte_clear(mm,addr,ptep)         \
 688         set_pte_at((mm), (addr), (ptep), __pte(0UL))
 689
 690 extern pgd_t swapper_pg_dir[2048];
 691 extern pmd_t swapper_low_pmd_dir[2048];
 692
 693 extern void paging_init(void);
 694 extern unsigned long find_ecache_flush_span(unsigned long size);
 695
 696 /* These do nothing with the way I have things setup. */
 697 #define mmu_lockarea(vaddr, len)                (vaddr)
 698 #define mmu_unlockarea(vaddr, len)              do { } while(0)
 699
 700 struct vm_area_struct;
 701 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 702
 703 /* Encode and de-code a swap entry */
 704 #define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
 705 #define __swp_offset(entry)     ((entry).val >> (PAGE_SHIFT + 8UL))
 706 #define __swp_entry(type, offset)       \
 707         ( (swp_entry_t) \
 708           { \
 709                 (((long)(type) << PAGE_SHIFT) | \
 710                  ((long)(offset) << (PAGE_SHIFT + 8UL))) \
 711           } )
 712 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 713 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 714
 715 /* File offset in PTE support. */
 716 extern unsigned long pte_file(pte_t);
 717 #define pte_to_pgoff(pte)       (pte_val(pte) >> PAGE_SHIFT)
 718 extern pte_t pgoff_to_pte(unsigned long);
 719 #define PTE_FILE_MAX_BITS       (64UL - PAGE_SHIFT - 1UL)
 720
 721 extern unsigned long prom_virt_to_phys(unsigned long, int *);
 722
 723 extern unsigned long sun4u_get_pte(unsigned long);
 724
 725 static inline unsigned long __get_phys(unsigned long addr)
 726 {
 727         return sun4u_get_pte(addr);
 728 }
 729
 730 static inline int __get_iospace(unsigned long addr)
 731 {
 732         return ((sun4u_get_pte(addr) & 0xf0000000) >> 28);
 733 }
 734
 735 extern unsigned long *sparc64_valid_addr_bitmap;
 736
 737 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 738 #define kern_addr_valid(addr)   \
 739         (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
 740
 741 extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
 742                                unsigned long pfn,
 743                                unsigned long size, pgprot_t prot);
 744
 745 /*
 746  * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 747  * its high 4 bits.  These macros/functions put it there or get it from there.
 748  */
 749 #define MK_IOSPACE_PFN(space, pfn)      (pfn | (space << (BITS_PER_LONG - 4)))
 750 #define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
 751 #define GET_PFN(pfn)                    (pfn & 0x0fffffffffffffffUL)
 752
 753 #include <asm-generic/pgtable.h>
 754
 755 /* We provide our own get_unmapped_area to cope with VA holes and
 756  * SHM area cache aliasing for userland.
 757  */
 758 #define HAVE_ARCH_UNMAPPED_AREA
 759 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 760
 761 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
 762  * the largest alignment possible such that larget PTEs can be used.
 763  */
 764 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
 765                                           unsigned long, unsigned long,
 766                                           unsigned long);
 767 #define HAVE_ARCH_FB_UNMAPPED_AREA
 768
 769 extern void pgtable_cache_init(void);
 770 extern void sun4v_register_fault_status(void);
 771 extern void sun4v_ktsb_register(void);
 772
 773 #endif /* !(__ASSEMBLY__) */
 774
 775 #endif /* !(_SPARC64_PGTABLE_H) */