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[NETFILTER]: nf_conntrack: export hash allocation/destruction functions
[linux-2.6/verdex.git] / drivers / atm / idt77252.c
blob3800bc0cb2efe8d9016f54fd19e007096cda1842
1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
3 *
4 * $Author: ecd $
5 * $Date: 2001/11/11 08:13:54 $
6 *
7 * Copyright (c) 2000 ATecoM GmbH
8 *
9 * The author may be reached at ecd@atecom.com.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
34
35
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <linux/jiffies.h>
50 #include <linux/mutex.h>
51
52 #include <asm/io.h>
53 #include <asm/uaccess.h>
54 #include <asm/atomic.h>
55 #include <asm/byteorder.h>
56
57 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
58 #include "suni.h"
59 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
60
61
62 #include "idt77252.h"
63 #include "idt77252_tables.h"
64
65 static unsigned int vpibits = 1;
66
67
68 #define CONFIG_ATM_IDT77252_SEND_IDLE 1
69
70
71 /*
72 * Debug HACKs.
73 */
74 #define DEBUG_MODULE 1
75 #undef HAVE_EEPROM /* does not work, yet. */
76
77 #ifdef CONFIG_ATM_IDT77252_DEBUG
78 static unsigned long debug = DBG_GENERAL;
79 #endif
80
81
82 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
83
84
85 /*
86 * SCQ Handling.
87 */
88 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
89 static void free_scq(struct idt77252_dev *, struct scq_info *);
90 static int queue_skb(struct idt77252_dev *, struct vc_map *,
91 struct sk_buff *, int oam);
92 static void drain_scq(struct idt77252_dev *, struct vc_map *);
93 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
94 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
95
96 /*
97 * FBQ Handling.
98 */
99 static int push_rx_skb(struct idt77252_dev *,
100 struct sk_buff *, int queue);
101 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
102 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
103 static void recycle_rx_pool_skb(struct idt77252_dev *,
104 struct rx_pool *);
105 static void add_rx_skb(struct idt77252_dev *, int queue,
106 unsigned int size, unsigned int count);
107
108 /*
109 * RSQ Handling.
110 */
111 static int init_rsq(struct idt77252_dev *);
112 static void deinit_rsq(struct idt77252_dev *);
113 static void idt77252_rx(struct idt77252_dev *);
114
115 /*
116 * TSQ handling.
117 */
118 static int init_tsq(struct idt77252_dev *);
119 static void deinit_tsq(struct idt77252_dev *);
120 static void idt77252_tx(struct idt77252_dev *);
121
122
123 /*
124 * ATM Interface.
125 */
126 static void idt77252_dev_close(struct atm_dev *dev);
127 static int idt77252_open(struct atm_vcc *vcc);
128 static void idt77252_close(struct atm_vcc *vcc);
129 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
130 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
131 int flags);
132 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
133 unsigned long addr);
134 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
135 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
136 int flags);
137 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
138 char *page);
139 static void idt77252_softint(struct work_struct *work);
140
141
142 static struct atmdev_ops idt77252_ops =
143 {
144 .dev_close = idt77252_dev_close,
145 .open = idt77252_open,
146 .close = idt77252_close,
147 .send = idt77252_send,
148 .send_oam = idt77252_send_oam,
149 .phy_put = idt77252_phy_put,
150 .phy_get = idt77252_phy_get,
151 .change_qos = idt77252_change_qos,
152 .proc_read = idt77252_proc_read,
153 .owner = THIS_MODULE
154 };
155
156 static struct idt77252_dev *idt77252_chain = NULL;
157 static unsigned int idt77252_sram_write_errors = 0;
158
159 /*****************************************************************************/
160 /* */
161 /* I/O and Utility Bus */
162 /* */
163 /*****************************************************************************/
164
165 static void
166 waitfor_idle(struct idt77252_dev *card)
167 {
168 u32 stat;
169
170 stat = readl(SAR_REG_STAT);
171 while (stat & SAR_STAT_CMDBZ)
172 stat = readl(SAR_REG_STAT);
173 }
174
175 static u32
176 read_sram(struct idt77252_dev *card, unsigned long addr)
177 {
178 unsigned long flags;
179 u32 value;
180
181 spin_lock_irqsave(&card->cmd_lock, flags);
182 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
183 waitfor_idle(card);
184 value = readl(SAR_REG_DR0);
185 spin_unlock_irqrestore(&card->cmd_lock, flags);
186 return value;
187 }
188
189 static void
190 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
191 {
192 unsigned long flags;
193
194 if ((idt77252_sram_write_errors == 0) &&
195 (((addr > card->tst[0] + card->tst_size - 2) &&
196 (addr < card->tst[0] + card->tst_size)) ||
197 ((addr > card->tst[1] + card->tst_size - 2) &&
198 (addr < card->tst[1] + card->tst_size)))) {
199 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
200 card->name, addr, value);
201 }
202
203 spin_lock_irqsave(&card->cmd_lock, flags);
204 writel(value, SAR_REG_DR0);
205 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
206 waitfor_idle(card);
207 spin_unlock_irqrestore(&card->cmd_lock, flags);
208 }
209
210 static u8
211 read_utility(void *dev, unsigned long ubus_addr)
212 {
213 struct idt77252_dev *card = dev;
214 unsigned long flags;
215 u8 value;
216
217 if (!card) {
218 printk("Error: No such device.\n");
219 return -1;
220 }
221
222 spin_lock_irqsave(&card->cmd_lock, flags);
223 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
224 waitfor_idle(card);
225 value = readl(SAR_REG_DR0);
226 spin_unlock_irqrestore(&card->cmd_lock, flags);
227 return value;
228 }
229
230 static void
231 write_utility(void *dev, unsigned long ubus_addr, u8 value)
232 {
233 struct idt77252_dev *card = dev;
234 unsigned long flags;
235
236 if (!card) {
237 printk("Error: No such device.\n");
238 return;
239 }
240
241 spin_lock_irqsave(&card->cmd_lock, flags);
242 writel((u32) value, SAR_REG_DR0);
243 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
244 waitfor_idle(card);
245 spin_unlock_irqrestore(&card->cmd_lock, flags);
246 }
247
248 #ifdef HAVE_EEPROM
249 static u32 rdsrtab[] =
250 {
251 SAR_GP_EECS | SAR_GP_EESCLK,
252 0,
253 SAR_GP_EESCLK, /* 0 */
254 0,
255 SAR_GP_EESCLK, /* 0 */
256 0,
257 SAR_GP_EESCLK, /* 0 */
258 0,
259 SAR_GP_EESCLK, /* 0 */
260 0,
261 SAR_GP_EESCLK, /* 0 */
262 SAR_GP_EEDO,
263 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
264 0,
265 SAR_GP_EESCLK, /* 0 */
266 SAR_GP_EEDO,
267 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
268 };
269
270 static u32 wrentab[] =
271 {
272 SAR_GP_EECS | SAR_GP_EESCLK,
273 0,
274 SAR_GP_EESCLK, /* 0 */
275 0,
276 SAR_GP_EESCLK, /* 0 */
277 0,
278 SAR_GP_EESCLK, /* 0 */
279 0,
280 SAR_GP_EESCLK, /* 0 */
281 SAR_GP_EEDO,
282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
283 SAR_GP_EEDO,
284 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
285 0,
286 SAR_GP_EESCLK, /* 0 */
287 0,
288 SAR_GP_EESCLK /* 0 */
289 };
290
291 static u32 rdtab[] =
292 {
293 SAR_GP_EECS | SAR_GP_EESCLK,
294 0,
295 SAR_GP_EESCLK, /* 0 */
296 0,
297 SAR_GP_EESCLK, /* 0 */
298 0,
299 SAR_GP_EESCLK, /* 0 */
300 0,
301 SAR_GP_EESCLK, /* 0 */
302 0,
303 SAR_GP_EESCLK, /* 0 */
304 0,
305 SAR_GP_EESCLK, /* 0 */
306 SAR_GP_EEDO,
307 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
308 SAR_GP_EEDO,
309 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
310 };
311
312 static u32 wrtab[] =
313 {
314 SAR_GP_EECS | SAR_GP_EESCLK,
315 0,
316 SAR_GP_EESCLK, /* 0 */
317 0,
318 SAR_GP_EESCLK, /* 0 */
319 0,
320 SAR_GP_EESCLK, /* 0 */
321 0,
322 SAR_GP_EESCLK, /* 0 */
323 0,
324 SAR_GP_EESCLK, /* 0 */
325 0,
326 SAR_GP_EESCLK, /* 0 */
327 SAR_GP_EEDO,
328 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
329 0,
330 SAR_GP_EESCLK /* 0 */
331 };
332
333 static u32 clktab[] =
334 {
335 0,
336 SAR_GP_EESCLK,
337 0,
338 SAR_GP_EESCLK,
339 0,
340 SAR_GP_EESCLK,
341 0,
342 SAR_GP_EESCLK,
343 0,
344 SAR_GP_EESCLK,
345 0,
346 SAR_GP_EESCLK,
347 0,
348 SAR_GP_EESCLK,
349 0,
350 SAR_GP_EESCLK,
351 0
352 };
353
354 static u32
355 idt77252_read_gp(struct idt77252_dev *card)
356 {
357 u32 gp;
358
359 gp = readl(SAR_REG_GP);
360 #if 0
361 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
362 #endif
363 return gp;
364 }
365
366 static void
367 idt77252_write_gp(struct idt77252_dev *card, u32 value)
368 {
369 unsigned long flags;
370
371 #if 0
372 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
373 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
374 value & SAR_GP_EEDO ? "1" : "0");
375 #endif
376
377 spin_lock_irqsave(&card->cmd_lock, flags);
378 waitfor_idle(card);
379 writel(value, SAR_REG_GP);
380 spin_unlock_irqrestore(&card->cmd_lock, flags);
381 }
382
383 static u8
384 idt77252_eeprom_read_status(struct idt77252_dev *card)
385 {
386 u8 byte;
387 u32 gp;
388 int i, j;
389
390 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
391
392 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
393 idt77252_write_gp(card, gp | rdsrtab[i]);
394 udelay(5);
395 }
396 idt77252_write_gp(card, gp | SAR_GP_EECS);
397 udelay(5);
398
399 byte = 0;
400 for (i = 0, j = 0; i < 8; i++) {
401 byte <<= 1;
402
403 idt77252_write_gp(card, gp | clktab[j++]);
404 udelay(5);
405
406 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
407
408 idt77252_write_gp(card, gp | clktab[j++]);
409 udelay(5);
410 }
411 idt77252_write_gp(card, gp | SAR_GP_EECS);
412 udelay(5);
413
414 return byte;
415 }
416
417 static u8
418 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
419 {
420 u8 byte;
421 u32 gp;
422 int i, j;
423
424 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
425
426 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
427 idt77252_write_gp(card, gp | rdtab[i]);
428 udelay(5);
429 }
430 idt77252_write_gp(card, gp | SAR_GP_EECS);
431 udelay(5);
432
433 for (i = 0, j = 0; i < 8; i++) {
434 idt77252_write_gp(card, gp | clktab[j++] |
435 (offset & 1 ? SAR_GP_EEDO : 0));
436 udelay(5);
437
438 idt77252_write_gp(card, gp | clktab[j++] |
439 (offset & 1 ? SAR_GP_EEDO : 0));
440 udelay(5);
441
442 offset >>= 1;
443 }
444 idt77252_write_gp(card, gp | SAR_GP_EECS);
445 udelay(5);
446
447 byte = 0;
448 for (i = 0, j = 0; i < 8; i++) {
449 byte <<= 1;
450
451 idt77252_write_gp(card, gp | clktab[j++]);
452 udelay(5);
453
454 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
455
456 idt77252_write_gp(card, gp | clktab[j++]);
457 udelay(5);
458 }
459 idt77252_write_gp(card, gp | SAR_GP_EECS);
460 udelay(5);
461
462 return byte;
463 }
464
465 static void
466 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
467 {
468 u32 gp;
469 int i, j;
470
471 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
472
473 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
474 idt77252_write_gp(card, gp | wrentab[i]);
475 udelay(5);
476 }
477 idt77252_write_gp(card, gp | SAR_GP_EECS);
478 udelay(5);
479
480 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
481 idt77252_write_gp(card, gp | wrtab[i]);
482 udelay(5);
483 }
484 idt77252_write_gp(card, gp | SAR_GP_EECS);
485 udelay(5);
486
487 for (i = 0, j = 0; i < 8; i++) {
488 idt77252_write_gp(card, gp | clktab[j++] |
489 (offset & 1 ? SAR_GP_EEDO : 0));
490 udelay(5);
491
492 idt77252_write_gp(card, gp | clktab[j++] |
493 (offset & 1 ? SAR_GP_EEDO : 0));
494 udelay(5);
495
496 offset >>= 1;
497 }
498 idt77252_write_gp(card, gp | SAR_GP_EECS);
499 udelay(5);
500
501 for (i = 0, j = 0; i < 8; i++) {
502 idt77252_write_gp(card, gp | clktab[j++] |
503 (data & 1 ? SAR_GP_EEDO : 0));
504 udelay(5);
505
506 idt77252_write_gp(card, gp | clktab[j++] |
507 (data & 1 ? SAR_GP_EEDO : 0));
508 udelay(5);
509
510 data >>= 1;
511 }
512 idt77252_write_gp(card, gp | SAR_GP_EECS);
513 udelay(5);
514 }
515
516 static void
517 idt77252_eeprom_init(struct idt77252_dev *card)
518 {
519 u32 gp;
520
521 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
522
523 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
524 udelay(5);
525 idt77252_write_gp(card, gp | SAR_GP_EECS);
526 udelay(5);
527 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
528 udelay(5);
529 idt77252_write_gp(card, gp | SAR_GP_EECS);
530 udelay(5);
531 }
532 #endif /* HAVE_EEPROM */
533
534
535 #ifdef CONFIG_ATM_IDT77252_DEBUG
536 static void
537 dump_tct(struct idt77252_dev *card, int index)
538 {
539 unsigned long tct;
540 int i;
541
542 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
543
544 printk("%s: TCT %x:", card->name, index);
545 for (i = 0; i < 8; i++) {
546 printk(" %08x", read_sram(card, tct + i));
547 }
548 printk("\n");
549 }
550
551 static void
552 idt77252_tx_dump(struct idt77252_dev *card)
553 {
554 struct atm_vcc *vcc;
555 struct vc_map *vc;
556 int i;
557
558 printk("%s\n", __FUNCTION__);
559 for (i = 0; i < card->tct_size; i++) {
560 vc = card->vcs[i];
561 if (!vc)
562 continue;
563
564 vcc = NULL;
565 if (vc->rx_vcc)
566 vcc = vc->rx_vcc;
567 else if (vc->tx_vcc)
568 vcc = vc->tx_vcc;
569
570 if (!vcc)
571 continue;
572
573 printk("%s: Connection %d:\n", card->name, vc->index);
574 dump_tct(card, vc->index);
575 }
576 }
577 #endif
578
579
580 /*****************************************************************************/
581 /* */
582 /* SCQ Handling */
583 /* */
584 /*****************************************************************************/
585
586 static int
587 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
588 {
589 struct sb_pool *pool = &card->sbpool[queue];
590 int index;
591
592 index = pool->index;
593 while (pool->skb[index]) {
594 index = (index + 1) & FBQ_MASK;
595 if (index == pool->index)
596 return -ENOBUFS;
597 }
598
599 pool->skb[index] = skb;
600 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
601
602 pool->index = (index + 1) & FBQ_MASK;
603 return 0;
604 }
605
606 static void
607 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
608 {
609 unsigned int queue, index;
610 u32 handle;
611
612 handle = IDT77252_PRV_POOL(skb);
613
614 queue = POOL_QUEUE(handle);
615 if (queue > 3)
616 return;
617
618 index = POOL_INDEX(handle);
619 if (index > FBQ_SIZE - 1)
620 return;
621
622 card->sbpool[queue].skb[index] = NULL;
623 }
624
625 static struct sk_buff *
626 sb_pool_skb(struct idt77252_dev *card, u32 handle)
627 {
628 unsigned int queue, index;
629
630 queue = POOL_QUEUE(handle);
631 if (queue > 3)
632 return NULL;
633
634 index = POOL_INDEX(handle);
635 if (index > FBQ_SIZE - 1)
636 return NULL;
637
638 return card->sbpool[queue].skb[index];
639 }
640
641 static struct scq_info *
642 alloc_scq(struct idt77252_dev *card, int class)
643 {
644 struct scq_info *scq;
645
646 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
647 if (!scq)
648 return NULL;
649 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
650 &scq->paddr);
651 if (scq->base == NULL) {
652 kfree(scq);
653 return NULL;
654 }
655 memset(scq->base, 0, SCQ_SIZE);
656
657 scq->next = scq->base;
658 scq->last = scq->base + (SCQ_ENTRIES - 1);
659 atomic_set(&scq->used, 0);
660
661 spin_lock_init(&scq->lock);
662 spin_lock_init(&scq->skblock);
663
664 skb_queue_head_init(&scq->transmit);
665 skb_queue_head_init(&scq->pending);
666
667 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
668 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
669
670 return scq;
671 }
672
673 static void
674 free_scq(struct idt77252_dev *card, struct scq_info *scq)
675 {
676 struct sk_buff *skb;
677 struct atm_vcc *vcc;
678
679 pci_free_consistent(card->pcidev, SCQ_SIZE,
680 scq->base, scq->paddr);
681
682 while ((skb = skb_dequeue(&scq->transmit))) {
683 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
684 skb->len, PCI_DMA_TODEVICE);
685
686 vcc = ATM_SKB(skb)->vcc;
687 if (vcc->pop)
688 vcc->pop(vcc, skb);
689 else
690 dev_kfree_skb(skb);
691 }
692
693 while ((skb = skb_dequeue(&scq->pending))) {
694 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
695 skb->len, PCI_DMA_TODEVICE);
696
697 vcc = ATM_SKB(skb)->vcc;
698 if (vcc->pop)
699 vcc->pop(vcc, skb);
700 else
701 dev_kfree_skb(skb);
702 }
703
704 kfree(scq);
705 }
706
707
708 static int
709 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
710 {
711 struct scq_info *scq = vc->scq;
712 unsigned long flags;
713 struct scqe *tbd;
714 int entries;
715
716 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
717
718 atomic_inc(&scq->used);
719 entries = atomic_read(&scq->used);
720 if (entries > (SCQ_ENTRIES - 1)) {
721 atomic_dec(&scq->used);
722 goto out;
723 }
724
725 skb_queue_tail(&scq->transmit, skb);
726
727 spin_lock_irqsave(&vc->lock, flags);
728 if (vc->estimator) {
729 struct atm_vcc *vcc = vc->tx_vcc;
730 struct sock *sk = sk_atm(vcc);
731
732 vc->estimator->cells += (skb->len + 47) / 48;
733 if (atomic_read(&sk->sk_wmem_alloc) >
734 (sk->sk_sndbuf >> 1)) {
735 u32 cps = vc->estimator->maxcps;
736
737 vc->estimator->cps = cps;
738 vc->estimator->avcps = cps << 5;
739 if (vc->lacr < vc->init_er) {
740 vc->lacr = vc->init_er;
741 writel(TCMDQ_LACR | (vc->lacr << 16) |
742 vc->index, SAR_REG_TCMDQ);
743 }
744 }
745 }
746 spin_unlock_irqrestore(&vc->lock, flags);
747
748 tbd = &IDT77252_PRV_TBD(skb);
749
750 spin_lock_irqsave(&scq->lock, flags);
751 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
752 SAR_TBD_TSIF | SAR_TBD_GTSI);
753 scq->next->word_2 = cpu_to_le32(tbd->word_2);
754 scq->next->word_3 = cpu_to_le32(tbd->word_3);
755 scq->next->word_4 = cpu_to_le32(tbd->word_4);
756
757 if (scq->next == scq->last)
758 scq->next = scq->base;
759 else
760 scq->next++;
761
762 write_sram(card, scq->scd,
763 scq->paddr +
764 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
765 spin_unlock_irqrestore(&scq->lock, flags);
766
767 scq->trans_start = jiffies;
768
769 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
770 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
771 SAR_REG_TCMDQ);
772 }
773
774 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
775
776 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
777 card->name, atomic_read(&scq->used),
778 read_sram(card, scq->scd + 1), scq->next);
779
780 return 0;
781
782 out:
783 if (time_after(jiffies, scq->trans_start + HZ)) {
784 printk("%s: Error pushing TBD for %d.%d\n",
785 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
786 #ifdef CONFIG_ATM_IDT77252_DEBUG
787 idt77252_tx_dump(card);
788 #endif
789 scq->trans_start = jiffies;
790 }
791
792 return -ENOBUFS;
793 }
794
795
796 static void
797 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
798 {
799 struct scq_info *scq = vc->scq;
800 struct sk_buff *skb;
801 struct atm_vcc *vcc;
802
803 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
804 card->name, atomic_read(&scq->used), scq->next);
805
806 skb = skb_dequeue(&scq->transmit);
807 if (skb) {
808 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
809
810 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
811 skb->len, PCI_DMA_TODEVICE);
812
813 vcc = ATM_SKB(skb)->vcc;
814
815 if (vcc->pop)
816 vcc->pop(vcc, skb);
817 else
818 dev_kfree_skb(skb);
819
820 atomic_inc(&vcc->stats->tx);
821 }
822
823 atomic_dec(&scq->used);
824
825 spin_lock(&scq->skblock);
826 while ((skb = skb_dequeue(&scq->pending))) {
827 if (push_on_scq(card, vc, skb)) {
828 skb_queue_head(&vc->scq->pending, skb);
829 break;
830 }
831 }
832 spin_unlock(&scq->skblock);
833 }
834
835 static int
836 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
837 struct sk_buff *skb, int oam)
838 {
839 struct atm_vcc *vcc;
840 struct scqe *tbd;
841 unsigned long flags;
842 int error;
843 int aal;
844
845 if (skb->len == 0) {
846 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
847 return -EINVAL;
848 }
849
850 TXPRINTK("%s: Sending %d bytes of data.\n",
851 card->name, skb->len);
852
853 tbd = &IDT77252_PRV_TBD(skb);
854 vcc = ATM_SKB(skb)->vcc;
855
856 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
857 skb->len, PCI_DMA_TODEVICE);
858
859 error = -EINVAL;
860
861 if (oam) {
862 if (skb->len != 52)
863 goto errout;
864
865 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
866 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
867 tbd->word_3 = 0x00000000;
868 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
869 (skb->data[2] << 8) | (skb->data[3] << 0);
870
871 if (test_bit(VCF_RSV, &vc->flags))
872 vc = card->vcs[0];
873
874 goto done;
875 }
876
877 if (test_bit(VCF_RSV, &vc->flags)) {
878 printk("%s: Trying to transmit on reserved VC\n", card->name);
879 goto errout;
880 }
881
882 aal = vcc->qos.aal;
883
884 switch (aal) {
885 case ATM_AAL0:
886 case ATM_AAL34:
887 if (skb->len > 52)
888 goto errout;
889
890 if (aal == ATM_AAL0)
891 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
892 ATM_CELL_PAYLOAD;
893 else
894 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
895 ATM_CELL_PAYLOAD;
896
897 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
898 tbd->word_3 = 0x00000000;
899 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
900 (skb->data[2] << 8) | (skb->data[3] << 0);
901 break;
902
903 case ATM_AAL5:
904 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
905 tbd->word_2 = IDT77252_PRV_PADDR(skb);
906 tbd->word_3 = skb->len;
907 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
908 (vcc->vci << SAR_TBD_VCI_SHIFT);
909 break;
910
911 case ATM_AAL1:
912 case ATM_AAL2:
913 default:
914 printk("%s: Traffic type not supported.\n", card->name);
915 error = -EPROTONOSUPPORT;
916 goto errout;
917 }
918
919 done:
920 spin_lock_irqsave(&vc->scq->skblock, flags);
921 skb_queue_tail(&vc->scq->pending, skb);
922
923 while ((skb = skb_dequeue(&vc->scq->pending))) {
924 if (push_on_scq(card, vc, skb)) {
925 skb_queue_head(&vc->scq->pending, skb);
926 break;
927 }
928 }
929 spin_unlock_irqrestore(&vc->scq->skblock, flags);
930
931 return 0;
932
933 errout:
934 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
935 skb->len, PCI_DMA_TODEVICE);
936 return error;
937 }
938
939 static unsigned long
940 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
941 {
942 int i;
943
944 for (i = 0; i < card->scd_size; i++) {
945 if (!card->scd2vc[i]) {
946 card->scd2vc[i] = vc;
947 vc->scd_index = i;
948 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
949 }
950 }
951 return 0;
952 }
953
954 static void
955 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
956 {
957 write_sram(card, scq->scd, scq->paddr);
958 write_sram(card, scq->scd + 1, 0x00000000);
959 write_sram(card, scq->scd + 2, 0xffffffff);
960 write_sram(card, scq->scd + 3, 0x00000000);
961 }
962
963 static void
964 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
965 {
966 return;
967 }
968
969 /*****************************************************************************/
970 /* */
971 /* RSQ Handling */
972 /* */
973 /*****************************************************************************/
974
975 static int
976 init_rsq(struct idt77252_dev *card)
977 {
978 struct rsq_entry *rsqe;
979
980 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
981 &card->rsq.paddr);
982 if (card->rsq.base == NULL) {
983 printk("%s: can't allocate RSQ.\n", card->name);
984 return -1;
985 }
986 memset(card->rsq.base, 0, RSQSIZE);
987
988 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
989 card->rsq.next = card->rsq.last;
990 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
991 rsqe->word_4 = 0;
992
993 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
994 SAR_REG_RSQH);
995 writel(card->rsq.paddr, SAR_REG_RSQB);
996
997 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
998 (unsigned long) card->rsq.base,
999 readl(SAR_REG_RSQB));
1000 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1001 card->name,
1002 readl(SAR_REG_RSQH),
1003 readl(SAR_REG_RSQB),
1004 readl(SAR_REG_RSQT));
1005
1006 return 0;
1007 }
1008
1009 static void
1010 deinit_rsq(struct idt77252_dev *card)
1011 {
1012 pci_free_consistent(card->pcidev, RSQSIZE,
1013 card->rsq.base, card->rsq.paddr);
1014 }
1015
1016 static void
1017 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1018 {
1019 struct atm_vcc *vcc;
1020 struct sk_buff *skb;
1021 struct rx_pool *rpp;
1022 struct vc_map *vc;
1023 u32 header, vpi, vci;
1024 u32 stat;
1025 int i;
1026
1027 stat = le32_to_cpu(rsqe->word_4);
1028
1029 if (stat & SAR_RSQE_IDLE) {
1030 RXPRINTK("%s: message about inactive connection.\n",
1031 card->name);
1032 return;
1033 }
1034
1035 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1036 if (skb == NULL) {
1037 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1038 card->name, __FUNCTION__,
1039 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1040 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1041 return;
1042 }
1043
1044 header = le32_to_cpu(rsqe->word_1);
1045 vpi = (header >> 16) & 0x00ff;
1046 vci = (header >> 0) & 0xffff;
1047
1048 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1049 card->name, vpi, vci, skb, skb->data);
1050
1051 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1052 printk("%s: SDU received for out-of-range vc %u.%u\n",
1053 card->name, vpi, vci);
1054 recycle_rx_skb(card, skb);
1055 return;
1056 }
1057
1058 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1059 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1060 printk("%s: SDU received on non RX vc %u.%u\n",
1061 card->name, vpi, vci);
1062 recycle_rx_skb(card, skb);
1063 return;
1064 }
1065
1066 vcc = vc->rx_vcc;
1067
1068 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1069 skb_end_pointer(skb) - skb->data,
1070 PCI_DMA_FROMDEVICE);
1071
1072 if ((vcc->qos.aal == ATM_AAL0) ||
1073 (vcc->qos.aal == ATM_AAL34)) {
1074 struct sk_buff *sb;
1075 unsigned char *cell;
1076 u32 aal0;
1077
1078 cell = skb->data;
1079 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1080 if ((sb = dev_alloc_skb(64)) == NULL) {
1081 printk("%s: Can't allocate buffers for aal0.\n",
1082 card->name);
1083 atomic_add(i, &vcc->stats->rx_drop);
1084 break;
1085 }
1086 if (!atm_charge(vcc, sb->truesize)) {
1087 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1088 card->name);
1089 atomic_add(i - 1, &vcc->stats->rx_drop);
1090 dev_kfree_skb(sb);
1091 break;
1092 }
1093 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1094 (vci << ATM_HDR_VCI_SHIFT);
1095 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1096 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1097
1098 *((u32 *) sb->data) = aal0;
1099 skb_put(sb, sizeof(u32));
1100 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1101 cell, ATM_CELL_PAYLOAD);
1102
1103 ATM_SKB(sb)->vcc = vcc;
1104 __net_timestamp(sb);
1105 vcc->push(vcc, sb);
1106 atomic_inc(&vcc->stats->rx);
1107
1108 cell += ATM_CELL_PAYLOAD;
1109 }
1110
1111 recycle_rx_skb(card, skb);
1112 return;
1113 }
1114 if (vcc->qos.aal != ATM_AAL5) {
1115 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1116 card->name, vcc->qos.aal);
1117 recycle_rx_skb(card, skb);
1118 return;
1119 }
1120 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1121
1122 rpp = &vc->rcv.rx_pool;
1123
1124 rpp->len += skb->len;
1125 if (!rpp->count++)
1126 rpp->first = skb;
1127 *rpp->last = skb;
1128 rpp->last = &skb->next;
1129
1130 if (stat & SAR_RSQE_EPDU) {
1131 unsigned char *l1l2;
1132 unsigned int len;
1133
1134 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1135
1136 len = (l1l2[0] << 8) | l1l2[1];
1137 len = len ? len : 0x10000;
1138
1139 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1140
1141 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1142 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1143 "(CDC: %08x)\n",
1144 card->name, len, rpp->len, readl(SAR_REG_CDC));
1145 recycle_rx_pool_skb(card, rpp);
1146 atomic_inc(&vcc->stats->rx_err);
1147 return;
1148 }
1149 if (stat & SAR_RSQE_CRC) {
1150 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1151 recycle_rx_pool_skb(card, rpp);
1152 atomic_inc(&vcc->stats->rx_err);
1153 return;
1154 }
1155 if (rpp->count > 1) {
1156 struct sk_buff *sb;
1157
1158 skb = dev_alloc_skb(rpp->len);
1159 if (!skb) {
1160 RXPRINTK("%s: Can't alloc RX skb.\n",
1161 card->name);
1162 recycle_rx_pool_skb(card, rpp);
1163 atomic_inc(&vcc->stats->rx_err);
1164 return;
1165 }
1166 if (!atm_charge(vcc, skb->truesize)) {
1167 recycle_rx_pool_skb(card, rpp);
1168 dev_kfree_skb(skb);
1169 return;
1170 }
1171 sb = rpp->first;
1172 for (i = 0; i < rpp->count; i++) {
1173 memcpy(skb_put(skb, sb->len),
1174 sb->data, sb->len);
1175 sb = sb->next;
1176 }
1177
1178 recycle_rx_pool_skb(card, rpp);
1179
1180 skb_trim(skb, len);
1181 ATM_SKB(skb)->vcc = vcc;
1182 __net_timestamp(skb);
1183
1184 vcc->push(vcc, skb);
1185 atomic_inc(&vcc->stats->rx);
1186
1187 return;
1188 }
1189
1190 skb->next = NULL;
1191 flush_rx_pool(card, rpp);
1192
1193 if (!atm_charge(vcc, skb->truesize)) {
1194 recycle_rx_skb(card, skb);
1195 return;
1196 }
1197
1198 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1199 skb_end_pointer(skb) - skb->data,
1200 PCI_DMA_FROMDEVICE);
1201 sb_pool_remove(card, skb);
1202
1203 skb_trim(skb, len);
1204 ATM_SKB(skb)->vcc = vcc;
1205 __net_timestamp(skb);
1206
1207 vcc->push(vcc, skb);
1208 atomic_inc(&vcc->stats->rx);
1209
1210 if (skb->truesize > SAR_FB_SIZE_3)
1211 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1212 else if (skb->truesize > SAR_FB_SIZE_2)
1213 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1214 else if (skb->truesize > SAR_FB_SIZE_1)
1215 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1216 else
1217 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1218 return;
1219 }
1220 }
1221
1222 static void
1223 idt77252_rx(struct idt77252_dev *card)
1224 {
1225 struct rsq_entry *rsqe;
1226
1227 if (card->rsq.next == card->rsq.last)
1228 rsqe = card->rsq.base;
1229 else
1230 rsqe = card->rsq.next + 1;
1231
1232 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1233 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1234 return;
1235 }
1236
1237 do {
1238 dequeue_rx(card, rsqe);
1239 rsqe->word_4 = 0;
1240 card->rsq.next = rsqe;
1241 if (card->rsq.next == card->rsq.last)
1242 rsqe = card->rsq.base;
1243 else
1244 rsqe = card->rsq.next + 1;
1245 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1246
1247 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1248 SAR_REG_RSQH);
1249 }
1250
1251 static void
1252 idt77252_rx_raw(struct idt77252_dev *card)
1253 {
1254 struct sk_buff *queue;
1255 u32 head, tail;
1256 struct atm_vcc *vcc;
1257 struct vc_map *vc;
1258 struct sk_buff *sb;
1259
1260 if (card->raw_cell_head == NULL) {
1261 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1262 card->raw_cell_head = sb_pool_skb(card, handle);
1263 }
1264
1265 queue = card->raw_cell_head;
1266 if (!queue)
1267 return;
1268
1269 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1270 tail = readl(SAR_REG_RAWCT);
1271
1272 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1273 skb_end_pointer(queue) - queue->head - 16,
1274 PCI_DMA_FROMDEVICE);
1275
1276 while (head != tail) {
1277 unsigned int vpi, vci, pti;
1278 u32 header;
1279
1280 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1281
1282 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1283 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1284 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1285
1286 #ifdef CONFIG_ATM_IDT77252_DEBUG
1287 if (debug & DBG_RAW_CELL) {
1288 int i;
1289
1290 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1291 card->name, (header >> 28) & 0x000f,
1292 (header >> 20) & 0x00ff,
1293 (header >> 4) & 0xffff,
1294 (header >> 1) & 0x0007,
1295 (header >> 0) & 0x0001);
1296 for (i = 16; i < 64; i++)
1297 printk(" %02x", queue->data[i]);
1298 printk("\n");
1299 }
1300 #endif
1301
1302 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1303 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1304 card->name, vpi, vci);
1305 goto drop;
1306 }
1307
1308 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1309 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1310 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1311 card->name, vpi, vci);
1312 goto drop;
1313 }
1314
1315 vcc = vc->rx_vcc;
1316
1317 if (vcc->qos.aal != ATM_AAL0) {
1318 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1319 card->name, vpi, vci);
1320 atomic_inc(&vcc->stats->rx_drop);
1321 goto drop;
1322 }
1323
1324 if ((sb = dev_alloc_skb(64)) == NULL) {
1325 printk("%s: Can't allocate buffers for AAL0.\n",
1326 card->name);
1327 atomic_inc(&vcc->stats->rx_err);
1328 goto drop;
1329 }
1330
1331 if (!atm_charge(vcc, sb->truesize)) {
1332 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1333 card->name);
1334 dev_kfree_skb(sb);
1335 goto drop;
1336 }
1337
1338 *((u32 *) sb->data) = header;
1339 skb_put(sb, sizeof(u32));
1340 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1341 ATM_CELL_PAYLOAD);
1342
1343 ATM_SKB(sb)->vcc = vcc;
1344 __net_timestamp(sb);
1345 vcc->push(vcc, sb);
1346 atomic_inc(&vcc->stats->rx);
1347
1348 drop:
1349 skb_pull(queue, 64);
1350
1351 head = IDT77252_PRV_PADDR(queue)
1352 + (queue->data - queue->head - 16);
1353
1354 if (queue->len < 128) {
1355 struct sk_buff *next;
1356 u32 handle;
1357
1358 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1359 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1360
1361 next = sb_pool_skb(card, handle);
1362 recycle_rx_skb(card, queue);
1363
1364 if (next) {
1365 card->raw_cell_head = next;
1366 queue = card->raw_cell_head;
1367 pci_dma_sync_single_for_cpu(card->pcidev,
1368 IDT77252_PRV_PADDR(queue),
1369 (skb_end_pointer(queue) -
1370 queue->data),
1371 PCI_DMA_FROMDEVICE);
1372 } else {
1373 card->raw_cell_head = NULL;
1374 printk("%s: raw cell queue overrun\n",
1375 card->name);
1376 break;
1377 }
1378 }
1379 }
1380 }
1381
1382
1383 /*****************************************************************************/
1384 /* */
1385 /* TSQ Handling */
1386 /* */
1387 /*****************************************************************************/
1388
1389 static int
1390 init_tsq(struct idt77252_dev *card)
1391 {
1392 struct tsq_entry *tsqe;
1393
1394 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1395 &card->tsq.paddr);
1396 if (card->tsq.base == NULL) {
1397 printk("%s: can't allocate TSQ.\n", card->name);
1398 return -1;
1399 }
1400 memset(card->tsq.base, 0, TSQSIZE);
1401
1402 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1403 card->tsq.next = card->tsq.last;
1404 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1405 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1406
1407 writel(card->tsq.paddr, SAR_REG_TSQB);
1408 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1409 SAR_REG_TSQH);
1410
1411 return 0;
1412 }
1413
1414 static void
1415 deinit_tsq(struct idt77252_dev *card)
1416 {
1417 pci_free_consistent(card->pcidev, TSQSIZE,
1418 card->tsq.base, card->tsq.paddr);
1419 }
1420
1421 static void
1422 idt77252_tx(struct idt77252_dev *card)
1423 {
1424 struct tsq_entry *tsqe;
1425 unsigned int vpi, vci;
1426 struct vc_map *vc;
1427 u32 conn, stat;
1428
1429 if (card->tsq.next == card->tsq.last)
1430 tsqe = card->tsq.base;
1431 else
1432 tsqe = card->tsq.next + 1;
1433
1434 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1435 card->tsq.base, card->tsq.next, card->tsq.last);
1436 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1437 readl(SAR_REG_TSQB),
1438 readl(SAR_REG_TSQT),
1439 readl(SAR_REG_TSQH));
1440
1441 stat = le32_to_cpu(tsqe->word_2);
1442
1443 if (stat & SAR_TSQE_INVALID)
1444 return;
1445
1446 do {
1447 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1448 le32_to_cpu(tsqe->word_1),
1449 le32_to_cpu(tsqe->word_2));
1450
1451 switch (stat & SAR_TSQE_TYPE) {
1452 case SAR_TSQE_TYPE_TIMER:
1453 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1454 break;
1455
1456 case SAR_TSQE_TYPE_IDLE:
1457
1458 conn = le32_to_cpu(tsqe->word_1);
1459
1460 if (SAR_TSQE_TAG(stat) == 0x10) {
1461 #ifdef NOTDEF
1462 printk("%s: Connection %d halted.\n",
1463 card->name,
1464 le32_to_cpu(tsqe->word_1) & 0x1fff);
1465 #endif
1466 break;
1467 }
1468
1469 vc = card->vcs[conn & 0x1fff];
1470 if (!vc) {
1471 printk("%s: could not find VC from conn %d\n",
1472 card->name, conn & 0x1fff);
1473 break;
1474 }
1475
1476 printk("%s: Connection %d IDLE.\n",
1477 card->name, vc->index);
1478
1479 set_bit(VCF_IDLE, &vc->flags);
1480 break;
1481
1482 case SAR_TSQE_TYPE_TSR:
1483
1484 conn = le32_to_cpu(tsqe->word_1);
1485
1486 vc = card->vcs[conn & 0x1fff];
1487 if (!vc) {
1488 printk("%s: no VC at index %d\n",
1489 card->name,
1490 le32_to_cpu(tsqe->word_1) & 0x1fff);
1491 break;
1492 }
1493
1494 drain_scq(card, vc);
1495 break;
1496
1497 case SAR_TSQE_TYPE_TBD_COMP:
1498
1499 conn = le32_to_cpu(tsqe->word_1);
1500
1501 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1502 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1503
1504 if (vpi >= (1 << card->vpibits) ||
1505 vci >= (1 << card->vcibits)) {
1506 printk("%s: TBD complete: "
1507 "out of range VPI.VCI %u.%u\n",
1508 card->name, vpi, vci);
1509 break;
1510 }
1511
1512 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1513 if (!vc) {
1514 printk("%s: TBD complete: "
1515 "no VC at VPI.VCI %u.%u\n",
1516 card->name, vpi, vci);
1517 break;
1518 }
1519
1520 drain_scq(card, vc);
1521 break;
1522 }
1523
1524 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1525
1526 card->tsq.next = tsqe;
1527 if (card->tsq.next == card->tsq.last)
1528 tsqe = card->tsq.base;
1529 else
1530 tsqe = card->tsq.next + 1;
1531
1532 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1533 card->tsq.base, card->tsq.next, card->tsq.last);
1534
1535 stat = le32_to_cpu(tsqe->word_2);
1536
1537 } while (!(stat & SAR_TSQE_INVALID));
1538
1539 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1540 SAR_REG_TSQH);
1541
1542 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1543 card->index, readl(SAR_REG_TSQH),
1544 readl(SAR_REG_TSQT), card->tsq.next);
1545 }
1546
1547
1548 static void
1549 tst_timer(unsigned long data)
1550 {
1551 struct idt77252_dev *card = (struct idt77252_dev *)data;
1552 unsigned long base, idle, jump;
1553 unsigned long flags;
1554 u32 pc;
1555 int e;
1556
1557 spin_lock_irqsave(&card->tst_lock, flags);
1558
1559 base = card->tst[card->tst_index];
1560 idle = card->tst[card->tst_index ^ 1];
1561
1562 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1563 jump = base + card->tst_size - 2;
1564
1565 pc = readl(SAR_REG_NOW) >> 2;
1566 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1567 mod_timer(&card->tst_timer, jiffies + 1);
1568 goto out;
1569 }
1570
1571 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1572
1573 card->tst_index ^= 1;
1574 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1575
1576 base = card->tst[card->tst_index];
1577 idle = card->tst[card->tst_index ^ 1];
1578
1579 for (e = 0; e < card->tst_size - 2; e++) {
1580 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1581 write_sram(card, idle + e,
1582 card->soft_tst[e].tste & TSTE_MASK);
1583 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1584 }
1585 }
1586 }
1587
1588 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1589
1590 for (e = 0; e < card->tst_size - 2; e++) {
1591 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1592 write_sram(card, idle + e,
1593 card->soft_tst[e].tste & TSTE_MASK);
1594 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1595 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1596 }
1597 }
1598
1599 jump = base + card->tst_size - 2;
1600
1601 write_sram(card, jump, TSTE_OPC_NULL);
1602 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1603
1604 mod_timer(&card->tst_timer, jiffies + 1);
1605 }
1606
1607 out:
1608 spin_unlock_irqrestore(&card->tst_lock, flags);
1609 }
1610
1611 static int
1612 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1613 int n, unsigned int opc)
1614 {
1615 unsigned long cl, avail;
1616 unsigned long idle;
1617 int e, r;
1618 u32 data;
1619
1620 avail = card->tst_size - 2;
1621 for (e = 0; e < avail; e++) {
1622 if (card->soft_tst[e].vc == NULL)
1623 break;
1624 }
1625 if (e >= avail) {
1626 printk("%s: No free TST entries found\n", card->name);
1627 return -1;
1628 }
1629
1630 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1631 card->name, vc ? vc->index : -1, e);
1632
1633 r = n;
1634 cl = avail;
1635 data = opc & TSTE_OPC_MASK;
1636 if (vc && (opc != TSTE_OPC_NULL))
1637 data = opc | vc->index;
1638
1639 idle = card->tst[card->tst_index ^ 1];
1640
1641 /*
1642 * Fill Soft TST.
1643 */
1644 while (r > 0) {
1645 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1646 if (vc)
1647 card->soft_tst[e].vc = vc;
1648 else
1649 card->soft_tst[e].vc = (void *)-1;
1650
1651 card->soft_tst[e].tste = data;
1652 if (timer_pending(&card->tst_timer))
1653 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1654 else {
1655 write_sram(card, idle + e, data);
1656 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1657 }
1658
1659 cl -= card->tst_size;
1660 r--;
1661 }
1662
1663 if (++e == avail)
1664 e = 0;
1665 cl += n;
1666 }
1667
1668 return 0;
1669 }
1670
1671 static int
1672 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1673 {
1674 unsigned long flags;
1675 int res;
1676
1677 spin_lock_irqsave(&card->tst_lock, flags);
1678
1679 res = __fill_tst(card, vc, n, opc);
1680
1681 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1682 if (!timer_pending(&card->tst_timer))
1683 mod_timer(&card->tst_timer, jiffies + 1);
1684
1685 spin_unlock_irqrestore(&card->tst_lock, flags);
1686 return res;
1687 }
1688
1689 static int
1690 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1691 {
1692 unsigned long idle;
1693 int e;
1694
1695 idle = card->tst[card->tst_index ^ 1];
1696
1697 for (e = 0; e < card->tst_size - 2; e++) {
1698 if (card->soft_tst[e].vc == vc) {
1699 card->soft_tst[e].vc = NULL;
1700
1701 card->soft_tst[e].tste = TSTE_OPC_VAR;
1702 if (timer_pending(&card->tst_timer))
1703 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1704 else {
1705 write_sram(card, idle + e, TSTE_OPC_VAR);
1706 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1707 }
1708 }
1709 }
1710
1711 return 0;
1712 }
1713
1714 static int
1715 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1716 {
1717 unsigned long flags;
1718 int res;
1719
1720 spin_lock_irqsave(&card->tst_lock, flags);
1721
1722 res = __clear_tst(card, vc);
1723
1724 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1725 if (!timer_pending(&card->tst_timer))
1726 mod_timer(&card->tst_timer, jiffies + 1);
1727
1728 spin_unlock_irqrestore(&card->tst_lock, flags);
1729 return res;
1730 }
1731
1732 static int
1733 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1734 int n, unsigned int opc)
1735 {
1736 unsigned long flags;
1737 int res;
1738
1739 spin_lock_irqsave(&card->tst_lock, flags);
1740
1741 __clear_tst(card, vc);
1742 res = __fill_tst(card, vc, n, opc);
1743
1744 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1745 if (!timer_pending(&card->tst_timer))
1746 mod_timer(&card->tst_timer, jiffies + 1);
1747
1748 spin_unlock_irqrestore(&card->tst_lock, flags);
1749 return res;
1750 }
1751
1752
1753 static int
1754 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1755 {
1756 unsigned long tct;
1757
1758 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1759
1760 switch (vc->class) {
1761 case SCHED_CBR:
1762 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1763 card->name, tct, vc->scq->scd);
1764
1765 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1766 write_sram(card, tct + 1, 0);
1767 write_sram(card, tct + 2, 0);
1768 write_sram(card, tct + 3, 0);
1769 write_sram(card, tct + 4, 0);
1770 write_sram(card, tct + 5, 0);
1771 write_sram(card, tct + 6, 0);
1772 write_sram(card, tct + 7, 0);
1773 break;
1774
1775 case SCHED_UBR:
1776 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1777 card->name, tct, vc->scq->scd);
1778
1779 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1780 write_sram(card, tct + 1, 0);
1781 write_sram(card, tct + 2, TCT_TSIF);
1782 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1783 write_sram(card, tct + 4, 0);
1784 write_sram(card, tct + 5, vc->init_er);
1785 write_sram(card, tct + 6, 0);
1786 write_sram(card, tct + 7, TCT_FLAG_UBR);
1787 break;
1788
1789 case SCHED_VBR:
1790 case SCHED_ABR:
1791 default:
1792 return -ENOSYS;
1793 }
1794
1795 return 0;
1796 }
1797
1798 /*****************************************************************************/
1799 /* */
1800 /* FBQ Handling */
1801 /* */
1802 /*****************************************************************************/
1803
1804 static __inline__ int
1805 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1806 {
1807 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1808 }
1809
1810 static __inline__ int
1811 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1812 {
1813 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1814 }
1815
1816 static int
1817 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1818 {
1819 unsigned long flags;
1820 u32 handle;
1821 u32 addr;
1822
1823 skb->data = skb->head;
1824 skb_reset_tail_pointer(skb);
1825 skb->len = 0;
1826
1827 skb_reserve(skb, 16);
1828
1829 switch (queue) {
1830 case 0:
1831 skb_put(skb, SAR_FB_SIZE_0);
1832 break;
1833 case 1:
1834 skb_put(skb, SAR_FB_SIZE_1);
1835 break;
1836 case 2:
1837 skb_put(skb, SAR_FB_SIZE_2);
1838 break;
1839 case 3:
1840 skb_put(skb, SAR_FB_SIZE_3);
1841 break;
1842 default:
1843 return -1;
1844 }
1845
1846 if (idt77252_fbq_full(card, queue))
1847 return -1;
1848
1849 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1850
1851 handle = IDT77252_PRV_POOL(skb);
1852 addr = IDT77252_PRV_PADDR(skb);
1853
1854 spin_lock_irqsave(&card->cmd_lock, flags);
1855 writel(handle, card->fbq[queue]);
1856 writel(addr, card->fbq[queue]);
1857 spin_unlock_irqrestore(&card->cmd_lock, flags);
1858
1859 return 0;
1860 }
1861
1862 static void
1863 add_rx_skb(struct idt77252_dev *card, int queue,
1864 unsigned int size, unsigned int count)
1865 {
1866 struct sk_buff *skb;
1867 dma_addr_t paddr;
1868 u32 handle;
1869
1870 while (count--) {
1871 skb = dev_alloc_skb(size);
1872 if (!skb)
1873 return;
1874
1875 if (sb_pool_add(card, skb, queue)) {
1876 printk("%s: SB POOL full\n", __FUNCTION__);
1877 goto outfree;
1878 }
1879
1880 paddr = pci_map_single(card->pcidev, skb->data,
1881 skb_end_pointer(skb) - skb->data,
1882 PCI_DMA_FROMDEVICE);
1883 IDT77252_PRV_PADDR(skb) = paddr;
1884
1885 if (push_rx_skb(card, skb, queue)) {
1886 printk("%s: FB QUEUE full\n", __FUNCTION__);
1887 goto outunmap;
1888 }
1889 }
1890
1891 return;
1892
1893 outunmap:
1894 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1895 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE);
1896
1897 handle = IDT77252_PRV_POOL(skb);
1898 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1899
1900 outfree:
1901 dev_kfree_skb(skb);
1902 }
1903
1904
1905 static void
1906 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1907 {
1908 u32 handle = IDT77252_PRV_POOL(skb);
1909 int err;
1910
1911 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1912 skb_end_pointer(skb) - skb->data,
1913 PCI_DMA_FROMDEVICE);
1914
1915 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1916 if (err) {
1917 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1918 skb_end_pointer(skb) - skb->data,
1919 PCI_DMA_FROMDEVICE);
1920 sb_pool_remove(card, skb);
1921 dev_kfree_skb(skb);
1922 }
1923 }
1924
1925 static void
1926 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1927 {
1928 rpp->len = 0;
1929 rpp->count = 0;
1930 rpp->first = NULL;
1931 rpp->last = &rpp->first;
1932 }
1933
1934 static void
1935 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1936 {
1937 struct sk_buff *skb, *next;
1938 int i;
1939
1940 skb = rpp->first;
1941 for (i = 0; i < rpp->count; i++) {
1942 next = skb->next;
1943 skb->next = NULL;
1944 recycle_rx_skb(card, skb);
1945 skb = next;
1946 }
1947 flush_rx_pool(card, rpp);
1948 }
1949
1950 /*****************************************************************************/
1951 /* */
1952 /* ATM Interface */
1953 /* */
1954 /*****************************************************************************/
1955
1956 static void
1957 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1958 {
1959 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1960 }
1961
1962 static unsigned char
1963 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1964 {
1965 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1966 }
1967
1968 static inline int
1969 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1970 {
1971 struct atm_dev *dev = vcc->dev;
1972 struct idt77252_dev *card = dev->dev_data;
1973 struct vc_map *vc = vcc->dev_data;
1974 int err;
1975
1976 if (vc == NULL) {
1977 printk("%s: NULL connection in send().\n", card->name);
1978 atomic_inc(&vcc->stats->tx_err);
1979 dev_kfree_skb(skb);
1980 return -EINVAL;
1981 }
1982 if (!test_bit(VCF_TX, &vc->flags)) {
1983 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1984 atomic_inc(&vcc->stats->tx_err);
1985 dev_kfree_skb(skb);
1986 return -EINVAL;
1987 }
1988
1989 switch (vcc->qos.aal) {
1990 case ATM_AAL0:
1991 case ATM_AAL1:
1992 case ATM_AAL5:
1993 break;
1994 default:
1995 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1996 atomic_inc(&vcc->stats->tx_err);
1997 dev_kfree_skb(skb);
1998 return -EINVAL;
1999 }
2000
2001 if (skb_shinfo(skb)->nr_frags != 0) {
2002 printk("%s: No scatter-gather yet.\n", card->name);
2003 atomic_inc(&vcc->stats->tx_err);
2004 dev_kfree_skb(skb);
2005 return -EINVAL;
2006 }
2007 ATM_SKB(skb)->vcc = vcc;
2008
2009 err = queue_skb(card, vc, skb, oam);
2010 if (err) {
2011 atomic_inc(&vcc->stats->tx_err);
2012 dev_kfree_skb(skb);
2013 return err;
2014 }
2015
2016 return 0;
2017 }
2018
2019 int
2020 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2021 {
2022 return idt77252_send_skb(vcc, skb, 0);
2023 }
2024
2025 static int
2026 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2027 {
2028 struct atm_dev *dev = vcc->dev;
2029 struct idt77252_dev *card = dev->dev_data;
2030 struct sk_buff *skb;
2031
2032 skb = dev_alloc_skb(64);
2033 if (!skb) {
2034 printk("%s: Out of memory in send_oam().\n", card->name);
2035 atomic_inc(&vcc->stats->tx_err);
2036 return -ENOMEM;
2037 }
2038 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2039
2040 memcpy(skb_put(skb, 52), cell, 52);
2041
2042 return idt77252_send_skb(vcc, skb, 1);
2043 }
2044
2045 static __inline__ unsigned int
2046 idt77252_fls(unsigned int x)
2047 {
2048 int r = 1;
2049
2050 if (x == 0)
2051 return 0;
2052 if (x & 0xffff0000) {
2053 x >>= 16;
2054 r += 16;
2055 }
2056 if (x & 0xff00) {
2057 x >>= 8;
2058 r += 8;
2059 }
2060 if (x & 0xf0) {
2061 x >>= 4;
2062 r += 4;
2063 }
2064 if (x & 0xc) {
2065 x >>= 2;
2066 r += 2;
2067 }
2068 if (x & 0x2)
2069 r += 1;
2070 return r;
2071 }
2072
2073 static u16
2074 idt77252_int_to_atmfp(unsigned int rate)
2075 {
2076 u16 m, e;
2077
2078 if (rate == 0)
2079 return 0;
2080 e = idt77252_fls(rate) - 1;
2081 if (e < 9)
2082 m = (rate - (1 << e)) << (9 - e);
2083 else if (e == 9)
2084 m = (rate - (1 << e));
2085 else /* e > 9 */
2086 m = (rate - (1 << e)) >> (e - 9);
2087 return 0x4000 | (e << 9) | m;
2088 }
2089
2090 static u8
2091 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2092 {
2093 u16 afp;
2094
2095 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2096 if (pcr < 0)
2097 return rate_to_log[(afp >> 5) & 0x1ff];
2098 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2099 }
2100
2101 static void
2102 idt77252_est_timer(unsigned long data)
2103 {
2104 struct vc_map *vc = (struct vc_map *)data;
2105 struct idt77252_dev *card = vc->card;
2106 struct rate_estimator *est;
2107 unsigned long flags;
2108 u32 rate, cps;
2109 u64 ncells;
2110 u8 lacr;
2111
2112 spin_lock_irqsave(&vc->lock, flags);
2113 est = vc->estimator;
2114 if (!est)
2115 goto out;
2116
2117 ncells = est->cells;
2118
2119 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2120 est->last_cells = ncells;
2121 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2122 est->cps = (est->avcps + 0x1f) >> 5;
2123
2124 cps = est->cps;
2125 if (cps < (est->maxcps >> 4))
2126 cps = est->maxcps >> 4;
2127
2128 lacr = idt77252_rate_logindex(card, cps);
2129 if (lacr > vc->max_er)
2130 lacr = vc->max_er;
2131
2132 if (lacr != vc->lacr) {
2133 vc->lacr = lacr;
2134 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2135 }
2136
2137 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2138 add_timer(&est->timer);
2139
2140 out:
2141 spin_unlock_irqrestore(&vc->lock, flags);
2142 }
2143
2144 static struct rate_estimator *
2145 idt77252_init_est(struct vc_map *vc, int pcr)
2146 {
2147 struct rate_estimator *est;
2148
2149 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2150 if (!est)
2151 return NULL;
2152 est->maxcps = pcr < 0 ? -pcr : pcr;
2153 est->cps = est->maxcps;
2154 est->avcps = est->cps << 5;
2155
2156 est->interval = 2; /* XXX: make this configurable */
2157 est->ewma_log = 2; /* XXX: make this configurable */
2158 init_timer(&est->timer);
2159 est->timer.data = (unsigned long)vc;
2160 est->timer.function = idt77252_est_timer;
2161
2162 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2163 add_timer(&est->timer);
2164
2165 return est;
2166 }
2167
2168 static int
2169 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2170 struct atm_vcc *vcc, struct atm_qos *qos)
2171 {
2172 int tst_free, tst_used, tst_entries;
2173 unsigned long tmpl, modl;
2174 int tcr, tcra;
2175
2176 if ((qos->txtp.max_pcr == 0) &&
2177 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2178 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2179 card->name);
2180 return -EINVAL;
2181 }
2182
2183 tst_used = 0;
2184 tst_free = card->tst_free;
2185 if (test_bit(VCF_TX, &vc->flags))
2186 tst_used = vc->ntste;
2187 tst_free += tst_used;
2188
2189 tcr = atm_pcr_goal(&qos->txtp);
2190 tcra = tcr >= 0 ? tcr : -tcr;
2191
2192 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2193
2194 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2195 modl = tmpl % (unsigned long)card->utopia_pcr;
2196
2197 tst_entries = (int) (tmpl / card->utopia_pcr);
2198 if (tcr > 0) {
2199 if (modl > 0)
2200 tst_entries++;
2201 } else if (tcr == 0) {
2202 tst_entries = tst_free - SAR_TST_RESERVED;
2203 if (tst_entries <= 0) {
2204 printk("%s: no CBR bandwidth free.\n", card->name);
2205 return -ENOSR;
2206 }
2207 }
2208
2209 if (tst_entries == 0) {
2210 printk("%s: selected CBR bandwidth < granularity.\n",
2211 card->name);
2212 return -EINVAL;
2213 }
2214
2215 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2216 printk("%s: not enough CBR bandwidth free.\n", card->name);
2217 return -ENOSR;
2218 }
2219
2220 vc->ntste = tst_entries;
2221
2222 card->tst_free = tst_free - tst_entries;
2223 if (test_bit(VCF_TX, &vc->flags)) {
2224 if (tst_used == tst_entries)
2225 return 0;
2226
2227 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2228 card->name, tst_used, tst_entries);
2229 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2230 return 0;
2231 }
2232
2233 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2234 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2235 return 0;
2236 }
2237
2238 static int
2239 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2240 struct atm_vcc *vcc, struct atm_qos *qos)
2241 {
2242 unsigned long flags;
2243 int tcr;
2244
2245 spin_lock_irqsave(&vc->lock, flags);
2246 if (vc->estimator) {
2247 del_timer(&vc->estimator->timer);
2248 kfree(vc->estimator);
2249 vc->estimator = NULL;
2250 }
2251 spin_unlock_irqrestore(&vc->lock, flags);
2252
2253 tcr = atm_pcr_goal(&qos->txtp);
2254 if (tcr == 0)
2255 tcr = card->link_pcr;
2256
2257 vc->estimator = idt77252_init_est(vc, tcr);
2258
2259 vc->class = SCHED_UBR;
2260 vc->init_er = idt77252_rate_logindex(card, tcr);
2261 vc->lacr = vc->init_er;
2262 if (tcr < 0)
2263 vc->max_er = vc->init_er;
2264 else
2265 vc->max_er = 0xff;
2266
2267 return 0;
2268 }
2269
2270 static int
2271 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2272 struct atm_vcc *vcc, struct atm_qos *qos)
2273 {
2274 int error;
2275
2276 if (test_bit(VCF_TX, &vc->flags))
2277 return -EBUSY;
2278
2279 switch (qos->txtp.traffic_class) {
2280 case ATM_CBR:
2281 vc->class = SCHED_CBR;
2282 break;
2283
2284 case ATM_UBR:
2285 vc->class = SCHED_UBR;
2286 break;
2287
2288 case ATM_VBR:
2289 case ATM_ABR:
2290 default:
2291 return -EPROTONOSUPPORT;
2292 }
2293
2294 vc->scq = alloc_scq(card, vc->class);
2295 if (!vc->scq) {
2296 printk("%s: can't get SCQ.\n", card->name);
2297 return -ENOMEM;
2298 }
2299
2300 vc->scq->scd = get_free_scd(card, vc);
2301 if (vc->scq->scd == 0) {
2302 printk("%s: no SCD available.\n", card->name);
2303 free_scq(card, vc->scq);
2304 return -ENOMEM;
2305 }
2306
2307 fill_scd(card, vc->scq, vc->class);
2308
2309 if (set_tct(card, vc)) {
2310 printk("%s: class %d not supported.\n",
2311 card->name, qos->txtp.traffic_class);
2312
2313 card->scd2vc[vc->scd_index] = NULL;
2314 free_scq(card, vc->scq);
2315 return -EPROTONOSUPPORT;
2316 }
2317
2318 switch (vc->class) {
2319 case SCHED_CBR:
2320 error = idt77252_init_cbr(card, vc, vcc, qos);
2321 if (error) {
2322 card->scd2vc[vc->scd_index] = NULL;
2323 free_scq(card, vc->scq);
2324 return error;
2325 }
2326
2327 clear_bit(VCF_IDLE, &vc->flags);
2328 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2329 break;
2330
2331 case SCHED_UBR:
2332 error = idt77252_init_ubr(card, vc, vcc, qos);
2333 if (error) {
2334 card->scd2vc[vc->scd_index] = NULL;
2335 free_scq(card, vc->scq);
2336 return error;
2337 }
2338
2339 set_bit(VCF_IDLE, &vc->flags);
2340 break;
2341 }
2342
2343 vc->tx_vcc = vcc;
2344 set_bit(VCF_TX, &vc->flags);
2345 return 0;
2346 }
2347
2348 static int
2349 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2350 struct atm_vcc *vcc, struct atm_qos *qos)
2351 {
2352 unsigned long flags;
2353 unsigned long addr;
2354 u32 rcte = 0;
2355
2356 if (test_bit(VCF_RX, &vc->flags))
2357 return -EBUSY;
2358
2359 vc->rx_vcc = vcc;
2360 set_bit(VCF_RX, &vc->flags);
2361
2362 if ((vcc->vci == 3) || (vcc->vci == 4))
2363 return 0;
2364
2365 flush_rx_pool(card, &vc->rcv.rx_pool);
2366
2367 rcte |= SAR_RCTE_CONNECTOPEN;
2368 rcte |= SAR_RCTE_RAWCELLINTEN;
2369
2370 switch (qos->aal) {
2371 case ATM_AAL0:
2372 rcte |= SAR_RCTE_RCQ;
2373 break;
2374 case ATM_AAL1:
2375 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2376 break;
2377 case ATM_AAL34:
2378 rcte |= SAR_RCTE_AAL34;
2379 break;
2380 case ATM_AAL5:
2381 rcte |= SAR_RCTE_AAL5;
2382 break;
2383 default:
2384 rcte |= SAR_RCTE_RCQ;
2385 break;
2386 }
2387
2388 if (qos->aal != ATM_AAL5)
2389 rcte |= SAR_RCTE_FBP_1;
2390 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2391 rcte |= SAR_RCTE_FBP_3;
2392 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2393 rcte |= SAR_RCTE_FBP_2;
2394 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2395 rcte |= SAR_RCTE_FBP_1;
2396 else
2397 rcte |= SAR_RCTE_FBP_01;
2398
2399 addr = card->rct_base + (vc->index << 2);
2400
2401 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2402 write_sram(card, addr, rcte);
2403
2404 spin_lock_irqsave(&card->cmd_lock, flags);
2405 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2406 waitfor_idle(card);
2407 spin_unlock_irqrestore(&card->cmd_lock, flags);
2408
2409 return 0;
2410 }
2411
2412 static int
2413 idt77252_open(struct atm_vcc *vcc)
2414 {
2415 struct atm_dev *dev = vcc->dev;
2416 struct idt77252_dev *card = dev->dev_data;
2417 struct vc_map *vc;
2418 unsigned int index;
2419 unsigned int inuse;
2420 int error;
2421 int vci = vcc->vci;
2422 short vpi = vcc->vpi;
2423
2424 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2425 return 0;
2426
2427 if (vpi >= (1 << card->vpibits)) {
2428 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2429 return -EINVAL;
2430 }
2431
2432 if (vci >= (1 << card->vcibits)) {
2433 printk("%s: unsupported VCI: %d\n", card->name, vci);
2434 return -EINVAL;
2435 }
2436
2437 set_bit(ATM_VF_ADDR, &vcc->flags);
2438
2439 mutex_lock(&card->mutex);
2440
2441 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2442
2443 switch (vcc->qos.aal) {
2444 case ATM_AAL0:
2445 case ATM_AAL1:
2446 case ATM_AAL5:
2447 break;
2448 default:
2449 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2450 mutex_unlock(&card->mutex);
2451 return -EPROTONOSUPPORT;
2452 }
2453
2454 index = VPCI2VC(card, vpi, vci);
2455 if (!card->vcs[index]) {
2456 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2457 if (!card->vcs[index]) {
2458 printk("%s: can't alloc vc in open()\n", card->name);
2459 mutex_unlock(&card->mutex);
2460 return -ENOMEM;
2461 }
2462 card->vcs[index]->card = card;
2463 card->vcs[index]->index = index;
2464
2465 spin_lock_init(&card->vcs[index]->lock);
2466 }
2467 vc = card->vcs[index];
2468
2469 vcc->dev_data = vc;
2470
2471 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2472 card->name, vc->index, vcc->vpi, vcc->vci,
2473 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2474 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2475 vcc->qos.rxtp.max_sdu);
2476
2477 inuse = 0;
2478 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2479 test_bit(VCF_TX, &vc->flags))
2480 inuse = 1;
2481 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2482 test_bit(VCF_RX, &vc->flags))
2483 inuse += 2;
2484
2485 if (inuse) {
2486 printk("%s: %s vci already in use.\n", card->name,
2487 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2488 mutex_unlock(&card->mutex);
2489 return -EADDRINUSE;
2490 }
2491
2492 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2493 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2494 if (error) {
2495 mutex_unlock(&card->mutex);
2496 return error;
2497 }
2498 }
2499
2500 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2501 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2502 if (error) {
2503 mutex_unlock(&card->mutex);
2504 return error;
2505 }
2506 }
2507
2508 set_bit(ATM_VF_READY, &vcc->flags);
2509
2510 mutex_unlock(&card->mutex);
2511 return 0;
2512 }
2513
2514 static void
2515 idt77252_close(struct atm_vcc *vcc)
2516 {
2517 struct atm_dev *dev = vcc->dev;
2518 struct idt77252_dev *card = dev->dev_data;
2519 struct vc_map *vc = vcc->dev_data;
2520 unsigned long flags;
2521 unsigned long addr;
2522 unsigned long timeout;
2523
2524 mutex_lock(&card->mutex);
2525
2526 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2527 card->name, vc->index, vcc->vpi, vcc->vci);
2528
2529 clear_bit(ATM_VF_READY, &vcc->flags);
2530
2531 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2532
2533 spin_lock_irqsave(&vc->lock, flags);
2534 clear_bit(VCF_RX, &vc->flags);
2535 vc->rx_vcc = NULL;
2536 spin_unlock_irqrestore(&vc->lock, flags);
2537
2538 if ((vcc->vci == 3) || (vcc->vci == 4))
2539 goto done;
2540
2541 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2542
2543 spin_lock_irqsave(&card->cmd_lock, flags);
2544 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2545 waitfor_idle(card);
2546 spin_unlock_irqrestore(&card->cmd_lock, flags);
2547
2548 if (vc->rcv.rx_pool.count) {
2549 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2550 card->name);
2551
2552 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2553 }
2554 }
2555
2556 done:
2557 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2558
2559 spin_lock_irqsave(&vc->lock, flags);
2560 clear_bit(VCF_TX, &vc->flags);
2561 clear_bit(VCF_IDLE, &vc->flags);
2562 clear_bit(VCF_RSV, &vc->flags);
2563 vc->tx_vcc = NULL;
2564
2565 if (vc->estimator) {
2566 del_timer(&vc->estimator->timer);
2567 kfree(vc->estimator);
2568 vc->estimator = NULL;
2569 }
2570 spin_unlock_irqrestore(&vc->lock, flags);
2571
2572 timeout = 5 * 1000;
2573 while (atomic_read(&vc->scq->used) > 0) {
2574 timeout = msleep_interruptible(timeout);
2575 if (!timeout)
2576 break;
2577 }
2578 if (!timeout)
2579 printk("%s: SCQ drain timeout: %u used\n",
2580 card->name, atomic_read(&vc->scq->used));
2581
2582 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2583 clear_scd(card, vc->scq, vc->class);
2584
2585 if (vc->class == SCHED_CBR) {
2586 clear_tst(card, vc);
2587 card->tst_free += vc->ntste;
2588 vc->ntste = 0;
2589 }
2590
2591 card->scd2vc[vc->scd_index] = NULL;
2592 free_scq(card, vc->scq);
2593 }
2594
2595 mutex_unlock(&card->mutex);
2596 }
2597
2598 static int
2599 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2600 {
2601 struct atm_dev *dev = vcc->dev;
2602 struct idt77252_dev *card = dev->dev_data;
2603 struct vc_map *vc = vcc->dev_data;
2604 int error = 0;
2605
2606 mutex_lock(&card->mutex);
2607
2608 if (qos->txtp.traffic_class != ATM_NONE) {
2609 if (!test_bit(VCF_TX, &vc->flags)) {
2610 error = idt77252_init_tx(card, vc, vcc, qos);
2611 if (error)
2612 goto out;
2613 } else {
2614 switch (qos->txtp.traffic_class) {
2615 case ATM_CBR:
2616 error = idt77252_init_cbr(card, vc, vcc, qos);
2617 if (error)
2618 goto out;
2619 break;
2620
2621 case ATM_UBR:
2622 error = idt77252_init_ubr(card, vc, vcc, qos);
2623 if (error)
2624 goto out;
2625
2626 if (!test_bit(VCF_IDLE, &vc->flags)) {
2627 writel(TCMDQ_LACR | (vc->lacr << 16) |
2628 vc->index, SAR_REG_TCMDQ);
2629 }
2630 break;
2631
2632 case ATM_VBR:
2633 case ATM_ABR:
2634 error = -EOPNOTSUPP;
2635 goto out;
2636 }
2637 }
2638 }
2639
2640 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2641 !test_bit(VCF_RX, &vc->flags)) {
2642 error = idt77252_init_rx(card, vc, vcc, qos);
2643 if (error)
2644 goto out;
2645 }
2646
2647 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2648
2649 set_bit(ATM_VF_HASQOS, &vcc->flags);
2650
2651 out:
2652 mutex_unlock(&card->mutex);
2653 return error;
2654 }
2655
2656 static int
2657 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2658 {
2659 struct idt77252_dev *card = dev->dev_data;
2660 int i, left;
2661
2662 left = (int) *pos;
2663 if (!left--)
2664 return sprintf(page, "IDT77252 Interrupts:\n");
2665 if (!left--)
2666 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2667 if (!left--)
2668 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2669 if (!left--)
2670 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2671 if (!left--)
2672 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2673 if (!left--)
2674 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2675 if (!left--)
2676 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2677 if (!left--)
2678 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2679 if (!left--)
2680 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2681 if (!left--)
2682 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2683 if (!left--)
2684 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2685 if (!left--)
2686 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2687 if (!left--)
2688 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2689 if (!left--)
2690 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2691 if (!left--)
2692 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2693
2694 for (i = 0; i < card->tct_size; i++) {
2695 unsigned long tct;
2696 struct atm_vcc *vcc;
2697 struct vc_map *vc;
2698 char *p;
2699
2700 vc = card->vcs[i];
2701 if (!vc)
2702 continue;
2703
2704 vcc = NULL;
2705 if (vc->tx_vcc)
2706 vcc = vc->tx_vcc;
2707 if (!vcc)
2708 continue;
2709 if (left--)
2710 continue;
2711
2712 p = page;
2713 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2714 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2715
2716 for (i = 0; i < 8; i++)
2717 p += sprintf(p, " %08x", read_sram(card, tct + i));
2718 p += sprintf(p, "\n");
2719 return p - page;
2720 }
2721 return 0;
2722 }
2723
2724 /*****************************************************************************/
2725 /* */
2726 /* Interrupt handler */
2727 /* */
2728 /*****************************************************************************/
2729
2730 static void
2731 idt77252_collect_stat(struct idt77252_dev *card)
2732 {
2733 u32 cdc, vpec, icc;
2734
2735 cdc = readl(SAR_REG_CDC);
2736 vpec = readl(SAR_REG_VPEC);
2737 icc = readl(SAR_REG_ICC);
2738
2739 #ifdef NOTDEF
2740 printk("%s:", card->name);
2741
2742 if (cdc & 0x7f0000) {
2743 char *s = "";
2744
2745 printk(" [");
2746 if (cdc & (1 << 22)) {
2747 printk("%sRM ID", s);
2748 s = " | ";
2749 }
2750 if (cdc & (1 << 21)) {
2751 printk("%sCON TAB", s);
2752 s = " | ";
2753 }
2754 if (cdc & (1 << 20)) {
2755 printk("%sNO FB", s);
2756 s = " | ";
2757 }
2758 if (cdc & (1 << 19)) {
2759 printk("%sOAM CRC", s);
2760 s = " | ";
2761 }
2762 if (cdc & (1 << 18)) {
2763 printk("%sRM CRC", s);
2764 s = " | ";
2765 }
2766 if (cdc & (1 << 17)) {
2767 printk("%sRM FIFO", s);
2768 s = " | ";
2769 }
2770 if (cdc & (1 << 16)) {
2771 printk("%sRX FIFO", s);
2772 s = " | ";
2773 }
2774 printk("]");
2775 }
2776
2777 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2778 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2779 #endif
2780 }
2781
2782 static irqreturn_t
2783 idt77252_interrupt(int irq, void *dev_id)
2784 {
2785 struct idt77252_dev *card = dev_id;
2786 u32 stat;
2787
2788 stat = readl(SAR_REG_STAT) & 0xffff;
2789 if (!stat) /* no interrupt for us */
2790 return IRQ_NONE;
2791
2792 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2793 printk("%s: Re-entering irq_handler()\n", card->name);
2794 goto out;
2795 }
2796
2797 writel(stat, SAR_REG_STAT); /* reset interrupt */
2798
2799 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2800 INTPRINTK("%s: TSIF\n", card->name);
2801 card->irqstat[15]++;
2802 idt77252_tx(card);
2803 }
2804 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2805 INTPRINTK("%s: TXICP\n", card->name);
2806 card->irqstat[14]++;
2807 #ifdef CONFIG_ATM_IDT77252_DEBUG
2808 idt77252_tx_dump(card);
2809 #endif
2810 }
2811 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2812 INTPRINTK("%s: TSQF\n", card->name);
2813 card->irqstat[12]++;
2814 idt77252_tx(card);
2815 }
2816 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2817 INTPRINTK("%s: TMROF\n", card->name);
2818 card->irqstat[11]++;
2819 idt77252_collect_stat(card);
2820 }
2821
2822 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2823 INTPRINTK("%s: EPDU\n", card->name);
2824 card->irqstat[5]++;
2825 idt77252_rx(card);
2826 }
2827 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2828 INTPRINTK("%s: RSQAF\n", card->name);
2829 card->irqstat[1]++;
2830 idt77252_rx(card);
2831 }
2832 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2833 INTPRINTK("%s: RSQF\n", card->name);
2834 card->irqstat[6]++;
2835 idt77252_rx(card);
2836 }
2837 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2838 INTPRINTK("%s: RAWCF\n", card->name);
2839 card->irqstat[4]++;
2840 idt77252_rx_raw(card);
2841 }
2842
2843 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2844 INTPRINTK("%s: PHYI", card->name);
2845 card->irqstat[10]++;
2846 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2847 card->atmdev->phy->interrupt(card->atmdev);
2848 }
2849
2850 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2851 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2852
2853 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2854
2855 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2856
2857 if (stat & SAR_STAT_FBQ0A)
2858 card->irqstat[2]++;
2859 if (stat & SAR_STAT_FBQ1A)
2860 card->irqstat[3]++;
2861 if (stat & SAR_STAT_FBQ2A)
2862 card->irqstat[7]++;
2863 if (stat & SAR_STAT_FBQ3A)
2864 card->irqstat[8]++;
2865
2866 schedule_work(&card->tqueue);
2867 }
2868
2869 out:
2870 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2871 return IRQ_HANDLED;
2872 }
2873
2874 static void
2875 idt77252_softint(struct work_struct *work)
2876 {
2877 struct idt77252_dev *card =
2878 container_of(work, struct idt77252_dev, tqueue);
2879 u32 stat;
2880 int done;
2881
2882 for (done = 1; ; done = 1) {
2883 stat = readl(SAR_REG_STAT) >> 16;
2884
2885 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2886 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2887 done = 0;
2888 }
2889
2890 stat >>= 4;
2891 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2892 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2893 done = 0;
2894 }
2895
2896 stat >>= 4;
2897 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2898 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2899 done = 0;
2900 }
2901
2902 stat >>= 4;
2903 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2904 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2905 done = 0;
2906 }
2907
2908 if (done)
2909 break;
2910 }
2911
2912 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2913 }
2914
2915
2916 static int
2917 open_card_oam(struct idt77252_dev *card)
2918 {
2919 unsigned long flags;
2920 unsigned long addr;
2921 struct vc_map *vc;
2922 int vpi, vci;
2923 int index;
2924 u32 rcte;
2925
2926 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2927 for (vci = 3; vci < 5; vci++) {
2928 index = VPCI2VC(card, vpi, vci);
2929
2930 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2931 if (!vc) {
2932 printk("%s: can't alloc vc\n", card->name);
2933 return -ENOMEM;
2934 }
2935 vc->index = index;
2936 card->vcs[index] = vc;
2937
2938 flush_rx_pool(card, &vc->rcv.rx_pool);
2939
2940 rcte = SAR_RCTE_CONNECTOPEN |
2941 SAR_RCTE_RAWCELLINTEN |
2942 SAR_RCTE_RCQ |
2943 SAR_RCTE_FBP_1;
2944
2945 addr = card->rct_base + (vc->index << 2);
2946 write_sram(card, addr, rcte);
2947
2948 spin_lock_irqsave(&card->cmd_lock, flags);
2949 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2950 SAR_REG_CMD);
2951 waitfor_idle(card);
2952 spin_unlock_irqrestore(&card->cmd_lock, flags);
2953 }
2954 }
2955
2956 return 0;
2957 }
2958
2959 static void
2960 close_card_oam(struct idt77252_dev *card)
2961 {
2962 unsigned long flags;
2963 unsigned long addr;
2964 struct vc_map *vc;
2965 int vpi, vci;
2966 int index;
2967
2968 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2969 for (vci = 3; vci < 5; vci++) {
2970 index = VPCI2VC(card, vpi, vci);
2971 vc = card->vcs[index];
2972
2973 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2974
2975 spin_lock_irqsave(&card->cmd_lock, flags);
2976 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2977 SAR_REG_CMD);
2978 waitfor_idle(card);
2979 spin_unlock_irqrestore(&card->cmd_lock, flags);
2980
2981 if (vc->rcv.rx_pool.count) {
2982 DPRINTK("%s: closing a VC "
2983 "with pending rx buffers.\n",
2984 card->name);
2985
2986 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2987 }
2988 }
2989 }
2990 }
2991
2992 static int
2993 open_card_ubr0(struct idt77252_dev *card)
2994 {
2995 struct vc_map *vc;
2996
2997 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2998 if (!vc) {
2999 printk("%s: can't alloc vc\n", card->name);
3000 return -ENOMEM;
3001 }
3002 card->vcs[0] = vc;
3003 vc->class = SCHED_UBR0;
3004
3005 vc->scq = alloc_scq(card, vc->class);
3006 if (!vc->scq) {
3007 printk("%s: can't get SCQ.\n", card->name);
3008 return -ENOMEM;
3009 }
3010
3011 card->scd2vc[0] = vc;
3012 vc->scd_index = 0;
3013 vc->scq->scd = card->scd_base;
3014
3015 fill_scd(card, vc->scq, vc->class);
3016
3017 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3018 write_sram(card, card->tct_base + 1, 0);
3019 write_sram(card, card->tct_base + 2, 0);
3020 write_sram(card, card->tct_base + 3, 0);
3021 write_sram(card, card->tct_base + 4, 0);
3022 write_sram(card, card->tct_base + 5, 0);
3023 write_sram(card, card->tct_base + 6, 0);
3024 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3025
3026 clear_bit(VCF_IDLE, &vc->flags);
3027 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3028 return 0;
3029 }
3030
3031 static int
3032 idt77252_dev_open(struct idt77252_dev *card)
3033 {
3034 u32 conf;
3035
3036 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3037 printk("%s: SAR not yet initialized.\n", card->name);
3038 return -1;
3039 }
3040
3041 conf = SAR_CFG_RXPTH| /* enable receive path */
3042 SAR_RX_DELAY | /* interrupt on complete PDU */
3043 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3044 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3045 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3046 SAR_CFG_FBIE | /* interrupt on low free buffers */
3047 SAR_CFG_TXEN | /* transmit operation enable */
3048 SAR_CFG_TXINT | /* interrupt on transmit status */
3049 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3050 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3051 SAR_CFG_PHYIE /* enable PHY interrupts */
3052 ;
3053
3054 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3055 /* Test RAW cell receive. */
3056 conf |= SAR_CFG_VPECA;
3057 #endif
3058
3059 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3060
3061 if (open_card_oam(card)) {
3062 printk("%s: Error initializing OAM.\n", card->name);
3063 return -1;
3064 }
3065
3066 if (open_card_ubr0(card)) {
3067 printk("%s: Error initializing UBR0.\n", card->name);
3068 return -1;
3069 }
3070
3071 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3072 return 0;
3073 }
3074
3075 void
3076 idt77252_dev_close(struct atm_dev *dev)
3077 {
3078 struct idt77252_dev *card = dev->dev_data;
3079 u32 conf;
3080
3081 close_card_oam(card);
3082
3083 conf = SAR_CFG_RXPTH | /* enable receive path */
3084 SAR_RX_DELAY | /* interrupt on complete PDU */
3085 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3086 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3087 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3088 SAR_CFG_FBIE | /* interrupt on low free buffers */
3089 SAR_CFG_TXEN | /* transmit operation enable */
3090 SAR_CFG_TXINT | /* interrupt on transmit status */
3091 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3092 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3093 ;
3094
3095 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3096
3097 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3098 }
3099
3100
3101 /*****************************************************************************/
3102 /* */
3103 /* Initialisation and Deinitialization of IDT77252 */
3104 /* */
3105 /*****************************************************************************/
3106
3107
3108 static void
3109 deinit_card(struct idt77252_dev *card)
3110 {
3111 struct sk_buff *skb;
3112 int i, j;
3113
3114 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3115 printk("%s: SAR not yet initialized.\n", card->name);
3116 return;
3117 }
3118 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3119
3120 writel(0, SAR_REG_CFG);
3121
3122 if (card->atmdev)
3123 atm_dev_deregister(card->atmdev);
3124
3125 for (i = 0; i < 4; i++) {
3126 for (j = 0; j < FBQ_SIZE; j++) {
3127 skb = card->sbpool[i].skb[j];
3128 if (skb) {
3129 pci_unmap_single(card->pcidev,
3130 IDT77252_PRV_PADDR(skb),
3131 (skb_end_pointer(skb) -
3132 skb->data),
3133 PCI_DMA_FROMDEVICE);
3134 card->sbpool[i].skb[j] = NULL;
3135 dev_kfree_skb(skb);
3136 }
3137 }
3138 }
3139
3140 vfree(card->soft_tst);
3141
3142 vfree(card->scd2vc);
3143
3144 vfree(card->vcs);
3145
3146 if (card->raw_cell_hnd) {
3147 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3148 card->raw_cell_hnd, card->raw_cell_paddr);
3149 }
3150
3151 if (card->rsq.base) {
3152 DIPRINTK("%s: Release RSQ ...\n", card->name);
3153 deinit_rsq(card);
3154 }
3155
3156 if (card->tsq.base) {
3157 DIPRINTK("%s: Release TSQ ...\n", card->name);
3158 deinit_tsq(card);
3159 }
3160
3161 DIPRINTK("idt77252: Release IRQ.\n");
3162 free_irq(card->pcidev->irq, card);
3163
3164 for (i = 0; i < 4; i++) {
3165 if (card->fbq[i])
3166 iounmap(card->fbq[i]);
3167 }
3168
3169 if (card->membase)
3170 iounmap(card->membase);
3171
3172 clear_bit(IDT77252_BIT_INIT, &card->flags);
3173 DIPRINTK("%s: Card deinitialized.\n", card->name);
3174 }
3175
3176
3177 static int __devinit
3178 init_sram(struct idt77252_dev *card)
3179 {
3180 int i;
3181
3182 for (i = 0; i < card->sramsize; i += 4)
3183 write_sram(card, (i >> 2), 0);
3184
3185 /* set SRAM layout for THIS card */
3186 if (card->sramsize == (512 * 1024)) {
3187 card->tct_base = SAR_SRAM_TCT_128_BASE;
3188 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3189 / SAR_SRAM_TCT_SIZE;
3190 card->rct_base = SAR_SRAM_RCT_128_BASE;
3191 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3192 / SAR_SRAM_RCT_SIZE;
3193 card->rt_base = SAR_SRAM_RT_128_BASE;
3194 card->scd_base = SAR_SRAM_SCD_128_BASE;
3195 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3196 / SAR_SRAM_SCD_SIZE;
3197 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3198 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3199 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3200 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3201 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3202 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3203 card->fifo_size = SAR_RXFD_SIZE_32K;
3204 } else {
3205 card->tct_base = SAR_SRAM_TCT_32_BASE;
3206 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3207 / SAR_SRAM_TCT_SIZE;
3208 card->rct_base = SAR_SRAM_RCT_32_BASE;
3209 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3210 / SAR_SRAM_RCT_SIZE;
3211 card->rt_base = SAR_SRAM_RT_32_BASE;
3212 card->scd_base = SAR_SRAM_SCD_32_BASE;
3213 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3214 / SAR_SRAM_SCD_SIZE;
3215 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3216 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3217 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3218 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3219 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3220 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3221 card->fifo_size = SAR_RXFD_SIZE_4K;
3222 }
3223
3224 /* Initialize TCT */
3225 for (i = 0; i < card->tct_size; i++) {
3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3233 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3234 }
3235
3236 /* Initialize RCT */
3237 for (i = 0; i < card->rct_size; i++) {
3238 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3239 (u32) SAR_RCTE_RAWCELLINTEN);
3240 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3241 (u32) 0);
3242 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3243 (u32) 0);
3244 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3245 (u32) 0xffffffff);
3246 }
3247
3248 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3249 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3250 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3251 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3252 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3253 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3254 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3255 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3256
3257 /* Initialize rate table */
3258 for (i = 0; i < 256; i++) {
3259 write_sram(card, card->rt_base + i, log_to_rate[i]);
3260 }
3261
3262 for (i = 0; i < 128; i++) {
3263 unsigned int tmp;
3264
3265 tmp = rate_to_log[(i << 2) + 0] << 0;
3266 tmp |= rate_to_log[(i << 2) + 1] << 8;
3267 tmp |= rate_to_log[(i << 2) + 2] << 16;
3268 tmp |= rate_to_log[(i << 2) + 3] << 24;
3269 write_sram(card, card->rt_base + 256 + i, tmp);
3270 }
3271
3272 #if 0 /* Fill RDF and AIR tables. */
3273 for (i = 0; i < 128; i++) {
3274 unsigned int tmp;
3275
3276 tmp = RDF[0][(i << 1) + 0] << 16;
3277 tmp |= RDF[0][(i << 1) + 1] << 0;
3278 write_sram(card, card->rt_base + 512 + i, tmp);
3279 }
3280
3281 for (i = 0; i < 128; i++) {
3282 unsigned int tmp;
3283
3284 tmp = AIR[0][(i << 1) + 0] << 16;
3285 tmp |= AIR[0][(i << 1) + 1] << 0;
3286 write_sram(card, card->rt_base + 640 + i, tmp);
3287 }
3288 #endif
3289
3290 IPRINTK("%s: initialize rate table ...\n", card->name);
3291 writel(card->rt_base << 2, SAR_REG_RTBL);
3292
3293 /* Initialize TSTs */
3294 IPRINTK("%s: initialize TST ...\n", card->name);
3295 card->tst_free = card->tst_size - 2; /* last two are jumps */
3296
3297 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3298 write_sram(card, i, TSTE_OPC_VAR);
3299 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3300 idt77252_sram_write_errors = 1;
3301 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3302 idt77252_sram_write_errors = 0;
3303 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3304 write_sram(card, i, TSTE_OPC_VAR);
3305 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3306 idt77252_sram_write_errors = 1;
3307 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3308 idt77252_sram_write_errors = 0;
3309
3310 card->tst_index = 0;
3311 writel(card->tst[0] << 2, SAR_REG_TSTB);
3312
3313 /* Initialize ABRSTD and Receive FIFO */
3314 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3315 writel(card->abrst_size | (card->abrst_base << 2),
3316 SAR_REG_ABRSTD);
3317
3318 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3319 writel(card->fifo_size | (card->fifo_base << 2),
3320 SAR_REG_RXFD);
3321
3322 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3323 return 0;
3324 }
3325
3326 static int __devinit
3327 init_card(struct atm_dev *dev)
3328 {
3329 struct idt77252_dev *card = dev->dev_data;
3330 struct pci_dev *pcidev = card->pcidev;
3331 unsigned long tmpl, modl;
3332 unsigned int linkrate, rsvdcr;
3333 unsigned int tst_entries;
3334 struct net_device *tmp;
3335 char tname[10];
3336
3337 u32 size;
3338 u_char pci_byte;
3339 u32 conf;
3340 int i, k;
3341
3342 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3343 printk("Error: SAR already initialized.\n");
3344 return -1;
3345 }
3346
3347 /*****************************************************************/
3348 /* P C I C O N F I G U R A T I O N */
3349 /*****************************************************************/
3350
3351 /* Set PCI Retry-Timeout and TRDY timeout */
3352 IPRINTK("%s: Checking PCI retries.\n", card->name);
3353 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3354 printk("%s: can't read PCI retry timeout.\n", card->name);
3355 deinit_card(card);
3356 return -1;
3357 }
3358 if (pci_byte != 0) {
3359 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3360 card->name, pci_byte);
3361 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3362 printk("%s: can't set PCI retry timeout.\n",
3363 card->name);
3364 deinit_card(card);
3365 return -1;
3366 }
3367 }
3368 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3369 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3370 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3371 deinit_card(card);
3372 return -1;
3373 }
3374 if (pci_byte != 0) {
3375 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3376 card->name, pci_byte);
3377 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3378 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3379 deinit_card(card);
3380 return -1;
3381 }
3382 }
3383 /* Reset Timer register */
3384 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3385 printk("%s: resetting timer overflow.\n", card->name);
3386 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3387 }
3388 IPRINTK("%s: Request IRQ ... ", card->name);
3389 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED,
3390 card->name, card) != 0) {
3391 printk("%s: can't allocate IRQ.\n", card->name);
3392 deinit_card(card);
3393 return -1;
3394 }
3395 IPRINTK("got %d.\n", pcidev->irq);
3396
3397 /*****************************************************************/
3398 /* C H E C K A N D I N I T S R A M */
3399 /*****************************************************************/
3400
3401 IPRINTK("%s: Initializing SRAM\n", card->name);
3402
3403 /* preset size of connecton table, so that init_sram() knows about it */
3404 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3405 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3406 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3407 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3408 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3409 #endif
3410 0;
3411
3412 if (card->sramsize == (512 * 1024))
3413 conf |= SAR_CFG_CNTBL_1k;
3414 else
3415 conf |= SAR_CFG_CNTBL_512;
3416
3417 switch (vpibits) {
3418 case 0:
3419 conf |= SAR_CFG_VPVCS_0;
3420 break;
3421 default:
3422 case 1:
3423 conf |= SAR_CFG_VPVCS_1;
3424 break;
3425 case 2:
3426 conf |= SAR_CFG_VPVCS_2;
3427 break;
3428 case 8:
3429 conf |= SAR_CFG_VPVCS_8;
3430 break;
3431 }
3432
3433 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3434
3435 if (init_sram(card) < 0)
3436 return -1;
3437
3438 /********************************************************************/
3439 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3440 /********************************************************************/
3441 /* Initialize TSQ */
3442 if (0 != init_tsq(card)) {
3443 deinit_card(card);
3444 return -1;
3445 }
3446 /* Initialize RSQ */
3447 if (0 != init_rsq(card)) {
3448 deinit_card(card);
3449 return -1;
3450 }
3451
3452 card->vpibits = vpibits;
3453 if (card->sramsize == (512 * 1024)) {
3454 card->vcibits = 10 - card->vpibits;
3455 } else {
3456 card->vcibits = 9 - card->vpibits;
3457 }
3458
3459 card->vcimask = 0;
3460 for (k = 0, i = 1; k < card->vcibits; k++) {
3461 card->vcimask |= i;
3462 i <<= 1;
3463 }
3464
3465 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3466 writel(0, SAR_REG_VPM);
3467
3468 /* Little Endian Order */
3469 writel(0, SAR_REG_GP);
3470
3471 /* Initialize RAW Cell Handle Register */
3472 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3473 &card->raw_cell_paddr);
3474 if (!card->raw_cell_hnd) {
3475 printk("%s: memory allocation failure.\n", card->name);
3476 deinit_card(card);
3477 return -1;
3478 }
3479 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3480 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3481 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3482 card->raw_cell_hnd);
3483
3484 size = sizeof(struct vc_map *) * card->tct_size;
3485 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3486 if (NULL == (card->vcs = vmalloc(size))) {
3487 printk("%s: memory allocation failure.\n", card->name);
3488 deinit_card(card);
3489 return -1;
3490 }
3491 memset(card->vcs, 0, size);
3492
3493 size = sizeof(struct vc_map *) * card->scd_size;
3494 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3495 card->name, size);
3496 if (NULL == (card->scd2vc = vmalloc(size))) {
3497 printk("%s: memory allocation failure.\n", card->name);
3498 deinit_card(card);
3499 return -1;
3500 }
3501 memset(card->scd2vc, 0, size);
3502
3503 size = sizeof(struct tst_info) * (card->tst_size - 2);
3504 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3505 card->name, size);
3506 if (NULL == (card->soft_tst = vmalloc(size))) {
3507 printk("%s: memory allocation failure.\n", card->name);
3508 deinit_card(card);
3509 return -1;
3510 }
3511 for (i = 0; i < card->tst_size - 2; i++) {
3512 card->soft_tst[i].tste = TSTE_OPC_VAR;
3513 card->soft_tst[i].vc = NULL;
3514 }
3515
3516 if (dev->phy == NULL) {
3517 printk("%s: No LT device defined.\n", card->name);
3518 deinit_card(card);
3519 return -1;
3520 }
3521 if (dev->phy->ioctl == NULL) {
3522 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3523 deinit_card(card);
3524 return -1;
3525 }
3526
3527 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3528 /*
3529 * this is a jhs hack to get around special functionality in the
3530 * phy driver for the atecom hardware; the functionality doesn't
3531 * exist in the linux atm suni driver
3532 *
3533 * it isn't the right way to do things, but as the guy from NIST
3534 * said, talking about their measurement of the fine structure
3535 * constant, "it's good enough for government work."
3536 */
3537 linkrate = 149760000;
3538 #endif
3539
3540 card->link_pcr = (linkrate / 8 / 53);
3541 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3542 card->name, linkrate, card->link_pcr);
3543
3544 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3545 card->utopia_pcr = card->link_pcr;
3546 #else
3547 card->utopia_pcr = (160000000 / 8 / 54);
3548 #endif
3549
3550 rsvdcr = 0;
3551 if (card->utopia_pcr > card->link_pcr)
3552 rsvdcr = card->utopia_pcr - card->link_pcr;
3553
3554 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3555 modl = tmpl % (unsigned long)card->utopia_pcr;
3556 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3557 if (modl)
3558 tst_entries++;
3559 card->tst_free -= tst_entries;
3560 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3561
3562 #ifdef HAVE_EEPROM
3563 idt77252_eeprom_init(card);
3564 printk("%s: EEPROM: %02x:", card->name,
3565 idt77252_eeprom_read_status(card));
3566
3567 for (i = 0; i < 0x80; i++) {
3568 printk(" %02x",
3569 idt77252_eeprom_read_byte(card, i)
3570 );
3571 }
3572 printk("\n");
3573 #endif /* HAVE_EEPROM */
3574
3575 /*
3576 * XXX: <hack>
3577 */
3578 sprintf(tname, "eth%d", card->index);
3579 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3580 if (tmp) {
3581 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3582
3583 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3584 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3585 card->atmdev->esi[2], card->atmdev->esi[3],
3586 card->atmdev->esi[4], card->atmdev->esi[5]);
3587 }
3588 /*
3589 * XXX: </hack>
3590 */
3591
3592 /* Set Maximum Deficit Count for now. */
3593 writel(0xffff, SAR_REG_MDFCT);
3594
3595 set_bit(IDT77252_BIT_INIT, &card->flags);
3596
3597 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3598 return 0;
3599 }
3600
3601
3602 /*****************************************************************************/
3603 /* */
3604 /* Probing of IDT77252 ABR SAR */
3605 /* */
3606 /*****************************************************************************/
3607
3608
3609 static int __devinit
3610 idt77252_preset(struct idt77252_dev *card)
3611 {
3612 u16 pci_command;
3613
3614 /*****************************************************************/
3615 /* P C I C O N F I G U R A T I O N */
3616 /*****************************************************************/
3617
3618 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3619 card->name);
3620 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3621 printk("%s: can't read PCI_COMMAND.\n", card->name);
3622 deinit_card(card);
3623 return -1;
3624 }
3625 if (!(pci_command & PCI_COMMAND_IO)) {
3626 printk("%s: PCI_COMMAND: %04x (???)\n",
3627 card->name, pci_command);
3628 deinit_card(card);
3629 return (-1);
3630 }
3631 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3632 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3633 printk("%s: can't write PCI_COMMAND.\n", card->name);
3634 deinit_card(card);
3635 return -1;
3636 }
3637 /*****************************************************************/
3638 /* G E N E R I C R E S E T */
3639 /*****************************************************************/
3640
3641 /* Software reset */
3642 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3643 mdelay(1);
3644 writel(0, SAR_REG_CFG);
3645
3646 IPRINTK("%s: Software resetted.\n", card->name);
3647 return 0;
3648 }
3649
3650
3651 static unsigned long __devinit
3652 probe_sram(struct idt77252_dev *card)
3653 {
3654 u32 data, addr;
3655
3656 writel(0, SAR_REG_DR0);
3657 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3658
3659 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3660 writel(ATM_POISON, SAR_REG_DR0);
3661 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3662
3663 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3664 data = readl(SAR_REG_DR0);
3665
3666 if (data != 0)
3667 break;
3668 }
3669
3670 return addr * sizeof(u32);
3671 }
3672
3673 static int __devinit
3674 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3675 {
3676 static struct idt77252_dev **last = &idt77252_chain;
3677 static int index = 0;
3678
3679 unsigned long membase, srambase;
3680 struct idt77252_dev *card;
3681 struct atm_dev *dev;
3682 ushort revision = 0;
3683 int i, err;
3684
3685
3686 if ((err = pci_enable_device(pcidev))) {
3687 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3688 return err;
3689 }
3690
3691 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3692 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3693 err = -ENODEV;
3694 goto err_out_disable_pdev;
3695 }
3696
3697 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3698 if (!card) {
3699 printk("idt77252-%d: can't allocate private data\n", index);
3700 err = -ENOMEM;
3701 goto err_out_disable_pdev;
3702 }
3703 card->revision = revision;
3704 card->index = index;
3705 card->pcidev = pcidev;
3706 sprintf(card->name, "idt77252-%d", card->index);
3707
3708 INIT_WORK(&card->tqueue, idt77252_softint);
3709
3710 membase = pci_resource_start(pcidev, 1);
3711 srambase = pci_resource_start(pcidev, 2);
3712
3713 mutex_init(&card->mutex);
3714 spin_lock_init(&card->cmd_lock);
3715 spin_lock_init(&card->tst_lock);
3716
3717 init_timer(&card->tst_timer);
3718 card->tst_timer.data = (unsigned long)card;
3719 card->tst_timer.function = tst_timer;
3720
3721 /* Do the I/O remapping... */
3722 card->membase = ioremap(membase, 1024);
3723 if (!card->membase) {
3724 printk("%s: can't ioremap() membase\n", card->name);
3725 err = -EIO;
3726 goto err_out_free_card;
3727 }
3728
3729 if (idt77252_preset(card)) {
3730 printk("%s: preset failed\n", card->name);
3731 err = -EIO;
3732 goto err_out_iounmap;
3733 }
3734
3735 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3736 if (!dev) {
3737 printk("%s: can't register atm device\n", card->name);
3738 err = -EIO;
3739 goto err_out_iounmap;
3740 }
3741 dev->dev_data = card;
3742 card->atmdev = dev;
3743
3744 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3745 suni_init(dev);
3746 if (!dev->phy) {
3747 printk("%s: can't init SUNI\n", card->name);
3748 err = -EIO;
3749 goto err_out_deinit_card;
3750 }
3751 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3752
3753 card->sramsize = probe_sram(card);
3754
3755 for (i = 0; i < 4; i++) {
3756 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3757 if (!card->fbq[i]) {
3758 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3759 err = -EIO;
3760 goto err_out_deinit_card;
3761 }
3762 }
3763
3764 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3765 card->name, ((revision > 1) && (revision < 25)) ?
3766 'A' + revision - 1 : '?', membase, srambase,
3767 card->sramsize / 1024);
3768
3769 if (init_card(dev)) {
3770 printk("%s: init_card failed\n", card->name);
3771 err = -EIO;
3772 goto err_out_deinit_card;
3773 }
3774
3775 dev->ci_range.vpi_bits = card->vpibits;
3776 dev->ci_range.vci_bits = card->vcibits;
3777 dev->link_rate = card->link_pcr;
3778
3779 if (dev->phy->start)
3780 dev->phy->start(dev);
3781
3782 if (idt77252_dev_open(card)) {
3783 printk("%s: dev_open failed\n", card->name);
3784 err = -EIO;
3785 goto err_out_stop;
3786 }
3787
3788 *last = card;
3789 last = &card->next;
3790 index++;
3791
3792 return 0;
3793
3794 err_out_stop:
3795 if (dev->phy->stop)
3796 dev->phy->stop(dev);
3797
3798 err_out_deinit_card:
3799 deinit_card(card);
3800
3801 err_out_iounmap:
3802 iounmap(card->membase);
3803
3804 err_out_free_card:
3805 kfree(card);
3806
3807 err_out_disable_pdev:
3808 pci_disable_device(pcidev);
3809 return err;
3810 }
3811
3812 static struct pci_device_id idt77252_pci_tbl[] =
3813 {
3814 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3816 { 0, }
3817 };
3818
3819 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3820
3821 static struct pci_driver idt77252_driver = {
3822 .name = "idt77252",
3823 .id_table = idt77252_pci_tbl,
3824 .probe = idt77252_init_one,
3825 };
3826
3827 static int __init idt77252_init(void)
3828 {
3829 struct sk_buff *skb;
3830
3831 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3832
3833 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3834 sizeof(struct idt77252_skb_prv)) {
3835 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3836 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3837 (unsigned long) sizeof(struct atm_skb_data) +
3838 sizeof(struct idt77252_skb_prv));
3839 return -EIO;
3840 }
3841
3842 return pci_register_driver(&idt77252_driver);
3843 }
3844
3845 static void __exit idt77252_exit(void)
3846 {
3847 struct idt77252_dev *card;
3848 struct atm_dev *dev;
3849
3850 pci_unregister_driver(&idt77252_driver);
3851
3852 while (idt77252_chain) {
3853 card = idt77252_chain;
3854 dev = card->atmdev;
3855 idt77252_chain = card->next;
3856
3857 if (dev->phy->stop)
3858 dev->phy->stop(dev);
3859 deinit_card(card);
3860 pci_disable_device(card->pcidev);
3861 kfree(card);
3862 }
3863
3864 DIPRINTK("idt77252: finished cleanup-module().\n");
3865 }
3866
3867 module_init(idt77252_init);
3868 module_exit(idt77252_exit);
3869
3870 MODULE_LICENSE("GPL");
3871
3872 module_param(vpibits, uint, 0);
3873 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3874 #ifdef CONFIG_ATM_IDT77252_DEBUG
3875 module_param(debug, ulong, 0644);
3876 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3877 #endif
3878
3879 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3880 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
Verdex Pro support