2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <asm/uaccess.h>
12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t
*, uint32_t);
13 static void qla2x00_nv_deselect(scsi_qla_host_t
*);
14 static void qla2x00_nv_write(scsi_qla_host_t
*, uint16_t);
17 * NVRAM support routines
21 * qla2x00_lock_nvram_access() -
25 qla2x00_lock_nvram_access(scsi_qla_host_t
*ha
)
28 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
30 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
31 data
= RD_REG_WORD(®
->nvram
);
32 while (data
& NVR_BUSY
) {
34 data
= RD_REG_WORD(®
->nvram
);
38 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
39 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
41 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
42 while ((data
& BIT_0
) == 0) {
45 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
46 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
48 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
54 * qla2x00_unlock_nvram_access() -
58 qla2x00_unlock_nvram_access(scsi_qla_host_t
*ha
)
60 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
62 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
63 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
64 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
72 * @addr: Address in NVRAM to read
74 * Returns the word read from nvram @addr.
77 qla2x00_get_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
)
84 data
= qla2x00_nvram_request(ha
, nv_cmd
);
90 * qla2x00_write_nvram_word() - Write NVRAM data.
92 * @addr: Address in NVRAM to write
93 * @data: word to program
96 qla2x00_write_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
)
100 uint32_t nv_cmd
, wait_cnt
;
101 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
103 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
104 qla2x00_nv_write(ha
, 0);
105 qla2x00_nv_write(ha
, 0);
107 for (word
= 0; word
< 8; word
++)
108 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
110 qla2x00_nv_deselect(ha
);
113 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
116 for (count
= 0; count
< 27; count
++) {
118 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
120 qla2x00_nv_write(ha
, 0);
125 qla2x00_nv_deselect(ha
);
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
129 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
130 wait_cnt
= NVR_WAIT_CNT
;
133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
134 __func__
, ha
->host_no
));
138 word
= RD_REG_WORD(®
->nvram
);
139 } while ((word
& NVR_DATA_IN
) == 0);
141 qla2x00_nv_deselect(ha
);
144 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
145 for (count
= 0; count
< 10; count
++)
146 qla2x00_nv_write(ha
, 0);
148 qla2x00_nv_deselect(ha
);
152 qla2x00_write_nvram_word_tmo(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
,
158 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
162 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
163 qla2x00_nv_write(ha
, 0);
164 qla2x00_nv_write(ha
, 0);
166 for (word
= 0; word
< 8; word
++)
167 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
169 qla2x00_nv_deselect(ha
);
172 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
175 for (count
= 0; count
< 27; count
++) {
177 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
179 qla2x00_nv_write(ha
, 0);
184 qla2x00_nv_deselect(ha
);
186 /* Wait for NVRAM to become ready */
187 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
188 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
191 word
= RD_REG_WORD(®
->nvram
);
193 ret
= QLA_FUNCTION_FAILED
;
196 } while ((word
& NVR_DATA_IN
) == 0);
198 qla2x00_nv_deselect(ha
);
201 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
202 for (count
= 0; count
< 10; count
++)
203 qla2x00_nv_write(ha
, 0);
205 qla2x00_nv_deselect(ha
);
211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
214 * @nv_cmd: NVRAM command
216 * Bit definitions for NVRAM command:
219 * Bit 25, 24 = opcode
220 * Bit 23-16 = address
221 * Bit 15-0 = write data
223 * Returns the word read from nvram @addr.
226 qla2x00_nvram_request(scsi_qla_host_t
*ha
, uint32_t nv_cmd
)
229 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
233 /* Send command to NVRAM. */
235 for (cnt
= 0; cnt
< 11; cnt
++) {
237 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
239 qla2x00_nv_write(ha
, 0);
243 /* Read data from NVRAM. */
244 for (cnt
= 0; cnt
< 16; cnt
++) {
245 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
246 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
249 reg_data
= RD_REG_WORD(®
->nvram
);
250 if (reg_data
& NVR_DATA_IN
)
252 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
253 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
258 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
259 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
266 * qla2x00_nv_write() - Clean NVRAM operations.
270 qla2x00_nv_deselect(scsi_qla_host_t
*ha
)
272 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
274 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
275 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
282 * @data: Serial interface selector
285 qla2x00_nv_write(scsi_qla_host_t
*ha
, uint16_t data
)
287 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
289 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
290 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
292 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
294 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
296 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
297 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
302 * qla2x00_clear_nvram_protection() -
306 qla2x00_clear_nvram_protection(scsi_qla_host_t
*ha
)
309 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
310 uint32_t word
, wait_cnt
;
311 uint16_t wprot
, wprot_old
;
313 /* Clear NVRAM write protection. */
314 ret
= QLA_FUNCTION_FAILED
;
316 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
317 stat
= qla2x00_write_nvram_word_tmo(ha
, ha
->nvram_base
,
318 __constant_cpu_to_le16(0x1234), 100000);
319 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
320 if (stat
!= QLA_SUCCESS
|| wprot
!= 0x1234) {
322 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
323 qla2x00_nv_write(ha
, 0);
324 qla2x00_nv_write(ha
, 0);
325 for (word
= 0; word
< 8; word
++)
326 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
328 qla2x00_nv_deselect(ha
);
330 /* Enable protection register. */
331 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
332 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
333 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
334 for (word
= 0; word
< 8; word
++)
335 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
337 qla2x00_nv_deselect(ha
);
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
341 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
342 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
343 for (word
= 0; word
< 8; word
++)
344 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
346 qla2x00_nv_deselect(ha
);
348 /* Wait for NVRAM to become ready. */
349 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
350 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
351 wait_cnt
= NVR_WAIT_CNT
;
354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
355 "ready...\n", __func__
,
360 word
= RD_REG_WORD(®
->nvram
);
361 } while ((word
& NVR_DATA_IN
) == 0);
366 qla2x00_write_nvram_word(ha
, ha
->nvram_base
, wprot_old
);
372 qla2x00_set_nvram_protection(scsi_qla_host_t
*ha
, int stat
)
374 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
375 uint32_t word
, wait_cnt
;
377 if (stat
!= QLA_SUCCESS
)
380 /* Set NVRAM write protection. */
382 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
383 qla2x00_nv_write(ha
, 0);
384 qla2x00_nv_write(ha
, 0);
385 for (word
= 0; word
< 8; word
++)
386 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
388 qla2x00_nv_deselect(ha
);
390 /* Enable protection register. */
391 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
392 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
393 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
394 for (word
= 0; word
< 8; word
++)
395 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
397 qla2x00_nv_deselect(ha
);
399 /* Enable protection register. */
400 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
401 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
402 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
403 for (word
= 0; word
< 8; word
++)
404 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
406 qla2x00_nv_deselect(ha
);
408 /* Wait for NVRAM to become ready. */
409 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
410 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
411 wait_cnt
= NVR_WAIT_CNT
;
414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
415 __func__
, ha
->host_no
));
419 word
= RD_REG_WORD(®
->nvram
);
420 } while ((word
& NVR_DATA_IN
) == 0);
424 /*****************************************************************************/
425 /* Flash Manipulation Routines */
426 /*****************************************************************************/
428 static inline uint32_t
429 flash_conf_to_access_addr(uint32_t faddr
)
431 return FARX_ACCESS_FLASH_CONF
| faddr
;
434 static inline uint32_t
435 flash_data_to_access_addr(uint32_t faddr
)
437 return FARX_ACCESS_FLASH_DATA
| faddr
;
440 static inline uint32_t
441 nvram_conf_to_access_addr(uint32_t naddr
)
443 return FARX_ACCESS_NVRAM_CONF
| naddr
;
446 static inline uint32_t
447 nvram_data_to_access_addr(uint32_t naddr
)
449 return FARX_ACCESS_NVRAM_DATA
| naddr
;
453 qla24xx_read_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
)
457 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
459 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
460 /* Wait for READ cycle to complete. */
463 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
464 rval
== QLA_SUCCESS
; cnt
--) {
468 rval
= QLA_FUNCTION_TIMEOUT
;
472 /* TODO: What happens if we time out? */
474 if (rval
== QLA_SUCCESS
)
475 data
= RD_REG_DWORD(®
->flash_data
);
481 qla24xx_read_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
486 /* Dword reads to flash. */
487 for (i
= 0; i
< dwords
; i
++, faddr
++)
488 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
489 flash_data_to_access_addr(faddr
)));
495 qla24xx_write_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
, uint32_t data
)
499 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
501 WRT_REG_DWORD(®
->flash_data
, data
);
502 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
503 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
504 /* Wait for Write cycle to complete. */
506 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
507 rval
== QLA_SUCCESS
; cnt
--) {
511 rval
= QLA_FUNCTION_TIMEOUT
;
518 qla24xx_get_flash_manufacturer(scsi_qla_host_t
*ha
, uint8_t *man_id
,
523 ids
= qla24xx_read_flash_dword(ha
, flash_data_to_access_addr(0xd03ab));
525 *flash_id
= MSB(ids
);
527 /* Check if man_id and flash_id are valid. */
528 if (ids
!= 0xDEADDEAD && (*man_id
== 0 || *flash_id
== 0)) {
529 /* Read information using 0x9f opcode
530 * Device ID, Mfg ID would be read in the format:
531 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
532 * Example: ATMEL 0x00 01 45 1F
533 * Extract MFG and Dev ID from last two bytes.
535 ids
= qla24xx_read_flash_dword(ha
,
536 flash_data_to_access_addr(0xd009f));
538 *flash_id
= MSB(ids
);
543 qla24xx_write_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
548 uint32_t sec_mask
, rest_addr
, conf_addr
, sec_end_mask
;
549 uint32_t fdata
, findex
;
550 uint8_t man_id
, flash_id
;
551 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
555 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
556 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__
,
557 ha
->host_no
, man_id
, flash_id
));
560 conf_addr
= flash_conf_to_access_addr(0x03d8);
562 case 0xbf: /* STT flash. */
565 if (flash_id
== 0x80)
566 conf_addr
= flash_conf_to_access_addr(0x0352);
568 case 0x13: /* ST M25P80. */
572 case 0x1f: // Atmel 26DF081A
575 sec_end_mask
= 0x003ff;
576 conf_addr
= flash_conf_to_access_addr(0x0320);
579 /* Default to 64 kb sector size. */
585 /* Enable flash write. */
586 WRT_REG_DWORD(®
->ctrl_status
,
587 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
588 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
590 /* Disable flash write-protection. */
591 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0);
592 /* Some flash parts need an additional zero-write to clear bits.*/
593 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0);
595 do { /* Loop once to provide quick error exit. */
596 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
597 if (man_id
== 0x1f) {
599 fdata
= findex
& sec_mask
;
602 fdata
= (findex
& sec_mask
) << 2;
605 /* Are we at the beginning of a sector? */
606 if ((findex
& rest_addr
) == 0) {
608 * Do sector unprotect at 4K boundry for Atmel
612 qla24xx_write_flash_dword(ha
,
613 flash_conf_to_access_addr(0x0339),
614 (fdata
& 0xff00) | ((fdata
<< 16) &
615 0xff0000) | ((fdata
>> 16) & 0xff));
616 ret
= qla24xx_write_flash_dword(ha
, conf_addr
,
617 (fdata
& 0xff00) |((fdata
<< 16) &
618 0xff0000) | ((fdata
>> 16) & 0xff));
619 if (ret
!= QLA_SUCCESS
) {
620 DEBUG9(printk("%s(%ld) Unable to flash "
621 "sector: address=%x.\n", __func__
,
622 ha
->host_no
, faddr
));
626 ret
= qla24xx_write_flash_dword(ha
,
627 flash_data_to_access_addr(faddr
),
628 cpu_to_le32(*dwptr
));
629 if (ret
!= QLA_SUCCESS
) {
630 DEBUG9(printk("%s(%ld) Unable to program flash "
631 "address=%x data=%x.\n", __func__
,
632 ha
->host_no
, faddr
, *dwptr
));
636 /* Do sector protect at 4K boundry for Atmel part. */
637 if (man_id
== 0x1f &&
638 ((faddr
& sec_end_mask
) == 0x3ff))
639 qla24xx_write_flash_dword(ha
,
640 flash_conf_to_access_addr(0x0336),
641 (fdata
& 0xff00) | ((fdata
<< 16) &
642 0xff0000) | ((fdata
>> 16) & 0xff));
646 /* Enable flash write-protection. */
647 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0x9c);
649 /* Disable flash write. */
650 WRT_REG_DWORD(®
->ctrl_status
,
651 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
652 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
658 qla2x00_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
664 /* Word reads to NVRAM via registers. */
665 wptr
= (uint16_t *)buf
;
666 qla2x00_lock_nvram_access(ha
);
667 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
668 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
670 qla2x00_unlock_nvram_access(ha
);
676 qla24xx_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
682 /* Dword reads to flash. */
683 dwptr
= (uint32_t *)buf
;
684 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
685 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
686 nvram_data_to_access_addr(naddr
)));
692 qla2x00_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
701 qla2x00_lock_nvram_access(ha
);
703 /* Disable NVRAM write-protection. */
704 stat
= qla2x00_clear_nvram_protection(ha
);
706 wptr
= (uint16_t *)buf
;
707 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
708 qla2x00_write_nvram_word(ha
, naddr
,
713 /* Enable NVRAM write-protection. */
714 qla2x00_set_nvram_protection(ha
, stat
);
716 qla2x00_unlock_nvram_access(ha
);
722 qla24xx_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
728 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
732 /* Enable flash write. */
733 WRT_REG_DWORD(®
->ctrl_status
,
734 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
735 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
737 /* Disable NVRAM write-protection. */
738 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
740 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
743 /* Dword writes to flash. */
744 dwptr
= (uint32_t *)buf
;
745 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
746 ret
= qla24xx_write_flash_dword(ha
,
747 nvram_data_to_access_addr(naddr
),
748 cpu_to_le32(*dwptr
));
749 if (ret
!= QLA_SUCCESS
) {
750 DEBUG9(printk("%s(%ld) Unable to program "
751 "nvram address=%x data=%x.\n", __func__
,
752 ha
->host_no
, naddr
, *dwptr
));
757 /* Enable NVRAM write-protection. */
758 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
761 /* Disable flash write. */
762 WRT_REG_DWORD(®
->ctrl_status
,
763 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
764 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
771 qla2x00_flip_colors(scsi_qla_host_t
*ha
, uint16_t *pflags
)
773 if (IS_QLA2322(ha
)) {
774 /* Flip all colors. */
775 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
777 ha
->beacon_color_state
= 0;
778 *pflags
= GPIO_LED_ALL_OFF
;
781 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
782 *pflags
= GPIO_LED_RGA_ON
;
785 /* Flip green led only. */
786 if (ha
->beacon_color_state
== QLA_LED_GRN_ON
) {
788 ha
->beacon_color_state
= 0;
789 *pflags
= GPIO_LED_GREEN_OFF_AMBER_OFF
;
792 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
793 *pflags
= GPIO_LED_GREEN_ON_AMBER_OFF
;
799 qla2x00_beacon_blink(struct scsi_qla_host
*ha
)
801 uint16_t gpio_enable
;
803 uint16_t led_color
= 0;
805 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
808 reg
= (struct device_reg_2xxx __iomem
*)ha
->pio_address
;
810 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
812 /* Save the Original GPIOE. */
813 if (ha
->pio_address
) {
814 gpio_enable
= RD_REG_WORD_PIO(®
->gpioe
);
815 gpio_data
= RD_REG_WORD_PIO(®
->gpiod
);
817 gpio_enable
= RD_REG_WORD(®
->gpioe
);
818 gpio_data
= RD_REG_WORD(®
->gpiod
);
821 /* Set the modified gpio_enable values */
822 gpio_enable
|= GPIO_LED_MASK
;
824 if (ha
->pio_address
) {
825 WRT_REG_WORD_PIO(®
->gpioe
, gpio_enable
);
827 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
828 RD_REG_WORD(®
->gpioe
);
831 qla2x00_flip_colors(ha
, &led_color
);
833 /* Clear out any previously set LED color. */
834 gpio_data
&= ~GPIO_LED_MASK
;
836 /* Set the new input LED color to GPIOD. */
837 gpio_data
|= led_color
;
839 /* Set the modified gpio_data values */
840 if (ha
->pio_address
) {
841 WRT_REG_WORD_PIO(®
->gpiod
, gpio_data
);
843 WRT_REG_WORD(®
->gpiod
, gpio_data
);
844 RD_REG_WORD(®
->gpiod
);
847 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
851 qla2x00_beacon_on(struct scsi_qla_host
*ha
)
853 uint16_t gpio_enable
;
856 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
858 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
859 ha
->fw_options
[1] |= FO1_DISABLE_GPIO6_7
;
861 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
862 qla_printk(KERN_WARNING
, ha
,
863 "Unable to update fw options (beacon on).\n");
864 return QLA_FUNCTION_FAILED
;
868 reg
= (struct device_reg_2xxx __iomem
*)ha
->pio_address
;
871 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
872 if (ha
->pio_address
) {
873 gpio_enable
= RD_REG_WORD_PIO(®
->gpioe
);
874 gpio_data
= RD_REG_WORD_PIO(®
->gpiod
);
876 gpio_enable
= RD_REG_WORD(®
->gpioe
);
877 gpio_data
= RD_REG_WORD(®
->gpiod
);
879 gpio_enable
|= GPIO_LED_MASK
;
881 /* Set the modified gpio_enable values. */
882 if (ha
->pio_address
) {
883 WRT_REG_WORD_PIO(®
->gpioe
, gpio_enable
);
885 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
886 RD_REG_WORD(®
->gpioe
);
889 /* Clear out previously set LED colour. */
890 gpio_data
&= ~GPIO_LED_MASK
;
891 if (ha
->pio_address
) {
892 WRT_REG_WORD_PIO(®
->gpiod
, gpio_data
);
894 WRT_REG_WORD(®
->gpiod
, gpio_data
);
895 RD_REG_WORD(®
->gpiod
);
897 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
900 * Let the per HBA timer kick off the blinking process based on
901 * the following flags. No need to do anything else now.
903 ha
->beacon_blink_led
= 1;
904 ha
->beacon_color_state
= 0;
910 qla2x00_beacon_off(struct scsi_qla_host
*ha
)
912 int rval
= QLA_SUCCESS
;
914 ha
->beacon_blink_led
= 0;
916 /* Set the on flag so when it gets flipped it will be off. */
918 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
920 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
922 ha
->isp_ops
.beacon_blink(ha
); /* This turns green LED off */
924 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
925 ha
->fw_options
[1] &= ~FO1_DISABLE_GPIO6_7
;
927 rval
= qla2x00_set_fw_options(ha
, ha
->fw_options
);
928 if (rval
!= QLA_SUCCESS
)
929 qla_printk(KERN_WARNING
, ha
,
930 "Unable to update fw options (beacon off).\n");
936 qla24xx_flip_colors(scsi_qla_host_t
*ha
, uint16_t *pflags
)
938 /* Flip all colors. */
939 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
941 ha
->beacon_color_state
= 0;
945 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
946 *pflags
= GPDX_LED_YELLOW_ON
| GPDX_LED_AMBER_ON
;
951 qla24xx_beacon_blink(struct scsi_qla_host
*ha
)
953 uint16_t led_color
= 0;
956 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
958 /* Save the Original GPIOD. */
959 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
960 gpio_data
= RD_REG_DWORD(®
->gpiod
);
962 /* Enable the gpio_data reg for update. */
963 gpio_data
|= GPDX_LED_UPDATE_MASK
;
965 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
966 gpio_data
= RD_REG_DWORD(®
->gpiod
);
968 /* Set the color bits. */
969 qla24xx_flip_colors(ha
, &led_color
);
971 /* Clear out any previously set LED color. */
972 gpio_data
&= ~GPDX_LED_COLOR_MASK
;
974 /* Set the new input LED color to GPIOD. */
975 gpio_data
|= led_color
;
977 /* Set the modified gpio_data values. */
978 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
979 gpio_data
= RD_REG_DWORD(®
->gpiod
);
980 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
984 qla24xx_beacon_on(struct scsi_qla_host
*ha
)
988 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
990 if (ha
->beacon_blink_led
== 0) {
991 /* Enable firmware for update */
992 ha
->fw_options
[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL
;
994 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
)
995 return QLA_FUNCTION_FAILED
;
997 if (qla2x00_get_fw_options(ha
, ha
->fw_options
) !=
999 qla_printk(KERN_WARNING
, ha
,
1000 "Unable to update fw options (beacon on).\n");
1001 return QLA_FUNCTION_FAILED
;
1004 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1005 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1007 /* Enable the gpio_data reg for update. */
1008 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1009 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1010 RD_REG_DWORD(®
->gpiod
);
1012 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1015 /* So all colors blink together. */
1016 ha
->beacon_color_state
= 0;
1018 /* Let the per HBA timer kick off the blinking process. */
1019 ha
->beacon_blink_led
= 1;
1025 qla24xx_beacon_off(struct scsi_qla_host
*ha
)
1028 unsigned long flags
;
1029 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1031 ha
->beacon_blink_led
= 0;
1032 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1034 ha
->isp_ops
.beacon_blink(ha
); /* Will flip to all off. */
1036 /* Give control back to firmware. */
1037 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1038 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1040 /* Disable the gpio_data reg for update. */
1041 gpio_data
&= ~GPDX_LED_UPDATE_MASK
;
1042 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1043 RD_REG_DWORD(®
->gpiod
);
1044 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1046 ha
->fw_options
[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1048 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
1049 qla_printk(KERN_WARNING
, ha
,
1050 "Unable to update fw options (beacon off).\n");
1051 return QLA_FUNCTION_FAILED
;
1054 if (qla2x00_get_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
1055 qla_printk(KERN_WARNING
, ha
,
1056 "Unable to get fw options (beacon off).\n");
1057 return QLA_FUNCTION_FAILED
;
1065 * Flash support routines
1069 * qla2x00_flash_enable() - Setup flash for reading and writing.
1073 qla2x00_flash_enable(scsi_qla_host_t
*ha
)
1076 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1078 data
= RD_REG_WORD(®
->ctrl_status
);
1079 data
|= CSR_FLASH_ENABLE
;
1080 WRT_REG_WORD(®
->ctrl_status
, data
);
1081 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1085 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1089 qla2x00_flash_disable(scsi_qla_host_t
*ha
)
1092 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1094 data
= RD_REG_WORD(®
->ctrl_status
);
1095 data
&= ~(CSR_FLASH_ENABLE
);
1096 WRT_REG_WORD(®
->ctrl_status
, data
);
1097 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1101 * qla2x00_read_flash_byte() - Reads a byte from flash
1103 * @addr: Address in flash to read
1105 * A word is read from the chip, but, only the lower byte is valid.
1107 * Returns the byte read from flash @addr.
1110 qla2x00_read_flash_byte(scsi_qla_host_t
*ha
, uint32_t addr
)
1113 uint16_t bank_select
;
1114 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1116 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1118 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1119 /* Specify 64K address range: */
1120 /* clear out Module Select and Flash Address bits [19:16]. */
1121 bank_select
&= ~0xf8;
1122 bank_select
|= addr
>> 12 & 0xf0;
1123 bank_select
|= CSR_FLASH_64K_BANK
;
1124 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1125 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1127 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1128 data
= RD_REG_WORD(®
->flash_data
);
1130 return (uint8_t)data
;
1133 /* Setup bit 16 of flash address. */
1134 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1135 bank_select
|= CSR_FLASH_64K_BANK
;
1136 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1137 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1138 } else if (((addr
& BIT_16
) == 0) &&
1139 (bank_select
& CSR_FLASH_64K_BANK
)) {
1140 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1141 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1142 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1145 /* Always perform IO mapped accesses to the FLASH registers. */
1146 if (ha
->pio_address
) {
1149 reg
= (struct device_reg_2xxx __iomem
*)ha
->pio_address
;
1150 WRT_REG_WORD_PIO(®
->flash_address
, (uint16_t)addr
);
1152 data
= RD_REG_WORD_PIO(®
->flash_data
);
1155 data2
= RD_REG_WORD_PIO(®
->flash_data
);
1156 } while (data
!= data2
);
1158 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1159 data
= qla2x00_debounce_register(®
->flash_data
);
1162 return (uint8_t)data
;
1166 * qla2x00_write_flash_byte() - Write a byte to flash
1168 * @addr: Address in flash to write
1169 * @data: Data to write
1172 qla2x00_write_flash_byte(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t data
)
1174 uint16_t bank_select
;
1175 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1177 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1178 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1179 /* Specify 64K address range: */
1180 /* clear out Module Select and Flash Address bits [19:16]. */
1181 bank_select
&= ~0xf8;
1182 bank_select
|= addr
>> 12 & 0xf0;
1183 bank_select
|= CSR_FLASH_64K_BANK
;
1184 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1185 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1187 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1188 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1189 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1190 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1195 /* Setup bit 16 of flash address. */
1196 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1197 bank_select
|= CSR_FLASH_64K_BANK
;
1198 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1199 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1200 } else if (((addr
& BIT_16
) == 0) &&
1201 (bank_select
& CSR_FLASH_64K_BANK
)) {
1202 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1203 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1204 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1207 /* Always perform IO mapped accesses to the FLASH registers. */
1208 if (ha
->pio_address
) {
1209 reg
= (struct device_reg_2xxx __iomem
*)ha
->pio_address
;
1210 WRT_REG_WORD_PIO(®
->flash_address
, (uint16_t)addr
);
1211 WRT_REG_WORD_PIO(®
->flash_data
, (uint16_t)data
);
1213 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1214 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1215 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1216 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1221 * qla2x00_poll_flash() - Polls flash for completion.
1223 * @addr: Address in flash to poll
1224 * @poll_data: Data to be polled
1225 * @man_id: Flash manufacturer ID
1226 * @flash_id: Flash ID
1228 * This function polls the device until bit 7 of what is read matches data
1229 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1230 * out (a fatal error). The flash book recommeds reading bit 7 again after
1231 * reading bit 5 as a 1.
1233 * Returns 0 on success, else non-zero.
1236 qla2x00_poll_flash(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t poll_data
,
1237 uint8_t man_id
, uint8_t flash_id
)
1245 /* Wait for 30 seconds for command to finish. */
1247 for (cnt
= 3000000; cnt
; cnt
--) {
1248 flash_data
= qla2x00_read_flash_byte(ha
, addr
);
1249 if ((flash_data
& BIT_7
) == poll_data
) {
1254 if (man_id
!= 0x40 && man_id
!= 0xda) {
1255 if ((flash_data
& BIT_5
) && cnt
> 2)
1266 * qla2x00_program_flash_address() - Programs a flash address
1268 * @addr: Address in flash to program
1269 * @data: Data to be written in flash
1270 * @man_id: Flash manufacturer ID
1271 * @flash_id: Flash ID
1273 * Returns 0 on success, else non-zero.
1276 qla2x00_program_flash_address(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t data
,
1277 uint8_t man_id
, uint8_t flash_id
)
1279 /* Write Program Command Sequence. */
1280 if (IS_OEM_001(ha
)) {
1281 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1282 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1283 qla2x00_write_flash_byte(ha
, 0xaaa, 0xa0);
1284 qla2x00_write_flash_byte(ha
, addr
, data
);
1286 if (man_id
== 0xda && flash_id
== 0xc1) {
1287 qla2x00_write_flash_byte(ha
, addr
, data
);
1291 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1292 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1293 qla2x00_write_flash_byte(ha
, 0x5555, 0xa0);
1294 qla2x00_write_flash_byte(ha
, addr
, data
);
1300 /* Wait for write to complete. */
1301 return qla2x00_poll_flash(ha
, addr
, data
, man_id
, flash_id
);
1305 * qla2x00_erase_flash() - Erase the flash.
1307 * @man_id: Flash manufacturer ID
1308 * @flash_id: Flash ID
1310 * Returns 0 on success, else non-zero.
1313 qla2x00_erase_flash(scsi_qla_host_t
*ha
, uint8_t man_id
, uint8_t flash_id
)
1315 /* Individual Sector Erase Command Sequence */
1316 if (IS_OEM_001(ha
)) {
1317 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1318 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1319 qla2x00_write_flash_byte(ha
, 0xaaa, 0x80);
1320 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1321 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1322 qla2x00_write_flash_byte(ha
, 0xaaa, 0x10);
1324 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1325 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1326 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1327 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1328 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1329 qla2x00_write_flash_byte(ha
, 0x5555, 0x10);
1334 /* Wait for erase to complete. */
1335 return qla2x00_poll_flash(ha
, 0x00, 0x80, man_id
, flash_id
);
1339 * qla2x00_erase_flash_sector() - Erase a flash sector.
1341 * @addr: Flash sector to erase
1342 * @sec_mask: Sector address mask
1343 * @man_id: Flash manufacturer ID
1344 * @flash_id: Flash ID
1346 * Returns 0 on success, else non-zero.
1349 qla2x00_erase_flash_sector(scsi_qla_host_t
*ha
, uint32_t addr
,
1350 uint32_t sec_mask
, uint8_t man_id
, uint8_t flash_id
)
1352 /* Individual Sector Erase Command Sequence */
1353 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1354 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1355 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1356 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1357 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1358 if (man_id
== 0x1f && flash_id
== 0x13)
1359 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x10);
1361 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x30);
1365 /* Wait for erase to complete. */
1366 return qla2x00_poll_flash(ha
, addr
, 0x80, man_id
, flash_id
);
1370 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1371 * @man_id: Flash manufacturer ID
1372 * @flash_id: Flash ID
1375 qla2x00_get_flash_manufacturer(scsi_qla_host_t
*ha
, uint8_t *man_id
,
1378 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1379 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1380 qla2x00_write_flash_byte(ha
, 0x5555, 0x90);
1381 *man_id
= qla2x00_read_flash_byte(ha
, 0x0000);
1382 *flash_id
= qla2x00_read_flash_byte(ha
, 0x0001);
1383 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1384 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1385 qla2x00_write_flash_byte(ha
, 0x5555, 0xf0);
1389 qla2x00_read_flash_data(scsi_qla_host_t
*ha
, uint8_t *tmp_buf
, uint32_t saddr
,
1392 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1393 uint32_t midpoint
, ilength
;
1396 midpoint
= length
/ 2;
1398 WRT_REG_WORD(®
->nvram
, 0);
1399 RD_REG_WORD(®
->nvram
);
1400 for (ilength
= 0; ilength
< length
; saddr
++, ilength
++, tmp_buf
++) {
1401 if (ilength
== midpoint
) {
1402 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1403 RD_REG_WORD(®
->nvram
);
1405 data
= qla2x00_read_flash_byte(ha
, saddr
);
1414 qla2x00_suspend_hba(struct scsi_qla_host
*ha
)
1417 unsigned long flags
;
1418 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1421 scsi_block_requests(ha
->host
);
1422 ha
->isp_ops
.disable_intrs(ha
);
1423 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1426 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1427 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
1428 RD_REG_WORD(®
->hccr
);
1429 if (IS_QLA2100(ha
) || IS_QLA2200(ha
) || IS_QLA2300(ha
)) {
1430 for (cnt
= 0; cnt
< 30000; cnt
++) {
1431 if ((RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) != 0)
1438 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1442 qla2x00_resume_hba(struct scsi_qla_host
*ha
)
1445 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1446 set_bit(ISP_ABORT_NEEDED
, &ha
->dpc_flags
);
1447 qla2xxx_wake_dpc(ha
);
1448 qla2x00_wait_for_hba_online(ha
);
1449 scsi_unblock_requests(ha
->host
);
1453 qla2x00_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1454 uint32_t offset
, uint32_t length
)
1456 uint32_t addr
, midpoint
;
1458 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1461 qla2x00_suspend_hba(ha
);
1464 midpoint
= ha
->optrom_size
/ 2;
1466 qla2x00_flash_enable(ha
);
1467 WRT_REG_WORD(®
->nvram
, 0);
1468 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
1469 for (addr
= offset
, data
= buf
; addr
< length
; addr
++, data
++) {
1470 if (addr
== midpoint
) {
1471 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1472 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
1475 *data
= qla2x00_read_flash_byte(ha
, addr
);
1477 qla2x00_flash_disable(ha
);
1480 qla2x00_resume_hba(ha
);
1486 qla2x00_write_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1487 uint32_t offset
, uint32_t length
)
1491 uint8_t man_id
, flash_id
, sec_number
, data
;
1493 uint32_t addr
, liter
, sec_mask
, rest_addr
;
1494 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1497 qla2x00_suspend_hba(ha
);
1502 /* Reset ISP chip. */
1503 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
1504 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
1506 /* Go with write. */
1507 qla2x00_flash_enable(ha
);
1508 do { /* Loop once to provide quick error exit */
1509 /* Structure of flash memory based on manufacturer */
1510 if (IS_OEM_001(ha
)) {
1511 /* OEM variant with special flash part. */
1512 man_id
= flash_id
= 0;
1517 qla2x00_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
1519 case 0x20: /* ST flash. */
1520 if (flash_id
== 0xd2 || flash_id
== 0xe3) {
1522 * ST m29w008at part - 64kb sector size with
1523 * 32kb,8kb,8kb,16kb sectors at memory address
1531 * ST m29w010b part - 16kb sector size
1532 * Default to 16kb sectors
1537 case 0x40: /* Mostel flash. */
1538 /* Mostel v29c51001 part - 512 byte sector size. */
1542 case 0xbf: /* SST flash. */
1543 /* SST39sf10 part - 4kb sector size. */
1547 case 0xda: /* Winbond flash. */
1548 /* Winbond W29EE011 part - 256 byte sector size. */
1552 case 0xc2: /* Macronix flash. */
1553 /* 64k sector size. */
1554 if (flash_id
== 0x38 || flash_id
== 0x4f) {
1559 /* Fall through... */
1561 case 0x1f: /* Atmel flash. */
1562 /* 512k sector size. */
1563 if (flash_id
== 0x13) {
1564 rest_addr
= 0x7fffffff;
1565 sec_mask
= 0x80000000;
1568 /* Fall through... */
1570 case 0x01: /* AMD flash. */
1571 if (flash_id
== 0x38 || flash_id
== 0x40 ||
1573 /* Am29LV081 part - 64kb sector size. */
1574 /* Am29LV002BT part - 64kb sector size. */
1578 } else if (flash_id
== 0x3e) {
1580 * Am29LV008b part - 64kb sector size with
1581 * 32kb,8kb,8kb,16kb sector at memory address
1587 } else if (flash_id
== 0x20 || flash_id
== 0x6e) {
1589 * Am29LV010 part or AM29f010 - 16kb sector
1595 } else if (flash_id
== 0x6d) {
1596 /* Am29LV001 part - 8kb sector size. */
1602 /* Default to 16 kb sector size. */
1609 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1610 if (qla2x00_erase_flash(ha
, man_id
, flash_id
)) {
1611 rval
= QLA_FUNCTION_FAILED
;
1616 for (addr
= offset
, liter
= 0; liter
< length
; liter
++,
1619 /* Are we at the beginning of a sector? */
1620 if ((addr
& rest_addr
) == 0) {
1621 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1622 if (addr
>= 0x10000UL
) {
1623 if (((addr
>> 12) & 0xf0) &&
1625 flash_id
== 0x3e) ||
1627 flash_id
== 0xd2))) {
1629 if (sec_number
== 1) {
1650 } else if (addr
== ha
->optrom_size
/ 2) {
1651 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1652 RD_REG_WORD(®
->nvram
);
1655 if (flash_id
== 0xda && man_id
== 0xc1) {
1656 qla2x00_write_flash_byte(ha
, 0x5555,
1658 qla2x00_write_flash_byte(ha
, 0x2aaa,
1660 qla2x00_write_flash_byte(ha
, 0x5555,
1662 } else if (!IS_QLA2322(ha
) && !IS_QLA6322(ha
)) {
1664 if (qla2x00_erase_flash_sector(ha
,
1665 addr
, sec_mask
, man_id
,
1667 rval
= QLA_FUNCTION_FAILED
;
1670 if (man_id
== 0x01 && flash_id
== 0x6d)
1675 if (man_id
== 0x01 && flash_id
== 0x6d) {
1676 if (sec_number
== 1 &&
1677 addr
== (rest_addr
- 1)) {
1680 } else if (sec_number
== 3 && (addr
& 0x7ffe)) {
1686 if (qla2x00_program_flash_address(ha
, addr
, data
,
1687 man_id
, flash_id
)) {
1688 rval
= QLA_FUNCTION_FAILED
;
1694 qla2x00_flash_disable(ha
);
1697 qla2x00_resume_hba(ha
);
1703 qla24xx_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1704 uint32_t offset
, uint32_t length
)
1707 scsi_block_requests(ha
->host
);
1708 ha
->isp_ops
.disable_intrs(ha
);
1709 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1712 qla24xx_read_flash_data(ha
, (uint32_t *)buf
, offset
>> 2, length
>> 2);
1715 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1716 ha
->isp_ops
.enable_intrs(ha
);
1717 scsi_unblock_requests(ha
->host
);
1723 qla24xx_write_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1724 uint32_t offset
, uint32_t length
)
1729 scsi_block_requests(ha
->host
);
1730 ha
->isp_ops
.disable_intrs(ha
);
1731 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1733 /* Go with write. */
1734 rval
= qla24xx_write_flash_data(ha
, (uint32_t *)buf
, offset
>> 2,
1737 /* Resume HBA -- RISC reset needed. */
1738 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1739 set_bit(ISP_ABORT_NEEDED
, &ha
->dpc_flags
);
1740 qla2xxx_wake_dpc(ha
);
1741 qla2x00_wait_for_hba_online(ha
);
1742 scsi_unblock_requests(ha
->host
);
1748 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1750 * @pcids: Pointer to the FCODE PCI data structure
1752 * The process of retrieving the FCODE version information is at best
1753 * described as interesting.
1755 * Within the first 100h bytes of the image an ASCII string is present
1756 * which contains several pieces of information including the FCODE
1757 * version. Unfortunately it seems the only reliable way to retrieve
1758 * the version is by scanning for another sentinel within the string,
1759 * the FCODE build date:
1761 * ... 2.00.02 10/17/02 ...
1763 * Returns QLA_SUCCESS on successful retrieval of version.
1766 qla2x00_get_fcode_version(scsi_qla_host_t
*ha
, uint32_t pcids
)
1768 int ret
= QLA_FUNCTION_FAILED
;
1769 uint32_t istart
, iend
, iter
, vend
;
1770 uint8_t do_next
, rbyte
, *vbyte
;
1772 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
1774 /* Skip the PCI data structure. */
1776 ((qla2x00_read_flash_byte(ha
, pcids
+ 0x0B) << 8) |
1777 qla2x00_read_flash_byte(ha
, pcids
+ 0x0A));
1778 iend
= istart
+ 0x100;
1780 /* Scan for the sentinel date string...eeewww. */
1783 while ((iter
< iend
) && !do_next
) {
1785 if (qla2x00_read_flash_byte(ha
, iter
) == '/') {
1786 if (qla2x00_read_flash_byte(ha
, iter
+ 2) ==
1789 else if (qla2x00_read_flash_byte(ha
,
1797 /* Backtrack to previous ' ' (space). */
1799 while ((iter
> istart
) && !do_next
) {
1801 if (qla2x00_read_flash_byte(ha
, iter
) == ' ')
1808 * Mark end of version tag, and find previous ' ' (space) or
1809 * string length (recent FCODE images -- major hack ahead!!!).
1813 while ((iter
> istart
) && !do_next
) {
1815 rbyte
= qla2x00_read_flash_byte(ha
, iter
);
1816 if (rbyte
== ' ' || rbyte
== 0xd || rbyte
== 0x10)
1822 /* Mark beginning of version tag, and copy data. */
1824 if ((vend
- iter
) &&
1825 ((vend
- iter
) < sizeof(ha
->fcode_revision
))) {
1826 vbyte
= ha
->fcode_revision
;
1827 while (iter
<= vend
) {
1828 *vbyte
++ = qla2x00_read_flash_byte(ha
, iter
);
1835 if (ret
!= QLA_SUCCESS
)
1836 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
1840 qla2x00_get_flash_version(scsi_qla_host_t
*ha
, void *mbuf
)
1842 int ret
= QLA_SUCCESS
;
1843 uint8_t code_type
, last_image
;
1844 uint32_t pcihdr
, pcids
;
1848 if (!ha
->pio_address
|| !mbuf
)
1849 return QLA_FUNCTION_FAILED
;
1851 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
1852 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
1853 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
1854 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
1856 qla2x00_flash_enable(ha
);
1858 /* Begin with first PCI expansion ROM header. */
1862 /* Verify PCI expansion ROM header. */
1863 if (qla2x00_read_flash_byte(ha
, pcihdr
) != 0x55 ||
1864 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x01) != 0xaa) {
1866 DEBUG2(printk("scsi(%ld): No matching ROM "
1867 "signature.\n", ha
->host_no
));
1868 ret
= QLA_FUNCTION_FAILED
;
1872 /* Locate PCI data structure. */
1874 ((qla2x00_read_flash_byte(ha
, pcihdr
+ 0x19) << 8) |
1875 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x18));
1877 /* Validate signature of PCI data structure. */
1878 if (qla2x00_read_flash_byte(ha
, pcids
) != 'P' ||
1879 qla2x00_read_flash_byte(ha
, pcids
+ 0x1) != 'C' ||
1880 qla2x00_read_flash_byte(ha
, pcids
+ 0x2) != 'I' ||
1881 qla2x00_read_flash_byte(ha
, pcids
+ 0x3) != 'R') {
1882 /* Incorrect header. */
1883 DEBUG2(printk("%s(): PCI data struct not found "
1884 "pcir_adr=%x.\n", __func__
, pcids
));
1885 ret
= QLA_FUNCTION_FAILED
;
1890 code_type
= qla2x00_read_flash_byte(ha
, pcids
+ 0x14);
1891 switch (code_type
) {
1892 case ROM_CODE_TYPE_BIOS
:
1893 /* Intel x86, PC-AT compatible. */
1894 ha
->bios_revision
[0] =
1895 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
1896 ha
->bios_revision
[1] =
1897 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
1898 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__
,
1899 ha
->bios_revision
[1], ha
->bios_revision
[0]));
1901 case ROM_CODE_TYPE_FCODE
:
1902 /* Open Firmware standard for PCI (FCode). */
1904 qla2x00_get_fcode_version(ha
, pcids
);
1906 case ROM_CODE_TYPE_EFI
:
1907 /* Extensible Firmware Interface (EFI). */
1908 ha
->efi_revision
[0] =
1909 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
1910 ha
->efi_revision
[1] =
1911 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
1912 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__
,
1913 ha
->efi_revision
[1], ha
->efi_revision
[0]));
1916 DEBUG2(printk("%s(): Unrecognized code type %x at "
1917 "pcids %x.\n", __func__
, code_type
, pcids
));
1921 last_image
= qla2x00_read_flash_byte(ha
, pcids
+ 0x15) & BIT_7
;
1923 /* Locate next PCI expansion ROM. */
1924 pcihdr
+= ((qla2x00_read_flash_byte(ha
, pcids
+ 0x11) << 8) |
1925 qla2x00_read_flash_byte(ha
, pcids
+ 0x10)) * 512;
1926 } while (!last_image
);
1928 if (IS_QLA2322(ha
)) {
1929 /* Read firmware image information. */
1930 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
1932 memset(dbyte
, 0, 8);
1933 dcode
= (uint16_t *)dbyte
;
1935 qla2x00_read_flash_data(ha
, dbyte
, FA_RISC_CODE_ADDR
* 4 + 10,
1937 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
1938 __func__
, ha
->host_no
));
1939 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte
, 8));
1941 if ((dcode
[0] == 0xffff && dcode
[1] == 0xffff &&
1942 dcode
[2] == 0xffff && dcode
[3] == 0xffff) ||
1943 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
1945 DEBUG2(printk("%s(): Unrecognized fw revision at "
1946 "%x.\n", __func__
, FA_RISC_CODE_ADDR
* 4));
1948 /* values are in big endian */
1949 ha
->fw_revision
[0] = dbyte
[0] << 16 | dbyte
[1];
1950 ha
->fw_revision
[1] = dbyte
[2] << 16 | dbyte
[3];
1951 ha
->fw_revision
[2] = dbyte
[4] << 16 | dbyte
[5];
1955 qla2x00_flash_disable(ha
);
1961 qla24xx_get_flash_version(scsi_qla_host_t
*ha
, void *mbuf
)
1963 int ret
= QLA_SUCCESS
;
1964 uint32_t pcihdr
, pcids
;
1967 uint8_t code_type
, last_image
;
1971 return QLA_FUNCTION_FAILED
;
1973 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
1974 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
1975 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
1976 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
1980 /* Begin with first PCI expansion ROM header. */
1984 /* Verify PCI expansion ROM header. */
1985 qla24xx_read_flash_data(ha
, dcode
, pcihdr
>> 2, 0x20);
1986 bcode
= mbuf
+ (pcihdr
% 4);
1987 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa) {
1989 DEBUG2(printk("scsi(%ld): No matching ROM "
1990 "signature.\n", ha
->host_no
));
1991 ret
= QLA_FUNCTION_FAILED
;
1995 /* Locate PCI data structure. */
1996 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
1998 qla24xx_read_flash_data(ha
, dcode
, pcids
>> 2, 0x20);
1999 bcode
= mbuf
+ (pcihdr
% 4);
2001 /* Validate signature of PCI data structure. */
2002 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
2003 bcode
[0x2] != 'I' || bcode
[0x3] != 'R') {
2004 /* Incorrect header. */
2005 DEBUG2(printk("%s(): PCI data struct not found "
2006 "pcir_adr=%x.\n", __func__
, pcids
));
2007 ret
= QLA_FUNCTION_FAILED
;
2012 code_type
= bcode
[0x14];
2013 switch (code_type
) {
2014 case ROM_CODE_TYPE_BIOS
:
2015 /* Intel x86, PC-AT compatible. */
2016 ha
->bios_revision
[0] = bcode
[0x12];
2017 ha
->bios_revision
[1] = bcode
[0x13];
2018 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__
,
2019 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2021 case ROM_CODE_TYPE_FCODE
:
2022 /* Open Firmware standard for PCI (FCode). */
2023 ha
->fcode_revision
[0] = bcode
[0x12];
2024 ha
->fcode_revision
[1] = bcode
[0x13];
2025 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__
,
2026 ha
->fcode_revision
[1], ha
->fcode_revision
[0]));
2028 case ROM_CODE_TYPE_EFI
:
2029 /* Extensible Firmware Interface (EFI). */
2030 ha
->efi_revision
[0] = bcode
[0x12];
2031 ha
->efi_revision
[1] = bcode
[0x13];
2032 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__
,
2033 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2036 DEBUG2(printk("%s(): Unrecognized code type %x at "
2037 "pcids %x.\n", __func__
, code_type
, pcids
));
2041 last_image
= bcode
[0x15] & BIT_7
;
2043 /* Locate next PCI expansion ROM. */
2044 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
2045 } while (!last_image
);
2047 /* Read firmware image information. */
2048 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2051 qla24xx_read_flash_data(ha
, dcode
, FA_RISC_CODE_ADDR
+ 4, 4);
2052 for (i
= 0; i
< 4; i
++)
2053 dcode
[i
] = be32_to_cpu(dcode
[i
]);
2055 if ((dcode
[0] == 0xffffffff && dcode
[1] == 0xffffffff &&
2056 dcode
[2] == 0xffffffff && dcode
[3] == 0xffffffff) ||
2057 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2059 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2060 __func__
, FA_RISC_CODE_ADDR
));
2062 ha
->fw_revision
[0] = dcode
[0];
2063 ha
->fw_revision
[1] = dcode
[1];
2064 ha
->fw_revision
[2] = dcode
[2];
2065 ha
->fw_revision
[3] = dcode
[3];