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[CONNECTOR]: async connector mode.
[linux-2.6/verdex.git] / drivers / serial / sunsab.c
blobe971156daa60c49e94fcf26ae1ddc3a3b3e387ad
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/oplib.h>
41 #include <asm/ebus.h>
42
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48
49 #include "suncore.h"
50 #include "sunsab.h"
51
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
74 };
75
76 /*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
80
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86 };
87
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
93
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95 {
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100 }
101
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103 {
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108 }
109
110 static struct tty_struct *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat,
113 struct pt_regs *regs)
114 {
115 struct tty_struct *tty = NULL;
116 unsigned char buf[32];
117 int saw_console_brk = 0;
118 int free_fifo = 0;
119 int count = 0;
120 int i;
121
122 if (up->port.info != NULL) /* Unopened serial console */
123 tty = up->port.info->tty;
124
125 /* Read number of BYTES (Character + Status) available. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
127 count = SAB82532_RECV_FIFO_SIZE;
128 free_fifo++;
129 }
130
131 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
132 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
133 free_fifo++;
134 }
135
136 /* Issue a FIFO read command in case we where idle. */
137 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 sunsab_cec_wait(up);
139 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
140 return tty;
141 }
142
143 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
144 free_fifo++;
145
146 /* Read the FIFO. */
147 for (i = 0; i < count; i++)
148 buf[i] = readb(&up->regs->r.rfifo[i]);
149
150 /* Issue Receive Message Complete command. */
151 if (free_fifo) {
152 sunsab_cec_wait(up);
153 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
154 }
155
156 /* Count may be zero for BRK, so we check for it here */
157 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
158 (up->port.line == up->port.cons->index))
159 saw_console_brk = 1;
160
161 for (i = 0; i < count; i++) {
162 unsigned char ch = buf[i];
163
164 if (tty == NULL) {
165 uart_handle_sysrq_char(&up->port, ch, regs);
166 continue;
167 }
168
169 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
170 tty->flip.work.func((void *)tty);
171 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
172 return tty; // if TTY_DONT_FLIP is set
173 }
174
175 *tty->flip.char_buf_ptr = ch;
176 *tty->flip.flag_buf_ptr = TTY_NORMAL;
177 up->port.icount.rx++;
178
179 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
180 SAB82532_ISR0_FERR |
181 SAB82532_ISR0_RFO)) ||
182 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
183 /*
184 * For statistics only
185 */
186 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
187 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
188 SAB82532_ISR0_FERR);
189 up->port.icount.brk++;
190 /*
191 * We do the SysRQ and SAK checking
192 * here because otherwise the break
193 * may get masked by ignore_status_mask
194 * or read_status_mask.
195 */
196 if (uart_handle_break(&up->port))
197 continue;
198 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
199 up->port.icount.parity++;
200 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
201 up->port.icount.frame++;
202 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
203 up->port.icount.overrun++;
204
205 /*
206 * Mask off conditions which should be ingored.
207 */
208 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
209 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
210
211 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
212 *tty->flip.flag_buf_ptr = TTY_BREAK;
213 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
214 *tty->flip.flag_buf_ptr = TTY_PARITY;
215 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
216 *tty->flip.flag_buf_ptr = TTY_FRAME;
217 }
218
219 if (uart_handle_sysrq_char(&up->port, ch, regs))
220 continue;
221
222 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
223 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
224 tty->flip.flag_buf_ptr++;
225 tty->flip.char_buf_ptr++;
226 tty->flip.count++;
227 }
228 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
229 tty->flip.count < TTY_FLIPBUF_SIZE) {
230 /*
231 * Overrun is special, since it's reported
232 * immediately, and doesn't affect the current
233 * character.
234 */
235 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
236 tty->flip.flag_buf_ptr++;
237 tty->flip.char_buf_ptr++;
238 tty->flip.count++;
239 }
240 }
241
242 if (saw_console_brk)
243 sun_do_break();
244
245 return tty;
246 }
247
248 static void sunsab_stop_tx(struct uart_port *);
249 static void sunsab_tx_idle(struct uart_sunsab_port *);
250
251 static void transmit_chars(struct uart_sunsab_port *up,
252 union sab82532_irq_status *stat)
253 {
254 struct circ_buf *xmit = &up->port.info->xmit;
255 int i;
256
257 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
258 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 set_bit(SAB82532_ALLS, &up->irqflags);
261 }
262
263 #if 0 /* bde@nwlink.com says this check causes problems */
264 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
265 return;
266 #endif
267
268 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
269 return;
270
271 set_bit(SAB82532_XPR, &up->irqflags);
272 sunsab_tx_idle(up);
273
274 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
275 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
276 writeb(up->interrupt_mask1, &up->regs->w.imr1);
277 uart_write_wakeup(&up->port);
278 return;
279 }
280
281 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
282 writeb(up->interrupt_mask1, &up->regs->w.imr1);
283 clear_bit(SAB82532_ALLS, &up->irqflags);
284
285 /* Stuff 32 bytes into Transmit FIFO. */
286 clear_bit(SAB82532_XPR, &up->irqflags);
287 for (i = 0; i < up->port.fifosize; i++) {
288 writeb(xmit->buf[xmit->tail],
289 &up->regs->w.xfifo[i]);
290 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
291 up->port.icount.tx++;
292 if (uart_circ_empty(xmit))
293 break;
294 }
295
296 /* Issue a Transmit Frame command. */
297 sunsab_cec_wait(up);
298 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
299
300 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
301 uart_write_wakeup(&up->port);
302
303 if (uart_circ_empty(xmit))
304 sunsab_stop_tx(&up->port);
305 }
306
307 static void check_status(struct uart_sunsab_port *up,
308 union sab82532_irq_status *stat)
309 {
310 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
311 uart_handle_dcd_change(&up->port,
312 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
313
314 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
315 uart_handle_cts_change(&up->port,
316 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
317
318 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
319 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
320 up->port.icount.dsr++;
321 }
322
323 wake_up_interruptible(&up->port.info->delta_msr_wait);
324 }
325
326 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
327 {
328 struct uart_sunsab_port *up = dev_id;
329 struct tty_struct *tty;
330 union sab82532_irq_status status;
331 unsigned long flags;
332
333 spin_lock_irqsave(&up->port.lock, flags);
334
335 status.stat = 0;
336 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
337 status.sreg.isr0 = readb(&up->regs->r.isr0);
338 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
339 status.sreg.isr1 = readb(&up->regs->r.isr1);
340
341 tty = NULL;
342 if (status.stat) {
343 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
344 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
345 (status.sreg.isr1 & SAB82532_ISR1_BRK))
346 tty = receive_chars(up, &status, regs);
347 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
348 (status.sreg.isr1 & SAB82532_ISR1_CSC))
349 check_status(up, &status);
350 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
351 transmit_chars(up, &status);
352 }
353
354 spin_unlock(&up->port.lock);
355
356 if (tty)
357 tty_flip_buffer_push(tty);
358
359 up++;
360
361 spin_lock(&up->port.lock);
362
363 status.stat = 0;
364 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
365 status.sreg.isr0 = readb(&up->regs->r.isr0);
366 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
367 status.sreg.isr1 = readb(&up->regs->r.isr1);
368
369 tty = NULL;
370 if (status.stat) {
371 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
372 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
373 (status.sreg.isr1 & SAB82532_ISR1_BRK))
374
375 tty = receive_chars(up, &status, regs);
376 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
377 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
378 check_status(up, &status);
379 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
380 transmit_chars(up, &status);
381 }
382
383 spin_unlock_irqrestore(&up->port.lock, flags);
384
385 if (tty)
386 tty_flip_buffer_push(tty);
387
388 return IRQ_HANDLED;
389 }
390
391 /* port->lock is not held. */
392 static unsigned int sunsab_tx_empty(struct uart_port *port)
393 {
394 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
395 int ret;
396
397 /* Do not need a lock for a state test like this. */
398 if (test_bit(SAB82532_ALLS, &up->irqflags))
399 ret = TIOCSER_TEMT;
400 else
401 ret = 0;
402
403 return ret;
404 }
405
406 /* port->lock held by caller. */
407 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
408 {
409 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
410
411 if (mctrl & TIOCM_RTS) {
412 up->cached_mode &= ~SAB82532_MODE_FRTS;
413 up->cached_mode |= SAB82532_MODE_RTS;
414 } else {
415 up->cached_mode |= (SAB82532_MODE_FRTS |
416 SAB82532_MODE_RTS);
417 }
418 if (mctrl & TIOCM_DTR) {
419 up->cached_pvr &= ~(up->pvr_dtr_bit);
420 } else {
421 up->cached_pvr |= up->pvr_dtr_bit;
422 }
423
424 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
425 if (test_bit(SAB82532_XPR, &up->irqflags))
426 sunsab_tx_idle(up);
427 }
428
429 /* port->lock is held by caller and interrupts are disabled. */
430 static unsigned int sunsab_get_mctrl(struct uart_port *port)
431 {
432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433 unsigned char val;
434 unsigned int result;
435
436 result = 0;
437
438 val = readb(&up->regs->r.pvr);
439 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
440
441 val = readb(&up->regs->r.vstr);
442 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
443
444 val = readb(&up->regs->r.star);
445 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
446
447 return result;
448 }
449
450 /* port->lock held by caller. */
451 static void sunsab_stop_tx(struct uart_port *port)
452 {
453 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
454
455 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
456 writeb(up->interrupt_mask1, &up->regs->w.imr1);
457 }
458
459 /* port->lock held by caller. */
460 static void sunsab_tx_idle(struct uart_sunsab_port *up)
461 {
462 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
463 u8 tmp;
464
465 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
466 writeb(up->cached_mode, &up->regs->rw.mode);
467 writeb(up->cached_pvr, &up->regs->rw.pvr);
468 writeb(up->cached_dafo, &up->regs->w.dafo);
469
470 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
471 tmp = readb(&up->regs->rw.ccr2);
472 tmp &= ~0xc0;
473 tmp |= (up->cached_ebrg >> 2) & 0xc0;
474 writeb(tmp, &up->regs->rw.ccr2);
475 }
476 }
477
478 /* port->lock held by caller. */
479 static void sunsab_start_tx(struct uart_port *port)
480 {
481 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
482 struct circ_buf *xmit = &up->port.info->xmit;
483 int i;
484
485 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
486 writeb(up->interrupt_mask1, &up->regs->w.imr1);
487
488 if (!test_bit(SAB82532_XPR, &up->irqflags))
489 return;
490
491 clear_bit(SAB82532_ALLS, &up->irqflags);
492 clear_bit(SAB82532_XPR, &up->irqflags);
493
494 for (i = 0; i < up->port.fifosize; i++) {
495 writeb(xmit->buf[xmit->tail],
496 &up->regs->w.xfifo[i]);
497 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
498 up->port.icount.tx++;
499 if (uart_circ_empty(xmit))
500 break;
501 }
502
503 /* Issue a Transmit Frame command. */
504 sunsab_cec_wait(up);
505 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
506 }
507
508 /* port->lock is not held. */
509 static void sunsab_send_xchar(struct uart_port *port, char ch)
510 {
511 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
512 unsigned long flags;
513
514 spin_lock_irqsave(&up->port.lock, flags);
515
516 sunsab_tec_wait(up);
517 writeb(ch, &up->regs->w.tic);
518
519 spin_unlock_irqrestore(&up->port.lock, flags);
520 }
521
522 /* port->lock held by caller. */
523 static void sunsab_stop_rx(struct uart_port *port)
524 {
525 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
526
527 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
528 writeb(up->interrupt_mask1, &up->regs->w.imr0);
529 }
530
531 /* port->lock held by caller. */
532 static void sunsab_enable_ms(struct uart_port *port)
533 {
534 /* For now we always receive these interrupts. */
535 }
536
537 /* port->lock is not held. */
538 static void sunsab_break_ctl(struct uart_port *port, int break_state)
539 {
540 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
541 unsigned long flags;
542 unsigned char val;
543
544 spin_lock_irqsave(&up->port.lock, flags);
545
546 val = up->cached_dafo;
547 if (break_state)
548 val |= SAB82532_DAFO_XBRK;
549 else
550 val &= ~SAB82532_DAFO_XBRK;
551 up->cached_dafo = val;
552
553 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
554 if (test_bit(SAB82532_XPR, &up->irqflags))
555 sunsab_tx_idle(up);
556
557 spin_unlock_irqrestore(&up->port.lock, flags);
558 }
559
560 /* port->lock is not held. */
561 static int sunsab_startup(struct uart_port *port)
562 {
563 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
564 unsigned long flags;
565 unsigned char tmp;
566
567 spin_lock_irqsave(&up->port.lock, flags);
568
569 /*
570 * Wait for any commands or immediate characters
571 */
572 sunsab_cec_wait(up);
573 sunsab_tec_wait(up);
574
575 /*
576 * Clear the FIFO buffers.
577 */
578 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
579 sunsab_cec_wait(up);
580 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
581
582 /*
583 * Clear the interrupt registers.
584 */
585 (void) readb(&up->regs->r.isr0);
586 (void) readb(&up->regs->r.isr1);
587
588 /*
589 * Now, initialize the UART
590 */
591 writeb(0, &up->regs->w.ccr0); /* power-down */
592 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
593 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
594 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
595 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
596 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
597 writeb(0, &up->regs->w.ccr3);
598 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
599 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
600 SAB82532_MODE_RAC);
601 writeb(up->cached_mode, &up->regs->w.mode);
602 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
603
604 tmp = readb(&up->regs->rw.ccr0);
605 tmp |= SAB82532_CCR0_PU; /* power-up */
606 writeb(tmp, &up->regs->rw.ccr0);
607
608 /*
609 * Finally, enable interrupts
610 */
611 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
612 SAB82532_IMR0_PLLA);
613 writeb(up->interrupt_mask0, &up->regs->w.imr0);
614 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
615 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
616 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
617 SAB82532_IMR1_XPR);
618 writeb(up->interrupt_mask1, &up->regs->w.imr1);
619 set_bit(SAB82532_ALLS, &up->irqflags);
620 set_bit(SAB82532_XPR, &up->irqflags);
621
622 spin_unlock_irqrestore(&up->port.lock, flags);
623
624 return 0;
625 }
626
627 /* port->lock is not held. */
628 static void sunsab_shutdown(struct uart_port *port)
629 {
630 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
631 unsigned long flags;
632
633 spin_lock_irqsave(&up->port.lock, flags);
634
635 /* Disable Interrupts */
636 up->interrupt_mask0 = 0xff;
637 writeb(up->interrupt_mask0, &up->regs->w.imr0);
638 up->interrupt_mask1 = 0xff;
639 writeb(up->interrupt_mask1, &up->regs->w.imr1);
640
641 /* Disable break condition */
642 up->cached_dafo = readb(&up->regs->rw.dafo);
643 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
644 writeb(up->cached_dafo, &up->regs->rw.dafo);
645
646 /* Disable Receiver */
647 up->cached_mode &= ~SAB82532_MODE_RAC;
648 writeb(up->cached_mode, &up->regs->rw.mode);
649
650 /*
651 * XXX FIXME
652 *
653 * If the chip is powered down here the system hangs/crashes during
654 * reboot or shutdown. This needs to be investigated further,
655 * similar behaviour occurs in 2.4 when the driver is configured
656 * as a module only. One hint may be that data is sometimes
657 * transmitted at 9600 baud during shutdown (regardless of the
658 * speed the chip was configured for when the port was open).
659 */
660 #if 0
661 /* Power Down */
662 tmp = readb(&up->regs->rw.ccr0);
663 tmp &= ~SAB82532_CCR0_PU;
664 writeb(tmp, &up->regs->rw.ccr0);
665 #endif
666
667 spin_unlock_irqrestore(&up->port.lock, flags);
668 }
669
670 /*
671 * This is used to figure out the divisor speeds.
672 *
673 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
674 *
675 * with 0 <= N < 64 and 0 <= M < 16
676 */
677
678 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
679 {
680 int n, m;
681
682 if (baud == 0) {
683 *n_ret = 0;
684 *m_ret = 0;
685 return;
686 }
687
688 /*
689 * We scale numbers by 10 so that we get better accuracy
690 * without having to use floating point. Here we increment m
691 * until n is within the valid range.
692 */
693 n = (SAB_BASE_BAUD * 10) / baud;
694 m = 0;
695 while (n >= 640) {
696 n = n / 2;
697 m++;
698 }
699 n = (n+5) / 10;
700 /*
701 * We try very hard to avoid speeds with M == 0 since they may
702 * not work correctly for XTAL frequences above 10 MHz.
703 */
704 if ((m == 0) && ((n & 1) == 0)) {
705 n = n / 2;
706 m++;
707 }
708 *n_ret = n - 1;
709 *m_ret = m;
710 }
711
712 /* Internal routine, port->lock is held and local interrupts are disabled. */
713 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
714 unsigned int iflag, unsigned int baud,
715 unsigned int quot)
716 {
717 unsigned char dafo;
718 int bits, n, m;
719
720 /* Byte size and parity */
721 switch (cflag & CSIZE) {
722 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
723 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
724 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
725 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
726 /* Never happens, but GCC is too dumb to figure it out */
727 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
728 }
729
730 if (cflag & CSTOPB) {
731 dafo |= SAB82532_DAFO_STOP;
732 bits++;
733 }
734
735 if (cflag & PARENB) {
736 dafo |= SAB82532_DAFO_PARE;
737 bits++;
738 }
739
740 if (cflag & PARODD) {
741 dafo |= SAB82532_DAFO_PAR_ODD;
742 } else {
743 dafo |= SAB82532_DAFO_PAR_EVEN;
744 }
745 up->cached_dafo = dafo;
746
747 calc_ebrg(baud, &n, &m);
748
749 up->cached_ebrg = n | (m << 6);
750
751 up->tec_timeout = (10 * 1000000) / baud;
752 up->cec_timeout = up->tec_timeout >> 2;
753
754 /* CTS flow control flags */
755 /* We encode read_status_mask and ignore_status_mask like so:
756 *
757 * ---------------------
758 * | ... | ISR1 | ISR0 |
759 * ---------------------
760 * .. 15 8 7 0
761 */
762
763 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
764 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
765 SAB82532_ISR0_CDSC);
766 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
767 SAB82532_ISR1_ALLS |
768 SAB82532_ISR1_XPR) << 8;
769 if (iflag & INPCK)
770 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
771 SAB82532_ISR0_FERR);
772 if (iflag & (BRKINT | PARMRK))
773 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
774
775 /*
776 * Characteres to ignore
777 */
778 up->port.ignore_status_mask = 0;
779 if (iflag & IGNPAR)
780 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
781 SAB82532_ISR0_FERR);
782 if (iflag & IGNBRK) {
783 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
784 /*
785 * If we're ignoring parity and break indicators,
786 * ignore overruns too (for real raw support).
787 */
788 if (iflag & IGNPAR)
789 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
790 }
791
792 /*
793 * ignore all characters if CREAD is not set
794 */
795 if ((cflag & CREAD) == 0)
796 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
797 SAB82532_ISR0_TCD);
798
799 uart_update_timeout(&up->port, cflag,
800 (up->port.uartclk / (16 * quot)));
801
802 /* Now schedule a register update when the chip's
803 * transmitter is idle.
804 */
805 up->cached_mode |= SAB82532_MODE_RAC;
806 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
807 if (test_bit(SAB82532_XPR, &up->irqflags))
808 sunsab_tx_idle(up);
809 }
810
811 /* port->lock is not held. */
812 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
813 struct termios *old)
814 {
815 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
816 unsigned long flags;
817 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
818 unsigned int quot = uart_get_divisor(port, baud);
819
820 spin_lock_irqsave(&up->port.lock, flags);
821 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
822 spin_unlock_irqrestore(&up->port.lock, flags);
823 }
824
825 static const char *sunsab_type(struct uart_port *port)
826 {
827 struct uart_sunsab_port *up = (void *)port;
828 static char buf[36];
829
830 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
831 return buf;
832 }
833
834 static void sunsab_release_port(struct uart_port *port)
835 {
836 }
837
838 static int sunsab_request_port(struct uart_port *port)
839 {
840 return 0;
841 }
842
843 static void sunsab_config_port(struct uart_port *port, int flags)
844 {
845 }
846
847 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
848 {
849 return -EINVAL;
850 }
851
852 static struct uart_ops sunsab_pops = {
853 .tx_empty = sunsab_tx_empty,
854 .set_mctrl = sunsab_set_mctrl,
855 .get_mctrl = sunsab_get_mctrl,
856 .stop_tx = sunsab_stop_tx,
857 .start_tx = sunsab_start_tx,
858 .send_xchar = sunsab_send_xchar,
859 .stop_rx = sunsab_stop_rx,
860 .enable_ms = sunsab_enable_ms,
861 .break_ctl = sunsab_break_ctl,
862 .startup = sunsab_startup,
863 .shutdown = sunsab_shutdown,
864 .set_termios = sunsab_set_termios,
865 .type = sunsab_type,
866 .release_port = sunsab_release_port,
867 .request_port = sunsab_request_port,
868 .config_port = sunsab_config_port,
869 .verify_port = sunsab_verify_port,
870 };
871
872 static struct uart_driver sunsab_reg = {
873 .owner = THIS_MODULE,
874 .driver_name = "serial",
875 .devfs_name = "tts/",
876 .dev_name = "ttyS",
877 .major = TTY_MAJOR,
878 };
879
880 static struct uart_sunsab_port *sunsab_ports;
881 static int num_channels;
882
883 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
884
885 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
886 {
887 unsigned long flags;
888
889 spin_lock_irqsave(&up->port.lock, flags);
890
891 sunsab_tec_wait(up);
892 writeb(c, &up->regs->w.tic);
893
894 spin_unlock_irqrestore(&up->port.lock, flags);
895 }
896
897 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
898 {
899 struct uart_sunsab_port *up = &sunsab_ports[con->index];
900 int i;
901
902 for (i = 0; i < n; i++) {
903 if (*s == '\n')
904 sunsab_console_putchar(up, '\r');
905 sunsab_console_putchar(up, *s++);
906 }
907 sunsab_tec_wait(up);
908 }
909
910 static int sunsab_console_setup(struct console *con, char *options)
911 {
912 struct uart_sunsab_port *up = &sunsab_ports[con->index];
913 unsigned long flags;
914 unsigned int baud, quot;
915
916 printk("Console: ttyS%d (SAB82532)\n",
917 (sunsab_reg.minor - 64) + con->index);
918
919 sunserial_console_termios(con);
920
921 /* Firmware console speed is limited to 150-->38400 baud so
922 * this hackish cflag thing is OK.
923 */
924 switch (con->cflag & CBAUD) {
925 case B150: baud = 150; break;
926 case B300: baud = 300; break;
927 case B600: baud = 600; break;
928 case B1200: baud = 1200; break;
929 case B2400: baud = 2400; break;
930 case B4800: baud = 4800; break;
931 default: case B9600: baud = 9600; break;
932 case B19200: baud = 19200; break;
933 case B38400: baud = 38400; break;
934 };
935
936 /*
937 * Temporary fix.
938 */
939 spin_lock_init(&up->port.lock);
940
941 /*
942 * Initialize the hardware
943 */
944 sunsab_startup(&up->port);
945
946 spin_lock_irqsave(&up->port.lock, flags);
947
948 /*
949 * Finally, enable interrupts
950 */
951 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
952 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
953 writeb(up->interrupt_mask0, &up->regs->w.imr0);
954 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
955 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
956 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
957 SAB82532_IMR1_XPR;
958 writeb(up->interrupt_mask1, &up->regs->w.imr1);
959
960 quot = uart_get_divisor(&up->port, baud);
961 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
962 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
963
964 spin_unlock_irqrestore(&up->port.lock, flags);
965
966 return 0;
967 }
968
969 static struct console sunsab_console = {
970 .name = "ttyS",
971 .write = sunsab_console_write,
972 .device = uart_console_device,
973 .setup = sunsab_console_setup,
974 .flags = CON_PRINTBUFFER,
975 .index = -1,
976 .data = &sunsab_reg,
977 };
978 #define SUNSAB_CONSOLE (&sunsab_console)
979
980 static void __init sunsab_console_init(void)
981 {
982 int i;
983
984 if (con_is_present())
985 return;
986
987 for (i = 0; i < num_channels; i++) {
988 int this_minor = sunsab_reg.minor + i;
989
990 if ((this_minor - 64) == (serial_console - 1))
991 break;
992 }
993 if (i == num_channels)
994 return;
995
996 sunsab_console.index = i;
997 register_console(&sunsab_console);
998 }
999 #else
1000 #define SUNSAB_CONSOLE (NULL)
1001 #define sunsab_console_init() do { } while (0)
1002 #endif
1003
1004 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
1005 {
1006 struct linux_ebus *ebus;
1007 struct linux_ebus_device *edev = NULL;
1008
1009 for_each_ebus(ebus) {
1010 for_each_ebusdev(edev, ebus) {
1011 if (!strcmp(edev->prom_name, "se")) {
1012 callback(edev, arg);
1013 continue;
1014 } else if (!strcmp(edev->prom_name, "serial")) {
1015 char compat[32];
1016 int clen;
1017
1018 /* On RIO this can be an SE, check it. We could
1019 * just check ebus->is_rio, but this is more portable.
1020 */
1021 clen = prom_getproperty(edev->prom_node, "compatible",
1022 compat, sizeof(compat));
1023 if (clen > 0) {
1024 if (strncmp(compat, "sab82532", 8) == 0) {
1025 callback(edev, arg);
1026 continue;
1027 }
1028 }
1029 }
1030 }
1031 }
1032 }
1033
1034 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1035 {
1036 int *count_p = arg;
1037
1038 (*count_p)++;
1039 }
1040
1041 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1042 {
1043 int *instance_p = arg;
1044 struct uart_sunsab_port *up;
1045 unsigned long regs, offset;
1046 int i;
1047
1048 /* Note: ports are located in reverse order */
1049 regs = edev->resource[0].start;
1050 offset = sizeof(union sab82532_async_regs);
1051 for (i = 0; i < 2; i++) {
1052 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1053
1054 memset(up, 0, sizeof(*up));
1055 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1056 up->port.irq = edev->irqs[0];
1057 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1058 up->port.mapbase = (unsigned long)up->regs;
1059 up->port.iotype = SERIAL_IO_MEM;
1060
1061 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1062
1063 offset -= sizeof(union sab82532_async_regs);
1064 }
1065
1066 (*instance_p)++;
1067 }
1068
1069 static int __init probe_for_sabs(void)
1070 {
1071 int this_sab = 0;
1072
1073 /* Find device instances. */
1074 for_each_sab_edev(&sab_count_callback, &this_sab);
1075 if (!this_sab)
1076 return -ENODEV;
1077
1078 /* Allocate tables. */
1079 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1080 GFP_KERNEL);
1081 if (!sunsab_ports)
1082 return -ENOMEM;
1083
1084 num_channels = this_sab * 2;
1085
1086 this_sab = 0;
1087 for_each_sab_edev(&sab_attach_callback, &this_sab);
1088 return 0;
1089 }
1090
1091 static void __init sunsab_init_hw(void)
1092 {
1093 int i;
1094
1095 for (i = 0; i < num_channels; i++) {
1096 struct uart_sunsab_port *up = &sunsab_ports[i];
1097
1098 up->port.line = i;
1099 up->port.ops = &sunsab_pops;
1100 up->port.type = PORT_SUNSAB;
1101 up->port.uartclk = SAB_BASE_BAUD;
1102
1103 up->type = readb(&up->regs->r.vstr) & 0x0f;
1104 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1105 writeb(0xff, &up->regs->w.pim);
1106 if (up->port.line == 0) {
1107 up->pvr_dsr_bit = (1 << 0);
1108 up->pvr_dtr_bit = (1 << 1);
1109 } else {
1110 up->pvr_dsr_bit = (1 << 3);
1111 up->pvr_dtr_bit = (1 << 2);
1112 }
1113 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1114 writeb(up->cached_pvr, &up->regs->w.pvr);
1115 up->cached_mode = readb(&up->regs->rw.mode);
1116 up->cached_mode |= SAB82532_MODE_FRTS;
1117 writeb(up->cached_mode, &up->regs->rw.mode);
1118 up->cached_mode |= SAB82532_MODE_RTS;
1119 writeb(up->cached_mode, &up->regs->rw.mode);
1120
1121 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1122 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1123
1124 if (!(up->port.line & 0x01)) {
1125 if (request_irq(up->port.irq, sunsab_interrupt,
1126 SA_SHIRQ, "serial(sab82532)", up)) {
1127 printk("sunsab%d: can't get IRQ %x\n",
1128 i, up->port.irq);
1129 continue;
1130 }
1131 }
1132 }
1133 }
1134
1135 static int __init sunsab_init(void)
1136 {
1137 int ret = probe_for_sabs();
1138 int i;
1139
1140 if (ret < 0)
1141 return ret;
1142
1143 sunsab_init_hw();
1144
1145 sunsab_reg.minor = sunserial_current_minor;
1146 sunsab_reg.nr = num_channels;
1147 sunsab_reg.cons = SUNSAB_CONSOLE;
1148
1149 ret = uart_register_driver(&sunsab_reg);
1150 if (ret < 0) {
1151 int i;
1152
1153 for (i = 0; i < num_channels; i++) {
1154 struct uart_sunsab_port *up = &sunsab_ports[i];
1155
1156 if (!(up->port.line & 0x01))
1157 free_irq(up->port.irq, up);
1158 iounmap(up->regs);
1159 }
1160 kfree(sunsab_ports);
1161 sunsab_ports = NULL;
1162
1163 return ret;
1164 }
1165
1166 sunserial_current_minor += num_channels;
1167
1168 sunsab_console_init();
1169
1170 for (i = 0; i < num_channels; i++) {
1171 struct uart_sunsab_port *up = &sunsab_ports[i];
1172
1173 uart_add_one_port(&sunsab_reg, &up->port);
1174 }
1175
1176 return 0;
1177 }
1178
1179 static void __exit sunsab_exit(void)
1180 {
1181 int i;
1182
1183 for (i = 0; i < num_channels; i++) {
1184 struct uart_sunsab_port *up = &sunsab_ports[i];
1185
1186 uart_remove_one_port(&sunsab_reg, &up->port);
1187
1188 if (!(up->port.line & 0x01))
1189 free_irq(up->port.irq, up);
1190 iounmap(up->regs);
1191 }
1192
1193 sunserial_current_minor -= num_channels;
1194 uart_unregister_driver(&sunsab_reg);
1195
1196 kfree(sunsab_ports);
1197 sunsab_ports = NULL;
1198 }
1199
1200 module_init(sunsab_init);
1201 module_exit(sunsab_exit);
1202
1203 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1204 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1205 MODULE_LICENSE("GPL");
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