include/asm-arm/arch-iop13xx/iop13xx.h

   1 #ifndef _IOP13XX_HW_H_
   2 #define _IOP13XX_HW_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /* The ATU offsets can change based on the strapping */
   6 extern u32 iop13xx_atux_pmmr_offset;
   7 extern u32 iop13xx_atue_pmmr_offset;
   8 void iop13xx_init_irq(void);
   9 void iop13xx_map_io(void);
  10 void iop13xx_platform_init(void);
  11 void iop13xx_init_irq(void);
  12
  13 /* CPUID CP6 R0 Page 0 */
  14 static inline int iop13xx_cpu_id(void)
  15 {
  16         int id;
  17         asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
  18         return id;
  19 }
  20
  21 #endif
  22
  23 /*
  24  * IOP13XX I/O and Mem space regions for PCI autoconfiguration
  25  */
  26 #define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
  27 #define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
  28
  29 /* PCI MAP
  30  * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
  31  * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
  32 */
  33 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
  34 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
  35 #define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
  36 #define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
  37 #define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
  38                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  39 #define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
  40                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  41 #define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
  42                                        IOP13XX_PCIX_LOWER_IO_BA)
  43 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
  44                                            (IOP13XX_PCIX_LOWER_IO_PA\
  45                                            - IOP13XX_PCIX_LOWER_IO_VA))
  46
  47 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
  48 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
  49 #define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  50 #define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
  51                                        IOP13XX_PCIX_LOWER_MEM_BA)
  52 #define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
  53                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  54 #define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
  55                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  56
  57 #define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
  58 #define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
  59 #define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
  60                                         IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  61 #define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
  62                                         IOP13XX_PCIX_LOWER_MEM_BA)
  63
  64 /* PCI-E ranges */
  65 #define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
  66 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
  67 #define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
  68 #define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
  69 #define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
  70                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
  71 #define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
  72                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
  73 #define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
  74                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
  75 #define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
  76                                          IOP13XX_PCIE_LOWER_IO_BA)
  77 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
  78                                            (IOP13XX_PCIE_LOWER_IO_PA\
  79                                            - IOP13XX_PCIE_LOWER_IO_VA))
  80
  81 #define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
  82 #define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
  83 #define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  84 #define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
  85                                          IOP13XX_PCIE_LOWER_MEM_BA)
  86 #define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
  87                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  88 #define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
  89                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  90
  91 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
  92 #define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
  93 #define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
  94 #define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
  95                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
  96 #define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
  97                                          IOP13XX_PCIE_LOWER_MEM_BA)
  98
  99 /* PBI Ranges */
 100 #define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
 101 #define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
 102 #define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
 103 #define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
 104 #define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
 105                                           IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
 106
 107 /*
 108  * IOP13XX chipset registers
 109  */
 110 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
 111 #define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
 112 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 113 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
 114                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 115 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
 116                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 117 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
 118                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 119                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 120 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
 121                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 122                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 123 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 124 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 125 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 126 #define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 127 #define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 128 #define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 129 #define IOP13XX_PMMR_SIZE                  0x00080000
 130
 131 /*=================== Defines for Platform Devices =====================*/
 132 #define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
 133 #define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
 134 #define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
 135 #define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
 136
 137 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 138 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
 139 #define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
 140 #define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
 141 #define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
 142 #define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
 143
 144 /* ATU selection flags */
 145 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
 146 #define IOP13XX_INIT_ATU_DEFAULT     (0)
 147 #define IOP13XX_INIT_ATU_ATUX         (1 << 0)
 148 #define IOP13XX_INIT_ATU_ATUE         (1 << 1)
 149 #define IOP13XX_INIT_ATU_NONE         (1 << 2)
 150
 151 /* UART selection flags */
 152 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
 153 #define IOP13XX_INIT_UART_DEFAULT    (0)
 154 #define IOP13XX_INIT_UART_0           (1 << 0)
 155 #define IOP13XX_INIT_UART_1           (1 << 1)
 156
 157 /* I2C selection flags */
 158 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
 159 #define IOP13XX_INIT_I2C_DEFAULT     (0)
 160 #define IOP13XX_INIT_I2C_0            (1 << 0)
 161 #define IOP13XX_INIT_I2C_1            (1 << 1)
 162 #define IOP13XX_INIT_I2C_2            (1 << 2)
 163
 164 #define IQ81340_NUM_UART     2
 165 #define IQ81340_NUM_I2C      3
 166 #define IQ81340_NUM_PHYS_MAP_FLASH 1
 167 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
 168                                 IQ81340_NUM_I2C +\
 169                                 IQ81340_NUM_PHYS_MAP_FLASH)
 170
 171 /*========================== PMMR offsets for key registers ============*/
 172 #define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
 173 #define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
 174 #define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
 175 #define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
 176 #define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
 177 #define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
 178 #define IOP13XX_PBI_PMMR_OFFSET         0x00001580
 179 #define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
 180 #define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
 181
 182 #define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
 183 #define IOP13XX_CONTROLLER_ONLY         (1 << 14)
 184 #define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
 185
 186 #define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
 187 #define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
 188                                         IOP13XX_PMON_PMMR_OFFSET)
 189 #define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
 190                                         IOP13XX_PMON_PMMR_OFFSET)
 191
 192 #define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
 193 #define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
 194 #define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
 195 #define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
 196
 197 #define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
 198 #define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
 199 #define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
 200 #define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
 201
 202 #define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
 203 #define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
 204 #define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
 205 #define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
 206
 207 #define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
 208 #define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
 209
 210 /*================================ATU===================================*/
 211 #define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 212                                         iop13xx_atux_pmmr_offset + (ofs))
 213
 214 #define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
 215                                         iop13xx_atux_pmmr_offset + 0x2)
 216
 217 #define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
 218                                         iop13xx_atux_pmmr_offset + 0x4)
 219 #define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
 220                                         iop13xx_atux_pmmr_offset + 0x6)
 221
 222 #define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
 223 #define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
 224 #define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
 225 #define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
 226 #define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
 227 #define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
 228 #define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
 229 #define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
 230 #define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
 231 #define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
 232 #define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
 233 #define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
 234 #define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
 235 #define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
 236 #define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
 237 #define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
 238 #define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
 239 #define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
 240 #define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
 241 #define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
 242 #define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
 243 #define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
 244 #define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
 245 #define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
 246
 247 #define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
 248 #define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
 249 #define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
 250 #define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
 251 #define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
 252 #define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
 253 #define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
 254 #define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
 255 #define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
 256 #define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
 257 #define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
 258 #define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
 259 #define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
 260 #define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
 261
 262 #define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
 263 #define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
 264 #define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
 265 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
 266 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
 267 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
 268
 269 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
 270 #define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
 271 #define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
 272 #define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
 273 #define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
 274 #define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
 275 #define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
 276 #define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
 277 #define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
 278 #define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
 279 #define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
 280 #define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
 281 #define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
 282 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
 283 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
 284 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
 285 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
 286
 287 #define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
 288 #define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
 289 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
 290
 291 #define IOP13XX_ATUX_IALR_DISABLE       0x00000001
 292 #define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
 293
 294 #define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 295                                         iop13xx_atue_pmmr_offset + (ofs))
 296
 297 #define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
 298                                         iop13xx_atue_pmmr_offset + 0x2)
 299 #define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
 300                                         iop13xx_atue_pmmr_offset + 0x4)
 301 #define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
 302                                         iop13xx_atue_pmmr_offset + 0x6)
 303
 304 #define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
 305 #define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
 306 #define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
 307 #define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
 308 #define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
 309 #define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
 310 #define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
 311 #define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
 312 #define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
 313 #define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
 314 #define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
 315 #define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
 316 #define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
 317 #define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
 318 #define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
 319 #define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
 320                                         iop13xx_atue_pmmr_offset + 0xe2)
 321 #define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
 322 #define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
 323 #define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
 324 #define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
 325 #define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
 326 #define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
 327 #define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
 328 #define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
 329 #define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
 330
 331 #define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
 332 #define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
 333 #define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
 334 #define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
 335 #define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
 336 #define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
 337
 338 #define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
 339 #define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
 340
 341 #define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
 342 #define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
 343 #define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
 344 #define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
 345 #define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
 346 #define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
 347 #define IOP13XX_ATUE_OCCAR_REG          (2)
 348
 349 #define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
 350 #define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
 351 #define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
 352 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
 353 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
 354 #define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
 355 #define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
 356
 357 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
 358 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
 359 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
 360
 361 #define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
 362 #define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
 363
 364 #define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
 365 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
 366 #define IOP13XX_ATUE_STAT_PME                   (1 << 27)
 367 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
 368 #define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
 369 #define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
 370 #define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
 371 #define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
 372 #define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
 373 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
 374 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
 375 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
 376 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
 377 #define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
 378 #define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
 379 #define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
 380 #define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
 381 #define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
 382 #define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
 383 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
 384 #define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
 385 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
 386 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
 387
 388 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
 389 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
 390 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
 391 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
 392 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
 393 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
 394 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
 395 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
 396 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
 397 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
 398 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
 399 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
 400 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
 401 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
 402 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
 403
 404 #define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
 405 #define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
 406 #define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
 407 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
 408 /*=======================================================================*/
 409
 410 /*==============================ADMA UNITS===============================*/
 411 #define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
 412 #define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
 413 #define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
 414
 415 #define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
 416 #define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
 417 #define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
 418 #define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
 419 #define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
 420 #define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
 421 #define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
 422 #define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
 423 #define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
 424 #define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
 425 #define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
 426 #define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
 427 #define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
 428 #define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
 429
 430 /*==============================XSI BRIDGE===============================*/
 431 #define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
 432 #define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
 433 #define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
 434 #define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 435                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 436                                         IOP13XX_ATUE_OCCDR))\
 437                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 438 #define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 439                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 440                                         IOP13XX_ATUX_OCCDR))\
 441                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 442 /*=======================================================================*/
 443
 444 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
 445                                                         (ofs))
 446
 447 #define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
 448 #define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
 449 #define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
 450 #define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
 451 #define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
 452 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 453
 454 #endif /* _IOP13XX_HW_H_ */