drivers/media/dvb/frontends/dib3000mb_priv.h

   1 /*
   2  * dib3000mb_priv.h
   3  *
   4  * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  *
  10  * for more information see dib3000mb.c .
  11  */
  12
  13 #ifndef __DIB3000MB_PRIV_H_INCLUDED__
  14 #define __DIB3000MB_PRIV_H_INCLUDED__
  15
  16 /* register addresses and some of their default values */
  17
  18 /* restart subsystems */
  19 #define DIB3000MB_REG_RESTART                   (     0)
  20
  21 #define DIB3000MB_RESTART_OFF                   (     0)
  22 #define DIB3000MB_RESTART_AUTO_SEARCH           (1 << 1)
  23 #define DIB3000MB_RESTART_CTRL                          (1 << 2)
  24 #define DIB3000MB_RESTART_AGC                           (1 << 3)
  25
  26 /* FFT size */
  27 #define DIB3000MB_REG_FFT                               (     1)
  28
  29 /* Guard time */
  30 #define DIB3000MB_REG_GUARD_TIME                (     2)
  31
  32 /* QAM */
  33 #define DIB3000MB_REG_QAM                               (     3)
  34
  35 /* Alpha coefficient high priority Viterbi algorithm */
  36 #define DIB3000MB_REG_VIT_ALPHA                 (     4)
  37
  38 /* spectrum inversion */
  39 #define DIB3000MB_REG_DDS_INV                   (     5)
  40
  41 /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
  42 #define DIB3000MB_REG_DDS_FREQ_MSB              (     6)
  43 #define DIB3000MB_REG_DDS_FREQ_LSB              (     7)
  44 #define DIB3000MB_DDS_FREQ_MSB                          (   178)
  45 #define DIB3000MB_DDS_FREQ_LSB                          (  8990)
  46
  47 /* timing frequency (carrier spacing) */
  48 static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
  49 static u16 dib3000mb_timing_freq[][2] = {
  50         { 126 , 48873 }, /* 6 MHz */
  51         { 147 , 57019 }, /* 7 MHz */
  52         { 168 , 65164 }, /* 8 MHz */
  53 };
  54
  55 /* impulse noise parameter */
  56 /* 36 ??? */
  57
  58 static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
  59
  60 enum dib3000mb_impulse_noise_type {
  61         DIB3000MB_IMPNOISE_OFF,
  62         DIB3000MB_IMPNOISE_MOBILE,
  63         DIB3000MB_IMPNOISE_FIXED,
  64         DIB3000MB_IMPNOISE_DEFAULT
  65 };
  66
  67 static u16 dib3000mb_impulse_noise_values[][5] = {
  68         { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
  69         { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
  70         { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
  71         { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
  72 };
  73
  74 /*
  75  * Dual Automatic-Gain-Control
  76  * - gains RF in tuner (AGC1)
  77  * - gains IF after filtering (AGC2)
  78  */
  79
  80 /* also from 16 to 18 */
  81 static u16 dib3000mb_reg_agc_gain[] = {
  82         19,20,21,22,23,24,25,26,27,28,29,30,31,32
  83 };
  84
  85 static u16 dib3000mb_default_agc_gain[] =
  86         { 0x0001, 52429,   623, 128, 166, 195, 61,   /* RF ??? */
  87           0x0001, 53766, 38011,   0,  90,  33, 23 }; /* IF ??? */
  88
  89 /* phase noise */
  90 /* 36 is set when setting the impulse noise */
  91 static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
  92
  93 static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
  94
  95 /* lock duration */
  96 static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
  97 static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
  98
  99 /* AGC loop bandwidth */
 100 static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
 101
 102 static u16 dib3000mb_agc_bandwidth_low[]  =
 103         { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
 104 static u16 dib3000mb_agc_bandwidth_high[] =
 105         { 2349,  5, 2349,  5, 2586, 2, 2586, 2 };
 106
 107 /*
 108  * lock0 definition (coff_lock)
 109  */
 110 #define DIB3000MB_REG_LOCK0_MASK                (    51)
 111 #define DIB3000MB_LOCK0_DEFAULT                         (     4)
 112
 113 /*
 114  * lock1 definition (cpil_lock)
 115  * for auto search
 116  * which values hide behind the lock masks
 117  */
 118 #define DIB3000MB_REG_LOCK1_MASK                (    52)
 119 #define DIB3000MB_LOCK1_SEARCH_4                        (0x0004)
 120 #define DIB3000MB_LOCK1_SEARCH_2048                     (0x0800)
 121 #define DIB3000MB_LOCK1_DEFAULT                         (0x0001)
 122
 123 /*
 124  * lock2 definition (fec_lock) */
 125 #define DIB3000MB_REG_LOCK2_MASK                (    53)
 126 #define DIB3000MB_LOCK2_DEFAULT                         (0x0080)
 127
 128 /*
 129  * SEQ ? what was that again ... :)
 130  * changes when, inversion, guard time and fft is
 131  * either automatically detected or not
 132  */
 133 #define DIB3000MB_REG_SEQ                               (    54)
 134
 135 /* bandwidth */
 136 static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
 137 static u16 dib3000mb_bandwidth_6mhz[] =
 138         { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
 139
 140 static u16 dib3000mb_bandwidth_7mhz[] =
 141         { 0, 28, 64421,  96, 39973, 483,  3255, 0, 1000, 0, 1010, 1, 45264 };
 142
 143 static u16 dib3000mb_bandwidth_8mhz[] =
 144         { 0, 25, 23600,  84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
 145
 146 #define DIB3000MB_REG_UNK_68                            (    68)
 147 #define DIB3000MB_UNK_68                                                (     0)
 148
 149 #define DIB3000MB_REG_UNK_69                            (    69)
 150 #define DIB3000MB_UNK_69                                                (     0)
 151
 152 #define DIB3000MB_REG_UNK_71                            (    71)
 153 #define DIB3000MB_UNK_71                                                (     0)
 154
 155 #define DIB3000MB_REG_UNK_77                            (    77)
 156 #define DIB3000MB_UNK_77                                                (     6)
 157
 158 #define DIB3000MB_REG_UNK_78                            (    78)
 159 #define DIB3000MB_UNK_78                                                (0x0080)
 160
 161 /* isi */
 162 #define DIB3000MB_REG_ISI                               (    79)
 163 #define DIB3000MB_ISI_ACTIVATE                          (     0)
 164 #define DIB3000MB_ISI_INHIBIT                           (     1)
 165
 166 /* sync impovement */
 167 #define DIB3000MB_REG_SYNC_IMPROVEMENT  (    84)
 168 #define DIB3000MB_SYNC_IMPROVE_2K_1_8           (     3)
 169 #define DIB3000MB_SYNC_IMPROVE_DEFAULT          (     0)
 170
 171 /* phase noise compensation inhibition */
 172 #define DIB3000MB_REG_PHASE_NOISE               (    87)
 173 #define DIB3000MB_PHASE_NOISE_DEFAULT   (     0)
 174
 175 #define DIB3000MB_REG_UNK_92                            (    92)
 176 #define DIB3000MB_UNK_92                                                (0x0080)
 177
 178 #define DIB3000MB_REG_UNK_96                            (    96)
 179 #define DIB3000MB_UNK_96                                                (0x0010)
 180
 181 #define DIB3000MB_REG_UNK_97                            (    97)
 182 #define DIB3000MB_UNK_97                                                (0x0009)
 183
 184 /* mobile mode ??? */
 185 #define DIB3000MB_REG_MOBILE_MODE               (   101)
 186 #define DIB3000MB_MOBILE_MODE_ON                        (     1)
 187 #define DIB3000MB_MOBILE_MODE_OFF                       (     0)
 188
 189 #define DIB3000MB_REG_UNK_106                   (   106)
 190 #define DIB3000MB_UNK_106                                       (0x0080)
 191
 192 #define DIB3000MB_REG_UNK_107                   (   107)
 193 #define DIB3000MB_UNK_107                                       (0x0080)
 194
 195 #define DIB3000MB_REG_UNK_108                   (   108)
 196 #define DIB3000MB_UNK_108                                       (0x0080)
 197
 198 /* fft */
 199 #define DIB3000MB_REG_UNK_121                   (   121)
 200 #define DIB3000MB_UNK_121_2K                            (     7)
 201 #define DIB3000MB_UNK_121_DEFAULT                       (     5)
 202
 203 #define DIB3000MB_REG_UNK_122                   (   122)
 204 #define DIB3000MB_UNK_122                                       (  2867)
 205
 206 /* QAM for mobile mode */
 207 #define DIB3000MB_REG_MOBILE_MODE_QAM   (   126)
 208 #define DIB3000MB_MOBILE_MODE_QAM_64            (     3)
 209 #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16       (     1)
 210 #define DIB3000MB_MOBILE_MODE_QAM_OFF           (     0)
 211
 212 /*
 213  * data diversity when having more than one chip on-board
 214  * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
 215  */
 216 #define DIB3000MB_REG_DATA_IN_DIVERSITY         (   127)
 217 #define DIB3000MB_DATA_DIVERSITY_IN_OFF                 (     0)
 218 #define DIB3000MB_DATA_DIVERSITY_IN_ON                  (     2)
 219
 220 /* vit hrch */
 221 #define DIB3000MB_REG_VIT_HRCH                  (   128)
 222
 223 /* vit code rate */
 224 #define DIB3000MB_REG_VIT_CODE_RATE             (   129)
 225
 226 /* vit select hp */
 227 #define DIB3000MB_REG_VIT_HP                    (   130)
 228
 229 /* time frame for Bit-Error-Rate calculation */
 230 #define DIB3000MB_REG_BERLEN                    (   135)
 231 #define DIB3000MB_BERLEN_LONG                           (     0)
 232 #define DIB3000MB_BERLEN_DEFAULT                        (     1)
 233 #define DIB3000MB_BERLEN_MEDIUM                         (     2)
 234 #define DIB3000MB_BERLEN_SHORT                          (     3)
 235
 236 /* 142 - 152 FIFO parameters
 237  * which is what ?
 238  */
 239
 240 #define DIB3000MB_REG_FIFO_142                  (   142)
 241 #define DIB3000MB_FIFO_142                                      (     0)
 242
 243 /* MPEG2 TS output mode */
 244 #define DIB3000MB_REG_MPEG2_OUT_MODE    (   143)
 245 #define DIB3000MB_MPEG2_OUT_MODE_204            (     0)
 246 #define DIB3000MB_MPEG2_OUT_MODE_188            (     1)
 247
 248 #define DIB3000MB_REG_PID_PARSE                 (   144)
 249 #define DIB3000MB_PID_PARSE_INHIBIT             (     0)
 250 #define DIB3000MB_PID_PARSE_ACTIVATE    (     1)
 251
 252 #define DIB3000MB_REG_FIFO                              (   145)
 253 #define DIB3000MB_FIFO_INHIBIT                          (     1)
 254 #define DIB3000MB_FIFO_ACTIVATE                         (     0)
 255
 256 #define DIB3000MB_REG_FIFO_146                  (   146)
 257 #define DIB3000MB_FIFO_146                                      (     3)
 258
 259 #define DIB3000MB_REG_FIFO_147                  (   147)
 260 #define DIB3000MB_FIFO_147                                      (0x0100)
 261
 262 /*
 263  * pidfilter
 264  * it is not a hardware pidfilter but a filter which drops all pids
 265  * except the ones set. Necessary because of the limited USB1.1 bandwidth.
 266  * regs 153-168
 267  */
 268
 269 #define DIB3000MB_REG_FIRST_PID                 (   153)
 270 #define DIB3000MB_NUM_PIDS                              (    16)
 271
 272 /*
 273  * output mode
 274  * USB devices have to use 'slave'-mode
 275  * see also DIB3000MB_REG_ELECT_OUT_MODE
 276  */
 277 #define DIB3000MB_REG_OUTPUT_MODE               (   169)
 278 #define DIB3000MB_OUTPUT_MODE_GATED_CLK         (     0)
 279 #define DIB3000MB_OUTPUT_MODE_CONT_CLK          (     1)
 280 #define DIB3000MB_OUTPUT_MODE_SERIAL            (     2)
 281 #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY    (     5)
 282 #define DIB3000MB_OUTPUT_MODE_SLAVE                     (     6)
 283
 284 /* irq event mask */
 285 #define DIB3000MB_REG_IRQ_EVENT_MASK            (   170)
 286 #define DIB3000MB_IRQ_EVENT_MASK                                (     0)
 287
 288 /* filter coefficients */
 289 static u16 dib3000mb_reg_filter_coeffs[] = {
 290         171, 172, 173, 174, 175, 176, 177, 178,
 291         179, 180, 181, 182, 183, 184, 185, 186,
 292         188, 189, 190, 191, 192, 194
 293 };
 294
 295 static u16 dib3000mb_filter_coeffs[] = {
 296          226,  160,   29,
 297          979,  998,   19,
 298           22, 1019, 1006,
 299         1022,   12,    6,
 300         1017, 1017,    3,
 301            6,       1019,
 302         1021,    2,    3,
 303            1,          0,
 304 };
 305
 306 /*
 307  * mobile algorithm (when you are moving with your device)
 308  * but not faster than 90 km/h
 309  */
 310 #define DIB3000MB_REG_MOBILE_ALGO               (   195)
 311 #define DIB3000MB_MOBILE_ALGO_ON                        (     0)
 312 #define DIB3000MB_MOBILE_ALGO_OFF                       (     1)
 313
 314 /* multiple demodulators algorithm */
 315 #define DIB3000MB_REG_MULTI_DEMOD_MSB   (   206)
 316 #define DIB3000MB_REG_MULTI_DEMOD_LSB   (   207)
 317
 318 /* terminator, no more demods */
 319 #define DIB3000MB_MULTI_DEMOD_MSB                       ( 32767)
 320 #define DIB3000MB_MULTI_DEMOD_LSB                       (  4095)
 321
 322 /* bring the device into a known  */
 323 #define DIB3000MB_REG_RESET_DEVICE              (  1024)
 324 #define DIB3000MB_RESET_DEVICE                          (0x812c)
 325 #define DIB3000MB_RESET_DEVICE_RST                      (     0)
 326
 327 /* hardware clock configuration */
 328 #define DIB3000MB_REG_CLOCK                             (  1027)
 329 #define DIB3000MB_CLOCK_DEFAULT                         (0x9000)
 330 #define DIB3000MB_CLOCK_DIVERSITY                       (0x92b0)
 331
 332 /* power down config */
 333 #define DIB3000MB_REG_POWER_CONTROL             (  1028)
 334 #define DIB3000MB_POWER_DOWN                            (     1)
 335 #define DIB3000MB_POWER_UP                                      (     0)
 336
 337 /* electrical output mode */
 338 #define DIB3000MB_REG_ELECT_OUT_MODE    (  1029)
 339 #define DIB3000MB_ELECT_OUT_MODE_OFF            (     0)
 340 #define DIB3000MB_ELECT_OUT_MODE_ON                     (     1)
 341
 342 /* set the tuner i2c address */
 343 #define DIB3000MB_REG_TUNER                             (  1089)
 344
 345 /* monitoring registers (read only) */
 346
 347 /* agc loop locked (size: 1) */
 348 #define DIB3000MB_REG_AGC_LOCK                  (   324)
 349
 350 /* agc power (size: 16) */
 351 #define DIB3000MB_REG_AGC_POWER                 (   325)
 352
 353 /* agc1 value (16) */
 354 #define DIB3000MB_REG_AGC1_VALUE                (   326)
 355
 356 /* agc2 value (16) */
 357 #define DIB3000MB_REG_AGC2_VALUE                (   327)
 358
 359 /* total RF power (16), can be used for signal strength */
 360 #define DIB3000MB_REG_RF_POWER                  (   328)
 361
 362 /* dds_frequency with offset (24) */
 363 #define DIB3000MB_REG_DDS_VALUE_MSB             (   339)
 364 #define DIB3000MB_REG_DDS_VALUE_LSB             (   340)
 365
 366 /* timing offset signed (24) */
 367 #define DIB3000MB_REG_TIMING_OFFSET_MSB (   341)
 368 #define DIB3000MB_REG_TIMING_OFFSET_LSB (   342)
 369
 370 /* fft start position (13) */
 371 #define DIB3000MB_REG_FFT_WINDOW_POS    (   353)
 372
 373 /* carriers locked (1) */
 374 #define DIB3000MB_REG_CARRIER_LOCK              (   355)
 375
 376 /* noise power (24) */
 377 #define DIB3000MB_REG_NOISE_POWER_MSB   (   372)
 378 #define DIB3000MB_REG_NOISE_POWER_LSB   (   373)
 379
 380 #define DIB3000MB_REG_MOBILE_NOISE_MSB  (   374)
 381 #define DIB3000MB_REG_MOBILE_NOISE_LSB  (   375)
 382
 383 /*
 384  * signal power (16), this and the above can be
 385  * used to calculate the signal/noise - ratio
 386  */
 387 #define DIB3000MB_REG_SIGNAL_POWER              (   380)
 388
 389 /* mer (24) */
 390 #define DIB3000MB_REG_MER_MSB                   (   381)
 391 #define DIB3000MB_REG_MER_LSB                   (   382)
 392
 393 /*
 394  * Transmission Parameter Signalling (TPS)
 395  * the following registers can be used to get TPS-information.
 396  * The values are according to the DVB-T standard.
 397  */
 398
 399 /* TPS locked (1) */
 400 #define DIB3000MB_REG_TPS_LOCK                  (   394)
 401
 402 /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
 403 #define DIB3000MB_REG_TPS_QAM                   (   398)
 404
 405 /* hierarchy from TPS (1) */
 406 #define DIB3000MB_REG_TPS_HRCH                  (   399)
 407
 408 /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
 409 #define DIB3000MB_REG_TPS_VIT_ALPHA             (   400)
 410
 411 /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
 412 #define DIB3000MB_REG_TPS_CODE_RATE_HP  (   401)
 413
 414 /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
 415 #define DIB3000MB_REG_TPS_CODE_RATE_LP  (   402)
 416
 417 /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
 418 #define DIB3000MB_REG_TPS_GUARD_TIME    (   403)
 419
 420 /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
 421 #define DIB3000MB_REG_TPS_FFT                   (   404)
 422
 423 /* cell id from TPS (16) */
 424 #define DIB3000MB_REG_TPS_CELL_ID               (   406)
 425
 426 /* TPS (68) */
 427 #define DIB3000MB_REG_TPS_1                             (   408)
 428 #define DIB3000MB_REG_TPS_2                             (   409)
 429 #define DIB3000MB_REG_TPS_3                             (   410)
 430 #define DIB3000MB_REG_TPS_4                             (   411)
 431 #define DIB3000MB_REG_TPS_5                             (   412)
 432
 433 /* bit error rate (before RS correction) (21) */
 434 #define DIB3000MB_REG_BER_MSB                   (   414)
 435 #define DIB3000MB_REG_BER_LSB                   (   415)
 436
 437 /* packet error rate (uncorrected TS packets) (16) */
 438 #define DIB3000MB_REG_PACKET_ERROR_RATE (   417)
 439
 440 /* uncorrected packet count (16) */
 441 #define DIB3000MB_REG_UNC                               (   420)
 442
 443 /* viterbi locked (1) */
 444 #define DIB3000MB_REG_VIT_LCK                   (   421)
 445
 446 /* viterbi inidcator (16) */
 447 #define DIB3000MB_REG_VIT_INDICATOR             (   422)
 448
 449 /* transport stream sync lock (1) */
 450 #define DIB3000MB_REG_TS_SYNC_LOCK              (   423)
 451
 452 /* transport stream RS lock (1) */
 453 #define DIB3000MB_REG_TS_RS_LOCK                (   424)
 454
 455 /* lock mask 0 value (1) */
 456 #define DIB3000MB_REG_LOCK0_VALUE               (   425)
 457
 458 /* lock mask 1 value (1) */
 459 #define DIB3000MB_REG_LOCK1_VALUE               (   426)
 460
 461 /* lock mask 2 value (1) */
 462 #define DIB3000MB_REG_LOCK2_VALUE               (   427)
 463
 464 /* interrupt pending for auto search */
 465 #define DIB3000MB_REG_AS_IRQ_PENDING    (   434)
 466
 467 #endif