drivers/media/dvb/frontends/l64781.c

   1 /*
   2     driver for LSI L64781 COFDM demodulator
   3
   4     Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
   5                        Marko Kohtala <marko.kohtala@luukku.com>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21 */
  22
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/string.h>
  28 #include <linux/slab.h>
  29 #include "dvb_frontend.h"
  30 #include "l64781.h"
  31
  32
  33 struct l64781_state {
  34         struct i2c_adapter* i2c;
  35         struct dvb_frontend_ops ops;
  36         const struct l64781_config* config;
  37         struct dvb_frontend frontend;
  38
  39         /* private demodulator data */
  40         int first:1;
  41 };
  42
  43 #define dprintk(args...) \
  44         do { \
  45                 if (debug) printk(KERN_DEBUG "l64781: " args); \
  46         } while (0)
  47
  48 static int debug;
  49
  50 module_param(debug, int, 0644);
  51 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  52
  53
  54 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
  55 {
  56         int ret;
  57         u8 buf [] = { reg, data };
  58         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
  59
  60         if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
  61                 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
  62                          __FUNCTION__, reg, ret);
  63
  64         return (ret != 1) ? -1 : 0;
  65 }
  66
  67 static int l64781_readreg (struct l64781_state* state, u8 reg)
  68 {
  69         int ret;
  70         u8 b0 [] = { reg };
  71         u8 b1 [] = { 0 };
  72         struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
  73                            { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
  74
  75         ret = i2c_transfer(state->i2c, msg, 2);
  76
  77         if (ret != 2) return ret;
  78
  79         return b1[0];
  80 }
  81
  82 static void apply_tps (struct l64781_state* state)
  83 {
  84         l64781_writereg (state, 0x2a, 0x00);
  85         l64781_writereg (state, 0x2a, 0x01);
  86
  87         /* This here is a little bit questionable because it enables
  88            the automatic update of TPS registers. I think we'd need to
  89            handle the IRQ from FE to update some other registers as
  90            well, or at least implement some magic to tuning to correct
  91            to the TPS received from transmission. */
  92         l64781_writereg (state, 0x2a, 0x02);
  93 }
  94
  95
  96 static void reset_afc (struct l64781_state* state)
  97 {
  98         /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
  99            timing offset */
 100         l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
 101         l64781_writereg (state, 0x08, 0);    /* AFC INIT FREQ */
 102         l64781_writereg (state, 0x09, 0);
 103         l64781_writereg (state, 0x0a, 0);
 104         l64781_writereg (state, 0x07, 0x8e);
 105         l64781_writereg (state, 0x0e, 0);    /* AGC gain to zero in beginning */
 106         l64781_writereg (state, 0x11, 0x80); /* stall TIM */
 107         l64781_writereg (state, 0x10, 0);    /* TIM_OFFSET_LSB */
 108         l64781_writereg (state, 0x12, 0);
 109         l64781_writereg (state, 0x13, 0);
 110         l64781_writereg (state, 0x11, 0x00);
 111 }
 112
 113 static int reset_and_configure (struct l64781_state* state)
 114 {
 115         u8 buf [] = { 0x06 };
 116         struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
 117         // NOTE: this is correct in writing to address 0x00
 118
 119         return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
 120 }
 121
 122 static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param)
 123 {
 124         struct l64781_state* state = fe->demodulator_priv;
 125         /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
 126         static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
 127         /* QPSK, QAM_16, QAM_64 */
 128         static const u8 qam_tab [] = { 2, 4, 0, 6 };
 129         static const u8 bw_tab [] = { 8, 7, 6 };  /* 8Mhz, 7MHz, 6MHz */
 130         static const u8 guard_tab [] = { 1, 2, 4, 8 };
 131         /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
 132         static const u32 ppm = 8000;
 133         struct dvb_ofdm_parameters *p = &param->u.ofdm;
 134         u32 ddfs_offset_fixed;
 135 /*      u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
 136 /*                      bw_tab[p->bandWidth]<<10)/15625; */
 137         u32 init_freq;
 138         u32 spi_bias;
 139         u8 val0x04;
 140         u8 val0x05;
 141         u8 val0x06;
 142         int bw = p->bandwidth - BANDWIDTH_8_MHZ;
 143
 144         state->config->pll_set(fe, param);
 145
 146         if (param->inversion != INVERSION_ON &&
 147             param->inversion != INVERSION_OFF)
 148                 return -EINVAL;
 149
 150         if (bw < 0 || bw > 2)
 151                 return -EINVAL;
 152
 153         if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
 154             p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
 155             p->code_rate_HP != FEC_7_8)
 156                 return -EINVAL;
 157
 158         if (p->hierarchy_information != HIERARCHY_NONE &&
 159             (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
 160              p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
 161              p->code_rate_LP != FEC_7_8))
 162                 return -EINVAL;
 163
 164         if (p->constellation != QPSK && p->constellation != QAM_16 &&
 165             p->constellation != QAM_64)
 166                 return -EINVAL;
 167
 168         if (p->transmission_mode != TRANSMISSION_MODE_2K &&
 169             p->transmission_mode != TRANSMISSION_MODE_8K)
 170                 return -EINVAL;
 171
 172         if (p->guard_interval < GUARD_INTERVAL_1_32 ||
 173             p->guard_interval > GUARD_INTERVAL_1_4)
 174                 return -EINVAL;
 175
 176         if (p->hierarchy_information < HIERARCHY_NONE ||
 177             p->hierarchy_information > HIERARCHY_4)
 178                 return -EINVAL;
 179
 180         ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000;
 181
 182         /* This works up to 20000 ppm, it overflows if too large ppm! */
 183         init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
 184                         bw_tab[p->bandwidth] & 0xFFFFFF);
 185
 186         /* SPI bias calculation is slightly modified to fit in 32bit */
 187         /* will work for high ppm only... */
 188         spi_bias = 378 * (1 << 10);
 189         spi_bias *= 16;
 190         spi_bias *= bw_tab[p->bandwidth];
 191         spi_bias *= qam_tab[p->constellation];
 192         spi_bias /= p->code_rate_HP + 1;
 193         spi_bias /= (guard_tab[p->guard_interval] + 32);
 194         spi_bias *= 1000ULL;
 195         spi_bias /= 1000ULL + ppm/1000;
 196         spi_bias *= p->code_rate_HP;
 197
 198         val0x04 = (p->transmission_mode << 2) | p->guard_interval;
 199         val0x05 = fec_tab[p->code_rate_HP];
 200
 201         if (p->hierarchy_information != HIERARCHY_NONE)
 202                 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
 203
 204         val0x06 = (p->hierarchy_information << 2) | p->constellation;
 205
 206         l64781_writereg (state, 0x04, val0x04);
 207         l64781_writereg (state, 0x05, val0x05);
 208         l64781_writereg (state, 0x06, val0x06);
 209
 210         reset_afc (state);
 211
 212         /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
 213         l64781_writereg (state, 0x15,
 214                          p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
 215         l64781_writereg (state, 0x16, init_freq & 0xff);
 216         l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
 217         l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
 218
 219         l64781_writereg (state, 0x1b, spi_bias & 0xff);
 220         l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
 221         l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
 222                 (param->inversion == INVERSION_ON ? 0x80 : 0x00));
 223
 224         l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
 225         l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
 226
 227         l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
 228         l64781_readreg (state, 0x01);  /*  dto. */
 229
 230         apply_tps (state);
 231
 232         return 0;
 233 }
 234
 235 static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param)
 236 {
 237         struct l64781_state* state = fe->demodulator_priv;
 238         int tmp;
 239
 240
 241         tmp = l64781_readreg(state, 0x04);
 242         switch(tmp & 3) {
 243         case 0:
 244                 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 245                 break;
 246         case 1:
 247                 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 248                 break;
 249         case 2:
 250                 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 251                 break;
 252         case 3:
 253                 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 254                 break;
 255         }
 256         switch((tmp >> 2) & 3) {
 257         case 0:
 258                 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 259                 break;
 260         case 1:
 261                 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 262                 break;
 263         default:
 264                 printk("Unexpected value for transmission_mode\n");
 265         }
 266
 267
 268
 269         tmp = l64781_readreg(state, 0x05);
 270         switch(tmp & 7) {
 271         case 0:
 272                 param->u.ofdm.code_rate_HP = FEC_1_2;
 273                 break;
 274         case 1:
 275                 param->u.ofdm.code_rate_HP = FEC_2_3;
 276                 break;
 277         case 2:
 278                 param->u.ofdm.code_rate_HP = FEC_3_4;
 279                 break;
 280         case 3:
 281                 param->u.ofdm.code_rate_HP = FEC_5_6;
 282                 break;
 283         case 4:
 284                 param->u.ofdm.code_rate_HP = FEC_7_8;
 285                 break;
 286         default:
 287                 printk("Unexpected value for code_rate_HP\n");
 288         }
 289         switch((tmp >> 3) & 7) {
 290         case 0:
 291                 param->u.ofdm.code_rate_LP = FEC_1_2;
 292                 break;
 293         case 1:
 294                 param->u.ofdm.code_rate_LP = FEC_2_3;
 295                 break;
 296         case 2:
 297                 param->u.ofdm.code_rate_LP = FEC_3_4;
 298                 break;
 299         case 3:
 300                 param->u.ofdm.code_rate_LP = FEC_5_6;
 301                 break;
 302         case 4:
 303                 param->u.ofdm.code_rate_LP = FEC_7_8;
 304                 break;
 305         default:
 306                 printk("Unexpected value for code_rate_LP\n");
 307         }
 308
 309
 310         tmp = l64781_readreg(state, 0x06);
 311         switch(tmp & 3) {
 312         case 0:
 313                 param->u.ofdm.constellation = QPSK;
 314                 break;
 315         case 1:
 316                 param->u.ofdm.constellation = QAM_16;
 317                 break;
 318         case 2:
 319                 param->u.ofdm.constellation = QAM_64;
 320                 break;
 321         default:
 322                 printk("Unexpected value for constellation\n");
 323         }
 324         switch((tmp >> 2) & 7) {
 325         case 0:
 326                 param->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 327                 break;
 328         case 1:
 329                 param->u.ofdm.hierarchy_information = HIERARCHY_1;
 330                 break;
 331         case 2:
 332                 param->u.ofdm.hierarchy_information = HIERARCHY_2;
 333                 break;
 334         case 3:
 335                 param->u.ofdm.hierarchy_information = HIERARCHY_4;
 336                 break;
 337         default:
 338                 printk("Unexpected value for hierarchy\n");
 339         }
 340
 341
 342         tmp = l64781_readreg (state, 0x1d);
 343         param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
 344
 345         tmp = (int) (l64781_readreg (state, 0x08) |
 346                      (l64781_readreg (state, 0x09) << 8) |
 347                      (l64781_readreg (state, 0x0a) << 16));
 348         param->frequency += tmp;
 349
 350         return 0;
 351 }
 352
 353 static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status)
 354 {
 355         struct l64781_state* state = fe->demodulator_priv;
 356         int sync = l64781_readreg (state, 0x32);
 357         int gain = l64781_readreg (state, 0x0e);
 358
 359         l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
 360         l64781_readreg (state, 0x01);  /*  dto. */
 361
 362         *status = 0;
 363
 364         if (gain > 5)
 365                 *status |= FE_HAS_SIGNAL;
 366
 367         if (sync & 0x02) /* VCXO locked, this criteria should be ok */
 368                 *status |= FE_HAS_CARRIER;
 369
 370         if (sync & 0x20)
 371                 *status |= FE_HAS_VITERBI;
 372
 373         if (sync & 0x40)
 374                 *status |= FE_HAS_SYNC;
 375
 376         if (sync == 0x7f)
 377                 *status |= FE_HAS_LOCK;
 378
 379         return 0;
 380 }
 381
 382 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
 383 {
 384         struct l64781_state* state = fe->demodulator_priv;
 385
 386         /*   XXX FIXME: set up counting period (reg 0x26...0x28)
 387          */
 388         *ber = l64781_readreg (state, 0x39)
 389             | (l64781_readreg (state, 0x3a) << 8);
 390
 391         return 0;
 392 }
 393
 394 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 395 {
 396         struct l64781_state* state = fe->demodulator_priv;
 397
 398         u8 gain = l64781_readreg (state, 0x0e);
 399         *signal_strength = (gain << 8) | gain;
 400
 401         return 0;
 402 }
 403
 404 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
 405 {
 406         struct l64781_state* state = fe->demodulator_priv;
 407
 408         u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
 409         *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
 410
 411         return 0;
 412 }
 413
 414 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 415 {
 416         struct l64781_state* state = fe->demodulator_priv;
 417
 418         *ucblocks = l64781_readreg (state, 0x37)
 419            | (l64781_readreg (state, 0x38) << 8);
 420
 421         return 0;
 422 }
 423
 424 static int l64781_sleep(struct dvb_frontend* fe)
 425 {
 426         struct l64781_state* state = fe->demodulator_priv;
 427
 428         /* Power down */
 429         return l64781_writereg (state, 0x3e, 0x5a);
 430 }
 431
 432 static int l64781_init(struct dvb_frontend* fe)
 433 {
 434         struct l64781_state* state = fe->demodulator_priv;
 435
 436         reset_and_configure (state);
 437
 438         /* Power up */
 439         l64781_writereg (state, 0x3e, 0xa5);
 440
 441         /* Reset hard */
 442         l64781_writereg (state, 0x2a, 0x04);
 443         l64781_writereg (state, 0x2a, 0x00);
 444
 445         /* Set tuner specific things */
 446         /* AFC_POL, set also in reset_afc */
 447         l64781_writereg (state, 0x07, 0x8e);
 448
 449         /* Use internal ADC */
 450         l64781_writereg (state, 0x0b, 0x81);
 451
 452         /* AGC loop gain, and polarity is positive */
 453         l64781_writereg (state, 0x0c, 0x84);
 454
 455         /* Internal ADC outputs two's complement */
 456         l64781_writereg (state, 0x0d, 0x8c);
 457
 458         /* With ppm=8000, it seems the DTR_SENSITIVITY will result in
 459            value of 2 with all possible bandwidths and guard
 460            intervals, which is the initial value anyway. */
 461         /*l64781_writereg (state, 0x19, 0x92);*/
 462
 463         /* Everything is two's complement, soft bit and CSI_OUT too */
 464         l64781_writereg (state, 0x1e, 0x09);
 465
 466         if (state->config->pll_init) state->config->pll_init(fe);
 467
 468         /* delay a bit after first init attempt */
 469         if (state->first) {
 470                 state->first = 0;
 471                 msleep(200);
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int l64781_get_tune_settings(struct dvb_frontend* fe,
 478                                     struct dvb_frontend_tune_settings* fesettings)
 479 {
 480         fesettings->min_delay_ms = 4000;
 481         fesettings->step_size = 0;
 482         fesettings->max_drift = 0;
 483         return 0;
 484 }
 485
 486 static void l64781_release(struct dvb_frontend* fe)
 487 {
 488         struct l64781_state* state = fe->demodulator_priv;
 489         kfree(state);
 490 }
 491
 492 static struct dvb_frontend_ops l64781_ops;
 493
 494 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
 495                                    struct i2c_adapter* i2c)
 496 {
 497         struct l64781_state* state = NULL;
 498         int reg0x3e = -1;
 499         u8 b0 [] = { 0x1a };
 500         u8 b1 [] = { 0x00 };
 501         struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 502                            { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 503
 504         /* allocate memory for the internal state */
 505         state = kmalloc(sizeof(struct l64781_state), GFP_KERNEL);
 506         if (state == NULL) goto error;
 507
 508         /* setup the state */
 509         state->config = config;
 510         state->i2c = i2c;
 511         memcpy(&state->ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
 512         state->first = 1;
 513
 514         /**
 515          *  the L64781 won't show up before we send the reset_and_configure()
 516          *  broadcast. If nothing responds there is no L64781 on the bus...
 517          */
 518         if (reset_and_configure(state) < 0) {
 519                 dprintk("No response to reset and configure broadcast...\n");
 520                 goto error;
 521         }
 522
 523         /* The chip always responds to reads */
 524         if (i2c_transfer(state->i2c, msg, 2) != 2) {
 525                 dprintk("No response to read on I2C bus\n");
 526                 goto error;
 527         }
 528
 529         /* Save current register contents for bailout */
 530         reg0x3e = l64781_readreg(state, 0x3e);
 531
 532         /* Reading the POWER_DOWN register always returns 0 */
 533         if (reg0x3e != 0) {
 534                 dprintk("Device doesn't look like L64781\n");
 535                 goto error;
 536         }
 537
 538         /* Turn the chip off */
 539         l64781_writereg (state, 0x3e, 0x5a);
 540
 541         /* Responds to all reads with 0 */
 542         if (l64781_readreg(state, 0x1a) != 0) {
 543                 dprintk("Read 1 returned unexpcted value\n");
 544                 goto error;
 545         }
 546
 547         /* Turn the chip on */
 548         l64781_writereg (state, 0x3e, 0xa5);
 549
 550         /* Responds with register default value */
 551         if (l64781_readreg(state, 0x1a) != 0xa1) {
 552                 dprintk("Read 2 returned unexpcted value\n");
 553                 goto error;
 554         }
 555
 556         /* create dvb_frontend */
 557         state->frontend.ops = &state->ops;
 558         state->frontend.demodulator_priv = state;
 559         return &state->frontend;
 560
 561 error:
 562         if (reg0x3e >= 0)
 563                 l64781_writereg (state, 0x3e, reg0x3e);  /* restore reg 0x3e */
 564         kfree(state);
 565         return NULL;
 566 }
 567
 568 static struct dvb_frontend_ops l64781_ops = {
 569
 570         .info = {
 571                 .name = "LSI L64781 DVB-T",
 572                 .type = FE_OFDM,
 573         /*      .frequency_min = ???,*/
 574         /*      .frequency_max = ???,*/
 575                 .frequency_stepsize = 166666,
 576         /*      .frequency_tolerance = ???,*/
 577         /*      .symbol_rate_tolerance = ???,*/
 578                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 579                       FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 580                       FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
 581                       FE_CAN_MUTE_TS
 582         },
 583
 584         .release = l64781_release,
 585
 586         .init = l64781_init,
 587         .sleep = l64781_sleep,
 588
 589         .set_frontend = apply_frontend_param,
 590         .get_frontend = get_frontend,
 591         .get_tune_settings = l64781_get_tune_settings,
 592
 593         .read_status = l64781_read_status,
 594         .read_ber = l64781_read_ber,
 595         .read_signal_strength = l64781_read_signal_strength,
 596         .read_snr = l64781_read_snr,
 597         .read_ucblocks = l64781_read_ucblocks,
 598 };
 599
 600 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
 601 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
 602 MODULE_LICENSE("GPL");
 603
 604 EXPORT_SYMBOL(l64781_attach);