drivers/media/dvb/frontends/mt312.c

   1 /*
   2     Driver for Zarlink VP310/MT312 Satellite Channel Decoder
   3
   4     Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21     References:
  22     http://products.zarlink.com/product_profiles/MT312.htm
  23     http://products.zarlink.com/product_profiles/SL1935.htm
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/string.h>
  33 #include <linux/slab.h>
  34
  35 #include "dvb_frontend.h"
  36 #include "mt312_priv.h"
  37 #include "mt312.h"
  38
  39
  40 struct mt312_state {
  41         struct i2c_adapter* i2c;
  42         struct dvb_frontend_ops ops;
  43         /* configuration settings */
  44         const struct mt312_config* config;
  45         struct dvb_frontend frontend;
  46
  47         u8 id;
  48         u8 frequency;
  49 };
  50
  51 static int debug;
  52 #define dprintk(args...) \
  53         do { \
  54                 if (debug) printk(KERN_DEBUG "mt312: " args); \
  55         } while (0)
  56
  57 #define MT312_SYS_CLK           90000000UL      /* 90 MHz */
  58 #define MT312_LPOWER_SYS_CLK    60000000UL      /* 60 MHz */
  59 #define MT312_PLL_CLK           10000000UL      /* 10 MHz */
  60
  61 static int mt312_read(struct mt312_state* state, const enum mt312_reg_addr reg,
  62                       void *buf, const size_t count)
  63 {
  64         int ret;
  65         struct i2c_msg msg[2];
  66         u8 regbuf[1] = { reg };
  67
  68         msg[0].addr = state->config->demod_address;
  69         msg[0].flags = 0;
  70         msg[0].buf = regbuf;
  71         msg[0].len = 1;
  72         msg[1].addr = state->config->demod_address;
  73         msg[1].flags = I2C_M_RD;
  74         msg[1].buf = buf;
  75         msg[1].len = count;
  76
  77         ret = i2c_transfer(state->i2c, msg, 2);
  78
  79         if (ret != 2) {
  80                 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
  81                 return -EREMOTEIO;
  82         }
  83
  84         if(debug) {
  85                 int i;
  86                 dprintk("R(%d):", reg & 0x7f);
  87                 for (i = 0; i < count; i++)
  88                         printk(" %02x", ((const u8 *) buf)[i]);
  89                 printk("\n");
  90         }
  91
  92         return 0;
  93 }
  94
  95 static int mt312_write(struct mt312_state* state, const enum mt312_reg_addr reg,
  96                        const void *src, const size_t count)
  97 {
  98         int ret;
  99         u8 buf[count + 1];
 100         struct i2c_msg msg;
 101
 102         if(debug) {
 103                 int i;
 104                 dprintk("W(%d):", reg & 0x7f);
 105                 for (i = 0; i < count; i++)
 106                         printk(" %02x", ((const u8 *) src)[i]);
 107                 printk("\n");
 108         }
 109
 110         buf[0] = reg;
 111         memcpy(&buf[1], src, count);
 112
 113         msg.addr = state->config->demod_address;
 114         msg.flags = 0;
 115         msg.buf = buf;
 116         msg.len = count + 1;
 117
 118         ret = i2c_transfer(state->i2c, &msg, 1);
 119
 120         if (ret != 1) {
 121                 dprintk("%s: ret == %d\n", __FUNCTION__, ret);
 122                 return -EREMOTEIO;
 123         }
 124
 125         return 0;
 126 }
 127
 128 static inline int mt312_readreg(struct mt312_state* state,
 129                                 const enum mt312_reg_addr reg, u8 *val)
 130 {
 131         return mt312_read(state, reg, val, 1);
 132 }
 133
 134 static inline int mt312_writereg(struct mt312_state* state,
 135                                  const enum mt312_reg_addr reg, const u8 val)
 136 {
 137         return mt312_write(state, reg, &val, 1);
 138 }
 139
 140 static inline u32 mt312_div(u32 a, u32 b)
 141 {
 142         return (a + (b / 2)) / b;
 143 }
 144
 145 static int mt312_reset(struct mt312_state* state, const u8 full)
 146 {
 147         return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
 148 }
 149
 150 static int mt312_get_inversion(struct mt312_state* state,
 151                                fe_spectral_inversion_t *i)
 152 {
 153         int ret;
 154         u8 vit_mode;
 155
 156         if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0)
 157                 return ret;
 158
 159         if (vit_mode & 0x80)    /* auto inversion was used */
 160                 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
 161
 162         return 0;
 163 }
 164
 165 static int mt312_get_symbol_rate(struct mt312_state* state, u32 *sr)
 166 {
 167         int ret;
 168         u8 sym_rate_h;
 169         u8 dec_ratio;
 170         u16 sym_rat_op;
 171         u16 monitor;
 172         u8 buf[2];
 173
 174         if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0)
 175                 return ret;
 176
 177         if (sym_rate_h & 0x80) {        /* symbol rate search was used */
 178                 if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0)
 179                         return ret;
 180
 181                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 182                         return ret;
 183
 184                 monitor = (buf[0] << 8) | buf[1];
 185
 186                 dprintk(KERN_DEBUG "sr(auto) = %u\n",
 187                        mt312_div(monitor * 15625, 4));
 188         } else {
 189                 if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0)
 190                         return ret;
 191
 192                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 193                         return ret;
 194
 195                 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
 196
 197                 if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
 198                         return ret;
 199
 200                 sym_rat_op = (buf[0] << 8) | buf[1];
 201
 202                 dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
 203                        sym_rat_op, dec_ratio);
 204                 dprintk(KERN_DEBUG "*sr(manual) = %lu\n",
 205                        (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
 206                         2) - dec_ratio);
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int mt312_get_code_rate(struct mt312_state* state, fe_code_rate_t *cr)
 213 {
 214         const fe_code_rate_t fec_tab[8] =
 215             { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
 216                 FEC_AUTO, FEC_AUTO };
 217
 218         int ret;
 219         u8 fec_status;
 220
 221         if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0)
 222                 return ret;
 223
 224         *cr = fec_tab[(fec_status >> 4) & 0x07];
 225
 226         return 0;
 227 }
 228
 229 static int mt312_initfe(struct dvb_frontend* fe)
 230 {
 231         struct mt312_state *state = fe->demodulator_priv;
 232         int ret;
 233         u8 buf[2];
 234
 235         /* wake up */
 236         if ((ret = mt312_writereg(state, CONFIG, (state->frequency == 60 ? 0x88 : 0x8c))) < 0)
 237                 return ret;
 238
 239         /* wait at least 150 usec */
 240         udelay(150);
 241
 242         /* full reset */
 243         if ((ret = mt312_reset(state, 1)) < 0)
 244                 return ret;
 245
 246 // Per datasheet, write correct values. 09/28/03 ACCJr.
 247 // If we don't do this, we won't get FE_HAS_VITERBI in the VP310.
 248         {
 249                 u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};
 250
 251                 if ((ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)
 252                         return ret;
 253         }
 254
 255         /* SYS_CLK */
 256         buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);
 257
 258         /* DISEQC_RATIO */
 259         buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
 260
 261         if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0)
 262                 return ret;
 263
 264         if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0)
 265                 return ret;
 266
 267         if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0)
 268                 return ret;
 269
 270         /* TS_SW_LIM */
 271         buf[0] = 0x8c;
 272         buf[1] = 0x98;
 273
 274         if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
 275                 return ret;
 276
 277         if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0)
 278                 return ret;
 279
 280         if (state->config->pll_init) {
 281                 mt312_writereg(state, GPP_CTRL, 0x40);
 282                 state->config->pll_init(fe);
 283                 mt312_writereg(state, GPP_CTRL, 0x00);
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int mt312_send_master_cmd(struct dvb_frontend* fe,
 290                                  struct dvb_diseqc_master_cmd *c)
 291 {
 292         struct mt312_state *state = fe->demodulator_priv;
 293         int ret;
 294         u8 diseqc_mode;
 295
 296         if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
 297                 return -EINVAL;
 298
 299         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 300                 return ret;
 301
 302         if ((ret =
 303              mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
 304                 return ret;
 305
 306         if ((ret =
 307              mt312_writereg(state, DISEQC_MODE,
 308                             (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
 309                             | 0x04)) < 0)
 310                 return ret;
 311
 312         /* set DISEQC_MODE[2:0] to zero if a return message is expected */
 313         if (c->msg[0] & 0x02)
 314                 if ((ret =
 315                      mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
 316                         return ret;
 317
 318         return 0;
 319 }
 320
 321 static int mt312_send_burst(struct dvb_frontend* fe, const fe_sec_mini_cmd_t c)
 322 {
 323         struct mt312_state *state = fe->demodulator_priv;
 324         const u8 mini_tab[2] = { 0x02, 0x03 };
 325
 326         int ret;
 327         u8 diseqc_mode;
 328
 329         if (c > SEC_MINI_B)
 330                 return -EINVAL;
 331
 332         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 333                 return ret;
 334
 335         if ((ret =
 336              mt312_writereg(state, DISEQC_MODE,
 337                             (diseqc_mode & 0x40) | mini_tab[c])) < 0)
 338                 return ret;
 339
 340         return 0;
 341 }
 342
 343 static int mt312_set_tone(struct dvb_frontend* fe, const fe_sec_tone_mode_t t)
 344 {
 345         struct mt312_state *state = fe->demodulator_priv;
 346         const u8 tone_tab[2] = { 0x01, 0x00 };
 347
 348         int ret;
 349         u8 diseqc_mode;
 350
 351         if (t > SEC_TONE_OFF)
 352                 return -EINVAL;
 353
 354         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 355                 return ret;
 356
 357         if ((ret =
 358              mt312_writereg(state, DISEQC_MODE,
 359                             (diseqc_mode & 0x40) | tone_tab[t])) < 0)
 360                 return ret;
 361
 362         return 0;
 363 }
 364
 365 static int mt312_set_voltage(struct dvb_frontend* fe, const fe_sec_voltage_t v)
 366 {
 367         struct mt312_state *state = fe->demodulator_priv;
 368         const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
 369
 370         if (v > SEC_VOLTAGE_OFF)
 371                 return -EINVAL;
 372
 373         return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
 374 }
 375
 376 static int mt312_read_status(struct dvb_frontend* fe, fe_status_t *s)
 377 {
 378         struct mt312_state *state = fe->demodulator_priv;
 379         int ret;
 380         u8 status[3];
 381
 382         *s = 0;
 383
 384         if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0)
 385                 return ret;
 386
 387         dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
 388
 389         if (status[0] & 0xc0)
 390                 *s |= FE_HAS_SIGNAL;    /* signal noise ratio */
 391         if (status[0] & 0x04)
 392                 *s |= FE_HAS_CARRIER;   /* qpsk carrier lock */
 393         if (status[2] & 0x02)
 394                 *s |= FE_HAS_VITERBI;   /* viterbi lock */
 395         if (status[2] & 0x04)
 396                 *s |= FE_HAS_SYNC;      /* byte align lock */
 397         if (status[0] & 0x01)
 398                 *s |= FE_HAS_LOCK;      /* qpsk lock */
 399
 400         return 0;
 401 }
 402
 403 static int mt312_read_ber(struct dvb_frontend* fe, u32 *ber)
 404 {
 405         struct mt312_state *state = fe->demodulator_priv;
 406         int ret;
 407         u8 buf[3];
 408
 409         if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0)
 410                 return ret;
 411
 412         *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
 413
 414         return 0;
 415 }
 416
 417 static int mt312_read_signal_strength(struct dvb_frontend* fe, u16 *signal_strength)
 418 {
 419         struct mt312_state *state = fe->demodulator_priv;
 420         int ret;
 421         u8 buf[3];
 422         u16 agc;
 423         s16 err_db;
 424
 425         if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0)
 426                 return ret;
 427
 428         agc = (buf[0] << 6) | (buf[1] >> 2);
 429         err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
 430
 431         *signal_strength = agc;
 432
 433         dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
 434
 435         return 0;
 436 }
 437
 438 static int mt312_read_snr(struct dvb_frontend* fe, u16 *snr)
 439 {
 440         struct mt312_state *state = fe->demodulator_priv;
 441         int ret;
 442         u8 buf[2];
 443
 444         if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0)
 445                 return ret;
 446
 447         *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
 448
 449         return 0;
 450 }
 451
 452 static int mt312_read_ucblocks(struct dvb_frontend* fe, u32 *ubc)
 453 {
 454         struct mt312_state *state = fe->demodulator_priv;
 455         int ret;
 456         u8 buf[2];
 457
 458         if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0)
 459                 return ret;
 460
 461         *ubc = (buf[0] << 8) | buf[1];
 462
 463         return 0;
 464 }
 465
 466 static int mt312_set_frontend(struct dvb_frontend* fe,
 467                               struct dvb_frontend_parameters *p)
 468 {
 469         struct mt312_state *state = fe->demodulator_priv;
 470         int ret;
 471         u8 buf[5], config_val;
 472         u16 sr;
 473
 474         const u8 fec_tab[10] =
 475             { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
 476         const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
 477
 478         dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
 479
 480         if ((p->frequency < fe->ops->info.frequency_min)
 481             || (p->frequency > fe->ops->info.frequency_max))
 482                 return -EINVAL;
 483
 484         if ((p->inversion < INVERSION_OFF)
 485             || (p->inversion > INVERSION_ON))
 486                 return -EINVAL;
 487
 488         if ((p->u.qpsk.symbol_rate < fe->ops->info.symbol_rate_min)
 489             || (p->u.qpsk.symbol_rate > fe->ops->info.symbol_rate_max))
 490                 return -EINVAL;
 491
 492         if ((p->u.qpsk.fec_inner < FEC_NONE)
 493             || (p->u.qpsk.fec_inner > FEC_AUTO))
 494                 return -EINVAL;
 495
 496         if ((p->u.qpsk.fec_inner == FEC_4_5)
 497             || (p->u.qpsk.fec_inner == FEC_8_9))
 498                 return -EINVAL;
 499
 500         switch (state->id) {
 501         case ID_VP310:
 502         // For now we will do this only for the VP310.
 503         // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03
 504                 ret = mt312_readreg(state, CONFIG, &config_val);
 505                 if (ret < 0)
 506                         return ret;
 507                 if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz
 508                 {
 509                         if ((config_val & 0x0c) == 0x08) { //We are running 60MHz
 510                                 state->frequency = 90;
 511                                 if ((ret = mt312_initfe(fe)) < 0)
 512                                         return ret;
 513                         }
 514                 }
 515                 else
 516                 {
 517                         if ((config_val & 0x0c) == 0x0C) { //We are running 90MHz
 518                                 state->frequency = 60;
 519                                 if ((ret = mt312_initfe(fe)) < 0)
 520                                         return ret;
 521                         }
 522                 }
 523                 break;
 524
 525         case ID_MT312:
 526                 break;
 527
 528         default:
 529                 return -EINVAL;
 530         }
 531
 532         mt312_writereg(state, GPP_CTRL, 0x40);
 533         state->config->pll_set(fe, p);
 534         mt312_writereg(state, GPP_CTRL, 0x00);
 535
 536         /* sr = (u16)(sr * 256.0 / 1000000.0) */
 537         sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
 538
 539         /* SYM_RATE */
 540         buf[0] = (sr >> 8) & 0x3f;
 541         buf[1] = (sr >> 0) & 0xff;
 542
 543         /* VIT_MODE */
 544         buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
 545
 546         /* QPSK_CTRL */
 547         buf[3] = 0x40;          /* swap I and Q before QPSK demodulation */
 548
 549         if (p->u.qpsk.symbol_rate < 10000000)
 550                 buf[3] |= 0x04; /* use afc mode */
 551
 552         /* GO */
 553         buf[4] = 0x01;
 554
 555         if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0)
 556                 return ret;
 557
 558         mt312_reset(state, 0);
 559
 560         return 0;
 561 }
 562
 563 static int mt312_get_frontend(struct dvb_frontend* fe,
 564                               struct dvb_frontend_parameters *p)
 565 {
 566         struct mt312_state *state = fe->demodulator_priv;
 567         int ret;
 568
 569         if ((ret = mt312_get_inversion(state, &p->inversion)) < 0)
 570                 return ret;
 571
 572         if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0)
 573                 return ret;
 574
 575         if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0)
 576                 return ret;
 577
 578         return 0;
 579 }
 580
 581 static int mt312_sleep(struct dvb_frontend* fe)
 582 {
 583         struct mt312_state *state = fe->demodulator_priv;
 584         int ret;
 585         u8 config;
 586
 587         /* reset all registers to defaults */
 588         if ((ret = mt312_reset(state, 1)) < 0)
 589                 return ret;
 590
 591         if ((ret = mt312_readreg(state, CONFIG, &config)) < 0)
 592                 return ret;
 593
 594         /* enter standby */
 595         if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0)
 596                 return ret;
 597
 598         return 0;
 599 }
 600
 601 static int mt312_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 602 {
 603         fesettings->min_delay_ms = 50;
 604         fesettings->step_size = 0;
 605         fesettings->max_drift = 0;
 606         return 0;
 607 }
 608
 609 static void mt312_release(struct dvb_frontend* fe)
 610 {
 611         struct mt312_state* state = fe->demodulator_priv;
 612         kfree(state);
 613 }
 614
 615 static struct dvb_frontend_ops vp310_mt312_ops;
 616
 617 struct dvb_frontend* vp310_attach(const struct mt312_config* config,
 618                                   struct i2c_adapter* i2c)
 619 {
 620         struct mt312_state* state = NULL;
 621
 622         /* allocate memory for the internal state */
 623         state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
 624         if (state == NULL)
 625                 goto error;
 626
 627         /* setup the state */
 628         state->config = config;
 629         state->i2c = i2c;
 630         memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
 631         strcpy(state->ops.info.name, "Zarlink VP310 DVB-S");
 632
 633         /* check if the demod is there */
 634         if (mt312_readreg(state, ID, &state->id) < 0)
 635                 goto error;
 636         if (state->id != ID_VP310) {
 637                 goto error;
 638         }
 639
 640         /* create dvb_frontend */
 641         state->frequency = 90;
 642         state->frontend.ops = &state->ops;
 643         state->frontend.demodulator_priv = state;
 644         return &state->frontend;
 645
 646 error:
 647         kfree(state);
 648         return NULL;
 649 }
 650
 651 struct dvb_frontend* mt312_attach(const struct mt312_config* config,
 652                                   struct i2c_adapter* i2c)
 653 {
 654         struct mt312_state* state = NULL;
 655
 656         /* allocate memory for the internal state */
 657         state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
 658         if (state == NULL)
 659                 goto error;
 660
 661         /* setup the state */
 662         state->config = config;
 663         state->i2c = i2c;
 664         memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
 665         strcpy(state->ops.info.name, "Zarlink MT312 DVB-S");
 666
 667         /* check if the demod is there */
 668         if (mt312_readreg(state, ID, &state->id) < 0)
 669                 goto error;
 670         if (state->id != ID_MT312) {
 671                 goto error;
 672         }
 673
 674         /* create dvb_frontend */
 675         state->frequency = 60;
 676         state->frontend.ops = &state->ops;
 677         state->frontend.demodulator_priv = state;
 678         return &state->frontend;
 679
 680 error:
 681         kfree(state);
 682         return NULL;
 683 }
 684
 685 static struct dvb_frontend_ops vp310_mt312_ops = {
 686
 687         .info = {
 688                 .name = "Zarlink ???? DVB-S",
 689                 .type = FE_QPSK,
 690                 .frequency_min = 950000,
 691                 .frequency_max = 2150000,
 692                 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
 693                 .symbol_rate_min = MT312_SYS_CLK / 128,
 694                 .symbol_rate_max = MT312_SYS_CLK / 2,
 695                 .caps =
 696                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 697                     FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 698                     FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
 699                     FE_CAN_RECOVER
 700         },
 701
 702         .release = mt312_release,
 703
 704         .init = mt312_initfe,
 705         .sleep = mt312_sleep,
 706
 707         .set_frontend = mt312_set_frontend,
 708         .get_frontend = mt312_get_frontend,
 709         .get_tune_settings = mt312_get_tune_settings,
 710
 711         .read_status = mt312_read_status,
 712         .read_ber = mt312_read_ber,
 713         .read_signal_strength = mt312_read_signal_strength,
 714         .read_snr = mt312_read_snr,
 715         .read_ucblocks = mt312_read_ucblocks,
 716
 717         .diseqc_send_master_cmd = mt312_send_master_cmd,
 718         .diseqc_send_burst = mt312_send_burst,
 719         .set_tone = mt312_set_tone,
 720         .set_voltage = mt312_set_voltage,
 721 };
 722
 723 module_param(debug, int, 0644);
 724 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 725
 726 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
 727 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
 728 MODULE_LICENSE("GPL");
 729
 730 EXPORT_SYMBOL(mt312_attach);
 731 EXPORT_SYMBOL(vp310_attach);