[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / drivers / net / fs_enet / mac-fcc.c
blobe67b1d06611cfb84bf44ce65bf35bba4852f63a9
1 /*
2 * FCC driver for Motorola MPC82xx (PQ2).
4 * Copyright (c) 2003 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/config.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/ptrace.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/spinlock.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/bitops.h>
36 #include <linux/fs.h>
37 #include <linux/platform_device.h>
39 #include <asm/immap_cpm2.h>
40 #include <asm/mpc8260.h>
41 #include <asm/cpm2.h>
43 #include <asm/pgtable.h>
44 #include <asm/irq.h>
45 #include <asm/uaccess.h>
47 #include "fs_enet.h"
49 /*************************************************/
51 /* FCC access macros */
53 #define __fcc_out32(addr, x) out_be32((unsigned *)addr, x)
54 #define __fcc_out16(addr, x) out_be16((unsigned short *)addr, x)
55 #define __fcc_out8(addr, x) out_8((unsigned char *)addr, x)
56 #define __fcc_in32(addr) in_be32((unsigned *)addr)
57 #define __fcc_in16(addr) in_be16((unsigned short *)addr)
58 #define __fcc_in8(addr) in_8((unsigned char *)addr)
60 /* parameter space */
62 /* write, read, set bits, clear bits */
63 #define W32(_p, _m, _v) __fcc_out32(&(_p)->_m, (_v))
64 #define R32(_p, _m) __fcc_in32(&(_p)->_m)
65 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
66 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
68 #define W16(_p, _m, _v) __fcc_out16(&(_p)->_m, (_v))
69 #define R16(_p, _m) __fcc_in16(&(_p)->_m)
70 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
71 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
73 #define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v))
74 #define R8(_p, _m) __fcc_in8(&(_p)->_m)
75 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
76 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
78 /*************************************************/
80 #define FCC_MAX_MULTICAST_ADDRS 64
82 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
83 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
84 #define mk_mii_end 0
86 #define MAX_CR_CMD_LOOPS 10000
88 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op)
90 const struct fs_platform_info *fpi = fep->fpi;
92 cpm2_map_t *immap = fs_enet_immap;
93 cpm_cpm2_t *cpmp = &immap->im_cpm;
94 u32 v;
95 int i;
97 /* Currently I don't know what feature call will look like. But
98 I guess there'd be something like do_cpm_cmd() which will require page & sblock */
99 v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op);
100 W32(cpmp, cp_cpcr, v | CPM_CR_FLG);
101 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
102 if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
103 break;
105 if (i >= MAX_CR_CMD_LOOPS) {
106 printk(KERN_ERR "%s(): Not able to issue CPM command\n",
107 __FUNCTION__);
108 return 1;
111 return 0;
114 static int do_pd_setup(struct fs_enet_private *fep)
116 struct platform_device *pdev = to_platform_device(fep->dev);
117 struct resource *r;
119 /* Fill out IRQ field */
120 fep->interrupt = platform_get_irq(pdev, 0);
122 /* Attach the memory for the FCC Parameter RAM */
123 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
124 fep->fcc.ep = (void *)r->start;
126 if (fep->fcc.ep == NULL)
127 return -EINVAL;
129 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
130 fep->fcc.fccp = (void *)r->start;
132 if (fep->fcc.fccp == NULL)
133 return -EINVAL;
135 fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
137 if (fep->fcc.fcccp == NULL)
138 return -EINVAL;
140 return 0;
143 #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
144 #define FCC_RX_EVENT (FCC_ENET_RXF)
145 #define FCC_TX_EVENT (FCC_ENET_TXB)
146 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
148 static int setup_data(struct net_device *dev)
150 struct fs_enet_private *fep = netdev_priv(dev);
151 const struct fs_platform_info *fpi = fep->fpi;
153 fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
154 if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
155 return -EINVAL;
157 fep->fcc.mem = (void *)fpi->mem_offset;
159 if (do_pd_setup(fep) != 0)
160 return -EINVAL;
162 fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
163 fep->ev_rx = FCC_RX_EVENT;
164 fep->ev_tx = FCC_TX_EVENT;
165 fep->ev_err = FCC_ERR_EVENT_MSK;
167 return 0;
170 static int allocate_bd(struct net_device *dev)
172 struct fs_enet_private *fep = netdev_priv(dev);
173 const struct fs_platform_info *fpi = fep->fpi;
175 fep->ring_base = dma_alloc_coherent(fep->dev,
176 (fpi->tx_ring + fpi->rx_ring) *
177 sizeof(cbd_t), &fep->ring_mem_addr,
178 GFP_KERNEL);
179 if (fep->ring_base == NULL)
180 return -ENOMEM;
182 return 0;
185 static void free_bd(struct net_device *dev)
187 struct fs_enet_private *fep = netdev_priv(dev);
188 const struct fs_platform_info *fpi = fep->fpi;
190 if (fep->ring_base)
191 dma_free_coherent(fep->dev,
192 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
193 fep->ring_base, fep->ring_mem_addr);
196 static void cleanup_data(struct net_device *dev)
198 /* nothing */
201 static void set_promiscuous_mode(struct net_device *dev)
203 struct fs_enet_private *fep = netdev_priv(dev);
204 fcc_t *fccp = fep->fcc.fccp;
206 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
209 static void set_multicast_start(struct net_device *dev)
211 struct fs_enet_private *fep = netdev_priv(dev);
212 fcc_enet_t *ep = fep->fcc.ep;
214 W32(ep, fen_gaddrh, 0);
215 W32(ep, fen_gaddrl, 0);
218 static void set_multicast_one(struct net_device *dev, const u8 *mac)
220 struct fs_enet_private *fep = netdev_priv(dev);
221 fcc_enet_t *ep = fep->fcc.ep;
222 u16 taddrh, taddrm, taddrl;
224 taddrh = ((u16)mac[5] << 8) | mac[4];
225 taddrm = ((u16)mac[3] << 8) | mac[2];
226 taddrl = ((u16)mac[1] << 8) | mac[0];
228 W16(ep, fen_taddrh, taddrh);
229 W16(ep, fen_taddrm, taddrm);
230 W16(ep, fen_taddrl, taddrl);
231 fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR);
234 static void set_multicast_finish(struct net_device *dev)
236 struct fs_enet_private *fep = netdev_priv(dev);
237 fcc_t *fccp = fep->fcc.fccp;
238 fcc_enet_t *ep = fep->fcc.ep;
240 /* clear promiscuous always */
241 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
243 /* if all multi or too many multicasts; just enable all */
244 if ((dev->flags & IFF_ALLMULTI) != 0 ||
245 dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
247 W32(ep, fen_gaddrh, 0xffffffff);
248 W32(ep, fen_gaddrl, 0xffffffff);
251 /* read back */
252 fep->fcc.gaddrh = R32(ep, fen_gaddrh);
253 fep->fcc.gaddrl = R32(ep, fen_gaddrl);
256 static void set_multicast_list(struct net_device *dev)
258 struct dev_mc_list *pmc;
260 if ((dev->flags & IFF_PROMISC) == 0) {
261 set_multicast_start(dev);
262 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
263 set_multicast_one(dev, pmc->dmi_addr);
264 set_multicast_finish(dev);
265 } else
266 set_promiscuous_mode(dev);
269 static void restart(struct net_device *dev)
271 struct fs_enet_private *fep = netdev_priv(dev);
272 const struct fs_platform_info *fpi = fep->fpi;
273 fcc_t *fccp = fep->fcc.fccp;
274 fcc_c_t *fcccp = fep->fcc.fcccp;
275 fcc_enet_t *ep = fep->fcc.ep;
276 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
277 u16 paddrh, paddrm, paddrl;
278 u16 mem_addr;
279 const unsigned char *mac;
280 int i;
282 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
284 /* clear everything (slow & steady does it) */
285 for (i = 0; i < sizeof(*ep); i++)
286 __fcc_out8((char *)ep + i, 0);
288 /* get physical address */
289 rx_bd_base_phys = fep->ring_mem_addr;
290 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
292 /* point to bds */
293 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
294 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
296 /* Set maximum bytes per receive buffer.
297 * It must be a multiple of 32.
299 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
301 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
302 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
304 /* Allocate space in the reserved FCC area of DPRAM for the
305 * internal buffers. No one uses this space (yet), so we
306 * can do this. Later, we will add resource management for
307 * this area.
310 mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
312 W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
313 W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
314 W16(ep, fen_padptr, mem_addr + 64);
316 /* fill with special symbol... */
317 memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
319 W32(ep, fen_genfcc.fcc_rbptr, 0);
320 W32(ep, fen_genfcc.fcc_tbptr, 0);
321 W32(ep, fen_genfcc.fcc_rcrc, 0);
322 W32(ep, fen_genfcc.fcc_tcrc, 0);
323 W16(ep, fen_genfcc.fcc_res1, 0);
324 W32(ep, fen_genfcc.fcc_res2, 0);
326 /* no CAM */
327 W32(ep, fen_camptr, 0);
329 /* Set CRC preset and mask */
330 W32(ep, fen_cmask, 0xdebb20e3);
331 W32(ep, fen_cpres, 0xffffffff);
333 W32(ep, fen_crcec, 0); /* CRC Error counter */
334 W32(ep, fen_alec, 0); /* alignment error counter */
335 W32(ep, fen_disfc, 0); /* discard frame counter */
336 W16(ep, fen_retlim, 15); /* Retry limit threshold */
337 W16(ep, fen_pper, 0); /* Normal persistence */
339 /* set group address */
340 W32(ep, fen_gaddrh, fep->fcc.gaddrh);
341 W32(ep, fen_gaddrl, fep->fcc.gaddrh);
343 /* Clear hash filter tables */
344 W32(ep, fen_iaddrh, 0);
345 W32(ep, fen_iaddrl, 0);
347 /* Clear the Out-of-sequence TxBD */
348 W16(ep, fen_tfcstat, 0);
349 W16(ep, fen_tfclen, 0);
350 W32(ep, fen_tfcptr, 0);
352 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
353 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
355 /* set address */
356 mac = dev->dev_addr;
357 paddrh = ((u16)mac[5] << 8) | mac[4];
358 paddrm = ((u16)mac[3] << 8) | mac[2];
359 paddrl = ((u16)mac[1] << 8) | mac[0];
361 W16(ep, fen_paddrh, paddrh);
362 W16(ep, fen_paddrm, paddrm);
363 W16(ep, fen_paddrl, paddrl);
365 W16(ep, fen_taddrh, 0);
366 W16(ep, fen_taddrm, 0);
367 W16(ep, fen_taddrl, 0);
369 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
370 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
372 /* Clear stat counters, in case we ever enable RMON */
373 W32(ep, fen_octc, 0);
374 W32(ep, fen_colc, 0);
375 W32(ep, fen_broc, 0);
376 W32(ep, fen_mulc, 0);
377 W32(ep, fen_uspc, 0);
378 W32(ep, fen_frgc, 0);
379 W32(ep, fen_ospc, 0);
380 W32(ep, fen_jbrc, 0);
381 W32(ep, fen_p64c, 0);
382 W32(ep, fen_p65c, 0);
383 W32(ep, fen_p128c, 0);
384 W32(ep, fen_p256c, 0);
385 W32(ep, fen_p512c, 0);
386 W32(ep, fen_p1024c, 0);
388 W16(ep, fen_rfthr, 0); /* Suggested by manual */
389 W16(ep, fen_rfcnt, 0);
390 W16(ep, fen_cftype, 0);
392 fs_init_bds(dev);
394 /* adjust to speed (for RMII mode) */
395 if (fpi->use_rmii) {
396 if (fep->speed == 100)
397 C8(fcccp, fcc_gfemr, 0x20);
398 else
399 S8(fcccp, fcc_gfemr, 0x20);
402 fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX);
404 /* clear events */
405 W16(fccp, fcc_fcce, 0xffff);
407 /* Enable interrupts we wish to service */
408 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
410 /* Set GFMR to enable Ethernet operating mode */
411 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
413 /* set sync/delimiters */
414 W16(fccp, fcc_fdsr, 0xd555);
416 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
418 if (fpi->use_rmii)
419 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
421 /* adjust to duplex mode */
422 if (fep->duplex)
423 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
424 else
425 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
427 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
430 static void stop(struct net_device *dev)
432 struct fs_enet_private *fep = netdev_priv(dev);
433 fcc_t *fccp = fep->fcc.fccp;
435 /* stop ethernet */
436 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
438 /* clear events */
439 W16(fccp, fcc_fcce, 0xffff);
441 /* clear interrupt mask */
442 W16(fccp, fcc_fccm, 0);
444 fs_cleanup_bds(dev);
447 static void pre_request_irq(struct net_device *dev, int irq)
449 /* nothing */
452 static void post_free_irq(struct net_device *dev, int irq)
454 /* nothing */
457 static void napi_clear_rx_event(struct net_device *dev)
459 struct fs_enet_private *fep = netdev_priv(dev);
460 fcc_t *fccp = fep->fcc.fccp;
462 W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
465 static void napi_enable_rx(struct net_device *dev)
467 struct fs_enet_private *fep = netdev_priv(dev);
468 fcc_t *fccp = fep->fcc.fccp;
470 S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
473 static void napi_disable_rx(struct net_device *dev)
475 struct fs_enet_private *fep = netdev_priv(dev);
476 fcc_t *fccp = fep->fcc.fccp;
478 C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
481 static void rx_bd_done(struct net_device *dev)
483 /* nothing */
486 static void tx_kickstart(struct net_device *dev)
488 /* nothing */
491 static u32 get_int_events(struct net_device *dev)
493 struct fs_enet_private *fep = netdev_priv(dev);
494 fcc_t *fccp = fep->fcc.fccp;
496 return (u32)R16(fccp, fcc_fcce);
499 static void clear_int_events(struct net_device *dev, u32 int_events)
501 struct fs_enet_private *fep = netdev_priv(dev);
502 fcc_t *fccp = fep->fcc.fccp;
504 W16(fccp, fcc_fcce, int_events & 0xffff);
507 static void ev_error(struct net_device *dev, u32 int_events)
509 printk(KERN_WARNING DRV_MODULE_NAME
510 ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
513 int get_regs(struct net_device *dev, void *p, int *sizep)
515 struct fs_enet_private *fep = netdev_priv(dev);
517 if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t))
518 return -EINVAL;
520 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
521 p = (char *)p + sizeof(fcc_t);
523 memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t));
524 p = (char *)p + sizeof(fcc_c_t);
526 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
528 return 0;
531 int get_regs_len(struct net_device *dev)
533 return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t);
536 /* Some transmit errors cause the transmitter to shut
537 * down. We now issue a restart transmit. Since the
538 * errors close the BD and update the pointers, the restart
539 * _should_ pick up without having to reset any of our
540 * pointers either. Also, To workaround 8260 device erratum
541 * CPM37, we must disable and then re-enable the transmitter
542 * following a Late Collision, Underrun, or Retry Limit error.
544 void tx_restart(struct net_device *dev)
546 struct fs_enet_private *fep = netdev_priv(dev);
547 fcc_t *fccp = fep->fcc.fccp;
549 C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
550 udelay(10);
551 S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
553 fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX);
556 /*************************************************************************/
558 const struct fs_ops fs_fcc_ops = {
559 .setup_data = setup_data,
560 .cleanup_data = cleanup_data,
561 .set_multicast_list = set_multicast_list,
562 .restart = restart,
563 .stop = stop,
564 .pre_request_irq = pre_request_irq,
565 .post_free_irq = post_free_irq,
566 .napi_clear_rx_event = napi_clear_rx_event,
567 .napi_enable_rx = napi_enable_rx,
568 .napi_disable_rx = napi_disable_rx,
569 .rx_bd_done = rx_bd_done,
570 .tx_kickstart = tx_kickstart,
571 .get_int_events = get_int_events,
572 .clear_int_events = clear_int_events,
573 .ev_error = ev_error,
574 .get_regs = get_regs,
575 .get_regs_len = get_regs_len,
576 .tx_restart = tx_restart,
577 .allocate_bd = allocate_bd,
578 .free_bd = free_bd,