?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / drivers / net / fs_enet / mac-fec.c
blob2e8f444696999312562430600ecb55d4c0f096aa
1 /*
2 * Freescale Ethernet controllers
3 *
4 * Copyright (c) 2005 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/config.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/ptrace.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/spinlock.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/bitops.h>
36 #include <linux/fs.h>
37 #include <linux/platform_device.h>
38
39 #include <asm/irq.h>
40 #include <asm/uaccess.h>
41
42 #ifdef CONFIG_8xx
43 #include <asm/8xx_immap.h>
44 #include <asm/pgtable.h>
45 #include <asm/mpc8xx.h>
46 #include <asm/commproc.h>
47 #endif
48
49 #include "fs_enet.h"
50
51 /*************************************************/
52
53 #if defined(CONFIG_CPM1)
54 /* for a CPM1 __raw_xxx's are sufficient */
55 #define __fs_out32(addr, x) __raw_writel(x, addr)
56 #define __fs_out16(addr, x) __raw_writew(x, addr)
57 #define __fs_in32(addr) __raw_readl(addr)
58 #define __fs_in16(addr) __raw_readw(addr)
59 #else
60 /* for others play it safe */
61 #define __fs_out32(addr, x) out_be32(addr, x)
62 #define __fs_out16(addr, x) out_be16(addr, x)
63 #define __fs_in32(addr) in_be32(addr)
64 #define __fs_in16(addr) in_be16(addr)
65 #endif
66
67 /* write */
68 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
69
70 /* read */
71 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
72
73 /* set bits */
74 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
75
76 /* clear bits */
77 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
78
79
80 /* CRC polynomium used by the FEC for the multicast group filtering */
81 #define FEC_CRC_POLY 0x04C11DB7
82
83 #define FEC_MAX_MULTICAST_ADDRS 64
84
85 /* Interrupt events/masks.
86 */
87 #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
88 #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
89 #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
90 #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
91 #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
92 #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
93 #define FEC_ENET_RXF 0x02000000U /* Full frame received */
94 #define FEC_ENET_RXB 0x01000000U /* A buffer was received */
95 #define FEC_ENET_MII 0x00800000U /* MII interrupt */
96 #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
97
98 #define FEC_ECNTRL_PINMUX 0x00000004
99 #define FEC_ECNTRL_ETHER_EN 0x00000002
100 #define FEC_ECNTRL_RESET 0x00000001
101
102 #define FEC_RCNTRL_BC_REJ 0x00000010
103 #define FEC_RCNTRL_PROM 0x00000008
104 #define FEC_RCNTRL_MII_MODE 0x00000004
105 #define FEC_RCNTRL_DRT 0x00000002
106 #define FEC_RCNTRL_LOOP 0x00000001
107
108 #define FEC_TCNTRL_FDEN 0x00000004
109 #define FEC_TCNTRL_HBC 0x00000002
110 #define FEC_TCNTRL_GTS 0x00000001
111
112
113 /* Make MII read/write commands for the FEC.
114 */
115 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
116 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
117 #define mk_mii_end 0
118
119 #define FEC_MII_LOOPS 10000
120
121 /*
122 * Delay to wait for FEC reset command to complete (in us)
123 */
124 #define FEC_RESET_DELAY 50
125
126 static int whack_reset(fec_t * fecp)
127 {
128 int i;
129
130 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
131 for (i = 0; i < FEC_RESET_DELAY; i++) {
132 if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
133 return 0; /* OK */
134 udelay(1);
135 }
136
137 return -1;
138 }
139
140 static int do_pd_setup(struct fs_enet_private *fep)
141 {
142 struct platform_device *pdev = to_platform_device(fep->dev);
143 struct resource *r;
144
145 /* Fill out IRQ field */
146 fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
147
148 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
149 fep->fec.fecp =(void*)r->start;
150
151 if(fep->fec.fecp == NULL)
152 return -EINVAL;
153
154 return 0;
155
156 }
157
158 #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
159 #define FEC_RX_EVENT (FEC_ENET_RXF)
160 #define FEC_TX_EVENT (FEC_ENET_TXF)
161 #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
162 FEC_ENET_BABT | FEC_ENET_EBERR)
163
164 static int setup_data(struct net_device *dev)
165 {
166 struct fs_enet_private *fep = netdev_priv(dev);
167
168 if (do_pd_setup(fep) != 0)
169 return -EINVAL;
170
171 fep->fec.hthi = 0;
172 fep->fec.htlo = 0;
173
174 fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
175 fep->ev_rx = FEC_RX_EVENT;
176 fep->ev_tx = FEC_TX_EVENT;
177 fep->ev_err = FEC_ERR_EVENT_MSK;
178
179 return 0;
180 }
181
182 static int allocate_bd(struct net_device *dev)
183 {
184 struct fs_enet_private *fep = netdev_priv(dev);
185 const struct fs_platform_info *fpi = fep->fpi;
186
187 fep->ring_base = dma_alloc_coherent(fep->dev,
188 (fpi->tx_ring + fpi->rx_ring) *
189 sizeof(cbd_t), &fep->ring_mem_addr,
190 GFP_KERNEL);
191 if (fep->ring_base == NULL)
192 return -ENOMEM;
193
194 return 0;
195 }
196
197 static void free_bd(struct net_device *dev)
198 {
199 struct fs_enet_private *fep = netdev_priv(dev);
200 const struct fs_platform_info *fpi = fep->fpi;
201
202 if(fep->ring_base)
203 dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
204 * sizeof(cbd_t),
205 fep->ring_base,
206 fep->ring_mem_addr);
207 }
208
209 static void cleanup_data(struct net_device *dev)
210 {
211 /* nothing */
212 }
213
214 static void set_promiscuous_mode(struct net_device *dev)
215 {
216 struct fs_enet_private *fep = netdev_priv(dev);
217 fec_t *fecp = fep->fec.fecp;
218
219 FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
220 }
221
222 static void set_multicast_start(struct net_device *dev)
223 {
224 struct fs_enet_private *fep = netdev_priv(dev);
225
226 fep->fec.hthi = 0;
227 fep->fec.htlo = 0;
228 }
229
230 static void set_multicast_one(struct net_device *dev, const u8 *mac)
231 {
232 struct fs_enet_private *fep = netdev_priv(dev);
233 int temp, hash_index, i, j;
234 u32 crc, csrVal;
235 u8 byte, msb;
236
237 crc = 0xffffffff;
238 for (i = 0; i < 6; i++) {
239 byte = mac[i];
240 for (j = 0; j < 8; j++) {
241 msb = crc >> 31;
242 crc <<= 1;
243 if (msb ^ (byte & 0x1))
244 crc ^= FEC_CRC_POLY;
245 byte >>= 1;
246 }
247 }
248
249 temp = (crc & 0x3f) >> 1;
250 hash_index = ((temp & 0x01) << 4) |
251 ((temp & 0x02) << 2) |
252 ((temp & 0x04)) |
253 ((temp & 0x08) >> 2) |
254 ((temp & 0x10) >> 4);
255 csrVal = 1 << hash_index;
256 if (crc & 1)
257 fep->fec.hthi |= csrVal;
258 else
259 fep->fec.htlo |= csrVal;
260 }
261
262 static void set_multicast_finish(struct net_device *dev)
263 {
264 struct fs_enet_private *fep = netdev_priv(dev);
265 fec_t *fecp = fep->fec.fecp;
266
267 /* if all multi or too many multicasts; just enable all */
268 if ((dev->flags & IFF_ALLMULTI) != 0 ||
269 dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
270 fep->fec.hthi = 0xffffffffU;
271 fep->fec.htlo = 0xffffffffU;
272 }
273
274 FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
275 FW(fecp, hash_table_high, fep->fec.hthi);
276 FW(fecp, hash_table_low, fep->fec.htlo);
277 }
278
279 static void set_multicast_list(struct net_device *dev)
280 {
281 struct dev_mc_list *pmc;
282
283 if ((dev->flags & IFF_PROMISC) == 0) {
284 set_multicast_start(dev);
285 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
286 set_multicast_one(dev, pmc->dmi_addr);
287 set_multicast_finish(dev);
288 } else
289 set_promiscuous_mode(dev);
290 }
291
292 static void restart(struct net_device *dev)
293 {
294 #ifdef CONFIG_DUET
295 immap_t *immap = fs_enet_immap;
296 u32 cptr;
297 #endif
298 struct fs_enet_private *fep = netdev_priv(dev);
299 fec_t *fecp = fep->fec.fecp;
300 const struct fs_platform_info *fpi = fep->fpi;
301 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
302 int r;
303 u32 addrhi, addrlo;
304
305 r = whack_reset(fep->fec.fecp);
306 if (r != 0)
307 printk(KERN_ERR DRV_MODULE_NAME
308 ": %s FEC Reset FAILED!\n", dev->name);
309
310 /*
311 * Set station address.
312 */
313 addrhi = ((u32) dev->dev_addr[0] << 24) |
314 ((u32) dev->dev_addr[1] << 16) |
315 ((u32) dev->dev_addr[2] << 8) |
316 (u32) dev->dev_addr[3];
317 addrlo = ((u32) dev->dev_addr[4] << 24) |
318 ((u32) dev->dev_addr[5] << 16);
319 FW(fecp, addr_low, addrhi);
320 FW(fecp, addr_high, addrlo);
321
322 /*
323 * Reset all multicast.
324 */
325 FW(fecp, hash_table_high, fep->fec.hthi);
326 FW(fecp, hash_table_low, fep->fec.htlo);
327
328 /*
329 * Set maximum receive buffer size.
330 */
331 FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
332 FW(fecp, r_hash, PKT_MAXBUF_SIZE);
333
334 /* get physical address */
335 rx_bd_base_phys = fep->ring_mem_addr;
336 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
337
338 /*
339 * Set receive and transmit descriptor base.
340 */
341 FW(fecp, r_des_start, rx_bd_base_phys);
342 FW(fecp, x_des_start, tx_bd_base_phys);
343
344 fs_init_bds(dev);
345
346 /*
347 * Enable big endian and don't care about SDMA FC.
348 */
349 FW(fecp, fun_code, 0x78000000);
350
351 /*
352 * Set MII speed.
353 */
354 FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
355
356 /*
357 * Clear any outstanding interrupt.
358 */
359 FW(fecp, ievent, 0xffc0);
360 FW(fecp, ivec, (fep->interrupt / 2) << 29);
361
362
363 /*
364 * adjust to speed (only for DUET & RMII)
365 */
366 #ifdef CONFIG_DUET
367 if (fpi->use_rmii) {
368 cptr = in_be32(&immap->im_cpm.cp_cptr);
369 switch (fs_get_fec_index(fpi->fs_no)) {
370 case 0:
371 cptr |= 0x100;
372 if (fep->speed == 10)
373 cptr |= 0x0000010;
374 else if (fep->speed == 100)
375 cptr &= ~0x0000010;
376 break;
377 case 1:
378 cptr |= 0x80;
379 if (fep->speed == 10)
380 cptr |= 0x0000008;
381 else if (fep->speed == 100)
382 cptr &= ~0x0000008;
383 break;
384 default:
385 BUG(); /* should never happen */
386 break;
387 }
388 out_be32(&immap->im_cpm.cp_cptr, cptr);
389 }
390 #endif
391
392 FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
393 /*
394 * adjust to duplex mode
395 */
396 if (fep->duplex) {
397 FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
398 FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
399 } else {
400 FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
401 FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
402 }
403
404 /*
405 * Enable interrupts we wish to service.
406 */
407 FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
408 FEC_ENET_RXF | FEC_ENET_RXB);
409
410 /*
411 * And last, enable the transmit and receive processing.
412 */
413 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
414 FW(fecp, r_des_active, 0x01000000);
415 }
416
417 static void stop(struct net_device *dev)
418 {
419 struct fs_enet_private *fep = netdev_priv(dev);
420 fec_t *fecp = fep->fec.fecp;
421 struct fs_enet_mii_bus *bus = fep->mii_bus;
422 const struct fs_mii_bus_info *bi = bus->bus_info;
423 int i;
424
425 if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
426 return; /* already down */
427
428 FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
429 for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
430 i < FEC_RESET_DELAY; i++)
431 udelay(1);
432
433 if (i == FEC_RESET_DELAY)
434 printk(KERN_WARNING DRV_MODULE_NAME
435 ": %s FEC timeout on graceful transmit stop\n",
436 dev->name);
437 /*
438 * Disable FEC. Let only MII interrupts.
439 */
440 FW(fecp, imask, 0);
441 FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
442
443 fs_cleanup_bds(dev);
444
445 /* shut down FEC1? that's where the mii bus is */
446 if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
447 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
448 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
449 FW(fecp, ievent, FEC_ENET_MII);
450 FW(fecp, mii_speed, bus->fec.mii_speed);
451 }
452 }
453
454 static void pre_request_irq(struct net_device *dev, int irq)
455 {
456 immap_t *immap = fs_enet_immap;
457 u32 siel;
458
459 /* SIU interrupt */
460 if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
461
462 siel = in_be32(&immap->im_siu_conf.sc_siel);
463 if ((irq & 1) == 0)
464 siel |= (0x80000000 >> irq);
465 else
466 siel &= ~(0x80000000 >> (irq & ~1));
467 out_be32(&immap->im_siu_conf.sc_siel, siel);
468 }
469 }
470
471 static void post_free_irq(struct net_device *dev, int irq)
472 {
473 /* nothing */
474 }
475
476 static void napi_clear_rx_event(struct net_device *dev)
477 {
478 struct fs_enet_private *fep = netdev_priv(dev);
479 fec_t *fecp = fep->fec.fecp;
480
481 FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
482 }
483
484 static void napi_enable_rx(struct net_device *dev)
485 {
486 struct fs_enet_private *fep = netdev_priv(dev);
487 fec_t *fecp = fep->fec.fecp;
488
489 FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
490 }
491
492 static void napi_disable_rx(struct net_device *dev)
493 {
494 struct fs_enet_private *fep = netdev_priv(dev);
495 fec_t *fecp = fep->fec.fecp;
496
497 FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
498 }
499
500 static void rx_bd_done(struct net_device *dev)
501 {
502 struct fs_enet_private *fep = netdev_priv(dev);
503 fec_t *fecp = fep->fec.fecp;
504
505 FW(fecp, r_des_active, 0x01000000);
506 }
507
508 static void tx_kickstart(struct net_device *dev)
509 {
510 struct fs_enet_private *fep = netdev_priv(dev);
511 fec_t *fecp = fep->fec.fecp;
512
513 FW(fecp, x_des_active, 0x01000000);
514 }
515
516 static u32 get_int_events(struct net_device *dev)
517 {
518 struct fs_enet_private *fep = netdev_priv(dev);
519 fec_t *fecp = fep->fec.fecp;
520
521 return FR(fecp, ievent) & FR(fecp, imask);
522 }
523
524 static void clear_int_events(struct net_device *dev, u32 int_events)
525 {
526 struct fs_enet_private *fep = netdev_priv(dev);
527 fec_t *fecp = fep->fec.fecp;
528
529 FW(fecp, ievent, int_events);
530 }
531
532 static void ev_error(struct net_device *dev, u32 int_events)
533 {
534 printk(KERN_WARNING DRV_MODULE_NAME
535 ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
536 }
537
538 int get_regs(struct net_device *dev, void *p, int *sizep)
539 {
540 struct fs_enet_private *fep = netdev_priv(dev);
541
542 if (*sizep < sizeof(fec_t))
543 return -EINVAL;
544
545 memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
546
547 return 0;
548 }
549
550 int get_regs_len(struct net_device *dev)
551 {
552 return sizeof(fec_t);
553 }
554
555 void tx_restart(struct net_device *dev)
556 {
557 /* nothing */
558 }
559
560 /*************************************************************************/
561
562 const struct fs_ops fs_fec_ops = {
563 .setup_data = setup_data,
564 .cleanup_data = cleanup_data,
565 .set_multicast_list = set_multicast_list,
566 .restart = restart,
567 .stop = stop,
568 .pre_request_irq = pre_request_irq,
569 .post_free_irq = post_free_irq,
570 .napi_clear_rx_event = napi_clear_rx_event,
571 .napi_enable_rx = napi_enable_rx,
572 .napi_disable_rx = napi_disable_rx,
573 .rx_bd_done = rx_bd_done,
574 .tx_kickstart = tx_kickstart,
575 .get_int_events = get_int_events,
576 .clear_int_events = clear_int_events,
577 .ev_error = ev_error,
578 .get_regs = get_regs,
579 .get_regs_len = get_regs_len,
580 .tx_restart = tx_restart,
581 .allocate_bd = allocate_bd,
582 .free_bd = free_bd,
583 };
584
585 /***********************************************************************/
586
587 static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
588 {
589 fec_t *fecp = bus->fec.fecp;
590 int i, ret = -1;
591
592 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
593 BUG();
594
595 /* Add PHY address to register command. */
596 FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
597
598 for (i = 0; i < FEC_MII_LOOPS; i++)
599 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
600 break;
601
602 if (i < FEC_MII_LOOPS) {
603 FW(fecp, ievent, FEC_ENET_MII);
604 ret = FR(fecp, mii_data) & 0xffff;
605 }
606
607 return ret;
608 }
609
610 static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
611 {
612 fec_t *fecp = bus->fec.fecp;
613 int i;
614
615 /* this must never happen */
616 if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
617 BUG();
618
619 /* Add PHY address to register command. */
620 FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
621
622 for (i = 0; i < FEC_MII_LOOPS; i++)
623 if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
624 break;
625
626 if (i < FEC_MII_LOOPS)
627 FW(fecp, ievent, FEC_ENET_MII);
628 }
629
630 int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
631 {
632 bd_t *bd = (bd_t *)__res;
633 const struct fs_mii_bus_info *bi = bus->bus_info;
634 fec_t *fecp;
635
636 if (bi->id != 0)
637 return -1;
638
639 bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
640 bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
641 & 0x3F) << 1;
642
643 fecp = bus->fec.fecp;
644
645 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
646 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
647 FW(fecp, ievent, FEC_ENET_MII);
648 FW(fecp, mii_speed, bus->fec.mii_speed);
649
650 bus->mii_read = mii_read;
651 bus->mii_write = mii_write;
652
653 return 0;
654 }
Verdex Pro support