drivers/net/gianfar.h

   1 /*
   2  * drivers/net/gianfar.h
   3  *
   4  * Gianfar Ethernet Driver
   5  * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  *
  11  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  *  Still left to do:
  19  *      -Add support for module parameters
  20  *      -Add patch for ethtool phys id
  21  */
  22 #ifndef __GIANFAR_H
  23 #define __GIANFAR_H
  24
  25 #include <linux/config.h>
  26 #include <linux/kernel.h>
  27 #include <linux/sched.h>
  28 #include <linux/string.h>
  29 #include <linux/errno.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/mm.h>
  39 #include <linux/mii.h>
  40 #include <linux/phy.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44 #include <asm/uaccess.h>
  45 #include <linux/module.h>
  46 #include <linux/crc32.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/ethtool.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/fsl_devices.h>
  51 #include "gianfar_mii.h"
  52
  53 /* The maximum number of packets to be handled in one call of gfar_poll */
  54 #define GFAR_DEV_WEIGHT 64
  55
  56 /* Length for FCB */
  57 #define GMAC_FCB_LEN 8
  58
  59 /* Default padding amount */
  60 #define DEFAULT_PADDING 2
  61
  62 /* Number of bytes to align the rx bufs to */
  63 #define RXBUF_ALIGNMENT 64
  64
  65 /* The number of bytes which composes a unit for the purpose of
  66  * allocating data buffers.  ie-for any given MTU, the data buffer
  67  * will be the next highest multiple of 512 bytes. */
  68 #define INCREMENTAL_BUFFER_SIZE 512
  69
  70
  71 #define MAC_ADDR_LEN 6
  72
  73 #define PHY_INIT_TIMEOUT 100000
  74 #define GFAR_PHY_CHANGE_TIME 2
  75
  76 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
  77 #define DRV_NAME "gfar-enet"
  78 extern const char gfar_driver_name[];
  79 extern const char gfar_driver_version[];
  80
  81 /* These need to be powers of 2 for this driver */
  82 #ifdef CONFIG_GFAR_NAPI
  83 #define DEFAULT_TX_RING_SIZE    256
  84 #define DEFAULT_RX_RING_SIZE    256
  85 #else
  86 #define DEFAULT_TX_RING_SIZE    64
  87 #define DEFAULT_RX_RING_SIZE    64
  88 #endif
  89
  90 #define GFAR_RX_MAX_RING_SIZE   256
  91 #define GFAR_TX_MAX_RING_SIZE   256
  92
  93 #define GFAR_MAX_FIFO_THRESHOLD 511
  94 #define GFAR_MAX_FIFO_STARVE    511
  95 #define GFAR_MAX_FIFO_STARVE_OFF 511
  96
  97 #define DEFAULT_RX_BUFFER_SIZE  1536
  98 #define TX_RING_MOD_MASK(size) (size-1)
  99 #define RX_RING_MOD_MASK(size) (size-1)
 100 #define JUMBO_BUFFER_SIZE 9728
 101 #define JUMBO_FRAME_SIZE 9600
 102
 103 #define DEFAULT_FIFO_TX_THR 0x100
 104 #define DEFAULT_FIFO_TX_STARVE 0x40
 105 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
 106 #define DEFAULT_BD_STASH 1
 107 #define DEFAULT_STASH_LENGTH    64
 108 #define DEFAULT_STASH_INDEX     0
 109
 110 /* The number of Exact Match registers */
 111 #define GFAR_EM_NUM     15
 112
 113 /* Latency of interface clock in nanoseconds */
 114 /* Interface clock latency , in this case, means the
 115  * time described by a value of 1 in the interrupt
 116  * coalescing registers' time fields.  Since those fields
 117  * refer to the time it takes for 64 clocks to pass, the
 118  * latencies are as such:
 119  * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 120  * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 121  * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 122  */
 123 #define GFAR_GBIT_TIME  512
 124 #define GFAR_100_TIME   2560
 125 #define GFAR_10_TIME    25600
 126
 127 #define DEFAULT_TX_COALESCE 1
 128 #define DEFAULT_TXCOUNT 16
 129 #define DEFAULT_TXTIME  4
 130
 131 #define DEFAULT_RX_COALESCE 1
 132 #define DEFAULT_RXCOUNT 16
 133 #define DEFAULT_RXTIME  4
 134
 135 #define TBIPA_VALUE             0x1f
 136 #define MIIMCFG_INIT_VALUE      0x00000007
 137 #define MIIMCFG_RESET           0x80000000
 138 #define MIIMIND_BUSY            0x00000001
 139
 140 /* MAC register bits */
 141 #define MACCFG1_SOFT_RESET      0x80000000
 142 #define MACCFG1_RESET_RX_MC     0x00080000
 143 #define MACCFG1_RESET_TX_MC     0x00040000
 144 #define MACCFG1_RESET_RX_FUN    0x00020000
 145 #define MACCFG1_RESET_TX_FUN    0x00010000
 146 #define MACCFG1_LOOPBACK        0x00000100
 147 #define MACCFG1_RX_FLOW         0x00000020
 148 #define MACCFG1_TX_FLOW         0x00000010
 149 #define MACCFG1_SYNCD_RX_EN     0x00000008
 150 #define MACCFG1_RX_EN           0x00000004
 151 #define MACCFG1_SYNCD_TX_EN     0x00000002
 152 #define MACCFG1_TX_EN           0x00000001
 153
 154 #define MACCFG2_INIT_SETTINGS   0x00007205
 155 #define MACCFG2_FULL_DUPLEX     0x00000001
 156 #define MACCFG2_IF              0x00000300
 157 #define MACCFG2_MII             0x00000100
 158 #define MACCFG2_GMII            0x00000200
 159 #define MACCFG2_HUGEFRAME       0x00000020
 160 #define MACCFG2_LENGTHCHECK     0x00000010
 161
 162 #define ECNTRL_INIT_SETTINGS    0x00001000
 163 #define ECNTRL_TBI_MODE         0x00000020
 164 #define ECNTRL_R100             0x00000008
 165
 166 #define MRBLR_INIT_SETTINGS     DEFAULT_RX_BUFFER_SIZE
 167
 168 #define MINFLR_INIT_SETTINGS    0x00000040
 169
 170 /* Init to do tx snooping for buffers and descriptors */
 171 #define DMACTRL_INIT_SETTINGS   0x000000c3
 172 #define DMACTRL_GRS             0x00000010
 173 #define DMACTRL_GTS             0x00000008
 174
 175 #define TSTAT_CLEAR_THALT       0x80000000
 176
 177 /* Interrupt coalescing macros */
 178 #define IC_ICEN                 0x80000000
 179 #define IC_ICFT_MASK            0x1fe00000
 180 #define IC_ICFT_SHIFT           21
 181 #define mk_ic_icft(x)           \
 182         (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
 183 #define IC_ICTT_MASK            0x0000ffff
 184 #define mk_ic_ictt(x)           (x&IC_ICTT_MASK)
 185
 186 #define mk_ic_value(count, time) (IC_ICEN | \
 187                                 mk_ic_icft(count) | \
 188                                 mk_ic_ictt(time))
 189
 190 #define RCTRL_PAL_MASK          0x001f0000
 191 #define RCTRL_VLEX              0x00002000
 192 #define RCTRL_FILREN            0x00001000
 193 #define RCTRL_GHTX              0x00000400
 194 #define RCTRL_IPCSEN            0x00000200
 195 #define RCTRL_TUCSEN            0x00000100
 196 #define RCTRL_PRSDEP_MASK       0x000000c0
 197 #define RCTRL_PRSDEP_INIT       0x000000c0
 198 #define RCTRL_PROM              0x00000008
 199 #define RCTRL_EMEN              0x00000002
 200 #define RCTRL_CHECKSUMMING      (RCTRL_IPCSEN \
 201                 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
 202 #define RCTRL_EXTHASH           (RCTRL_GHTX)
 203 #define RCTRL_VLAN              (RCTRL_PRSDEP_INIT)
 204 #define RCTRL_PADDING(x)        ((x << 16) & RCTRL_PAL_MASK)
 205
 206
 207 #define RSTAT_CLEAR_RHALT       0x00800000
 208
 209 #define TCTRL_IPCSEN            0x00004000
 210 #define TCTRL_TUCSEN            0x00002000
 211 #define TCTRL_VLINS             0x00001000
 212 #define TCTRL_INIT_CSUM         (TCTRL_TUCSEN | TCTRL_IPCSEN)
 213
 214 #define IEVENT_INIT_CLEAR       0xffffffff
 215 #define IEVENT_BABR             0x80000000
 216 #define IEVENT_RXC              0x40000000
 217 #define IEVENT_BSY              0x20000000
 218 #define IEVENT_EBERR            0x10000000
 219 #define IEVENT_MSRO             0x04000000
 220 #define IEVENT_GTSC             0x02000000
 221 #define IEVENT_BABT             0x01000000
 222 #define IEVENT_TXC              0x00800000
 223 #define IEVENT_TXE              0x00400000
 224 #define IEVENT_TXB              0x00200000
 225 #define IEVENT_TXF              0x00100000
 226 #define IEVENT_LC               0x00040000
 227 #define IEVENT_CRL              0x00020000
 228 #define IEVENT_XFUN             0x00010000
 229 #define IEVENT_RXB0             0x00008000
 230 #define IEVENT_GRSC             0x00000100
 231 #define IEVENT_RXF0             0x00000080
 232 #define IEVENT_FIR              0x00000008
 233 #define IEVENT_FIQ              0x00000004
 234 #define IEVENT_DPE              0x00000002
 235 #define IEVENT_PERR             0x00000001
 236 #define IEVENT_RX_MASK          (IEVENT_RXB0 | IEVENT_RXF0)
 237 #define IEVENT_TX_MASK          (IEVENT_TXB | IEVENT_TXF)
 238 #define IEVENT_ERR_MASK         \
 239 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
 240  IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
 241  | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
 242
 243 #define IMASK_INIT_CLEAR        0x00000000
 244 #define IMASK_BABR              0x80000000
 245 #define IMASK_RXC               0x40000000
 246 #define IMASK_BSY               0x20000000
 247 #define IMASK_EBERR             0x10000000
 248 #define IMASK_MSRO              0x04000000
 249 #define IMASK_GRSC              0x02000000
 250 #define IMASK_BABT              0x01000000
 251 #define IMASK_TXC               0x00800000
 252 #define IMASK_TXEEN             0x00400000
 253 #define IMASK_TXBEN             0x00200000
 254 #define IMASK_TXFEN             0x00100000
 255 #define IMASK_LC                0x00040000
 256 #define IMASK_CRL               0x00020000
 257 #define IMASK_XFUN              0x00010000
 258 #define IMASK_RXB0              0x00008000
 259 #define IMASK_GTSC              0x00000100
 260 #define IMASK_RXFEN0            0x00000080
 261 #define IMASK_FIR               0x00000008
 262 #define IMASK_FIQ               0x00000004
 263 #define IMASK_DPE               0x00000002
 264 #define IMASK_PERR              0x00000001
 265 #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
 266 #define IMASK_DEFAULT  (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
 267                 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
 268                 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
 269                 | IMASK_PERR)
 270
 271 /* Fifo management */
 272 #define FIFO_TX_THR_MASK        0x01ff
 273 #define FIFO_TX_STARVE_MASK     0x01ff
 274 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
 275
 276 /* Attribute fields */
 277
 278 /* This enables rx snooping for buffers and descriptors */
 279 #define ATTR_BDSTASH            0x00000800
 280
 281 #define ATTR_BUFSTASH           0x00004000
 282
 283 #define ATTR_SNOOPING           0x000000c0
 284 #define ATTR_INIT_SETTINGS      ATTR_SNOOPING
 285
 286 #define ATTRELI_INIT_SETTINGS   0x0
 287 #define ATTRELI_EL_MASK         0x3fff0000
 288 #define ATTRELI_EL(x) (x << 16)
 289 #define ATTRELI_EI_MASK         0x00003fff
 290 #define ATTRELI_EI(x) (x)
 291
 292
 293 /* TxBD status field bits */
 294 #define TXBD_READY              0x8000
 295 #define TXBD_PADCRC             0x4000
 296 #define TXBD_WRAP               0x2000
 297 #define TXBD_INTERRUPT          0x1000
 298 #define TXBD_LAST               0x0800
 299 #define TXBD_CRC                0x0400
 300 #define TXBD_DEF                0x0200
 301 #define TXBD_HUGEFRAME          0x0080
 302 #define TXBD_LATECOLLISION      0x0080
 303 #define TXBD_RETRYLIMIT         0x0040
 304 #define TXBD_RETRYCOUNTMASK     0x003c
 305 #define TXBD_UNDERRUN           0x0002
 306 #define TXBD_TOE                0x0002
 307
 308 /* Tx FCB param bits */
 309 #define TXFCB_VLN               0x80
 310 #define TXFCB_IP                0x40
 311 #define TXFCB_IP6               0x20
 312 #define TXFCB_TUP               0x10
 313 #define TXFCB_UDP               0x08
 314 #define TXFCB_CIP               0x04
 315 #define TXFCB_CTU               0x02
 316 #define TXFCB_NPH               0x01
 317 #define TXFCB_DEFAULT           (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
 318
 319 /* RxBD status field bits */
 320 #define RXBD_EMPTY              0x8000
 321 #define RXBD_RO1                0x4000
 322 #define RXBD_WRAP               0x2000
 323 #define RXBD_INTERRUPT          0x1000
 324 #define RXBD_LAST               0x0800
 325 #define RXBD_FIRST              0x0400
 326 #define RXBD_MISS               0x0100
 327 #define RXBD_BROADCAST          0x0080
 328 #define RXBD_MULTICAST          0x0040
 329 #define RXBD_LARGE              0x0020
 330 #define RXBD_NONOCTET           0x0010
 331 #define RXBD_SHORT              0x0008
 332 #define RXBD_CRCERR             0x0004
 333 #define RXBD_OVERRUN            0x0002
 334 #define RXBD_TRUNCATED          0x0001
 335 #define RXBD_STATS              0x01ff
 336
 337 /* Rx FCB status field bits */
 338 #define RXFCB_VLN               0x8000
 339 #define RXFCB_IP                0x4000
 340 #define RXFCB_IP6               0x2000
 341 #define RXFCB_TUP               0x1000
 342 #define RXFCB_CIP               0x0800
 343 #define RXFCB_CTU               0x0400
 344 #define RXFCB_EIP               0x0200
 345 #define RXFCB_ETU               0x0100
 346 #define RXFCB_CSUM_MASK         0x0f00
 347 #define RXFCB_PERR_MASK         0x000c
 348 #define RXFCB_PERR_BADL3        0x0008
 349
 350 struct txbd8
 351 {
 352         u16     status; /* Status Fields */
 353         u16     length; /* Buffer length */
 354         u32     bufPtr; /* Buffer Pointer */
 355 };
 356
 357 struct txfcb {
 358         u8      flags;
 359         u8      reserved;
 360         u8      l4os;   /* Level 4 Header Offset */
 361         u8      l3os;   /* Level 3 Header Offset */
 362         u16     phcs;   /* Pseudo-header Checksum */
 363         u16     vlctl;  /* VLAN control word */
 364 };
 365
 366 struct rxbd8
 367 {
 368         u16     status; /* Status Fields */
 369         u16     length; /* Buffer Length */
 370         u32     bufPtr; /* Buffer Pointer */
 371 };
 372
 373 struct rxfcb {
 374         u16     flags;
 375         u8      rq;     /* Receive Queue index */
 376         u8      pro;    /* Layer 4 Protocol */
 377         u16     reserved;
 378         u16     vlctl;  /* VLAN control word */
 379 };
 380
 381 struct rmon_mib
 382 {
 383         u32     tr64;   /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
 384         u32     tr127;  /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
 385         u32     tr255;  /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
 386         u32     tr511;  /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
 387         u32     tr1k;   /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
 388         u32     trmax;  /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
 389         u32     trmgv;  /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 390         u32     rbyt;   /* 0x.69c - Receive Byte Counter */
 391         u32     rpkt;   /* 0x.6a0 - Receive Packet Counter */
 392         u32     rfcs;   /* 0x.6a4 - Receive FCS Error Counter */
 393         u32     rmca;   /* 0x.6a8 - Receive Multicast Packet Counter */
 394         u32     rbca;   /* 0x.6ac - Receive Broadcast Packet Counter */
 395         u32     rxcf;   /* 0x.6b0 - Receive Control Frame Packet Counter */
 396         u32     rxpf;   /* 0x.6b4 - Receive Pause Frame Packet Counter */
 397         u32     rxuo;   /* 0x.6b8 - Receive Unknown OP Code Counter */
 398         u32     raln;   /* 0x.6bc - Receive Alignment Error Counter */
 399         u32     rflr;   /* 0x.6c0 - Receive Frame Length Error Counter */
 400         u32     rcde;   /* 0x.6c4 - Receive Code Error Counter */
 401         u32     rcse;   /* 0x.6c8 - Receive Carrier Sense Error Counter */
 402         u32     rund;   /* 0x.6cc - Receive Undersize Packet Counter */
 403         u32     rovr;   /* 0x.6d0 - Receive Oversize Packet Counter */
 404         u32     rfrg;   /* 0x.6d4 - Receive Fragments Counter */
 405         u32     rjbr;   /* 0x.6d8 - Receive Jabber Counter */
 406         u32     rdrp;   /* 0x.6dc - Receive Drop Counter */
 407         u32     tbyt;   /* 0x.6e0 - Transmit Byte Counter Counter */
 408         u32     tpkt;   /* 0x.6e4 - Transmit Packet Counter */
 409         u32     tmca;   /* 0x.6e8 - Transmit Multicast Packet Counter */
 410         u32     tbca;   /* 0x.6ec - Transmit Broadcast Packet Counter */
 411         u32     txpf;   /* 0x.6f0 - Transmit Pause Control Frame Counter */
 412         u32     tdfr;   /* 0x.6f4 - Transmit Deferral Packet Counter */
 413         u32     tedf;   /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
 414         u32     tscl;   /* 0x.6fc - Transmit Single Collision Packet Counter */
 415         u32     tmcl;   /* 0x.700 - Transmit Multiple Collision Packet Counter */
 416         u32     tlcl;   /* 0x.704 - Transmit Late Collision Packet Counter */
 417         u32     txcl;   /* 0x.708 - Transmit Excessive Collision Packet Counter */
 418         u32     tncl;   /* 0x.70c - Transmit Total Collision Counter */
 419         u8      res1[4];
 420         u32     tdrp;   /* 0x.714 - Transmit Drop Frame Counter */
 421         u32     tjbr;   /* 0x.718 - Transmit Jabber Frame Counter */
 422         u32     tfcs;   /* 0x.71c - Transmit FCS Error Counter */
 423         u32     txcf;   /* 0x.720 - Transmit Control Frame Counter */
 424         u32     tovr;   /* 0x.724 - Transmit Oversize Frame Counter */
 425         u32     tund;   /* 0x.728 - Transmit Undersize Frame Counter */
 426         u32     tfrg;   /* 0x.72c - Transmit Fragments Frame Counter */
 427         u32     car1;   /* 0x.730 - Carry Register One */
 428         u32     car2;   /* 0x.734 - Carry Register Two */
 429         u32     cam1;   /* 0x.738 - Carry Mask Register One */
 430         u32     cam2;   /* 0x.73c - Carry Mask Register Two */
 431 };
 432
 433 struct gfar_extra_stats {
 434         u64 kernel_dropped;
 435         u64 rx_large;
 436         u64 rx_short;
 437         u64 rx_nonoctet;
 438         u64 rx_crcerr;
 439         u64 rx_overrun;
 440         u64 rx_bsy;
 441         u64 rx_babr;
 442         u64 rx_trunc;
 443         u64 eberr;
 444         u64 tx_babt;
 445         u64 tx_underrun;
 446         u64 rx_skbmissing;
 447         u64 tx_timeout;
 448 };
 449
 450 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
 451 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
 452
 453 /* Number of stats in the stats structure (ignore car and cam regs)*/
 454 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
 455
 456 #define GFAR_INFOSTR_LEN 32
 457
 458 struct gfar_stats {
 459         u64 extra[GFAR_EXTRA_STATS_LEN];
 460         u64 rmon[GFAR_RMON_LEN];
 461 };
 462
 463
 464 struct gfar {
 465         u32     tsec_id;        /* 0x.000 - Controller ID register */
 466         u8      res1[12];
 467         u32     ievent;         /* 0x.010 - Interrupt Event Register */
 468         u32     imask;          /* 0x.014 - Interrupt Mask Register */
 469         u32     edis;           /* 0x.018 - Error Disabled Register */
 470         u8      res2[4];
 471         u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
 472         u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
 473         u32     ptv;            /* 0x.028 - Pause Time Value Register */
 474         u32     dmactrl;        /* 0x.02c - DMA Control Register */
 475         u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
 476         u8      res3[88];
 477         u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
 478         u8      res4[8];
 479         u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
 480         u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
 481         u8      res5[4];
 482         u32     fifo_rx_pause;  /* 0x.0a4 - FIFO receive pause threshold register */
 483         u32     fifo_rx_alarm;  /* 0x.0a8 - FIFO receive alarm threshold register */
 484         u8      res6[84];
 485         u32     tctrl;          /* 0x.100 - Transmit Control Register */
 486         u32     tstat;          /* 0x.104 - Transmit Status Register */
 487         u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
 488         u32     tbdlen;         /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
 489         u32     txic;           /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
 490         u32     tqueue;         /* 0x.114 - Transmit queue control register */
 491         u8      res7[40];
 492         u32     tr03wt;         /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
 493         u32     tr47wt;         /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
 494         u8      res8[52];
 495         u32     tbdbph;         /* 0x.17c - Tx data buffer pointer high */
 496         u8      res9a[4];
 497         u32     tbptr0;         /* 0x.184 - TxBD Pointer for ring 0 */
 498         u8      res9b[4];
 499         u32     tbptr1;         /* 0x.18c - TxBD Pointer for ring 1 */
 500         u8      res9c[4];
 501         u32     tbptr2;         /* 0x.194 - TxBD Pointer for ring 2 */
 502         u8      res9d[4];
 503         u32     tbptr3;         /* 0x.19c - TxBD Pointer for ring 3 */
 504         u8      res9e[4];
 505         u32     tbptr4;         /* 0x.1a4 - TxBD Pointer for ring 4 */
 506         u8      res9f[4];
 507         u32     tbptr5;         /* 0x.1ac - TxBD Pointer for ring 5 */
 508         u8      res9g[4];
 509         u32     tbptr6;         /* 0x.1b4 - TxBD Pointer for ring 6 */
 510         u8      res9h[4];
 511         u32     tbptr7;         /* 0x.1bc - TxBD Pointer for ring 7 */
 512         u8      res9[64];
 513         u32     tbaseh;         /* 0x.200 - TxBD base address high */
 514         u32     tbase0;         /* 0x.204 - TxBD Base Address of ring 0 */
 515         u8      res10a[4];
 516         u32     tbase1;         /* 0x.20c - TxBD Base Address of ring 1 */
 517         u8      res10b[4];
 518         u32     tbase2;         /* 0x.214 - TxBD Base Address of ring 2 */
 519         u8      res10c[4];
 520         u32     tbase3;         /* 0x.21c - TxBD Base Address of ring 3 */
 521         u8      res10d[4];
 522         u32     tbase4;         /* 0x.224 - TxBD Base Address of ring 4 */
 523         u8      res10e[4];
 524         u32     tbase5;         /* 0x.22c - TxBD Base Address of ring 5 */
 525         u8      res10f[4];
 526         u32     tbase6;         /* 0x.234 - TxBD Base Address of ring 6 */
 527         u8      res10g[4];
 528         u32     tbase7;         /* 0x.23c - TxBD Base Address of ring 7 */
 529         u8      res10[192];
 530         u32     rctrl;          /* 0x.300 - Receive Control Register */
 531         u32     rstat;          /* 0x.304 - Receive Status Register */
 532         u8      res12[8];
 533         u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
 534         u32     rqueue;         /* 0x.314 - Receive queue control register */
 535         u8      res13[24];
 536         u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
 537         u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
 538         u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
 539         u32     rqfpr;          /* 0x.33c - Receive queue filing table property register */
 540         u32     mrblr;          /* 0x.340 - Maximum Receive Buffer Length Register */
 541         u8      res14[56];
 542         u32     rbdbph;         /* 0x.37c - Rx data buffer pointer high */
 543         u8      res15a[4];
 544         u32     rbptr0;         /* 0x.384 - RxBD pointer for ring 0 */
 545         u8      res15b[4];
 546         u32     rbptr1;         /* 0x.38c - RxBD pointer for ring 1 */
 547         u8      res15c[4];
 548         u32     rbptr2;         /* 0x.394 - RxBD pointer for ring 2 */
 549         u8      res15d[4];
 550         u32     rbptr3;         /* 0x.39c - RxBD pointer for ring 3 */
 551         u8      res15e[4];
 552         u32     rbptr4;         /* 0x.3a4 - RxBD pointer for ring 4 */
 553         u8      res15f[4];
 554         u32     rbptr5;         /* 0x.3ac - RxBD pointer for ring 5 */
 555         u8      res15g[4];
 556         u32     rbptr6;         /* 0x.3b4 - RxBD pointer for ring 6 */
 557         u8      res15h[4];
 558         u32     rbptr7;         /* 0x.3bc - RxBD pointer for ring 7 */
 559         u8      res16[64];
 560         u32     rbaseh;         /* 0x.400 - RxBD base address high */
 561         u32     rbase0;         /* 0x.404 - RxBD base address of ring 0 */
 562         u8      res17a[4];
 563         u32     rbase1;         /* 0x.40c - RxBD base address of ring 1 */
 564         u8      res17b[4];
 565         u32     rbase2;         /* 0x.414 - RxBD base address of ring 2 */
 566         u8      res17c[4];
 567         u32     rbase3;         /* 0x.41c - RxBD base address of ring 3 */
 568         u8      res17d[4];
 569         u32     rbase4;         /* 0x.424 - RxBD base address of ring 4 */
 570         u8      res17e[4];
 571         u32     rbase5;         /* 0x.42c - RxBD base address of ring 5 */
 572         u8      res17f[4];
 573         u32     rbase6;         /* 0x.434 - RxBD base address of ring 6 */
 574         u8      res17g[4];
 575         u32     rbase7;         /* 0x.43c - RxBD base address of ring 7 */
 576         u8      res17[192];
 577         u32     maccfg1;        /* 0x.500 - MAC Configuration 1 Register */
 578         u32     maccfg2;        /* 0x.504 - MAC Configuration 2 Register */
 579         u32     ipgifg;         /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
 580         u32     hafdup;         /* 0x.50c - Half Duplex Register */
 581         u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
 582         u8      res18[12];
 583         u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
 584         u8      res19[4];
 585         u32     ifstat;         /* 0x.53c - Interface Status Register */
 586         u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
 587         u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
 588         u32     mac01addr1;     /* 0x.548 - MAC exact match address 1, part 1 */
 589         u32     mac01addr2;     /* 0x.54c - MAC exact match address 1, part 2 */
 590         u32     mac02addr1;     /* 0x.550 - MAC exact match address 2, part 1 */
 591         u32     mac02addr2;     /* 0x.554 - MAC exact match address 2, part 2 */
 592         u32     mac03addr1;     /* 0x.558 - MAC exact match address 3, part 1 */
 593         u32     mac03addr2;     /* 0x.55c - MAC exact match address 3, part 2 */
 594         u32     mac04addr1;     /* 0x.560 - MAC exact match address 4, part 1 */
 595         u32     mac04addr2;     /* 0x.564 - MAC exact match address 4, part 2 */
 596         u32     mac05addr1;     /* 0x.568 - MAC exact match address 5, part 1 */
 597         u32     mac05addr2;     /* 0x.56c - MAC exact match address 5, part 2 */
 598         u32     mac06addr1;     /* 0x.570 - MAC exact match address 6, part 1 */
 599         u32     mac06addr2;     /* 0x.574 - MAC exact match address 6, part 2 */
 600         u32     mac07addr1;     /* 0x.578 - MAC exact match address 7, part 1 */
 601         u32     mac07addr2;     /* 0x.57c - MAC exact match address 7, part 2 */
 602         u32     mac08addr1;     /* 0x.580 - MAC exact match address 8, part 1 */
 603         u32     mac08addr2;     /* 0x.584 - MAC exact match address 8, part 2 */
 604         u32     mac09addr1;     /* 0x.588 - MAC exact match address 9, part 1 */
 605         u32     mac09addr2;     /* 0x.58c - MAC exact match address 9, part 2 */
 606         u32     mac10addr1;     /* 0x.590 - MAC exact match address 10, part 1*/
 607         u32     mac10addr2;     /* 0x.594 - MAC exact match address 10, part 2*/
 608         u32     mac11addr1;     /* 0x.598 - MAC exact match address 11, part 1*/
 609         u32     mac11addr2;     /* 0x.59c - MAC exact match address 11, part 2*/
 610         u32     mac12addr1;     /* 0x.5a0 - MAC exact match address 12, part 1*/
 611         u32     mac12addr2;     /* 0x.5a4 - MAC exact match address 12, part 2*/
 612         u32     mac13addr1;     /* 0x.5a8 - MAC exact match address 13, part 1*/
 613         u32     mac13addr2;     /* 0x.5ac - MAC exact match address 13, part 2*/
 614         u32     mac14addr1;     /* 0x.5b0 - MAC exact match address 14, part 1*/
 615         u32     mac14addr2;     /* 0x.5b4 - MAC exact match address 14, part 2*/
 616         u32     mac15addr1;     /* 0x.5b8 - MAC exact match address 15, part 1*/
 617         u32     mac15addr2;     /* 0x.5bc - MAC exact match address 15, part 2*/
 618         u8      res20[192];
 619         struct rmon_mib rmon;   /* 0x.680-0x.73c */
 620         u32     rrej;           /* 0x.740 - Receive filer rejected packet counter */
 621         u8      res21[188];
 622         u32     igaddr0;        /* 0x.800 - Indivdual/Group address register 0*/
 623         u32     igaddr1;        /* 0x.804 - Indivdual/Group address register 1*/
 624         u32     igaddr2;        /* 0x.808 - Indivdual/Group address register 2*/
 625         u32     igaddr3;        /* 0x.80c - Indivdual/Group address register 3*/
 626         u32     igaddr4;        /* 0x.810 - Indivdual/Group address register 4*/
 627         u32     igaddr5;        /* 0x.814 - Indivdual/Group address register 5*/
 628         u32     igaddr6;        /* 0x.818 - Indivdual/Group address register 6*/
 629         u32     igaddr7;        /* 0x.81c - Indivdual/Group address register 7*/
 630         u8      res22[96];
 631         u32     gaddr0;         /* 0x.880 - Group address register 0 */
 632         u32     gaddr1;         /* 0x.884 - Group address register 1 */
 633         u32     gaddr2;         /* 0x.888 - Group address register 2 */
 634         u32     gaddr3;         /* 0x.88c - Group address register 3 */
 635         u32     gaddr4;         /* 0x.890 - Group address register 4 */
 636         u32     gaddr5;         /* 0x.894 - Group address register 5 */
 637         u32     gaddr6;         /* 0x.898 - Group address register 6 */
 638         u32     gaddr7;         /* 0x.89c - Group address register 7 */
 639         u8      res23a[352];
 640         u32     fifocfg;        /* 0x.a00 - FIFO interface config register */
 641         u8      res23b[252];
 642         u8      res23c[248];
 643         u32     attr;           /* 0x.bf8 - Attributes Register */
 644         u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
 645         u8      res24[1024];
 646
 647 };
 648
 649 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
 650  * (Ok, that's not so true anymore, but there is a family resemblence)
 651  * The GFAR buffer descriptors track the ring buffers.  The rx_bd_base
 652  * and tx_bd_base always point to the currently available buffer.
 653  * The dirty_tx tracks the current buffer that is being sent by the
 654  * controller.  The cur_tx and dirty_tx are equal under both completely
 655  * empty and completely full conditions.  The empty/ready indicator in
 656  * the buffer descriptor determines the actual condition.
 657  */
 658 struct gfar_private {
 659         /* pointers to arrays of skbuffs for tx and rx */
 660         struct sk_buff ** tx_skbuff;
 661         struct sk_buff ** rx_skbuff;
 662
 663         /* indices pointing to the next free sbk in skb arrays */
 664         u16 skb_curtx;
 665         u16 skb_currx;
 666
 667         /* index of the first skb which hasn't been transmitted
 668          * yet. */
 669         u16 skb_dirtytx;
 670
 671         /* Configuration info for the coalescing features */
 672         unsigned char txcoalescing;
 673         unsigned short txcount;
 674         unsigned short txtime;
 675         unsigned char rxcoalescing;
 676         unsigned short rxcount;
 677         unsigned short rxtime;
 678
 679         /* GFAR addresses */
 680         struct rxbd8 *rx_bd_base;       /* Base addresses of Rx and Tx Buffers */
 681         struct txbd8 *tx_bd_base;
 682         struct rxbd8 *cur_rx;           /* Next free rx ring entry */
 683         struct txbd8 *cur_tx;           /* Next free ring entry */
 684         struct txbd8 *dirty_tx;         /* The Ring entry to be freed. */
 685         struct gfar *regs;      /* Pointer to the GFAR memory mapped Registers */
 686         u32 *hash_regs[16];
 687         int hash_width;
 688         struct net_device_stats stats; /* linux network statistics */
 689         struct gfar_extra_stats extra_stats;
 690         spinlock_t lock;
 691         unsigned int rx_buffer_size;
 692         unsigned int rx_stash_size;
 693         unsigned int rx_stash_index;
 694         unsigned int tx_ring_size;
 695         unsigned int rx_ring_size;
 696         unsigned int fifo_threshold;
 697         unsigned int fifo_starve;
 698         unsigned int fifo_starve_off;
 699
 700         unsigned char vlan_enable:1,
 701                 rx_csum_enable:1,
 702                 extended_hash:1,
 703                 bd_stash_en:1;
 704         unsigned short padding;
 705         struct vlan_group *vlgrp;
 706         /* Info structure initialized by board setup code */
 707         unsigned int interruptTransmit;
 708         unsigned int interruptReceive;
 709         unsigned int interruptError;
 710         struct gianfar_platform_data *einfo;
 711
 712         struct phy_device *phydev;
 713         struct mii_bus *mii_bus;
 714         int oldspeed;
 715         int oldduplex;
 716         int oldlink;
 717
 718         uint32_t msg_enable;
 719 };
 720
 721 static inline u32 gfar_read(volatile unsigned *addr)
 722 {
 723         u32 val;
 724         val = in_be32(addr);
 725         return val;
 726 }
 727
 728 static inline void gfar_write(volatile unsigned *addr, u32 val)
 729 {
 730         out_be32(addr, val);
 731 }
 732
 733 extern struct ethtool_ops *gfar_op_array[];
 734
 735 extern irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
 736 extern int startup_gfar(struct net_device *dev);
 737 extern void stop_gfar(struct net_device *dev);
 738 extern void gfar_halt(struct net_device *dev);
 739 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
 740                 int enable, u32 regnum, u32 read);
 741 void gfar_init_sysfs(struct net_device *dev);
 742
 743 #endif /* __GIANFAR_H */