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[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / drivers / net / skge.c
blobb538e3038058a7afe022a83fbadf9876dac0ffbb
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.3"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 { 0 }
87 };
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_phy_reset(struct skge_port *skge);
93 static void skge_tx_clean(struct skge_port *skge);
94 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static void genesis_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_init(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
101
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401 int err;
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
415 }
416
417 return 0;
418 }
419
420 static u32 skge_get_msglevel(struct net_device *netdev)
421 {
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424 }
425
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 {
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430 }
431
432 static int skge_nway_reset(struct net_device *dev)
433 {
434 struct skge_port *skge = netdev_priv(dev);
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 skge_phy_reset(skge);
440 return 0;
441 }
442
443 static int skge_set_sg(struct net_device *dev, u32 data)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451 }
452
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 {
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462 }
463
464 static u32 skge_get_rx_csum(struct net_device *dev)
465 {
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469 }
470
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481 }
482
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494 }
495
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498 {
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
511 if (netif_running(dev))
512 skge_phy_reset(skge);
513 return 0;
514 }
515
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
518 {
519 if (hw->chip_id == CHIP_ID_GENESIS)
520 return 53215; /* or: 53.125 MHz */
521 else
522 return 78215; /* or: 78.125 MHz */
523 }
524
525 /* Chip HZ to microseconds */
526 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 {
528 return (ticks * 1000) / hwkhz(hw);
529 }
530
531 /* Microseconds to chip HZ */
532 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 {
534 return hwkhz(hw) * usec / 1000;
535 }
536
537 static int skge_get_coalesce(struct net_device *dev,
538 struct ethtool_coalesce *ecmd)
539 {
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542 int port = skge->port;
543
544 ecmd->rx_coalesce_usecs = 0;
545 ecmd->tx_coalesce_usecs = 0;
546
547 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
548 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
549 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550
551 if (msk & rxirqmask[port])
552 ecmd->rx_coalesce_usecs = delay;
553 if (msk & txirqmask[port])
554 ecmd->tx_coalesce_usecs = delay;
555 }
556
557 return 0;
558 }
559
560 /* Note: interrupt timer is per board, but can turn on/off per port */
561 static int skge_set_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563 {
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567 u32 msk = skge_read32(hw, B2_IRQM_MSK);
568 u32 delay = 25;
569
570 if (ecmd->rx_coalesce_usecs == 0)
571 msk &= ~rxirqmask[port];
572 else if (ecmd->rx_coalesce_usecs < 25 ||
573 ecmd->rx_coalesce_usecs > 33333)
574 return -EINVAL;
575 else {
576 msk |= rxirqmask[port];
577 delay = ecmd->rx_coalesce_usecs;
578 }
579
580 if (ecmd->tx_coalesce_usecs == 0)
581 msk &= ~txirqmask[port];
582 else if (ecmd->tx_coalesce_usecs < 25 ||
583 ecmd->tx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= txirqmask[port];
587 delay = min(delay, ecmd->rx_coalesce_usecs);
588 }
589
590 skge_write32(hw, B2_IRQM_MSK, msk);
591 if (msk == 0)
592 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 else {
594 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
595 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
596 }
597 return 0;
598 }
599
600 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
601 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 {
603 struct skge_hw *hw = skge->hw;
604 int port = skge->port;
605
606 spin_lock_bh(&hw->phy_lock);
607 if (hw->chip_id == CHIP_ID_GENESIS) {
608 switch (mode) {
609 case LED_MODE_OFF:
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
612 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 break;
615
616 case LED_MODE_ON:
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619
620 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
621 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
622
623 break;
624
625 case LED_MODE_TST:
626 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
627 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
628 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 break;
632 }
633 } else {
634 switch (mode) {
635 case LED_MODE_OFF:
636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
638 PHY_M_LED_MO_DUP(MO_LED_OFF) |
639 PHY_M_LED_MO_10(MO_LED_OFF) |
640 PHY_M_LED_MO_100(MO_LED_OFF) |
641 PHY_M_LED_MO_1000(MO_LED_OFF) |
642 PHY_M_LED_MO_RX(MO_LED_OFF));
643 break;
644 case LED_MODE_ON:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
646 PHY_M_LED_PULS_DUR(PULS_170MS) |
647 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 PHY_M_LEDC_TX_CTRL |
649 PHY_M_LEDC_DP_CTRL);
650
651 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
652 PHY_M_LED_MO_RX(MO_LED_OFF) |
653 (skge->speed == SPEED_100 ?
654 PHY_M_LED_MO_100(MO_LED_ON) : 0));
655 break;
656 case LED_MODE_TST:
657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
665 }
666 spin_unlock_bh(&hw->phy_lock);
667 }
668
669 /* blink LED's for finding board */
670 static int skge_phys_id(struct net_device *dev, u32 data)
671 {
672 struct skge_port *skge = netdev_priv(dev);
673 unsigned long ms;
674 enum led_mode mode = LED_MODE_TST;
675
676 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
677 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
678 else
679 ms = data * 1000;
680
681 while (ms > 0) {
682 skge_led(skge, mode);
683 mode ^= LED_MODE_TST;
684
685 if (msleep_interruptible(BLINK_MS))
686 break;
687 ms -= BLINK_MS;
688 }
689
690 /* back to regular LED state */
691 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
692
693 return 0;
694 }
695
696 static struct ethtool_ops skge_ethtool_ops = {
697 .get_settings = skge_get_settings,
698 .set_settings = skge_set_settings,
699 .get_drvinfo = skge_get_drvinfo,
700 .get_regs_len = skge_get_regs_len,
701 .get_regs = skge_get_regs,
702 .get_wol = skge_get_wol,
703 .set_wol = skge_set_wol,
704 .get_msglevel = skge_get_msglevel,
705 .set_msglevel = skge_set_msglevel,
706 .nway_reset = skge_nway_reset,
707 .get_link = ethtool_op_get_link,
708 .get_ringparam = skge_get_ring_param,
709 .set_ringparam = skge_set_ring_param,
710 .get_pauseparam = skge_get_pauseparam,
711 .set_pauseparam = skge_set_pauseparam,
712 .get_coalesce = skge_get_coalesce,
713 .set_coalesce = skge_set_coalesce,
714 .get_sg = ethtool_op_get_sg,
715 .set_sg = skge_set_sg,
716 .get_tx_csum = ethtool_op_get_tx_csum,
717 .set_tx_csum = skge_set_tx_csum,
718 .get_rx_csum = skge_get_rx_csum,
719 .set_rx_csum = skge_set_rx_csum,
720 .get_strings = skge_get_strings,
721 .phys_id = skge_phys_id,
722 .get_stats_count = skge_get_stats_count,
723 .get_ethtool_stats = skge_get_ethtool_stats,
724 .get_perm_addr = ethtool_op_get_perm_addr,
725 };
726
727 /*
728 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements
730 */
731 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
732 {
733 struct skge_tx_desc *d;
734 struct skge_element *e;
735 int i;
736
737 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
738 if (!ring->start)
739 return -ENOMEM;
740
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d;
743 e->skb = NULL;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755 }
756
757 /* Allocate and setup a new buffer for receiving */
758 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760 {
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
780 }
781
782 /* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
786 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 {
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796 }
797
798
799 /* Free all buffers in receive ring, assumes receiver stopped */
800 static void skge_rx_clean(struct skge_port *skge)
801 {
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
806 e = ring->start;
807 do {
808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
819 }
820
821
822 /* Allocate buffers for receive ring
823 * For receive: to_clean is next received frame.
824 */
825 static int skge_rx_fill(struct skge_port *skge)
826 {
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
829
830 e = ring->start;
831 do {
832 struct sk_buff *skb;
833
834 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
835 if (!skb)
836 return -ENOMEM;
837
838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
840 } while ( (e = e->next) != ring->start);
841
842 ring->to_clean = ring->start;
843 return 0;
844 }
845
846 static void skge_link_up(struct skge_port *skge)
847 {
848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
851 netif_carrier_on(skge->netdev);
852 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
853 netif_wake_queue(skge->netdev);
854
855 if (netif_msg_link(skge))
856 printk(KERN_INFO PFX
857 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
858 skge->netdev->name, skge->speed,
859 skge->duplex == DUPLEX_FULL ? "full" : "half",
860 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
861 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
862 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
863 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
864 "unknown");
865 }
866
867 static void skge_link_down(struct skge_port *skge)
868 {
869 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
870 netif_carrier_off(skge->netdev);
871 netif_stop_queue(skge->netdev);
872
873 if (netif_msg_link(skge))
874 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
875 }
876
877 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
878 {
879 int i;
880
881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
882 xm_read16(hw, port, XM_PHY_DATA);
883
884 /* Need to wait for external PHY */
885 for (i = 0; i < PHY_RETRIES; i++) {
886 udelay(1);
887 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
888 goto ready;
889 }
890
891 return -ETIMEDOUT;
892 ready:
893 *val = xm_read16(hw, port, XM_PHY_DATA);
894
895 return 0;
896 }
897
898 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
899 {
900 u16 v = 0;
901 if (__xm_phy_read(hw, port, reg, &v))
902 printk(KERN_WARNING PFX "%s: phy read timed out\n",
903 hw->dev[port]->name);
904 return v;
905 }
906
907 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
908 {
909 int i;
910
911 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
912 for (i = 0; i < PHY_RETRIES; i++) {
913 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
914 goto ready;
915 udelay(1);
916 }
917 return -EIO;
918
919 ready:
920 xm_write16(hw, port, XM_PHY_DATA, val);
921 return 0;
922 }
923
924 static void genesis_init(struct skge_hw *hw)
925 {
926 /* set blink source counter */
927 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
928 skge_write8(hw, B2_BSC_CTRL, BSC_START);
929
930 /* configure mac arbiter */
931 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
932
933 /* configure mac arbiter timeout values */
934 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
938
939 skge_write8(hw, B3_MA_RCINI_RX1, 0);
940 skge_write8(hw, B3_MA_RCINI_RX2, 0);
941 skge_write8(hw, B3_MA_RCINI_TX1, 0);
942 skge_write8(hw, B3_MA_RCINI_TX2, 0);
943
944 /* configure packet arbiter timeout */
945 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
946 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
950 }
951
952 static void genesis_reset(struct skge_hw *hw, int port)
953 {
954 const u8 zero[8] = { 0 };
955
956 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
957
958 /* reset the statistics module */
959 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
960 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
961 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
962 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
963 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
964
965 /* disable Broadcom PHY IRQ */
966 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
967
968 xm_outhash(hw, port, XM_HSM, zero);
969 }
970
971
972 /* Convert mode to MII values */
973 static const u16 phy_pause_map[] = {
974 [FLOW_MODE_NONE] = 0,
975 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
976 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
977 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
978 };
979
980
981 /* Check status of Broadcom phy link */
982 static void bcom_check_link(struct skge_hw *hw, int port)
983 {
984 struct net_device *dev = hw->dev[port];
985 struct skge_port *skge = netdev_priv(dev);
986 u16 status;
987
988 /* read twice because of latch */
989 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
990 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
991
992 if ((status & PHY_ST_LSYNC) == 0) {
993 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
994 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
995 xm_write16(hw, port, XM_MMU_CMD, cmd);
996 /* dummy read to ensure writing */
997 (void) xm_read16(hw, port, XM_MMU_CMD);
998
999 if (netif_carrier_ok(dev))
1000 skge_link_down(skge);
1001 } else {
1002 if (skge->autoneg == AUTONEG_ENABLE &&
1003 (status & PHY_ST_AN_OVER)) {
1004 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1005 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1006
1007 if (lpa & PHY_B_AN_RF) {
1008 printk(KERN_NOTICE PFX "%s: remote fault\n",
1009 dev->name);
1010 return;
1011 }
1012
1013 /* Check Duplex mismatch */
1014 switch (aux & PHY_B_AS_AN_RES_MSK) {
1015 case PHY_B_RES_1000FD:
1016 skge->duplex = DUPLEX_FULL;
1017 break;
1018 case PHY_B_RES_1000HD:
1019 skge->duplex = DUPLEX_HALF;
1020 break;
1021 default:
1022 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1023 dev->name);
1024 return;
1025 }
1026
1027
1028 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1029 switch (aux & PHY_B_AS_PAUSE_MSK) {
1030 case PHY_B_AS_PAUSE_MSK:
1031 skge->flow_control = FLOW_MODE_SYMMETRIC;
1032 break;
1033 case PHY_B_AS_PRR:
1034 skge->flow_control = FLOW_MODE_REM_SEND;
1035 break;
1036 case PHY_B_AS_PRT:
1037 skge->flow_control = FLOW_MODE_LOC_SEND;
1038 break;
1039 default:
1040 skge->flow_control = FLOW_MODE_NONE;
1041 }
1042
1043 skge->speed = SPEED_1000;
1044 }
1045
1046 if (!netif_carrier_ok(dev))
1047 genesis_link_up(skge);
1048 }
1049 }
1050
1051 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1052 * Phy on for 100 or 10Mbit operation
1053 */
1054 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1055 {
1056 struct skge_hw *hw = skge->hw;
1057 int port = skge->port;
1058 int i;
1059 u16 id1, r, ext, ctl;
1060
1061 /* magic workaround patterns for Broadcom */
1062 static const struct {
1063 u16 reg;
1064 u16 val;
1065 } A1hack[] = {
1066 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1067 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1068 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1069 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1070 }, C0hack[] = {
1071 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1072 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1073 };
1074
1075 /* read Id from external PHY (all have the same address) */
1076 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1077
1078 /* Optimize MDIO transfer by suppressing preamble. */
1079 r = xm_read16(hw, port, XM_MMU_CMD);
1080 r |= XM_MMU_NO_PRE;
1081 xm_write16(hw, port, XM_MMU_CMD,r);
1082
1083 switch (id1) {
1084 case PHY_BCOM_ID1_C0:
1085 /*
1086 * Workaround BCOM Errata for the C0 type.
1087 * Write magic patterns to reserved registers.
1088 */
1089 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1090 xm_phy_write(hw, port,
1091 C0hack[i].reg, C0hack[i].val);
1092
1093 break;
1094 case PHY_BCOM_ID1_A1:
1095 /*
1096 * Workaround BCOM Errata for the A1 type.
1097 * Write magic patterns to reserved registers.
1098 */
1099 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1100 xm_phy_write(hw, port,
1101 A1hack[i].reg, A1hack[i].val);
1102 break;
1103 }
1104
1105 /*
1106 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1107 * Disable Power Management after reset.
1108 */
1109 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1110 r |= PHY_B_AC_DIS_PM;
1111 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1112
1113 /* Dummy read */
1114 xm_read16(hw, port, XM_ISRC);
1115
1116 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1117 ctl = PHY_CT_SP1000; /* always 1000mbit */
1118
1119 if (skge->autoneg == AUTONEG_ENABLE) {
1120 /*
1121 * Workaround BCOM Errata #1 for the C5 type.
1122 * 1000Base-T Link Acquisition Failure in Slave Mode
1123 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1124 */
1125 u16 adv = PHY_B_1000C_RD;
1126 if (skge->advertising & ADVERTISED_1000baseT_Half)
1127 adv |= PHY_B_1000C_AHD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Full)
1129 adv |= PHY_B_1000C_AFD;
1130 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1131
1132 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1133 } else {
1134 if (skge->duplex == DUPLEX_FULL)
1135 ctl |= PHY_CT_DUP_MD;
1136 /* Force to slave */
1137 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1138 }
1139
1140 /* Set autonegotiation pause parameters */
1141 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1142 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1143
1144 /* Handle Jumbo frames */
1145 if (jumbo) {
1146 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1147 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1148
1149 ext |= PHY_B_PEC_HIGH_LA;
1150
1151 }
1152
1153 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1154 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1155
1156 /* Use link status change interrupt */
1157 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1158
1159 bcom_check_link(hw, port);
1160 }
1161
1162 static void genesis_mac_init(struct skge_hw *hw, int port)
1163 {
1164 struct net_device *dev = hw->dev[port];
1165 struct skge_port *skge = netdev_priv(dev);
1166 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1167 int i;
1168 u32 r;
1169 const u8 zero[6] = { 0 };
1170
1171 /* Clear MIB counters */
1172 xm_write16(hw, port, XM_STAT_CMD,
1173 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1174 /* Clear two times according to Errata #3 */
1175 xm_write16(hw, port, XM_STAT_CMD,
1176 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1177
1178 /* Unreset the XMAC. */
1179 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1180
1181 /*
1182 * Perform additional initialization for external PHYs,
1183 * namely for the 1000baseTX cards that use the XMAC's
1184 * GMII mode.
1185 */
1186 /* Take external Phy out of reset */
1187 r = skge_read32(hw, B2_GP_IO);
1188 if (port == 0)
1189 r |= GP_DIR_0|GP_IO_0;
1190 else
1191 r |= GP_DIR_2|GP_IO_2;
1192
1193 skge_write32(hw, B2_GP_IO, r);
1194 skge_read32(hw, B2_GP_IO);
1195
1196 /* Enable GMII interface */
1197 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1198
1199 bcom_phy_init(skge, jumbo);
1200
1201 /* Set Station Address */
1202 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1203
1204 /* We don't use match addresses so clear */
1205 for (i = 1; i < 16; i++)
1206 xm_outaddr(hw, port, XM_EXM(i), zero);
1207
1208 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1209 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1210
1211 /* We don't need the FCS appended to the packet. */
1212 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1213 if (jumbo)
1214 r |= XM_RX_BIG_PK_OK;
1215
1216 if (skge->duplex == DUPLEX_HALF) {
1217 /*
1218 * If in manual half duplex mode the other side might be in
1219 * full duplex mode, so ignore if a carrier extension is not seen
1220 * on frames received
1221 */
1222 r |= XM_RX_DIS_CEXT;
1223 }
1224 xm_write16(hw, port, XM_RX_CMD, r);
1225
1226
1227 /* We want short frames padded to 60 bytes. */
1228 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1229
1230 /*
1231 * Bump up the transmit threshold. This helps hold off transmit
1232 * underruns when we're blasting traffic from both ports at once.
1233 */
1234 xm_write16(hw, port, XM_TX_THR, 512);
1235
1236 /*
1237 * Enable the reception of all error frames. This is is
1238 * a necessary evil due to the design of the XMAC. The
1239 * XMAC's receive FIFO is only 8K in size, however jumbo
1240 * frames can be up to 9000 bytes in length. When bad
1241 * frame filtering is enabled, the XMAC's RX FIFO operates
1242 * in 'store and forward' mode. For this to work, the
1243 * entire frame has to fit into the FIFO, but that means
1244 * that jumbo frames larger than 8192 bytes will be
1245 * truncated. Disabling all bad frame filtering causes
1246 * the RX FIFO to operate in streaming mode, in which
1247 * case the XMAC will start transferring frames out of the
1248 * RX FIFO as soon as the FIFO threshold is reached.
1249 */
1250 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1251
1252
1253 /*
1254 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1255 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1256 * and 'Octets Rx OK Hi Cnt Ov'.
1257 */
1258 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1259
1260 /*
1261 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1262 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1263 * and 'Octets Tx OK Hi Cnt Ov'.
1264 */
1265 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1266
1267 /* Configure MAC arbiter */
1268 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1269
1270 /* configure timeout values */
1271 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1272 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1273 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1274 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1275
1276 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1277 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1278 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1279 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1280
1281 /* Configure Rx MAC FIFO */
1282 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1283 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1284 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1285
1286 /* Configure Tx MAC FIFO */
1287 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1288 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1289 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1290
1291 if (jumbo) {
1292 /* Enable frame flushing if jumbo frames used */
1293 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1294 } else {
1295 /* enable timeout timers if normal frames */
1296 skge_write16(hw, B3_PA_CTRL,
1297 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1298 }
1299 }
1300
1301 static void genesis_stop(struct skge_port *skge)
1302 {
1303 struct skge_hw *hw = skge->hw;
1304 int port = skge->port;
1305 u32 reg;
1306
1307 genesis_reset(hw, port);
1308
1309 /* Clear Tx packet arbiter timeout IRQ */
1310 skge_write16(hw, B3_PA_CTRL,
1311 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1312
1313 /*
1314 * If the transfer sticks at the MAC the STOP command will not
1315 * terminate if we don't flush the XMAC's transmit FIFO !
1316 */
1317 xm_write32(hw, port, XM_MODE,
1318 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1319
1320
1321 /* Reset the MAC */
1322 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1323
1324 /* For external PHYs there must be special handling */
1325 reg = skge_read32(hw, B2_GP_IO);
1326 if (port == 0) {
1327 reg |= GP_DIR_0;
1328 reg &= ~GP_IO_0;
1329 } else {
1330 reg |= GP_DIR_2;
1331 reg &= ~GP_IO_2;
1332 }
1333 skge_write32(hw, B2_GP_IO, reg);
1334 skge_read32(hw, B2_GP_IO);
1335
1336 xm_write16(hw, port, XM_MMU_CMD,
1337 xm_read16(hw, port, XM_MMU_CMD)
1338 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1339
1340 xm_read16(hw, port, XM_MMU_CMD);
1341 }
1342
1343
1344 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1345 {
1346 struct skge_hw *hw = skge->hw;
1347 int port = skge->port;
1348 int i;
1349 unsigned long timeout = jiffies + HZ;
1350
1351 xm_write16(hw, port,
1352 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1353
1354 /* wait for update to complete */
1355 while (xm_read16(hw, port, XM_STAT_CMD)
1356 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1357 if (time_after(jiffies, timeout))
1358 break;
1359 udelay(10);
1360 }
1361
1362 /* special case for 64 bit octet counter */
1363 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1364 | xm_read32(hw, port, XM_TXO_OK_LO);
1365 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1366 | xm_read32(hw, port, XM_RXO_OK_LO);
1367
1368 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1369 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1370 }
1371
1372 static void genesis_mac_intr(struct skge_hw *hw, int port)
1373 {
1374 struct skge_port *skge = netdev_priv(hw->dev[port]);
1375 u16 status = xm_read16(hw, port, XM_ISRC);
1376
1377 if (netif_msg_intr(skge))
1378 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1379 skge->netdev->name, status);
1380
1381 if (status & XM_IS_TXF_UR) {
1382 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1383 ++skge->net_stats.tx_fifo_errors;
1384 }
1385 if (status & XM_IS_RXF_OV) {
1386 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1387 ++skge->net_stats.rx_fifo_errors;
1388 }
1389 }
1390
1391 static void genesis_link_up(struct skge_port *skge)
1392 {
1393 struct skge_hw *hw = skge->hw;
1394 int port = skge->port;
1395 u16 cmd;
1396 u32 mode, msk;
1397
1398 cmd = xm_read16(hw, port, XM_MMU_CMD);
1399
1400 /*
1401 * enabling pause frame reception is required for 1000BT
1402 * because the XMAC is not reset if the link is going down
1403 */
1404 if (skge->flow_control == FLOW_MODE_NONE ||
1405 skge->flow_control == FLOW_MODE_LOC_SEND)
1406 /* Disable Pause Frame Reception */
1407 cmd |= XM_MMU_IGN_PF;
1408 else
1409 /* Enable Pause Frame Reception */
1410 cmd &= ~XM_MMU_IGN_PF;
1411
1412 xm_write16(hw, port, XM_MMU_CMD, cmd);
1413
1414 mode = xm_read32(hw, port, XM_MODE);
1415 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1416 skge->flow_control == FLOW_MODE_LOC_SEND) {
1417 /*
1418 * Configure Pause Frame Generation
1419 * Use internal and external Pause Frame Generation.
1420 * Sending pause frames is edge triggered.
1421 * Send a Pause frame with the maximum pause time if
1422 * internal oder external FIFO full condition occurs.
1423 * Send a zero pause time frame to re-start transmission.
1424 */
1425 /* XM_PAUSE_DA = '010000C28001' (default) */
1426 /* XM_MAC_PTIME = 0xffff (maximum) */
1427 /* remember this value is defined in big endian (!) */
1428 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1429
1430 mode |= XM_PAUSE_MODE;
1431 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1432 } else {
1433 /*
1434 * disable pause frame generation is required for 1000BT
1435 * because the XMAC is not reset if the link is going down
1436 */
1437 /* Disable Pause Mode in Mode Register */
1438 mode &= ~XM_PAUSE_MODE;
1439
1440 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1441 }
1442
1443 xm_write32(hw, port, XM_MODE, mode);
1444
1445 msk = XM_DEF_MSK;
1446 /* disable GP0 interrupt bit for external Phy */
1447 msk |= XM_IS_INP_ASS;
1448
1449 xm_write16(hw, port, XM_IMSK, msk);
1450 xm_read16(hw, port, XM_ISRC);
1451
1452 /* get MMU Command Reg. */
1453 cmd = xm_read16(hw, port, XM_MMU_CMD);
1454 if (skge->duplex == DUPLEX_FULL)
1455 cmd |= XM_MMU_GMII_FD;
1456
1457 /*
1458 * Workaround BCOM Errata (#10523) for all BCom Phys
1459 * Enable Power Management after link up
1460 */
1461 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1462 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1463 & ~PHY_B_AC_DIS_PM);
1464 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1465
1466 /* enable Rx/Tx */
1467 xm_write16(hw, port, XM_MMU_CMD,
1468 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1469 skge_link_up(skge);
1470 }
1471
1472
1473 static inline void bcom_phy_intr(struct skge_port *skge)
1474 {
1475 struct skge_hw *hw = skge->hw;
1476 int port = skge->port;
1477 u16 isrc;
1478
1479 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1480 if (netif_msg_intr(skge))
1481 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1482 skge->netdev->name, isrc);
1483
1484 if (isrc & PHY_B_IS_PSE)
1485 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1486 hw->dev[port]->name);
1487
1488 /* Workaround BCom Errata:
1489 * enable and disable loopback mode if "NO HCD" occurs.
1490 */
1491 if (isrc & PHY_B_IS_NO_HDCL) {
1492 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1493 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1494 ctrl | PHY_CT_LOOP);
1495 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1496 ctrl & ~PHY_CT_LOOP);
1497 }
1498
1499 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1500 bcom_check_link(hw, port);
1501
1502 }
1503
1504 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1505 {
1506 int i;
1507
1508 gma_write16(hw, port, GM_SMI_DATA, val);
1509 gma_write16(hw, port, GM_SMI_CTRL,
1510 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1511 for (i = 0; i < PHY_RETRIES; i++) {
1512 udelay(1);
1513
1514 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1515 return 0;
1516 }
1517
1518 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1519 hw->dev[port]->name);
1520 return -EIO;
1521 }
1522
1523 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1524 {
1525 int i;
1526
1527 gma_write16(hw, port, GM_SMI_CTRL,
1528 GM_SMI_CT_PHY_AD(hw->phy_addr)
1529 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1530
1531 for (i = 0; i < PHY_RETRIES; i++) {
1532 udelay(1);
1533 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1534 goto ready;
1535 }
1536
1537 return -ETIMEDOUT;
1538 ready:
1539 *val = gma_read16(hw, port, GM_SMI_DATA);
1540 return 0;
1541 }
1542
1543 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1544 {
1545 u16 v = 0;
1546 if (__gm_phy_read(hw, port, reg, &v))
1547 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1548 hw->dev[port]->name);
1549 return v;
1550 }
1551
1552 /* Marvell Phy Initialization */
1553 static void yukon_init(struct skge_hw *hw, int port)
1554 {
1555 struct skge_port *skge = netdev_priv(hw->dev[port]);
1556 u16 ctrl, ct1000, adv;
1557
1558 if (skge->autoneg == AUTONEG_ENABLE) {
1559 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1560
1561 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1562 PHY_M_EC_MAC_S_MSK);
1563 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1564
1565 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1566
1567 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1568 }
1569
1570 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1571 if (skge->autoneg == AUTONEG_DISABLE)
1572 ctrl &= ~PHY_CT_ANE;
1573
1574 ctrl |= PHY_CT_RESET;
1575 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1576
1577 ctrl = 0;
1578 ct1000 = 0;
1579 adv = PHY_AN_CSMA;
1580
1581 if (skge->autoneg == AUTONEG_ENABLE) {
1582 if (hw->copper) {
1583 if (skge->advertising & ADVERTISED_1000baseT_Full)
1584 ct1000 |= PHY_M_1000C_AFD;
1585 if (skge->advertising & ADVERTISED_1000baseT_Half)
1586 ct1000 |= PHY_M_1000C_AHD;
1587 if (skge->advertising & ADVERTISED_100baseT_Full)
1588 adv |= PHY_M_AN_100_FD;
1589 if (skge->advertising & ADVERTISED_100baseT_Half)
1590 adv |= PHY_M_AN_100_HD;
1591 if (skge->advertising & ADVERTISED_10baseT_Full)
1592 adv |= PHY_M_AN_10_FD;
1593 if (skge->advertising & ADVERTISED_10baseT_Half)
1594 adv |= PHY_M_AN_10_HD;
1595 } else /* special defines for FIBER (88E1011S only) */
1596 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1597
1598 /* Set Flow-control capabilities */
1599 adv |= phy_pause_map[skge->flow_control];
1600
1601 /* Restart Auto-negotiation */
1602 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1603 } else {
1604 /* forced speed/duplex settings */
1605 ct1000 = PHY_M_1000C_MSE;
1606
1607 if (skge->duplex == DUPLEX_FULL)
1608 ctrl |= PHY_CT_DUP_MD;
1609
1610 switch (skge->speed) {
1611 case SPEED_1000:
1612 ctrl |= PHY_CT_SP1000;
1613 break;
1614 case SPEED_100:
1615 ctrl |= PHY_CT_SP100;
1616 break;
1617 }
1618
1619 ctrl |= PHY_CT_RESET;
1620 }
1621
1622 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1623
1624 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1625 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1626
1627 /* Enable phy interrupt on autonegotiation complete (or link up) */
1628 if (skge->autoneg == AUTONEG_ENABLE)
1629 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1630 else
1631 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1632 }
1633
1634 static void yukon_reset(struct skge_hw *hw, int port)
1635 {
1636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1637 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1638 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1639 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1640 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1641
1642 gma_write16(hw, port, GM_RX_CTRL,
1643 gma_read16(hw, port, GM_RX_CTRL)
1644 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1645 }
1646
1647 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1648 static int is_yukon_lite_a0(struct skge_hw *hw)
1649 {
1650 u32 reg;
1651 int ret;
1652
1653 if (hw->chip_id != CHIP_ID_YUKON)
1654 return 0;
1655
1656 reg = skge_read32(hw, B2_FAR);
1657 skge_write8(hw, B2_FAR + 3, 0xff);
1658 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1659 skge_write32(hw, B2_FAR, reg);
1660 return ret;
1661 }
1662
1663 static void yukon_mac_init(struct skge_hw *hw, int port)
1664 {
1665 struct skge_port *skge = netdev_priv(hw->dev[port]);
1666 int i;
1667 u32 reg;
1668 const u8 *addr = hw->dev[port]->dev_addr;
1669
1670 /* WA code for COMA mode -- set PHY reset */
1671 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1672 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1673 reg = skge_read32(hw, B2_GP_IO);
1674 reg |= GP_DIR_9 | GP_IO_9;
1675 skge_write32(hw, B2_GP_IO, reg);
1676 }
1677
1678 /* hard reset */
1679 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1680 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1681
1682 /* WA code for COMA mode -- clear PHY reset */
1683 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1684 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1685 reg = skge_read32(hw, B2_GP_IO);
1686 reg |= GP_DIR_9;
1687 reg &= ~GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
1690
1691 /* Set hardware config mode */
1692 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1693 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1694 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695
1696 /* Clear GMC reset */
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1700 if (skge->autoneg == AUTONEG_DISABLE) {
1701 reg = GM_GPCR_AU_ALL_DIS;
1702 gma_write16(hw, port, GM_GP_CTRL,
1703 gma_read16(hw, port, GM_GP_CTRL) | reg);
1704
1705 switch (skge->speed) {
1706 case SPEED_1000:
1707 reg |= GM_GPCR_SPEED_1000;
1708 /* fallthru */
1709 case SPEED_100:
1710 reg |= GM_GPCR_SPEED_100;
1711 }
1712
1713 if (skge->duplex == DUPLEX_FULL)
1714 reg |= GM_GPCR_DUP_FULL;
1715 } else
1716 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1717 switch (skge->flow_control) {
1718 case FLOW_MODE_NONE:
1719 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1720 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 break;
1722 case FLOW_MODE_LOC_SEND:
1723 /* disable Rx flow-control */
1724 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1725 }
1726
1727 gma_write16(hw, port, GM_GP_CTRL, reg);
1728 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1729
1730 yukon_init(hw, port);
1731
1732 /* MIB clear */
1733 reg = gma_read16(hw, port, GM_PHY_ADDR);
1734 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1735
1736 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1737 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1738 gma_write16(hw, port, GM_PHY_ADDR, reg);
1739
1740 /* transmit control */
1741 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1742
1743 /* receive control reg: unicast + multicast + no FCS */
1744 gma_write16(hw, port, GM_RX_CTRL,
1745 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1746
1747 /* transmit flow control */
1748 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1749
1750 /* transmit parameter */
1751 gma_write16(hw, port, GM_TX_PARAM,
1752 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1753 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1754 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1755
1756 /* serial mode register */
1757 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1758 if (hw->dev[port]->mtu > 1500)
1759 reg |= GM_SMOD_JUMBO_ENA;
1760
1761 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1762
1763 /* physical address: used for pause frames */
1764 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1765 /* virtual address for data */
1766 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1767
1768 /* enable interrupt mask for counter overflows */
1769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1772
1773 /* Initialize Mac Fifo */
1774
1775 /* Configure Rx MAC FIFO */
1776 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1777 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1778
1779 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1780 if (is_yukon_lite_a0(hw))
1781 reg &= ~GMF_RX_F_FL_ON;
1782
1783 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1784 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1785 /*
1786 * because Pause Packet Truncation in GMAC is not working
1787 * we have to increase the Flush Threshold to 64 bytes
1788 * in order to flush pause packets in Rx FIFO on Yukon-1
1789 */
1790 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1791
1792 /* Configure Tx MAC FIFO */
1793 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1794 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1795 }
1796
1797 /* Go into power down mode */
1798 static void yukon_suspend(struct skge_hw *hw, int port)
1799 {
1800 u16 ctrl;
1801
1802 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1803 ctrl |= PHY_M_PC_POL_R_DIS;
1804 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1805
1806 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1807 ctrl |= PHY_CT_RESET;
1808 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1809
1810 /* switch IEEE compatible power down mode on */
1811 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1812 ctrl |= PHY_CT_PDOWN;
1813 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1814 }
1815
1816 static void yukon_stop(struct skge_port *skge)
1817 {
1818 struct skge_hw *hw = skge->hw;
1819 int port = skge->port;
1820
1821 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1822 yukon_reset(hw, port);
1823
1824 gma_write16(hw, port, GM_GP_CTRL,
1825 gma_read16(hw, port, GM_GP_CTRL)
1826 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1827 gma_read16(hw, port, GM_GP_CTRL);
1828
1829 yukon_suspend(hw, port);
1830
1831 /* set GPHY Control reset */
1832 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1833 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1834 }
1835
1836 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1837 {
1838 struct skge_hw *hw = skge->hw;
1839 int port = skge->port;
1840 int i;
1841
1842 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1843 | gma_read32(hw, port, GM_TXO_OK_LO);
1844 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1845 | gma_read32(hw, port, GM_RXO_OK_LO);
1846
1847 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1848 data[i] = gma_read32(hw, port,
1849 skge_stats[i].gma_offset);
1850 }
1851
1852 static void yukon_mac_intr(struct skge_hw *hw, int port)
1853 {
1854 struct net_device *dev = hw->dev[port];
1855 struct skge_port *skge = netdev_priv(dev);
1856 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1857
1858 if (netif_msg_intr(skge))
1859 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1860 dev->name, status);
1861
1862 if (status & GM_IS_RX_FF_OR) {
1863 ++skge->net_stats.rx_fifo_errors;
1864 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1865 }
1866
1867 if (status & GM_IS_TX_FF_UR) {
1868 ++skge->net_stats.tx_fifo_errors;
1869 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1870 }
1871
1872 }
1873
1874 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1875 {
1876 switch (aux & PHY_M_PS_SPEED_MSK) {
1877 case PHY_M_PS_SPEED_1000:
1878 return SPEED_1000;
1879 case PHY_M_PS_SPEED_100:
1880 return SPEED_100;
1881 default:
1882 return SPEED_10;
1883 }
1884 }
1885
1886 static void yukon_link_up(struct skge_port *skge)
1887 {
1888 struct skge_hw *hw = skge->hw;
1889 int port = skge->port;
1890 u16 reg;
1891
1892 /* Enable Transmit FIFO Underrun */
1893 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1894
1895 reg = gma_read16(hw, port, GM_GP_CTRL);
1896 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1897 reg |= GM_GPCR_DUP_FULL;
1898
1899 /* enable Rx/Tx */
1900 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1901 gma_write16(hw, port, GM_GP_CTRL, reg);
1902
1903 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1904 skge_link_up(skge);
1905 }
1906
1907 static void yukon_link_down(struct skge_port *skge)
1908 {
1909 struct skge_hw *hw = skge->hw;
1910 int port = skge->port;
1911 u16 ctrl;
1912
1913 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1914
1915 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1916 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1917 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1918
1919 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1920 /* restore Asymmetric Pause bit */
1921 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1922 gm_phy_read(hw, port,
1923 PHY_MARV_AUNE_ADV)
1924 | PHY_M_AN_ASP);
1925
1926 }
1927
1928 yukon_reset(hw, port);
1929 skge_link_down(skge);
1930
1931 yukon_init(hw, port);
1932 }
1933
1934 static void yukon_phy_intr(struct skge_port *skge)
1935 {
1936 struct skge_hw *hw = skge->hw;
1937 int port = skge->port;
1938 const char *reason = NULL;
1939 u16 istatus, phystat;
1940
1941 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1942 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1943
1944 if (netif_msg_intr(skge))
1945 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1946 skge->netdev->name, istatus, phystat);
1947
1948 if (istatus & PHY_M_IS_AN_COMPL) {
1949 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1950 & PHY_M_AN_RF) {
1951 reason = "remote fault";
1952 goto failed;
1953 }
1954
1955 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1956 reason = "master/slave fault";
1957 goto failed;
1958 }
1959
1960 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1961 reason = "speed/duplex";
1962 goto failed;
1963 }
1964
1965 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1966 ? DUPLEX_FULL : DUPLEX_HALF;
1967 skge->speed = yukon_speed(hw, phystat);
1968
1969 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1970 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1971 case PHY_M_PS_PAUSE_MSK:
1972 skge->flow_control = FLOW_MODE_SYMMETRIC;
1973 break;
1974 case PHY_M_PS_RX_P_EN:
1975 skge->flow_control = FLOW_MODE_REM_SEND;
1976 break;
1977 case PHY_M_PS_TX_P_EN:
1978 skge->flow_control = FLOW_MODE_LOC_SEND;
1979 break;
1980 default:
1981 skge->flow_control = FLOW_MODE_NONE;
1982 }
1983
1984 if (skge->flow_control == FLOW_MODE_NONE ||
1985 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1986 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1987 else
1988 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1989 yukon_link_up(skge);
1990 return;
1991 }
1992
1993 if (istatus & PHY_M_IS_LSP_CHANGE)
1994 skge->speed = yukon_speed(hw, phystat);
1995
1996 if (istatus & PHY_M_IS_DUP_CHANGE)
1997 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1998 if (istatus & PHY_M_IS_LST_CHANGE) {
1999 if (phystat & PHY_M_PS_LINK_UP)
2000 yukon_link_up(skge);
2001 else
2002 yukon_link_down(skge);
2003 }
2004 return;
2005 failed:
2006 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2007 skge->netdev->name, reason);
2008
2009 /* XXX restart autonegotiation? */
2010 }
2011
2012 static void skge_phy_reset(struct skge_port *skge)
2013 {
2014 struct skge_hw *hw = skge->hw;
2015 int port = skge->port;
2016
2017 netif_stop_queue(skge->netdev);
2018 netif_carrier_off(skge->netdev);
2019
2020 spin_lock_bh(&hw->phy_lock);
2021 if (hw->chip_id == CHIP_ID_GENESIS) {
2022 genesis_reset(hw, port);
2023 genesis_mac_init(hw, port);
2024 } else {
2025 yukon_reset(hw, port);
2026 yukon_init(hw, port);
2027 }
2028 spin_unlock_bh(&hw->phy_lock);
2029 }
2030
2031 /* Basic MII support */
2032 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2033 {
2034 struct mii_ioctl_data *data = if_mii(ifr);
2035 struct skge_port *skge = netdev_priv(dev);
2036 struct skge_hw *hw = skge->hw;
2037 int err = -EOPNOTSUPP;
2038
2039 if (!netif_running(dev))
2040 return -ENODEV; /* Phy still in reset */
2041
2042 switch(cmd) {
2043 case SIOCGMIIPHY:
2044 data->phy_id = hw->phy_addr;
2045
2046 /* fallthru */
2047 case SIOCGMIIREG: {
2048 u16 val = 0;
2049 spin_lock_bh(&hw->phy_lock);
2050 if (hw->chip_id == CHIP_ID_GENESIS)
2051 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2052 else
2053 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2054 spin_unlock_bh(&hw->phy_lock);
2055 data->val_out = val;
2056 break;
2057 }
2058
2059 case SIOCSMIIREG:
2060 if (!capable(CAP_NET_ADMIN))
2061 return -EPERM;
2062
2063 spin_lock_bh(&hw->phy_lock);
2064 if (hw->chip_id == CHIP_ID_GENESIS)
2065 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2066 data->val_in);
2067 else
2068 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2069 data->val_in);
2070 spin_unlock_bh(&hw->phy_lock);
2071 break;
2072 }
2073 return err;
2074 }
2075
2076 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2077 {
2078 u32 end;
2079
2080 start /= 8;
2081 len /= 8;
2082 end = start + len - 1;
2083
2084 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2085 skge_write32(hw, RB_ADDR(q, RB_START), start);
2086 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2087 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2088 skge_write32(hw, RB_ADDR(q, RB_END), end);
2089
2090 if (q == Q_R1 || q == Q_R2) {
2091 /* Set thresholds on receive queue's */
2092 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2093 start + (2*len)/3);
2094 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2095 start + (len/3));
2096 } else {
2097 /* Enable store & forward on Tx queue's because
2098 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2099 */
2100 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2101 }
2102
2103 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2104 }
2105
2106 /* Setup Bus Memory Interface */
2107 static void skge_qset(struct skge_port *skge, u16 q,
2108 const struct skge_element *e)
2109 {
2110 struct skge_hw *hw = skge->hw;
2111 u32 watermark = 0x600;
2112 u64 base = skge->dma + (e->desc - skge->mem);
2113
2114 /* optimization to reduce window on 32bit/33mhz */
2115 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2116 watermark /= 2;
2117
2118 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2119 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2120 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2121 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2122 }
2123
2124 static int skge_up(struct net_device *dev)
2125 {
2126 struct skge_port *skge = netdev_priv(dev);
2127 struct skge_hw *hw = skge->hw;
2128 int port = skge->port;
2129 u32 chunk, ram_addr;
2130 size_t rx_size, tx_size;
2131 int err;
2132
2133 if (netif_msg_ifup(skge))
2134 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2135
2136 if (dev->mtu > RX_BUF_SIZE)
2137 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2138 else
2139 skge->rx_buf_size = RX_BUF_SIZE;
2140
2141
2142 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2143 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2144 skge->mem_size = tx_size + rx_size;
2145 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2146 if (!skge->mem)
2147 return -ENOMEM;
2148
2149 memset(skge->mem, 0, skge->mem_size);
2150
2151 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2152 goto free_pci_mem;
2153
2154 err = skge_rx_fill(skge);
2155 if (err)
2156 goto free_rx_ring;
2157
2158 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2159 skge->dma + rx_size)))
2160 goto free_rx_ring;
2161
2162 skge->tx_avail = skge->tx_ring.count - 1;
2163
2164 /* Enable IRQ from port */
2165 hw->intr_mask |= portirqmask[port];
2166 skge_write32(hw, B0_IMSK, hw->intr_mask);
2167
2168 /* Initialize MAC */
2169 spin_lock_bh(&hw->phy_lock);
2170 if (hw->chip_id == CHIP_ID_GENESIS)
2171 genesis_mac_init(hw, port);
2172 else
2173 yukon_mac_init(hw, port);
2174 spin_unlock_bh(&hw->phy_lock);
2175
2176 /* Configure RAMbuffers */
2177 chunk = hw->ram_size / ((hw->ports + 1)*2);
2178 ram_addr = hw->ram_offset + 2 * chunk * port;
2179
2180 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2181 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2182
2183 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2184 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2185 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2186
2187 /* Start receiver BMU */
2188 wmb();
2189 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2190 skge_led(skge, LED_MODE_ON);
2191
2192 return 0;
2193
2194 free_rx_ring:
2195 skge_rx_clean(skge);
2196 kfree(skge->rx_ring.start);
2197 free_pci_mem:
2198 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2199 skge->mem = NULL;
2200
2201 return err;
2202 }
2203
2204 static int skge_down(struct net_device *dev)
2205 {
2206 struct skge_port *skge = netdev_priv(dev);
2207 struct skge_hw *hw = skge->hw;
2208 int port = skge->port;
2209
2210 if (skge->mem == NULL)
2211 return 0;
2212
2213 if (netif_msg_ifdown(skge))
2214 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2215
2216 netif_stop_queue(dev);
2217
2218 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2219 if (hw->chip_id == CHIP_ID_GENESIS)
2220 genesis_stop(skge);
2221 else
2222 yukon_stop(skge);
2223
2224 hw->intr_mask &= ~portirqmask[skge->port];
2225 skge_write32(hw, B0_IMSK, hw->intr_mask);
2226
2227 /* Stop transmitter */
2228 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2229 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2230 RB_RST_SET|RB_DIS_OP_MD);
2231
2232
2233 /* Disable Force Sync bit and Enable Alloc bit */
2234 skge_write8(hw, SK_REG(port, TXA_CTRL),
2235 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2236
2237 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2238 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2239 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2240
2241 /* Reset PCI FIFO */
2242 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2243 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2244
2245 /* Reset the RAM Buffer async Tx queue */
2246 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2247 /* stop receiver */
2248 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2249 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2250 RB_RST_SET|RB_DIS_OP_MD);
2251 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2252
2253 if (hw->chip_id == CHIP_ID_GENESIS) {
2254 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2255 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2256 } else {
2257 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2258 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2259 }
2260
2261 skge_led(skge, LED_MODE_OFF);
2262
2263 skge_tx_clean(skge);
2264 skge_rx_clean(skge);
2265
2266 kfree(skge->rx_ring.start);
2267 kfree(skge->tx_ring.start);
2268 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2269 skge->mem = NULL;
2270 return 0;
2271 }
2272
2273 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2274 {
2275 struct skge_port *skge = netdev_priv(dev);
2276 struct skge_hw *hw = skge->hw;
2277 struct skge_ring *ring = &skge->tx_ring;
2278 struct skge_element *e;
2279 struct skge_tx_desc *td;
2280 int i;
2281 u32 control, len;
2282 u64 map;
2283 unsigned long flags;
2284
2285 skb = skb_padto(skb, ETH_ZLEN);
2286 if (!skb)
2287 return NETDEV_TX_OK;
2288
2289 local_irq_save(flags);
2290 if (!spin_trylock(&skge->tx_lock)) {
2291 /* Collision - tell upper layer to requeue */
2292 local_irq_restore(flags);
2293 return NETDEV_TX_LOCKED;
2294 }
2295
2296 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2297 if (!netif_queue_stopped(dev)) {
2298 netif_stop_queue(dev);
2299
2300 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2301 dev->name);
2302 }
2303 spin_unlock_irqrestore(&skge->tx_lock, flags);
2304 return NETDEV_TX_BUSY;
2305 }
2306
2307 e = ring->to_use;
2308 td = e->desc;
2309 e->skb = skb;
2310 len = skb_headlen(skb);
2311 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2312 pci_unmap_addr_set(e, mapaddr, map);
2313 pci_unmap_len_set(e, maplen, len);
2314
2315 td->dma_lo = map;
2316 td->dma_hi = map >> 32;
2317
2318 if (skb->ip_summed == CHECKSUM_HW) {
2319 int offset = skb->h.raw - skb->data;
2320
2321 /* This seems backwards, but it is what the sk98lin
2322 * does. Looks like hardware is wrong?
2323 */
2324 if (skb->h.ipiph->protocol == IPPROTO_UDP
2325 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2326 control = BMU_TCP_CHECK;
2327 else
2328 control = BMU_UDP_CHECK;
2329
2330 td->csum_offs = 0;
2331 td->csum_start = offset;
2332 td->csum_write = offset + skb->csum;
2333 } else
2334 control = BMU_CHECK;
2335
2336 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2337 control |= BMU_EOF| BMU_IRQ_EOF;
2338 else {
2339 struct skge_tx_desc *tf = td;
2340
2341 control |= BMU_STFWD;
2342 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2343 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2344
2345 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2346 frag->size, PCI_DMA_TODEVICE);
2347
2348 e = e->next;
2349 e->skb = NULL;
2350 tf = e->desc;
2351 tf->dma_lo = map;
2352 tf->dma_hi = (u64) map >> 32;
2353 pci_unmap_addr_set(e, mapaddr, map);
2354 pci_unmap_len_set(e, maplen, frag->size);
2355
2356 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2357 }
2358 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2359 }
2360 /* Make sure all the descriptors written */
2361 wmb();
2362 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2363 wmb();
2364
2365 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2366
2367 if (netif_msg_tx_queued(skge))
2368 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2369 dev->name, e - ring->start, skb->len);
2370
2371 ring->to_use = e->next;
2372 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2373 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2374 pr_debug("%s: transmit queue full\n", dev->name);
2375 netif_stop_queue(dev);
2376 }
2377
2378 dev->trans_start = jiffies;
2379 spin_unlock_irqrestore(&skge->tx_lock, flags);
2380
2381 return NETDEV_TX_OK;
2382 }
2383
2384 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2385 {
2386 /* This ring element can be skb or fragment */
2387 if (e->skb) {
2388 pci_unmap_single(hw->pdev,
2389 pci_unmap_addr(e, mapaddr),
2390 pci_unmap_len(e, maplen),
2391 PCI_DMA_TODEVICE);
2392 dev_kfree_skb_any(e->skb);
2393 e->skb = NULL;
2394 } else {
2395 pci_unmap_page(hw->pdev,
2396 pci_unmap_addr(e, mapaddr),
2397 pci_unmap_len(e, maplen),
2398 PCI_DMA_TODEVICE);
2399 }
2400 }
2401
2402 static void skge_tx_clean(struct skge_port *skge)
2403 {
2404 struct skge_ring *ring = &skge->tx_ring;
2405 struct skge_element *e;
2406 unsigned long flags;
2407
2408 spin_lock_irqsave(&skge->tx_lock, flags);
2409 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2410 ++skge->tx_avail;
2411 skge_tx_free(skge->hw, e);
2412 }
2413 ring->to_clean = e;
2414 spin_unlock_irqrestore(&skge->tx_lock, flags);
2415 }
2416
2417 static void skge_tx_timeout(struct net_device *dev)
2418 {
2419 struct skge_port *skge = netdev_priv(dev);
2420
2421 if (netif_msg_timer(skge))
2422 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2423
2424 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2425 skge_tx_clean(skge);
2426 }
2427
2428 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2429 {
2430 int err;
2431
2432 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2433 return -EINVAL;
2434
2435 if (!netif_running(dev)) {
2436 dev->mtu = new_mtu;
2437 return 0;
2438 }
2439
2440 skge_down(dev);
2441
2442 dev->mtu = new_mtu;
2443
2444 err = skge_up(dev);
2445 if (err)
2446 dev_close(dev);
2447
2448 return err;
2449 }
2450
2451 static void genesis_set_multicast(struct net_device *dev)
2452 {
2453 struct skge_port *skge = netdev_priv(dev);
2454 struct skge_hw *hw = skge->hw;
2455 int port = skge->port;
2456 int i, count = dev->mc_count;
2457 struct dev_mc_list *list = dev->mc_list;
2458 u32 mode;
2459 u8 filter[8];
2460
2461 mode = xm_read32(hw, port, XM_MODE);
2462 mode |= XM_MD_ENA_HASH;
2463 if (dev->flags & IFF_PROMISC)
2464 mode |= XM_MD_ENA_PROM;
2465 else
2466 mode &= ~XM_MD_ENA_PROM;
2467
2468 if (dev->flags & IFF_ALLMULTI)
2469 memset(filter, 0xff, sizeof(filter));
2470 else {
2471 memset(filter, 0, sizeof(filter));
2472 for (i = 0; list && i < count; i++, list = list->next) {
2473 u32 crc, bit;
2474 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2475 bit = ~crc & 0x3f;
2476 filter[bit/8] |= 1 << (bit%8);
2477 }
2478 }
2479
2480 xm_write32(hw, port, XM_MODE, mode);
2481 xm_outhash(hw, port, XM_HSM, filter);
2482 }
2483
2484 static void yukon_set_multicast(struct net_device *dev)
2485 {
2486 struct skge_port *skge = netdev_priv(dev);
2487 struct skge_hw *hw = skge->hw;
2488 int port = skge->port;
2489 struct dev_mc_list *list = dev->mc_list;
2490 u16 reg;
2491 u8 filter[8];
2492
2493 memset(filter, 0, sizeof(filter));
2494
2495 reg = gma_read16(hw, port, GM_RX_CTRL);
2496 reg |= GM_RXCR_UCF_ENA;
2497
2498 if (dev->flags & IFF_PROMISC) /* promiscuous */
2499 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2500 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2501 memset(filter, 0xff, sizeof(filter));
2502 else if (dev->mc_count == 0) /* no multicast */
2503 reg &= ~GM_RXCR_MCF_ENA;
2504 else {
2505 int i;
2506 reg |= GM_RXCR_MCF_ENA;
2507
2508 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2509 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2510 filter[bit/8] |= 1 << (bit%8);
2511 }
2512 }
2513
2514
2515 gma_write16(hw, port, GM_MC_ADDR_H1,
2516 (u16)filter[0] | ((u16)filter[1] << 8));
2517 gma_write16(hw, port, GM_MC_ADDR_H2,
2518 (u16)filter[2] | ((u16)filter[3] << 8));
2519 gma_write16(hw, port, GM_MC_ADDR_H3,
2520 (u16)filter[4] | ((u16)filter[5] << 8));
2521 gma_write16(hw, port, GM_MC_ADDR_H4,
2522 (u16)filter[6] | ((u16)filter[7] << 8));
2523
2524 gma_write16(hw, port, GM_RX_CTRL, reg);
2525 }
2526
2527 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2528 {
2529 if (hw->chip_id == CHIP_ID_GENESIS)
2530 return status >> XMR_FS_LEN_SHIFT;
2531 else
2532 return status >> GMR_FS_LEN_SHIFT;
2533 }
2534
2535 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2536 {
2537 if (hw->chip_id == CHIP_ID_GENESIS)
2538 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2539 else
2540 return (status & GMR_FS_ANY_ERR) ||
2541 (status & GMR_FS_RX_OK) == 0;
2542 }
2543
2544
2545 /* Get receive buffer from descriptor.
2546 * Handles copy of small buffers and reallocation failures
2547 */
2548 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2549 struct skge_element *e,
2550 u32 control, u32 status, u16 csum)
2551 {
2552 struct sk_buff *skb;
2553 u16 len = control & BMU_BBC;
2554
2555 if (unlikely(netif_msg_rx_status(skge)))
2556 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2557 skge->netdev->name, e - skge->rx_ring.start,
2558 status, len);
2559
2560 if (len > skge->rx_buf_size)
2561 goto error;
2562
2563 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2564 goto error;
2565
2566 if (bad_phy_status(skge->hw, status))
2567 goto error;
2568
2569 if (phy_length(skge->hw, status) != len)
2570 goto error;
2571
2572 if (len < RX_COPY_THRESHOLD) {
2573 skb = dev_alloc_skb(len + 2);
2574 if (!skb)
2575 goto resubmit;
2576
2577 skb_reserve(skb, 2);
2578 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2579 pci_unmap_addr(e, mapaddr),
2580 len, PCI_DMA_FROMDEVICE);
2581 memcpy(skb->data, e->skb->data, len);
2582 pci_dma_sync_single_for_device(skge->hw->pdev,
2583 pci_unmap_addr(e, mapaddr),
2584 len, PCI_DMA_FROMDEVICE);
2585 skge_rx_reuse(e, skge->rx_buf_size);
2586 } else {
2587 struct sk_buff *nskb;
2588 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2589 if (!nskb)
2590 goto resubmit;
2591
2592 pci_unmap_single(skge->hw->pdev,
2593 pci_unmap_addr(e, mapaddr),
2594 pci_unmap_len(e, maplen),
2595 PCI_DMA_FROMDEVICE);
2596 skb = e->skb;
2597 prefetch(skb->data);
2598 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2599 }
2600
2601 skb_put(skb, len);
2602 skb->dev = skge->netdev;
2603 if (skge->rx_csum) {
2604 skb->csum = csum;
2605 skb->ip_summed = CHECKSUM_HW;
2606 }
2607
2608 skb->protocol = eth_type_trans(skb, skge->netdev);
2609
2610 return skb;
2611 error:
2612
2613 if (netif_msg_rx_err(skge))
2614 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2615 skge->netdev->name, e - skge->rx_ring.start,
2616 control, status);
2617
2618 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2619 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2620 skge->net_stats.rx_length_errors++;
2621 if (status & XMR_FS_FRA_ERR)
2622 skge->net_stats.rx_frame_errors++;
2623 if (status & XMR_FS_FCS_ERR)
2624 skge->net_stats.rx_crc_errors++;
2625 } else {
2626 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2627 skge->net_stats.rx_length_errors++;
2628 if (status & GMR_FS_FRAGMENT)
2629 skge->net_stats.rx_frame_errors++;
2630 if (status & GMR_FS_CRC_ERR)
2631 skge->net_stats.rx_crc_errors++;
2632 }
2633
2634 resubmit:
2635 skge_rx_reuse(e, skge->rx_buf_size);
2636 return NULL;
2637 }
2638
2639
2640 static int skge_poll(struct net_device *dev, int *budget)
2641 {
2642 struct skge_port *skge = netdev_priv(dev);
2643 struct skge_hw *hw = skge->hw;
2644 struct skge_ring *ring = &skge->rx_ring;
2645 struct skge_element *e;
2646 unsigned int to_do = min(dev->quota, *budget);
2647 unsigned int work_done = 0;
2648
2649 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2650 struct skge_rx_desc *rd = e->desc;
2651 struct sk_buff *skb;
2652 u32 control;
2653
2654 rmb();
2655 control = rd->control;
2656 if (control & BMU_OWN)
2657 break;
2658
2659 skb = skge_rx_get(skge, e, control, rd->status,
2660 le16_to_cpu(rd->csum2));
2661 if (likely(skb)) {
2662 dev->last_rx = jiffies;
2663 netif_receive_skb(skb);
2664
2665 ++work_done;
2666 } else
2667 skge_rx_reuse(e, skge->rx_buf_size);
2668 }
2669 ring->to_clean = e;
2670
2671 /* restart receiver */
2672 wmb();
2673 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2674 CSR_START | CSR_IRQ_CL_F);
2675
2676 *budget -= work_done;
2677 dev->quota -= work_done;
2678
2679 if (work_done >= to_do)
2680 return 1; /* not done */
2681
2682 netif_rx_complete(dev);
2683 hw->intr_mask |= portirqmask[skge->port];
2684 skge_write32(hw, B0_IMSK, hw->intr_mask);
2685 skge_read32(hw, B0_IMSK);
2686
2687 return 0;
2688 }
2689
2690 static inline void skge_tx_intr(struct net_device *dev)
2691 {
2692 struct skge_port *skge = netdev_priv(dev);
2693 struct skge_hw *hw = skge->hw;
2694 struct skge_ring *ring = &skge->tx_ring;
2695 struct skge_element *e;
2696
2697 spin_lock(&skge->tx_lock);
2698 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2699 struct skge_tx_desc *td = e->desc;
2700 u32 control;
2701
2702 rmb();
2703 control = td->control;
2704 if (control & BMU_OWN)
2705 break;
2706
2707 if (unlikely(netif_msg_tx_done(skge)))
2708 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2709 dev->name, e - ring->start, td->status);
2710
2711 skge_tx_free(hw, e);
2712 e->skb = NULL;
2713 ++skge->tx_avail;
2714 }
2715 ring->to_clean = e;
2716 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2717
2718 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2719 netif_wake_queue(dev);
2720
2721 spin_unlock(&skge->tx_lock);
2722 }
2723
2724 /* Parity errors seem to happen when Genesis is connected to a switch
2725 * with no other ports present. Heartbeat error??
2726 */
2727 static void skge_mac_parity(struct skge_hw *hw, int port)
2728 {
2729 struct net_device *dev = hw->dev[port];
2730
2731 if (dev) {
2732 struct skge_port *skge = netdev_priv(dev);
2733 ++skge->net_stats.tx_heartbeat_errors;
2734 }
2735
2736 if (hw->chip_id == CHIP_ID_GENESIS)
2737 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2738 MFF_CLR_PERR);
2739 else
2740 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2741 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2742 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2743 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2744 }
2745
2746 static void skge_pci_clear(struct skge_hw *hw)
2747 {
2748 u16 status;
2749
2750 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2751 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2752 pci_write_config_word(hw->pdev, PCI_STATUS,
2753 status | PCI_STATUS_ERROR_BITS);
2754 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2755 }
2756
2757 static void skge_mac_intr(struct skge_hw *hw, int port)
2758 {
2759 if (hw->chip_id == CHIP_ID_GENESIS)
2760 genesis_mac_intr(hw, port);
2761 else
2762 yukon_mac_intr(hw, port);
2763 }
2764
2765 /* Handle device specific framing and timeout interrupts */
2766 static void skge_error_irq(struct skge_hw *hw)
2767 {
2768 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2769
2770 if (hw->chip_id == CHIP_ID_GENESIS) {
2771 /* clear xmac errors */
2772 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2773 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2774 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2775 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2776 } else {
2777 /* Timestamp (unused) overflow */
2778 if (hwstatus & IS_IRQ_TIST_OV)
2779 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2780 }
2781
2782 if (hwstatus & IS_RAM_RD_PAR) {
2783 printk(KERN_ERR PFX "Ram read data parity error\n");
2784 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2785 }
2786
2787 if (hwstatus & IS_RAM_WR_PAR) {
2788 printk(KERN_ERR PFX "Ram write data parity error\n");
2789 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2790 }
2791
2792 if (hwstatus & IS_M1_PAR_ERR)
2793 skge_mac_parity(hw, 0);
2794
2795 if (hwstatus & IS_M2_PAR_ERR)
2796 skge_mac_parity(hw, 1);
2797
2798 if (hwstatus & IS_R1_PAR_ERR)
2799 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2800
2801 if (hwstatus & IS_R2_PAR_ERR)
2802 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2803
2804 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2805 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2806 hwstatus);
2807
2808 skge_pci_clear(hw);
2809
2810 /* if error still set then just ignore it */
2811 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2812 if (hwstatus & IS_IRQ_STAT) {
2813 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2814 hwstatus);
2815 hw->intr_mask &= ~IS_HW_ERR;
2816 }
2817 }
2818 }
2819
2820 /*
2821 * Interrupt from PHY are handled in tasklet (soft irq)
2822 * because accessing phy registers requires spin wait which might
2823 * cause excess interrupt latency.
2824 */
2825 static void skge_extirq(unsigned long data)
2826 {
2827 struct skge_hw *hw = (struct skge_hw *) data;
2828 int port;
2829
2830 spin_lock(&hw->phy_lock);
2831 for (port = 0; port < 2; port++) {
2832 struct net_device *dev = hw->dev[port];
2833
2834 if (dev && netif_running(dev)) {
2835 struct skge_port *skge = netdev_priv(dev);
2836
2837 if (hw->chip_id != CHIP_ID_GENESIS)
2838 yukon_phy_intr(skge);
2839 else
2840 bcom_phy_intr(skge);
2841 }
2842 }
2843 spin_unlock(&hw->phy_lock);
2844
2845 local_irq_disable();
2846 hw->intr_mask |= IS_EXT_REG;
2847 skge_write32(hw, B0_IMSK, hw->intr_mask);
2848 local_irq_enable();
2849 }
2850
2851 static inline void skge_wakeup(struct net_device *dev)
2852 {
2853 struct skge_port *skge = netdev_priv(dev);
2854
2855 prefetch(skge->rx_ring.to_clean);
2856 netif_rx_schedule(dev);
2857 }
2858
2859 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2860 {
2861 struct skge_hw *hw = dev_id;
2862 u32 status = skge_read32(hw, B0_SP_ISRC);
2863
2864 if (status == 0 || status == ~0) /* hotplug or shared irq */
2865 return IRQ_NONE;
2866
2867 status &= hw->intr_mask;
2868 if (status & IS_R1_F) {
2869 hw->intr_mask &= ~IS_R1_F;
2870 skge_wakeup(hw->dev[0]);
2871 }
2872
2873 if (status & IS_R2_F) {
2874 hw->intr_mask &= ~IS_R2_F;
2875 skge_wakeup(hw->dev[1]);
2876 }
2877
2878 if (status & IS_XA1_F)
2879 skge_tx_intr(hw->dev[0]);
2880
2881 if (status & IS_XA2_F)
2882 skge_tx_intr(hw->dev[1]);
2883
2884 if (status & IS_PA_TO_RX1) {
2885 struct skge_port *skge = netdev_priv(hw->dev[0]);
2886 ++skge->net_stats.rx_over_errors;
2887 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2888 }
2889
2890 if (status & IS_PA_TO_RX2) {
2891 struct skge_port *skge = netdev_priv(hw->dev[1]);
2892 ++skge->net_stats.rx_over_errors;
2893 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2894 }
2895
2896 if (status & IS_PA_TO_TX1)
2897 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2898
2899 if (status & IS_PA_TO_TX2)
2900 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2901
2902 if (status & IS_MAC1)
2903 skge_mac_intr(hw, 0);
2904
2905 if (status & IS_MAC2)
2906 skge_mac_intr(hw, 1);
2907
2908 if (status & IS_HW_ERR)
2909 skge_error_irq(hw);
2910
2911 if (status & IS_EXT_REG) {
2912 hw->intr_mask &= ~IS_EXT_REG;
2913 tasklet_schedule(&hw->ext_tasklet);
2914 }
2915
2916 skge_write32(hw, B0_IMSK, hw->intr_mask);
2917
2918 return IRQ_HANDLED;
2919 }
2920
2921 #ifdef CONFIG_NET_POLL_CONTROLLER
2922 static void skge_netpoll(struct net_device *dev)
2923 {
2924 struct skge_port *skge = netdev_priv(dev);
2925
2926 disable_irq(dev->irq);
2927 skge_intr(dev->irq, skge->hw, NULL);
2928 enable_irq(dev->irq);
2929 }
2930 #endif
2931
2932 static int skge_set_mac_address(struct net_device *dev, void *p)
2933 {
2934 struct skge_port *skge = netdev_priv(dev);
2935 struct skge_hw *hw = skge->hw;
2936 unsigned port = skge->port;
2937 const struct sockaddr *addr = p;
2938
2939 if (!is_valid_ether_addr(addr->sa_data))
2940 return -EADDRNOTAVAIL;
2941
2942 spin_lock_bh(&hw->phy_lock);
2943 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2944 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2945 dev->dev_addr, ETH_ALEN);
2946 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2947 dev->dev_addr, ETH_ALEN);
2948
2949 if (hw->chip_id == CHIP_ID_GENESIS)
2950 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2951 else {
2952 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2953 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2954 }
2955 spin_unlock_bh(&hw->phy_lock);
2956
2957 return 0;
2958 }
2959
2960 static const struct {
2961 u8 id;
2962 const char *name;
2963 } skge_chips[] = {
2964 { CHIP_ID_GENESIS, "Genesis" },
2965 { CHIP_ID_YUKON, "Yukon" },
2966 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2967 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2968 };
2969
2970 static const char *skge_board_name(const struct skge_hw *hw)
2971 {
2972 int i;
2973 static char buf[16];
2974
2975 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2976 if (skge_chips[i].id == hw->chip_id)
2977 return skge_chips[i].name;
2978
2979 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2980 return buf;
2981 }
2982
2983
2984 /*
2985 * Setup the board data structure, but don't bring up
2986 * the port(s)
2987 */
2988 static int skge_reset(struct skge_hw *hw)
2989 {
2990 u32 reg;
2991 u16 ctst;
2992 u8 t8, mac_cfg, pmd_type, phy_type;
2993 int i;
2994
2995 ctst = skge_read16(hw, B0_CTST);
2996
2997 /* do a SW reset */
2998 skge_write8(hw, B0_CTST, CS_RST_SET);
2999 skge_write8(hw, B0_CTST, CS_RST_CLR);
3000
3001 /* clear PCI errors, if any */
3002 skge_pci_clear(hw);
3003
3004 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3005
3006 /* restore CLK_RUN bits (for Yukon-Lite) */
3007 skge_write16(hw, B0_CTST,
3008 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3009
3010 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3011 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3012 pmd_type = skge_read8(hw, B2_PMD_TYP);
3013 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3014
3015 switch (hw->chip_id) {
3016 case CHIP_ID_GENESIS:
3017 switch (phy_type) {
3018 case SK_PHY_BCOM:
3019 hw->phy_addr = PHY_ADDR_BCOM;
3020 break;
3021 default:
3022 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3023 pci_name(hw->pdev), phy_type);
3024 return -EOPNOTSUPP;
3025 }
3026 break;
3027
3028 case CHIP_ID_YUKON:
3029 case CHIP_ID_YUKON_LITE:
3030 case CHIP_ID_YUKON_LP:
3031 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3032 hw->copper = 1;
3033
3034 hw->phy_addr = PHY_ADDR_MARV;
3035 break;
3036
3037 default:
3038 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3039 pci_name(hw->pdev), hw->chip_id);
3040 return -EOPNOTSUPP;
3041 }
3042
3043 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3044 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3045 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3046
3047 /* read the adapters RAM size */
3048 t8 = skge_read8(hw, B2_E_0);
3049 if (hw->chip_id == CHIP_ID_GENESIS) {
3050 if (t8 == 3) {
3051 /* special case: 4 x 64k x 36, offset = 0x80000 */
3052 hw->ram_size = 0x100000;
3053 hw->ram_offset = 0x80000;
3054 } else
3055 hw->ram_size = t8 * 512;
3056 }
3057 else if (t8 == 0)
3058 hw->ram_size = 0x20000;
3059 else
3060 hw->ram_size = t8 * 4096;
3061
3062 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3063 if (hw->chip_id == CHIP_ID_GENESIS)
3064 genesis_init(hw);
3065 else {
3066 /* switch power to VCC (WA for VAUX problem) */
3067 skge_write8(hw, B0_POWER_CTRL,
3068 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3069
3070 /* avoid boards with stuck Hardware error bits */
3071 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3072 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3073 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3074 hw->intr_mask &= ~IS_HW_ERR;
3075 }
3076
3077 /* Clear PHY COMA */
3078 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3079 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3080 reg &= ~PCI_PHY_COMA;
3081 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3082 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3083
3084
3085 for (i = 0; i < hw->ports; i++) {
3086 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3087 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3088 }
3089 }
3090
3091 /* turn off hardware timer (unused) */
3092 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3093 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3094 skge_write8(hw, B0_LED, LED_STAT_ON);
3095
3096 /* enable the Tx Arbiters */
3097 for (i = 0; i < hw->ports; i++)
3098 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3099
3100 /* Initialize ram interface */
3101 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3102
3103 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3104 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3105 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3106 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3107 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3108 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3109 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3110 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3111 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3112 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3113 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3114 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3115
3116 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3117
3118 /* Set interrupt moderation for Transmit only
3119 * Receive interrupts avoided by NAPI
3120 */
3121 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3122 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3123 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3124
3125 skge_write32(hw, B0_IMSK, hw->intr_mask);
3126
3127 spin_lock_bh(&hw->phy_lock);
3128 for (i = 0; i < hw->ports; i++) {
3129 if (hw->chip_id == CHIP_ID_GENESIS)
3130 genesis_reset(hw, i);
3131 else
3132 yukon_reset(hw, i);
3133 }
3134 spin_unlock_bh(&hw->phy_lock);
3135
3136 return 0;
3137 }
3138
3139 /* Initialize network device */
3140 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3141 int highmem)
3142 {
3143 struct skge_port *skge;
3144 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3145
3146 if (!dev) {
3147 printk(KERN_ERR "skge etherdev alloc failed");
3148 return NULL;
3149 }
3150
3151 SET_MODULE_OWNER(dev);
3152 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3153 dev->open = skge_up;
3154 dev->stop = skge_down;
3155 dev->do_ioctl = skge_ioctl;
3156 dev->hard_start_xmit = skge_xmit_frame;
3157 dev->get_stats = skge_get_stats;
3158 if (hw->chip_id == CHIP_ID_GENESIS)
3159 dev->set_multicast_list = genesis_set_multicast;
3160 else
3161 dev->set_multicast_list = yukon_set_multicast;
3162
3163 dev->set_mac_address = skge_set_mac_address;
3164 dev->change_mtu = skge_change_mtu;
3165 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3166 dev->tx_timeout = skge_tx_timeout;
3167 dev->watchdog_timeo = TX_WATCHDOG;
3168 dev->poll = skge_poll;
3169 dev->weight = NAPI_WEIGHT;
3170 #ifdef CONFIG_NET_POLL_CONTROLLER
3171 dev->poll_controller = skge_netpoll;
3172 #endif
3173 dev->irq = hw->pdev->irq;
3174 dev->features = NETIF_F_LLTX;
3175 if (highmem)
3176 dev->features |= NETIF_F_HIGHDMA;
3177
3178 skge = netdev_priv(dev);
3179 skge->netdev = dev;
3180 skge->hw = hw;
3181 skge->msg_enable = netif_msg_init(debug, default_msg);
3182 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3183 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3184
3185 /* Auto speed and flow control */
3186 skge->autoneg = AUTONEG_ENABLE;
3187 skge->flow_control = FLOW_MODE_SYMMETRIC;
3188 skge->duplex = -1;
3189 skge->speed = -1;
3190 skge->advertising = skge_supported_modes(hw);
3191
3192 hw->dev[port] = dev;
3193
3194 skge->port = port;
3195
3196 spin_lock_init(&skge->tx_lock);
3197
3198 if (hw->chip_id != CHIP_ID_GENESIS) {
3199 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3200 skge->rx_csum = 1;
3201 }
3202
3203 /* read the mac address */
3204 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3205 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3206
3207 /* device is off until link detection */
3208 netif_carrier_off(dev);
3209 netif_stop_queue(dev);
3210
3211 return dev;
3212 }
3213
3214 static void __devinit skge_show_addr(struct net_device *dev)
3215 {
3216 const struct skge_port *skge = netdev_priv(dev);
3217
3218 if (netif_msg_probe(skge))
3219 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3220 dev->name,
3221 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3222 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3223 }
3224
3225 static int __devinit skge_probe(struct pci_dev *pdev,
3226 const struct pci_device_id *ent)
3227 {
3228 struct net_device *dev, *dev1;
3229 struct skge_hw *hw;
3230 int err, using_dac = 0;
3231
3232 if ((err = pci_enable_device(pdev))) {
3233 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3234 pci_name(pdev));
3235 goto err_out;
3236 }
3237
3238 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3239 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3240 pci_name(pdev));
3241 goto err_out_disable_pdev;
3242 }
3243
3244 pci_set_master(pdev);
3245
3246 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3247 using_dac = 1;
3248 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3249 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3250 pci_name(pdev));
3251 goto err_out_free_regions;
3252 }
3253
3254 #ifdef __BIG_ENDIAN
3255 /* byte swap descriptors in hardware */
3256 {
3257 u32 reg;
3258
3259 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3260 reg |= PCI_REV_DESC;
3261 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3262 }
3263 #endif
3264
3265 err = -ENOMEM;
3266 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3267 if (!hw) {
3268 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3269 pci_name(pdev));
3270 goto err_out_free_regions;
3271 }
3272
3273 hw->pdev = pdev;
3274 spin_lock_init(&hw->phy_lock);
3275 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3276
3277 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3278 if (!hw->regs) {
3279 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3280 pci_name(pdev));
3281 goto err_out_free_hw;
3282 }
3283
3284 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3285 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3286 pci_name(pdev), pdev->irq);
3287 goto err_out_iounmap;
3288 }
3289 pci_set_drvdata(pdev, hw);
3290
3291 err = skge_reset(hw);
3292 if (err)
3293 goto err_out_free_irq;
3294
3295 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3296 pci_resource_start(pdev, 0), pdev->irq,
3297 skge_board_name(hw), hw->chip_rev);
3298
3299 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3300 goto err_out_led_off;
3301
3302 if ((err = register_netdev(dev))) {
3303 printk(KERN_ERR PFX "%s: cannot register net device\n",
3304 pci_name(pdev));
3305 goto err_out_free_netdev;
3306 }
3307
3308 skge_show_addr(dev);
3309
3310 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3311 if (register_netdev(dev1) == 0)
3312 skge_show_addr(dev1);
3313 else {
3314 /* Failure to register second port need not be fatal */
3315 printk(KERN_WARNING PFX "register of second port failed\n");
3316 hw->dev[1] = NULL;
3317 free_netdev(dev1);
3318 }
3319 }
3320
3321 return 0;
3322
3323 err_out_free_netdev:
3324 free_netdev(dev);
3325 err_out_led_off:
3326 skge_write16(hw, B0_LED, LED_STAT_OFF);
3327 err_out_free_irq:
3328 free_irq(pdev->irq, hw);
3329 err_out_iounmap:
3330 iounmap(hw->regs);
3331 err_out_free_hw:
3332 kfree(hw);
3333 err_out_free_regions:
3334 pci_release_regions(pdev);
3335 err_out_disable_pdev:
3336 pci_disable_device(pdev);
3337 pci_set_drvdata(pdev, NULL);
3338 err_out:
3339 return err;
3340 }
3341
3342 static void __devexit skge_remove(struct pci_dev *pdev)
3343 {
3344 struct skge_hw *hw = pci_get_drvdata(pdev);
3345 struct net_device *dev0, *dev1;
3346
3347 if (!hw)
3348 return;
3349
3350 if ((dev1 = hw->dev[1]))
3351 unregister_netdev(dev1);
3352 dev0 = hw->dev[0];
3353 unregister_netdev(dev0);
3354
3355 skge_write32(hw, B0_IMSK, 0);
3356 skge_write16(hw, B0_LED, LED_STAT_OFF);
3357 skge_pci_clear(hw);
3358 skge_write8(hw, B0_CTST, CS_RST_SET);
3359
3360 tasklet_kill(&hw->ext_tasklet);
3361
3362 free_irq(pdev->irq, hw);
3363 pci_release_regions(pdev);
3364 pci_disable_device(pdev);
3365 if (dev1)
3366 free_netdev(dev1);
3367 free_netdev(dev0);
3368
3369 iounmap(hw->regs);
3370 kfree(hw);
3371 pci_set_drvdata(pdev, NULL);
3372 }
3373
3374 #ifdef CONFIG_PM
3375 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3376 {
3377 struct skge_hw *hw = pci_get_drvdata(pdev);
3378 int i, wol = 0;
3379
3380 for (i = 0; i < 2; i++) {
3381 struct net_device *dev = hw->dev[i];
3382
3383 if (dev) {
3384 struct skge_port *skge = netdev_priv(dev);
3385 if (netif_running(dev)) {
3386 netif_carrier_off(dev);
3387 if (skge->wol)
3388 netif_stop_queue(dev);
3389 else
3390 skge_down(dev);
3391 }
3392 netif_device_detach(dev);
3393 wol |= skge->wol;
3394 }
3395 }
3396
3397 pci_save_state(pdev);
3398 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3399 pci_disable_device(pdev);
3400 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3401
3402 return 0;
3403 }
3404
3405 static int skge_resume(struct pci_dev *pdev)
3406 {
3407 struct skge_hw *hw = pci_get_drvdata(pdev);
3408 int i;
3409
3410 pci_set_power_state(pdev, PCI_D0);
3411 pci_restore_state(pdev);
3412 pci_enable_wake(pdev, PCI_D0, 0);
3413
3414 skge_reset(hw);
3415
3416 for (i = 0; i < 2; i++) {
3417 struct net_device *dev = hw->dev[i];
3418 if (dev) {
3419 netif_device_attach(dev);
3420 if (netif_running(dev) && skge_up(dev))
3421 dev_close(dev);
3422 }
3423 }
3424 return 0;
3425 }
3426 #endif
3427
3428 static struct pci_driver skge_driver = {
3429 .name = DRV_NAME,
3430 .id_table = skge_id_table,
3431 .probe = skge_probe,
3432 .remove = __devexit_p(skge_remove),
3433 #ifdef CONFIG_PM
3434 .suspend = skge_suspend,
3435 .resume = skge_resume,
3436 #endif
3437 };
3438
3439 static int __init skge_init_module(void)
3440 {
3441 return pci_module_init(&skge_driver);
3442 }
3443
3444 static void __exit skge_cleanup_module(void)
3445 {
3446 pci_unregister_driver(&skge_driver);
3447 }
3448
3449 module_init(skge_init_module);
3450 module_exit(skge_cleanup_module);
Verdex Pro support