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[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / drivers / net / tulip / dmfe.c
blob74e9075d9c48edee4d5c908849025d8dfe2cb169
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65 */
66
67 #define DRV_NAME "dmfe"
68 #define DRV_VERSION "1.36.4"
69 #define DRV_RELDATE "2002-01-17"
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/ptrace.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/dma-mapping.h>
82 #include <linux/init.h>
83 #include <linux/netdevice.h>
84 #include <linux/etherdevice.h>
85 #include <linux/ethtool.h>
86 #include <linux/skbuff.h>
87 #include <linux/delay.h>
88 #include <linux/spinlock.h>
89 #include <linux/crc32.h>
90 #include <linux/bitops.h>
91
92 #include <asm/processor.h>
93 #include <asm/io.h>
94 #include <asm/dma.h>
95 #include <asm/uaccess.h>
96 #include <asm/irq.h>
97
98
99 /* Board/System/Debug information/definition ---------------- */
100 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
101 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
102 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
103 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
104
105 #define DM9102_IO_SIZE 0x80
106 #define DM9102A_IO_SIZE 0x100
107 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
108 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
109 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
110 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
111 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
112 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
113 #define TX_BUF_ALLOC 0x600
114 #define RX_ALLOC_SIZE 0x620
115 #define DM910X_RESET 1
116 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
117 #define CR6_DEFAULT 0x00080000 /* HD */
118 #define CR7_DEFAULT 0x180c1
119 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
120 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
121 #define MAX_PACKET_SIZE 1514
122 #define DMFE_MAX_MULTICAST 14
123 #define RX_COPY_SIZE 100
124 #define MAX_CHECK_PACKET 0x8000
125 #define DM9801_NOISE_FLOOR 8
126 #define DM9802_NOISE_FLOOR 5
127
128 #define DMFE_10MHF 0
129 #define DMFE_100MHF 1
130 #define DMFE_10MFD 4
131 #define DMFE_100MFD 5
132 #define DMFE_AUTO 8
133 #define DMFE_1M_HPNA 0x10
134
135 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
136 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
137 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
138 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
139 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
140 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
141
142 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
143 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
144 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
145
146 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
147
148 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
149
150
151 /* CR9 definition: SROM/MII */
152 #define CR9_SROM_READ 0x4800
153 #define CR9_SRCS 0x1
154 #define CR9_SRCLK 0x2
155 #define CR9_CRDOUT 0x8
156 #define SROM_DATA_0 0x0
157 #define SROM_DATA_1 0x4
158 #define PHY_DATA_1 0x20000
159 #define PHY_DATA_0 0x00000
160 #define MDCLKH 0x10000
161
162 #define PHY_POWER_DOWN 0x800
163
164 #define SROM_V41_CODE 0x14
165
166 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
167
168 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
169 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
170
171 /* Sten Check */
172 #define DEVICE net_device
173
174 /* Structure/enum declaration ------------------------------- */
175 struct tx_desc {
176 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
177 char *tx_buf_ptr; /* Data for us */
178 struct tx_desc *next_tx_desc;
179 } __attribute__(( aligned(32) ));
180
181 struct rx_desc {
182 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
183 struct sk_buff *rx_skb_ptr; /* Data for us */
184 struct rx_desc *next_rx_desc;
185 } __attribute__(( aligned(32) ));
186
187 struct dmfe_board_info {
188 u32 chip_id; /* Chip vendor/Device ID */
189 u32 chip_revision; /* Chip revision */
190 struct DEVICE *next_dev; /* next device */
191 struct pci_dev *pdev; /* PCI device */
192 spinlock_t lock;
193
194 long ioaddr; /* I/O base address */
195 u32 cr0_data;
196 u32 cr5_data;
197 u32 cr6_data;
198 u32 cr7_data;
199 u32 cr15_data;
200
201 /* pointer for memory physical address */
202 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
203 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
204 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
205 dma_addr_t first_tx_desc_dma;
206 dma_addr_t first_rx_desc_dma;
207
208 /* descriptor pointer */
209 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
210 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
211 unsigned char *desc_pool_ptr; /* descriptor pool memory */
212 struct tx_desc *first_tx_desc;
213 struct tx_desc *tx_insert_ptr;
214 struct tx_desc *tx_remove_ptr;
215 struct rx_desc *first_rx_desc;
216 struct rx_desc *rx_insert_ptr;
217 struct rx_desc *rx_ready_ptr; /* packet come pointer */
218 unsigned long tx_packet_cnt; /* transmitted packet count */
219 unsigned long tx_queue_cnt; /* wait to send packet count */
220 unsigned long rx_avail_cnt; /* available rx descriptor count */
221 unsigned long interval_rx_cnt; /* rx packet count a callback time */
222
223 u16 HPNA_command; /* For HPNA register 16 */
224 u16 HPNA_timer; /* For HPNA remote device check */
225 u16 dbug_cnt;
226 u16 NIC_capability; /* NIC media capability */
227 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
228
229 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
230 u8 chip_type; /* Keep DM9102A chip type */
231 u8 media_mode; /* user specify media mode */
232 u8 op_mode; /* real work media mode */
233 u8 phy_addr;
234 u8 link_failed; /* Ever link failed */
235 u8 wait_reset; /* Hardware failed, need to reset */
236 u8 dm910x_chk_mode; /* Operating mode check */
237 u8 first_in_callback; /* Flag to record state */
238 struct timer_list timer;
239
240 /* System defined statistic counter */
241 struct net_device_stats stats;
242
243 /* Driver defined statistic counter */
244 unsigned long tx_fifo_underrun;
245 unsigned long tx_loss_carrier;
246 unsigned long tx_no_carrier;
247 unsigned long tx_late_collision;
248 unsigned long tx_excessive_collision;
249 unsigned long tx_jabber_timeout;
250 unsigned long reset_count;
251 unsigned long reset_cr8;
252 unsigned long reset_fatal;
253 unsigned long reset_TXtimeout;
254
255 /* NIC SROM data */
256 unsigned char srom[128];
257 };
258
259 enum dmfe_offsets {
260 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
261 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
262 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
263 DCR15 = 0x78
264 };
265
266 enum dmfe_CR6_bits {
267 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
268 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
269 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
270 };
271
272 /* Global variable declaration ----------------------------- */
273 static int __devinitdata printed_version;
274 static char version[] __devinitdata =
275 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
276 DRV_VERSION " (" DRV_RELDATE ")\n";
277
278 static int dmfe_debug;
279 static unsigned char dmfe_media_mode = DMFE_AUTO;
280 static u32 dmfe_cr6_user_set;
281
282 /* For module input parameter */
283 static int debug;
284 static u32 cr6set;
285 static unsigned char mode = 8;
286 static u8 chkmode = 1;
287 static u8 HPNA_mode; /* Default: Low Power/High Speed */
288 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
289 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
290 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
291 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
292 4: TX pause packet */
293
294
295 /* function declaration ------------------------------------- */
296 static int dmfe_open(struct DEVICE *);
297 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
298 static int dmfe_stop(struct DEVICE *);
299 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
300 static void dmfe_set_filter_mode(struct DEVICE *);
301 static struct ethtool_ops netdev_ethtool_ops;
302 static u16 read_srom_word(long ,int);
303 static irqreturn_t dmfe_interrupt(int , void *, struct pt_regs *);
304 #ifdef CONFIG_NET_POLL_CONTROLLER
305 static void poll_dmfe (struct net_device *dev);
306 #endif
307 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
308 static void allocate_rx_buffer(struct dmfe_board_info *);
309 static void update_cr6(u32, unsigned long);
310 static void send_filter_frame(struct DEVICE * ,int);
311 static void dm9132_id_table(struct DEVICE * ,int);
312 static u16 phy_read(unsigned long, u8, u8, u32);
313 static void phy_write(unsigned long, u8, u8, u16, u32);
314 static void phy_write_1bit(unsigned long, u32);
315 static u16 phy_read_1bit(unsigned long);
316 static u8 dmfe_sense_speed(struct dmfe_board_info *);
317 static void dmfe_process_mode(struct dmfe_board_info *);
318 static void dmfe_timer(unsigned long);
319 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
320 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
321 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
322 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
323 static void dmfe_dynamic_reset(struct DEVICE *);
324 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
325 static void dmfe_init_dm910x(struct DEVICE *);
326 static void dmfe_parse_srom(struct dmfe_board_info *);
327 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
328 static void dmfe_program_DM9802(struct dmfe_board_info *);
329 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
330 static void dmfe_set_phyxcer(struct dmfe_board_info *);
331
332 /* DM910X network baord routine ---------------------------- */
333
334 /*
335 * Search DM910X board ,allocate space and register it
336 */
337
338 static int __devinit dmfe_init_one (struct pci_dev *pdev,
339 const struct pci_device_id *ent)
340 {
341 struct dmfe_board_info *db; /* board information structure */
342 struct net_device *dev;
343 u32 dev_rev, pci_pmr;
344 int i, err;
345
346 DMFE_DBUG(0, "dmfe_init_one()", 0);
347
348 if (!printed_version++)
349 printk(version);
350
351 /* Init network device */
352 dev = alloc_etherdev(sizeof(*db));
353 if (dev == NULL)
354 return -ENOMEM;
355 SET_MODULE_OWNER(dev);
356 SET_NETDEV_DEV(dev, &pdev->dev);
357
358 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
359 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
360 err = -ENODEV;
361 goto err_out_free;
362 }
363
364 /* Enable Master/IO access, Disable memory access */
365 err = pci_enable_device(pdev);
366 if (err)
367 goto err_out_free;
368
369 if (!pci_resource_start(pdev, 0)) {
370 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
371 err = -ENODEV;
372 goto err_out_disable;
373 }
374
375 /* Read Chip revision */
376 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
377
378 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
379 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
380 err = -ENODEV;
381 goto err_out_disable;
382 }
383
384 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
385
386 /* Set Latency Timer 80h */
387 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
388 Need a PCI quirk.. */
389
390 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
391 #endif
392
393 if (pci_request_regions(pdev, DRV_NAME)) {
394 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
395 err = -ENODEV;
396 goto err_out_disable;
397 }
398
399 /* Init system & device */
400 db = netdev_priv(dev);
401
402 /* Allocate Tx/Rx descriptor memory */
403 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
404 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
405
406 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
407 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
408 db->buf_pool_start = db->buf_pool_ptr;
409 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
410
411 db->chip_id = ent->driver_data;
412 db->ioaddr = pci_resource_start(pdev, 0);
413 db->chip_revision = dev_rev;
414
415 db->pdev = pdev;
416
417 dev->base_addr = db->ioaddr;
418 dev->irq = pdev->irq;
419 pci_set_drvdata(pdev, dev);
420 dev->open = &dmfe_open;
421 dev->hard_start_xmit = &dmfe_start_xmit;
422 dev->stop = &dmfe_stop;
423 dev->get_stats = &dmfe_get_stats;
424 dev->set_multicast_list = &dmfe_set_filter_mode;
425 #ifdef CONFIG_NET_POLL_CONTROLLER
426 dev->poll_controller = &poll_dmfe;
427 #endif
428 dev->ethtool_ops = &netdev_ethtool_ops;
429 spin_lock_init(&db->lock);
430
431 pci_read_config_dword(pdev, 0x50, &pci_pmr);
432 pci_pmr &= 0x70000;
433 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
434 db->chip_type = 1; /* DM9102A E3 */
435 else
436 db->chip_type = 0;
437
438 /* read 64 word srom data */
439 for (i = 0; i < 64; i++)
440 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
441
442 /* Set Node address */
443 for (i = 0; i < 6; i++)
444 dev->dev_addr[i] = db->srom[20 + i];
445
446 err = register_netdev (dev);
447 if (err)
448 goto err_out_res;
449
450 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
451 dev->name,
452 ent->driver_data >> 16,
453 pci_name(pdev));
454 for (i = 0; i < 6; i++)
455 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
456 printk(", irq %d.\n", dev->irq);
457
458 pci_set_master(pdev);
459
460 return 0;
461
462 err_out_res:
463 pci_release_regions(pdev);
464 err_out_disable:
465 pci_disable_device(pdev);
466 err_out_free:
467 pci_set_drvdata(pdev, NULL);
468 free_netdev(dev);
469
470 return err;
471 }
472
473
474 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
475 {
476 struct net_device *dev = pci_get_drvdata(pdev);
477 struct dmfe_board_info *db = netdev_priv(dev);
478
479 DMFE_DBUG(0, "dmfe_remove_one()", 0);
480
481 if (dev) {
482 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
483 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
484 db->desc_pool_dma_ptr);
485 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
486 db->buf_pool_ptr, db->buf_pool_dma_ptr);
487 unregister_netdev(dev);
488 pci_release_regions(pdev);
489 free_netdev(dev); /* free board information */
490 pci_set_drvdata(pdev, NULL);
491 }
492
493 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
494 }
495
496
497 /*
498 * Open the interface.
499 * The interface is opened whenever "ifconfig" actives it.
500 */
501
502 static int dmfe_open(struct DEVICE *dev)
503 {
504 int ret;
505 struct dmfe_board_info *db = netdev_priv(dev);
506
507 DMFE_DBUG(0, "dmfe_open", 0);
508
509 ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
510 if (ret)
511 return ret;
512
513 /* system variable init */
514 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
515 db->tx_packet_cnt = 0;
516 db->tx_queue_cnt = 0;
517 db->rx_avail_cnt = 0;
518 db->link_failed = 1;
519 db->wait_reset = 0;
520
521 db->first_in_callback = 0;
522 db->NIC_capability = 0xf; /* All capability*/
523 db->PHY_reg4 = 0x1e0;
524
525 /* CR6 operation mode decision */
526 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
527 (db->chip_revision >= 0x02000030) ) {
528 db->cr6_data |= DMFE_TXTH_256;
529 db->cr0_data = CR0_DEFAULT;
530 db->dm910x_chk_mode=4; /* Enter the normal mode */
531 } else {
532 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
533 db->cr0_data = 0;
534 db->dm910x_chk_mode = 1; /* Enter the check mode */
535 }
536
537 /* Initilize DM910X board */
538 dmfe_init_dm910x(dev);
539
540 /* Active System Interface */
541 netif_wake_queue(dev);
542
543 /* set and active a timer process */
544 init_timer(&db->timer);
545 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
546 db->timer.data = (unsigned long)dev;
547 db->timer.function = &dmfe_timer;
548 add_timer(&db->timer);
549
550 return 0;
551 }
552
553
554 /* Initilize DM910X board
555 * Reset DM910X board
556 * Initilize TX/Rx descriptor chain structure
557 * Send the set-up frame
558 * Enable Tx/Rx machine
559 */
560
561 static void dmfe_init_dm910x(struct DEVICE *dev)
562 {
563 struct dmfe_board_info *db = netdev_priv(dev);
564 unsigned long ioaddr = db->ioaddr;
565
566 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
567
568 /* Reset DM910x MAC controller */
569 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
570 udelay(100);
571 outl(db->cr0_data, ioaddr + DCR0);
572 udelay(5);
573
574 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
575 db->phy_addr = 1;
576
577 /* Parser SROM and media mode */
578 dmfe_parse_srom(db);
579 db->media_mode = dmfe_media_mode;
580
581 /* RESET Phyxcer Chip by GPR port bit 7 */
582 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
583 if (db->chip_id == PCI_DM9009_ID) {
584 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
585 mdelay(300); /* Delay 300 ms */
586 }
587 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
588
589 /* Process Phyxcer Media Mode */
590 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
591 dmfe_set_phyxcer(db);
592
593 /* Media Mode Process */
594 if ( !(db->media_mode & DMFE_AUTO) )
595 db->op_mode = db->media_mode; /* Force Mode */
596
597 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
598 dmfe_descriptor_init(db, ioaddr);
599
600 /* Init CR6 to program DM910x operation */
601 update_cr6(db->cr6_data, ioaddr);
602
603 /* Send setup frame */
604 if (db->chip_id == PCI_DM9132_ID)
605 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
606 else
607 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
608
609 /* Init CR7, interrupt active bit */
610 db->cr7_data = CR7_DEFAULT;
611 outl(db->cr7_data, ioaddr + DCR7);
612
613 /* Init CR15, Tx jabber and Rx watchdog timer */
614 outl(db->cr15_data, ioaddr + DCR15);
615
616 /* Enable DM910X Tx/Rx function */
617 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
618 update_cr6(db->cr6_data, ioaddr);
619 }
620
621
622 /*
623 * Hardware start transmission.
624 * Send a packet to media from the upper layer.
625 */
626
627 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
628 {
629 struct dmfe_board_info *db = netdev_priv(dev);
630 struct tx_desc *txptr;
631 unsigned long flags;
632
633 DMFE_DBUG(0, "dmfe_start_xmit", 0);
634
635 /* Resource flag check */
636 netif_stop_queue(dev);
637
638 /* Too large packet check */
639 if (skb->len > MAX_PACKET_SIZE) {
640 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
641 dev_kfree_skb(skb);
642 return 0;
643 }
644
645 spin_lock_irqsave(&db->lock, flags);
646
647 /* No Tx resource check, it never happen nromally */
648 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
649 spin_unlock_irqrestore(&db->lock, flags);
650 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
651 return 1;
652 }
653
654 /* Disable NIC interrupt */
655 outl(0, dev->base_addr + DCR7);
656
657 /* transmit this packet */
658 txptr = db->tx_insert_ptr;
659 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
660 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
661
662 /* Point to next transmit free descriptor */
663 db->tx_insert_ptr = txptr->next_tx_desc;
664
665 /* Transmit Packet Process */
666 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
667 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
668 db->tx_packet_cnt++; /* Ready to send */
669 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
670 dev->trans_start = jiffies; /* saved time stamp */
671 } else {
672 db->tx_queue_cnt++; /* queue TX packet */
673 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
674 }
675
676 /* Tx resource check */
677 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
678 netif_wake_queue(dev);
679
680 /* Restore CR7 to enable interrupt */
681 spin_unlock_irqrestore(&db->lock, flags);
682 outl(db->cr7_data, dev->base_addr + DCR7);
683
684 /* free this SKB */
685 dev_kfree_skb(skb);
686
687 return 0;
688 }
689
690
691 /*
692 * Stop the interface.
693 * The interface is stopped when it is brought.
694 */
695
696 static int dmfe_stop(struct DEVICE *dev)
697 {
698 struct dmfe_board_info *db = netdev_priv(dev);
699 unsigned long ioaddr = dev->base_addr;
700
701 DMFE_DBUG(0, "dmfe_stop", 0);
702
703 /* disable system */
704 netif_stop_queue(dev);
705
706 /* deleted timer */
707 del_timer_sync(&db->timer);
708
709 /* Reset & stop DM910X board */
710 outl(DM910X_RESET, ioaddr + DCR0);
711 udelay(5);
712 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
713
714 /* free interrupt */
715 free_irq(dev->irq, dev);
716
717 /* free allocated rx buffer */
718 dmfe_free_rxbuffer(db);
719
720 #if 0
721 /* show statistic counter */
722 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
723 db->tx_fifo_underrun, db->tx_excessive_collision,
724 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
725 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
726 db->reset_fatal, db->reset_TXtimeout);
727 #endif
728
729 return 0;
730 }
731
732
733 /*
734 * DM9102 insterrupt handler
735 * receive the packet to upper layer, free the transmitted packet
736 */
737
738 static irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
739 {
740 struct DEVICE *dev = dev_id;
741 struct dmfe_board_info *db = netdev_priv(dev);
742 unsigned long ioaddr = dev->base_addr;
743 unsigned long flags;
744
745 DMFE_DBUG(0, "dmfe_interrupt()", 0);
746
747 spin_lock_irqsave(&db->lock, flags);
748
749 /* Got DM910X status */
750 db->cr5_data = inl(ioaddr + DCR5);
751 outl(db->cr5_data, ioaddr + DCR5);
752 if ( !(db->cr5_data & 0xc1) ) {
753 spin_unlock_irqrestore(&db->lock, flags);
754 return IRQ_HANDLED;
755 }
756
757 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
758 outl(0, ioaddr + DCR7);
759
760 /* Check system status */
761 if (db->cr5_data & 0x2000) {
762 /* system bus error happen */
763 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
764 db->reset_fatal++;
765 db->wait_reset = 1; /* Need to RESET */
766 spin_unlock_irqrestore(&db->lock, flags);
767 return IRQ_HANDLED;
768 }
769
770 /* Received the coming packet */
771 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
772 dmfe_rx_packet(dev, db);
773
774 /* reallocate rx descriptor buffer */
775 if (db->rx_avail_cnt<RX_DESC_CNT)
776 allocate_rx_buffer(db);
777
778 /* Free the transmitted descriptor */
779 if ( db->cr5_data & 0x01)
780 dmfe_free_tx_pkt(dev, db);
781
782 /* Mode Check */
783 if (db->dm910x_chk_mode & 0x2) {
784 db->dm910x_chk_mode = 0x4;
785 db->cr6_data |= 0x100;
786 update_cr6(db->cr6_data, db->ioaddr);
787 }
788
789 /* Restore CR7 to enable interrupt mask */
790 outl(db->cr7_data, ioaddr + DCR7);
791
792 spin_unlock_irqrestore(&db->lock, flags);
793 return IRQ_HANDLED;
794 }
795
796
797 #ifdef CONFIG_NET_POLL_CONTROLLER
798 /*
799 * Polling 'interrupt' - used by things like netconsole to send skbs
800 * without having to re-enable interrupts. It's not called while
801 * the interrupt routine is executing.
802 */
803
804 static void poll_dmfe (struct net_device *dev)
805 {
806 /* disable_irq here is not very nice, but with the lockless
807 interrupt handler we have no other choice. */
808 disable_irq(dev->irq);
809 dmfe_interrupt (dev->irq, dev, NULL);
810 enable_irq(dev->irq);
811 }
812 #endif
813
814 /*
815 * Free TX resource after TX complete
816 */
817
818 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
819 {
820 struct tx_desc *txptr;
821 unsigned long ioaddr = dev->base_addr;
822 u32 tdes0;
823
824 txptr = db->tx_remove_ptr;
825 while(db->tx_packet_cnt) {
826 tdes0 = le32_to_cpu(txptr->tdes0);
827 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
828 if (tdes0 & 0x80000000)
829 break;
830
831 /* A packet sent completed */
832 db->tx_packet_cnt--;
833 db->stats.tx_packets++;
834
835 /* Transmit statistic counter */
836 if ( tdes0 != 0x7fffffff ) {
837 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
838 db->stats.collisions += (tdes0 >> 3) & 0xf;
839 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
840 if (tdes0 & TDES0_ERR_MASK) {
841 db->stats.tx_errors++;
842
843 if (tdes0 & 0x0002) { /* UnderRun */
844 db->tx_fifo_underrun++;
845 if ( !(db->cr6_data & CR6_SFT) ) {
846 db->cr6_data = db->cr6_data | CR6_SFT;
847 update_cr6(db->cr6_data, db->ioaddr);
848 }
849 }
850 if (tdes0 & 0x0100)
851 db->tx_excessive_collision++;
852 if (tdes0 & 0x0200)
853 db->tx_late_collision++;
854 if (tdes0 & 0x0400)
855 db->tx_no_carrier++;
856 if (tdes0 & 0x0800)
857 db->tx_loss_carrier++;
858 if (tdes0 & 0x4000)
859 db->tx_jabber_timeout++;
860 }
861 }
862
863 txptr = txptr->next_tx_desc;
864 }/* End of while */
865
866 /* Update TX remove pointer to next */
867 db->tx_remove_ptr = txptr;
868
869 /* Send the Tx packet in queue */
870 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
871 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
872 db->tx_packet_cnt++; /* Ready to send */
873 db->tx_queue_cnt--;
874 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
875 dev->trans_start = jiffies; /* saved time stamp */
876 }
877
878 /* Resource available check */
879 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
880 netif_wake_queue(dev); /* Active upper layer, send again */
881 }
882
883
884 /*
885 * Calculate the CRC valude of the Rx packet
886 * flag = 1 : return the reverse CRC (for the received packet CRC)
887 * 0 : return the normal CRC (for Hash Table index)
888 */
889
890 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
891 {
892 u32 crc = crc32(~0, Data, Len);
893 if (flag) crc = ~crc;
894 return crc;
895 }
896
897
898 /*
899 * Receive the come packet and pass to upper layer
900 */
901
902 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
903 {
904 struct rx_desc *rxptr;
905 struct sk_buff *skb;
906 int rxlen;
907 u32 rdes0;
908
909 rxptr = db->rx_ready_ptr;
910
911 while(db->rx_avail_cnt) {
912 rdes0 = le32_to_cpu(rxptr->rdes0);
913 if (rdes0 & 0x80000000) /* packet owner check */
914 break;
915
916 db->rx_avail_cnt--;
917 db->interval_rx_cnt++;
918
919 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
920 if ( (rdes0 & 0x300) != 0x300) {
921 /* A packet without First/Last flag */
922 /* reuse this SKB */
923 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
924 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
925 } else {
926 /* A packet with First/Last flag */
927 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
928
929 /* error summary bit check */
930 if (rdes0 & 0x8000) {
931 /* This is a error packet */
932 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
933 db->stats.rx_errors++;
934 if (rdes0 & 1)
935 db->stats.rx_fifo_errors++;
936 if (rdes0 & 2)
937 db->stats.rx_crc_errors++;
938 if (rdes0 & 0x80)
939 db->stats.rx_length_errors++;
940 }
941
942 if ( !(rdes0 & 0x8000) ||
943 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
944 skb = rxptr->rx_skb_ptr;
945
946 /* Received Packet CRC check need or not */
947 if ( (db->dm910x_chk_mode & 1) &&
948 (cal_CRC(skb->data, rxlen, 1) !=
949 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
950 /* Found a error received packet */
951 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
952 db->dm910x_chk_mode = 3;
953 } else {
954 /* Good packet, send to upper layer */
955 /* Shorst packet used new SKB */
956 if ( (rxlen < RX_COPY_SIZE) &&
957 ( (skb = dev_alloc_skb(rxlen + 2) )
958 != NULL) ) {
959 /* size less than COPY_SIZE, allocate a rxlen SKB */
960 skb->dev = dev;
961 skb_reserve(skb, 2); /* 16byte align */
962 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->data, rxlen);
963 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
964 } else {
965 skb->dev = dev;
966 skb_put(skb, rxlen);
967 }
968 skb->protocol = eth_type_trans(skb, dev);
969 netif_rx(skb);
970 dev->last_rx = jiffies;
971 db->stats.rx_packets++;
972 db->stats.rx_bytes += rxlen;
973 }
974 } else {
975 /* Reuse SKB buffer when the packet is error */
976 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
977 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
978 }
979 }
980
981 rxptr = rxptr->next_rx_desc;
982 }
983
984 db->rx_ready_ptr = rxptr;
985 }
986
987
988 /*
989 * Get statistics from driver.
990 */
991
992 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
993 {
994 struct dmfe_board_info *db = netdev_priv(dev);
995
996 DMFE_DBUG(0, "dmfe_get_stats", 0);
997 return &db->stats;
998 }
999
1000
1001 /*
1002 * Set DM910X multicast address
1003 */
1004
1005 static void dmfe_set_filter_mode(struct DEVICE * dev)
1006 {
1007 struct dmfe_board_info *db = netdev_priv(dev);
1008 unsigned long flags;
1009
1010 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1011 spin_lock_irqsave(&db->lock, flags);
1012
1013 if (dev->flags & IFF_PROMISC) {
1014 DMFE_DBUG(0, "Enable PROM Mode", 0);
1015 db->cr6_data |= CR6_PM | CR6_PBF;
1016 update_cr6(db->cr6_data, db->ioaddr);
1017 spin_unlock_irqrestore(&db->lock, flags);
1018 return;
1019 }
1020
1021 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1022 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1023 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1024 db->cr6_data |= CR6_PAM;
1025 spin_unlock_irqrestore(&db->lock, flags);
1026 return;
1027 }
1028
1029 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1030 if (db->chip_id == PCI_DM9132_ID)
1031 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1032 else
1033 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1034 spin_unlock_irqrestore(&db->lock, flags);
1035 }
1036
1037 static void netdev_get_drvinfo(struct net_device *dev,
1038 struct ethtool_drvinfo *info)
1039 {
1040 struct dmfe_board_info *np = netdev_priv(dev);
1041
1042 strcpy(info->driver, DRV_NAME);
1043 strcpy(info->version, DRV_VERSION);
1044 if (np->pdev)
1045 strcpy(info->bus_info, pci_name(np->pdev));
1046 else
1047 sprintf(info->bus_info, "EISA 0x%lx %d",
1048 dev->base_addr, dev->irq);
1049 }
1050
1051 static struct ethtool_ops netdev_ethtool_ops = {
1052 .get_drvinfo = netdev_get_drvinfo,
1053 };
1054
1055 /*
1056 * A periodic timer routine
1057 * Dynamic media sense, allocate Rx buffer...
1058 */
1059
1060 static void dmfe_timer(unsigned long data)
1061 {
1062 u32 tmp_cr8;
1063 unsigned char tmp_cr12;
1064 struct DEVICE *dev = (struct DEVICE *) data;
1065 struct dmfe_board_info *db = netdev_priv(dev);
1066 unsigned long flags;
1067
1068 DMFE_DBUG(0, "dmfe_timer()", 0);
1069 spin_lock_irqsave(&db->lock, flags);
1070
1071 /* Media mode process when Link OK before enter this route */
1072 if (db->first_in_callback == 0) {
1073 db->first_in_callback = 1;
1074 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1075 db->cr6_data &= ~0x40000;
1076 update_cr6(db->cr6_data, db->ioaddr);
1077 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1078 db->cr6_data |= 0x40000;
1079 update_cr6(db->cr6_data, db->ioaddr);
1080 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1081 add_timer(&db->timer);
1082 spin_unlock_irqrestore(&db->lock, flags);
1083 return;
1084 }
1085 }
1086
1087
1088 /* Operating Mode Check */
1089 if ( (db->dm910x_chk_mode & 0x1) &&
1090 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1091 db->dm910x_chk_mode = 0x4;
1092
1093 /* Dynamic reset DM910X : system error or transmit time-out */
1094 tmp_cr8 = inl(db->ioaddr + DCR8);
1095 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1096 db->reset_cr8++;
1097 db->wait_reset = 1;
1098 }
1099 db->interval_rx_cnt = 0;
1100
1101 /* TX polling kick monitor */
1102 if ( db->tx_packet_cnt &&
1103 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1104 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1105
1106 /* TX Timeout */
1107 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1108 db->reset_TXtimeout++;
1109 db->wait_reset = 1;
1110 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1111 dev->name);
1112 }
1113 }
1114
1115 if (db->wait_reset) {
1116 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1117 db->reset_count++;
1118 dmfe_dynamic_reset(dev);
1119 db->first_in_callback = 0;
1120 db->timer.expires = DMFE_TIMER_WUT;
1121 add_timer(&db->timer);
1122 spin_unlock_irqrestore(&db->lock, flags);
1123 return;
1124 }
1125
1126 /* Link status check, Dynamic media type change */
1127 if (db->chip_id == PCI_DM9132_ID)
1128 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1129 else
1130 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1131
1132 if ( ((db->chip_id == PCI_DM9102_ID) &&
1133 (db->chip_revision == 0x02000030)) ||
1134 ((db->chip_id == PCI_DM9132_ID) &&
1135 (db->chip_revision == 0x02000010)) ) {
1136 /* DM9102A Chip */
1137 if (tmp_cr12 & 2)
1138 tmp_cr12 = 0x0; /* Link failed */
1139 else
1140 tmp_cr12 = 0x3; /* Link OK */
1141 }
1142
1143 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1144 /* Link Failed */
1145 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1146 db->link_failed = 1;
1147
1148 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1149 /* AUTO or force 1M Homerun/Longrun don't need */
1150 if ( !(db->media_mode & 0x38) )
1151 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1152
1153 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1154 if (db->media_mode & DMFE_AUTO) {
1155 /* 10/100M link failed, used 1M Home-Net */
1156 db->cr6_data|=0x00040000; /* bit18=1, MII */
1157 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1158 update_cr6(db->cr6_data, db->ioaddr);
1159 }
1160 } else
1161 if ((tmp_cr12 & 0x3) && db->link_failed) {
1162 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1163 db->link_failed = 0;
1164
1165 /* Auto Sense Speed */
1166 if ( (db->media_mode & DMFE_AUTO) &&
1167 dmfe_sense_speed(db) )
1168 db->link_failed = 1;
1169 dmfe_process_mode(db);
1170 /* SHOW_MEDIA_TYPE(db->op_mode); */
1171 }
1172
1173 /* HPNA remote command check */
1174 if (db->HPNA_command & 0xf00) {
1175 db->HPNA_timer--;
1176 if (!db->HPNA_timer)
1177 dmfe_HPNA_remote_cmd_chk(db);
1178 }
1179
1180 /* Timer active again */
1181 db->timer.expires = DMFE_TIMER_WUT;
1182 add_timer(&db->timer);
1183 spin_unlock_irqrestore(&db->lock, flags);
1184 }
1185
1186
1187 /*
1188 * Dynamic reset the DM910X board
1189 * Stop DM910X board
1190 * Free Tx/Rx allocated memory
1191 * Reset DM910X board
1192 * Re-initilize DM910X board
1193 */
1194
1195 static void dmfe_dynamic_reset(struct DEVICE *dev)
1196 {
1197 struct dmfe_board_info *db = netdev_priv(dev);
1198
1199 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1200
1201 /* Sopt MAC controller */
1202 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1203 update_cr6(db->cr6_data, dev->base_addr);
1204 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1205 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1206
1207 /* Disable upper layer interface */
1208 netif_stop_queue(dev);
1209
1210 /* Free Rx Allocate buffer */
1211 dmfe_free_rxbuffer(db);
1212
1213 /* system variable init */
1214 db->tx_packet_cnt = 0;
1215 db->tx_queue_cnt = 0;
1216 db->rx_avail_cnt = 0;
1217 db->link_failed = 1;
1218 db->wait_reset = 0;
1219
1220 /* Re-initilize DM910X board */
1221 dmfe_init_dm910x(dev);
1222
1223 /* Restart upper layer interface */
1224 netif_wake_queue(dev);
1225 }
1226
1227
1228 /*
1229 * free all allocated rx buffer
1230 */
1231
1232 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1233 {
1234 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1235
1236 /* free allocated rx buffer */
1237 while (db->rx_avail_cnt) {
1238 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1239 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1240 db->rx_avail_cnt--;
1241 }
1242 }
1243
1244
1245 /*
1246 * Reuse the SK buffer
1247 */
1248
1249 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1250 {
1251 struct rx_desc *rxptr = db->rx_insert_ptr;
1252
1253 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1254 rxptr->rx_skb_ptr = skb;
1255 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1256 wmb();
1257 rxptr->rdes0 = cpu_to_le32(0x80000000);
1258 db->rx_avail_cnt++;
1259 db->rx_insert_ptr = rxptr->next_rx_desc;
1260 } else
1261 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1262 }
1263
1264
1265 /*
1266 * Initialize transmit/Receive descriptor
1267 * Using Chain structure, and allocate Tx/Rx buffer
1268 */
1269
1270 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1271 {
1272 struct tx_desc *tmp_tx;
1273 struct rx_desc *tmp_rx;
1274 unsigned char *tmp_buf;
1275 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1276 dma_addr_t tmp_buf_dma;
1277 int i;
1278
1279 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1280
1281 /* tx descriptor start pointer */
1282 db->tx_insert_ptr = db->first_tx_desc;
1283 db->tx_remove_ptr = db->first_tx_desc;
1284 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1285
1286 /* rx descriptor start pointer */
1287 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1288 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1289 db->rx_insert_ptr = db->first_rx_desc;
1290 db->rx_ready_ptr = db->first_rx_desc;
1291 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1292
1293 /* Init Transmit chain */
1294 tmp_buf = db->buf_pool_start;
1295 tmp_buf_dma = db->buf_pool_dma_start;
1296 tmp_tx_dma = db->first_tx_desc_dma;
1297 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1298 tmp_tx->tx_buf_ptr = tmp_buf;
1299 tmp_tx->tdes0 = cpu_to_le32(0);
1300 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1301 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1302 tmp_tx_dma += sizeof(struct tx_desc);
1303 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1304 tmp_tx->next_tx_desc = tmp_tx + 1;
1305 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1306 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1307 }
1308 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1309 tmp_tx->next_tx_desc = db->first_tx_desc;
1310
1311 /* Init Receive descriptor chain */
1312 tmp_rx_dma=db->first_rx_desc_dma;
1313 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1314 tmp_rx->rdes0 = cpu_to_le32(0);
1315 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1316 tmp_rx_dma += sizeof(struct rx_desc);
1317 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1318 tmp_rx->next_rx_desc = tmp_rx + 1;
1319 }
1320 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1321 tmp_rx->next_rx_desc = db->first_rx_desc;
1322
1323 /* pre-allocate Rx buffer */
1324 allocate_rx_buffer(db);
1325 }
1326
1327
1328 /*
1329 * Update CR6 value
1330 * Firstly stop DM910X , then written value and start
1331 */
1332
1333 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1334 {
1335 u32 cr6_tmp;
1336
1337 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1338 outl(cr6_tmp, ioaddr + DCR6);
1339 udelay(5);
1340 outl(cr6_data, ioaddr + DCR6);
1341 udelay(5);
1342 }
1343
1344
1345 /*
1346 * Send a setup frame for DM9132
1347 * This setup frame initilize DM910X address filter mode
1348 */
1349
1350 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1351 {
1352 struct dev_mc_list *mcptr;
1353 u16 * addrptr;
1354 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1355 u32 hash_val;
1356 u16 i, hash_table[4];
1357
1358 DMFE_DBUG(0, "dm9132_id_table()", 0);
1359
1360 /* Node address */
1361 addrptr = (u16 *) dev->dev_addr;
1362 outw(addrptr[0], ioaddr);
1363 ioaddr += 4;
1364 outw(addrptr[1], ioaddr);
1365 ioaddr += 4;
1366 outw(addrptr[2], ioaddr);
1367 ioaddr += 4;
1368
1369 /* Clear Hash Table */
1370 for (i = 0; i < 4; i++)
1371 hash_table[i] = 0x0;
1372
1373 /* broadcast address */
1374 hash_table[3] = 0x8000;
1375
1376 /* the multicast address in Hash Table : 64 bits */
1377 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1378 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1379 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1380 }
1381
1382 /* Write the hash table to MAC MD table */
1383 for (i = 0; i < 4; i++, ioaddr += 4)
1384 outw(hash_table[i], ioaddr);
1385 }
1386
1387
1388 /*
1389 * Send a setup frame for DM9102/DM9102A
1390 * This setup frame initilize DM910X address filter mode
1391 */
1392
1393 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1394 {
1395 struct dmfe_board_info *db = netdev_priv(dev);
1396 struct dev_mc_list *mcptr;
1397 struct tx_desc *txptr;
1398 u16 * addrptr;
1399 u32 * suptr;
1400 int i;
1401
1402 DMFE_DBUG(0, "send_filter_frame()", 0);
1403
1404 txptr = db->tx_insert_ptr;
1405 suptr = (u32 *) txptr->tx_buf_ptr;
1406
1407 /* Node address */
1408 addrptr = (u16 *) dev->dev_addr;
1409 *suptr++ = addrptr[0];
1410 *suptr++ = addrptr[1];
1411 *suptr++ = addrptr[2];
1412
1413 /* broadcast address */
1414 *suptr++ = 0xffff;
1415 *suptr++ = 0xffff;
1416 *suptr++ = 0xffff;
1417
1418 /* fit the multicast address */
1419 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1420 addrptr = (u16 *) mcptr->dmi_addr;
1421 *suptr++ = addrptr[0];
1422 *suptr++ = addrptr[1];
1423 *suptr++ = addrptr[2];
1424 }
1425
1426 for (; i<14; i++) {
1427 *suptr++ = 0xffff;
1428 *suptr++ = 0xffff;
1429 *suptr++ = 0xffff;
1430 }
1431
1432 /* prepare the setup frame */
1433 db->tx_insert_ptr = txptr->next_tx_desc;
1434 txptr->tdes1 = cpu_to_le32(0x890000c0);
1435
1436 /* Resource Check and Send the setup packet */
1437 if (!db->tx_packet_cnt) {
1438 /* Resource Empty */
1439 db->tx_packet_cnt++;
1440 txptr->tdes0 = cpu_to_le32(0x80000000);
1441 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1442 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1443 update_cr6(db->cr6_data, dev->base_addr);
1444 dev->trans_start = jiffies;
1445 } else
1446 db->tx_queue_cnt++; /* Put in TX queue */
1447 }
1448
1449
1450 /*
1451 * Allocate rx buffer,
1452 * As possible as allocate maxiumn Rx buffer
1453 */
1454
1455 static void allocate_rx_buffer(struct dmfe_board_info *db)
1456 {
1457 struct rx_desc *rxptr;
1458 struct sk_buff *skb;
1459
1460 rxptr = db->rx_insert_ptr;
1461
1462 while(db->rx_avail_cnt < RX_DESC_CNT) {
1463 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1464 break;
1465 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1466 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1467 wmb();
1468 rxptr->rdes0 = cpu_to_le32(0x80000000);
1469 rxptr = rxptr->next_rx_desc;
1470 db->rx_avail_cnt++;
1471 }
1472
1473 db->rx_insert_ptr = rxptr;
1474 }
1475
1476
1477 /*
1478 * Read one word data from the serial ROM
1479 */
1480
1481 static u16 read_srom_word(long ioaddr, int offset)
1482 {
1483 int i;
1484 u16 srom_data = 0;
1485 long cr9_ioaddr = ioaddr + DCR9;
1486
1487 outl(CR9_SROM_READ, cr9_ioaddr);
1488 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1489
1490 /* Send the Read Command 110b */
1491 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1492 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1493 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1494
1495 /* Send the offset */
1496 for (i = 5; i >= 0; i--) {
1497 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1498 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1499 }
1500
1501 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1502
1503 for (i = 16; i > 0; i--) {
1504 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1505 udelay(5);
1506 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1507 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1508 udelay(5);
1509 }
1510
1511 outl(CR9_SROM_READ, cr9_ioaddr);
1512 return srom_data;
1513 }
1514
1515
1516 /*
1517 * Auto sense the media mode
1518 */
1519
1520 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1521 {
1522 u8 ErrFlag = 0;
1523 u16 phy_mode;
1524
1525 /* CR6 bit18=0, select 10/100M */
1526 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1527
1528 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1529 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1530
1531 if ( (phy_mode & 0x24) == 0x24 ) {
1532 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1533 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1534 else /* DM9102/DM9102A */
1535 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1536 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1537 switch (phy_mode) {
1538 case 0x1000: db->op_mode = DMFE_10MHF; break;
1539 case 0x2000: db->op_mode = DMFE_10MFD; break;
1540 case 0x4000: db->op_mode = DMFE_100MHF; break;
1541 case 0x8000: db->op_mode = DMFE_100MFD; break;
1542 default: db->op_mode = DMFE_10MHF;
1543 ErrFlag = 1;
1544 break;
1545 }
1546 } else {
1547 db->op_mode = DMFE_10MHF;
1548 DMFE_DBUG(0, "Link Failed :", phy_mode);
1549 ErrFlag = 1;
1550 }
1551
1552 return ErrFlag;
1553 }
1554
1555
1556 /*
1557 * Set 10/100 phyxcer capability
1558 * AUTO mode : phyxcer register4 is NIC capability
1559 * Force mode: phyxcer register4 is the force media
1560 */
1561
1562 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1563 {
1564 u16 phy_reg;
1565
1566 /* Select 10/100M phyxcer */
1567 db->cr6_data &= ~0x40000;
1568 update_cr6(db->cr6_data, db->ioaddr);
1569
1570 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1571 if (db->chip_id == PCI_DM9009_ID) {
1572 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1573 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1574 }
1575
1576 /* Phyxcer capability setting */
1577 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1578
1579 if (db->media_mode & DMFE_AUTO) {
1580 /* AUTO Mode */
1581 phy_reg |= db->PHY_reg4;
1582 } else {
1583 /* Force Mode */
1584 switch(db->media_mode) {
1585 case DMFE_10MHF: phy_reg |= 0x20; break;
1586 case DMFE_10MFD: phy_reg |= 0x40; break;
1587 case DMFE_100MHF: phy_reg |= 0x80; break;
1588 case DMFE_100MFD: phy_reg |= 0x100; break;
1589 }
1590 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1591 }
1592
1593 /* Write new capability to Phyxcer Reg4 */
1594 if ( !(phy_reg & 0x01e0)) {
1595 phy_reg|=db->PHY_reg4;
1596 db->media_mode|=DMFE_AUTO;
1597 }
1598 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1599
1600 /* Restart Auto-Negotiation */
1601 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1602 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1603 if ( !db->chip_type )
1604 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1605 }
1606
1607
1608 /*
1609 * Process op-mode
1610 * AUTO mode : PHY controller in Auto-negotiation Mode
1611 * Force mode: PHY controller in force mode with HUB
1612 * N-way force capability with SWITCH
1613 */
1614
1615 static void dmfe_process_mode(struct dmfe_board_info *db)
1616 {
1617 u16 phy_reg;
1618
1619 /* Full Duplex Mode Check */
1620 if (db->op_mode & 0x4)
1621 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1622 else
1623 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1624
1625 /* Transciver Selection */
1626 if (db->op_mode & 0x10) /* 1M HomePNA */
1627 db->cr6_data |= 0x40000;/* External MII select */
1628 else
1629 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1630
1631 update_cr6(db->cr6_data, db->ioaddr);
1632
1633 /* 10/100M phyxcer force mode need */
1634 if ( !(db->media_mode & 0x18)) {
1635 /* Forece Mode */
1636 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1637 if ( !(phy_reg & 0x1) ) {
1638 /* parter without N-Way capability */
1639 phy_reg = 0x0;
1640 switch(db->op_mode) {
1641 case DMFE_10MHF: phy_reg = 0x0; break;
1642 case DMFE_10MFD: phy_reg = 0x100; break;
1643 case DMFE_100MHF: phy_reg = 0x2000; break;
1644 case DMFE_100MFD: phy_reg = 0x2100; break;
1645 }
1646 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1647 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1648 mdelay(20);
1649 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1650 }
1651 }
1652 }
1653
1654
1655 /*
1656 * Write a word to Phy register
1657 */
1658
1659 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1660 {
1661 u16 i;
1662 unsigned long ioaddr;
1663
1664 if (chip_id == PCI_DM9132_ID) {
1665 ioaddr = iobase + 0x80 + offset * 4;
1666 outw(phy_data, ioaddr);
1667 } else {
1668 /* DM9102/DM9102A Chip */
1669 ioaddr = iobase + DCR9;
1670
1671 /* Send 33 synchronization clock to Phy controller */
1672 for (i = 0; i < 35; i++)
1673 phy_write_1bit(ioaddr, PHY_DATA_1);
1674
1675 /* Send start command(01) to Phy */
1676 phy_write_1bit(ioaddr, PHY_DATA_0);
1677 phy_write_1bit(ioaddr, PHY_DATA_1);
1678
1679 /* Send write command(01) to Phy */
1680 phy_write_1bit(ioaddr, PHY_DATA_0);
1681 phy_write_1bit(ioaddr, PHY_DATA_1);
1682
1683 /* Send Phy address */
1684 for (i = 0x10; i > 0; i = i >> 1)
1685 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1686
1687 /* Send register address */
1688 for (i = 0x10; i > 0; i = i >> 1)
1689 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1690
1691 /* written trasnition */
1692 phy_write_1bit(ioaddr, PHY_DATA_1);
1693 phy_write_1bit(ioaddr, PHY_DATA_0);
1694
1695 /* Write a word data to PHY controller */
1696 for ( i = 0x8000; i > 0; i >>= 1)
1697 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1698 }
1699 }
1700
1701
1702 /*
1703 * Read a word data from phy register
1704 */
1705
1706 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1707 {
1708 int i;
1709 u16 phy_data;
1710 unsigned long ioaddr;
1711
1712 if (chip_id == PCI_DM9132_ID) {
1713 /* DM9132 Chip */
1714 ioaddr = iobase + 0x80 + offset * 4;
1715 phy_data = inw(ioaddr);
1716 } else {
1717 /* DM9102/DM9102A Chip */
1718 ioaddr = iobase + DCR9;
1719
1720 /* Send 33 synchronization clock to Phy controller */
1721 for (i = 0; i < 35; i++)
1722 phy_write_1bit(ioaddr, PHY_DATA_1);
1723
1724 /* Send start command(01) to Phy */
1725 phy_write_1bit(ioaddr, PHY_DATA_0);
1726 phy_write_1bit(ioaddr, PHY_DATA_1);
1727
1728 /* Send read command(10) to Phy */
1729 phy_write_1bit(ioaddr, PHY_DATA_1);
1730 phy_write_1bit(ioaddr, PHY_DATA_0);
1731
1732 /* Send Phy address */
1733 for (i = 0x10; i > 0; i = i >> 1)
1734 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1735
1736 /* Send register address */
1737 for (i = 0x10; i > 0; i = i >> 1)
1738 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1739
1740 /* Skip transition state */
1741 phy_read_1bit(ioaddr);
1742
1743 /* read 16bit data */
1744 for (phy_data = 0, i = 0; i < 16; i++) {
1745 phy_data <<= 1;
1746 phy_data |= phy_read_1bit(ioaddr);
1747 }
1748 }
1749
1750 return phy_data;
1751 }
1752
1753
1754 /*
1755 * Write one bit data to Phy Controller
1756 */
1757
1758 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1759 {
1760 outl(phy_data, ioaddr); /* MII Clock Low */
1761 udelay(1);
1762 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1763 udelay(1);
1764 outl(phy_data, ioaddr); /* MII Clock Low */
1765 udelay(1);
1766 }
1767
1768
1769 /*
1770 * Read one bit phy data from PHY controller
1771 */
1772
1773 static u16 phy_read_1bit(unsigned long ioaddr)
1774 {
1775 u16 phy_data;
1776
1777 outl(0x50000, ioaddr);
1778 udelay(1);
1779 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1780 outl(0x40000, ioaddr);
1781 udelay(1);
1782
1783 return phy_data;
1784 }
1785
1786
1787 /*
1788 * Parser SROM and media mode
1789 */
1790
1791 static void dmfe_parse_srom(struct dmfe_board_info * db)
1792 {
1793 char * srom = db->srom;
1794 int dmfe_mode, tmp_reg;
1795
1796 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1797
1798 /* Init CR15 */
1799 db->cr15_data = CR15_DEFAULT;
1800
1801 /* Check SROM Version */
1802 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1803 /* SROM V4.01 */
1804 /* Get NIC support media mode */
1805 db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2);
1806 db->PHY_reg4 = 0;
1807 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1808 switch( db->NIC_capability & tmp_reg ) {
1809 case 0x1: db->PHY_reg4 |= 0x0020; break;
1810 case 0x2: db->PHY_reg4 |= 0x0040; break;
1811 case 0x4: db->PHY_reg4 |= 0x0080; break;
1812 case 0x8: db->PHY_reg4 |= 0x0100; break;
1813 }
1814 }
1815
1816 /* Media Mode Force or not check */
1817 dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) &
1818 le32_to_cpup((__le32 *)srom + 36/4);
1819 switch(dmfe_mode) {
1820 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1821 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1822 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1823 case 0x100:
1824 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1825 }
1826
1827 /* Special Function setting */
1828 /* VLAN function */
1829 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1830 db->cr15_data |= 0x40;
1831
1832 /* Flow Control */
1833 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1834 db->cr15_data |= 0x400;
1835
1836 /* TX pause packet */
1837 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1838 db->cr15_data |= 0x9800;
1839 }
1840
1841 /* Parse HPNA parameter */
1842 db->HPNA_command = 1;
1843
1844 /* Accept remote command or not */
1845 if (HPNA_rx_cmd == 0)
1846 db->HPNA_command |= 0x8000;
1847
1848 /* Issue remote command & operation mode */
1849 if (HPNA_tx_cmd == 1)
1850 switch(HPNA_mode) { /* Issue Remote Command */
1851 case 0: db->HPNA_command |= 0x0904; break;
1852 case 1: db->HPNA_command |= 0x0a00; break;
1853 case 2: db->HPNA_command |= 0x0506; break;
1854 case 3: db->HPNA_command |= 0x0602; break;
1855 }
1856 else
1857 switch(HPNA_mode) { /* Don't Issue */
1858 case 0: db->HPNA_command |= 0x0004; break;
1859 case 1: db->HPNA_command |= 0x0000; break;
1860 case 2: db->HPNA_command |= 0x0006; break;
1861 case 3: db->HPNA_command |= 0x0002; break;
1862 }
1863
1864 /* Check DM9801 or DM9802 present or not */
1865 db->HPNA_present = 0;
1866 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1867 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1868 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1869 /* DM9801 or DM9802 present */
1870 db->HPNA_timer = 8;
1871 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1872 /* DM9801 HomeRun */
1873 db->HPNA_present = 1;
1874 dmfe_program_DM9801(db, tmp_reg);
1875 } else {
1876 /* DM9802 LongRun */
1877 db->HPNA_present = 2;
1878 dmfe_program_DM9802(db);
1879 }
1880 }
1881
1882 }
1883
1884
1885 /*
1886 * Init HomeRun DM9801
1887 */
1888
1889 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1890 {
1891 uint reg17, reg25;
1892
1893 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1894 switch(HPNA_rev) {
1895 case 0xb900: /* DM9801 E3 */
1896 db->HPNA_command |= 0x1000;
1897 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1898 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1899 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1900 break;
1901 case 0xb901: /* DM9801 E4 */
1902 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1903 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1904 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1905 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1906 break;
1907 case 0xb902: /* DM9801 E5 */
1908 case 0xb903: /* DM9801 E6 */
1909 default:
1910 db->HPNA_command |= 0x1000;
1911 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1912 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1913 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1914 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1915 break;
1916 }
1917 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1918 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1919 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1920 }
1921
1922
1923 /*
1924 * Init HomeRun DM9802
1925 */
1926
1927 static void dmfe_program_DM9802(struct dmfe_board_info * db)
1928 {
1929 uint phy_reg;
1930
1931 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1932 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1933 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1934 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1935 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1936 }
1937
1938
1939 /*
1940 * Check remote HPNA power and speed status. If not correct,
1941 * issue command again.
1942 */
1943
1944 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1945 {
1946 uint phy_reg;
1947
1948 /* Got remote device status */
1949 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1950 switch(phy_reg) {
1951 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1952 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1953 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1954 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1955 }
1956
1957 /* Check remote device status match our setting ot not */
1958 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1959 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1960 db->HPNA_timer=8;
1961 } else
1962 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1963 }
1964
1965
1966
1967 static struct pci_device_id dmfe_pci_tbl[] = {
1968 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1969 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1970 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1971 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1972 { 0, }
1973 };
1974 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1975
1976
1977 static struct pci_driver dmfe_driver = {
1978 .name = "dmfe",
1979 .id_table = dmfe_pci_tbl,
1980 .probe = dmfe_init_one,
1981 .remove = __devexit_p(dmfe_remove_one),
1982 };
1983
1984 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1985 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1986 MODULE_LICENSE("GPL");
1987 MODULE_VERSION(DRV_VERSION);
1988
1989 module_param(debug, int, 0);
1990 module_param(mode, byte, 0);
1991 module_param(cr6set, int, 0);
1992 module_param(chkmode, byte, 0);
1993 module_param(HPNA_mode, byte, 0);
1994 module_param(HPNA_rx_cmd, byte, 0);
1995 module_param(HPNA_tx_cmd, byte, 0);
1996 module_param(HPNA_NoiseFloor, byte, 0);
1997 module_param(SF_mode, byte, 0);
1998 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
1999 MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2000 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2001
2002 /* Description:
2003 * when user used insmod to add module, system invoked init_module()
2004 * to initilize and register.
2005 */
2006
2007 static int __init dmfe_init_module(void)
2008 {
2009 int rc;
2010
2011 printk(version);
2012 printed_version = 1;
2013
2014 DMFE_DBUG(0, "init_module() ", debug);
2015
2016 if (debug)
2017 dmfe_debug = debug; /* set debug flag */
2018 if (cr6set)
2019 dmfe_cr6_user_set = cr6set;
2020
2021 switch(mode) {
2022 case DMFE_10MHF:
2023 case DMFE_100MHF:
2024 case DMFE_10MFD:
2025 case DMFE_100MFD:
2026 case DMFE_1M_HPNA:
2027 dmfe_media_mode = mode;
2028 break;
2029 default:dmfe_media_mode = DMFE_AUTO;
2030 break;
2031 }
2032
2033 if (HPNA_mode > 4)
2034 HPNA_mode = 0; /* Default: LP/HS */
2035 if (HPNA_rx_cmd > 1)
2036 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2037 if (HPNA_tx_cmd > 1)
2038 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2039 if (HPNA_NoiseFloor > 15)
2040 HPNA_NoiseFloor = 0;
2041
2042 rc = pci_module_init(&dmfe_driver);
2043 if (rc < 0)
2044 return rc;
2045
2046 return 0;
2047 }
2048
2049
2050 /*
2051 * Description:
2052 * when user used rmmod to delete module, system invoked clean_module()
2053 * to un-register all registered services.
2054 */
2055
2056 static void __exit dmfe_cleanup_module(void)
2057 {
2058 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2059 pci_unregister_driver(&dmfe_driver);
2060 }
2061
2062 module_init(dmfe_init_module);
2063 module_exit(dmfe_cleanup_module);
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