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[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / drivers / serial / pmac_zilog.c
blob5f52883e64d2ade773b968edd967e395121a58bd
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/tty.h>
48
49 #include <linux/tty_flip.h>
50 #include <linux/major.h>
51 #include <linux/string.h>
52 #include <linux/fcntl.h>
53 #include <linux/mm.h>
54 #include <linux/kernel.h>
55 #include <linux/delay.h>
56 #include <linux/init.h>
57 #include <linux/console.h>
58 #include <linux/slab.h>
59 #include <linux/adb.h>
60 #include <linux/pmu.h>
61 #include <linux/bitops.h>
62 #include <linux/sysrq.h>
63 #include <linux/mutex.h>
64 #include <asm/sections.h>
65 #include <asm/io.h>
66 #include <asm/irq.h>
67 #include <asm/prom.h>
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
70 #include <asm/dbdma.h>
71 #include <asm/macio.h>
72 #include <asm/semaphore.h>
73
74 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
75 #define SUPPORT_SYSRQ
76 #endif
77
78 #include <linux/serial.h>
79 #include <linux/serial_core.h>
80
81 #include "pmac_zilog.h"
82
83 /* Not yet implemented */
84 #undef HAS_DBDMA
85
86 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
87 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
88 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
89 MODULE_LICENSE("GPL");
90
91 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
92
93
94 /*
95 * For the sake of early serial console, we can do a pre-probe
96 * (optional) of the ports at rather early boot time.
97 */
98 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
99 static int pmz_ports_count;
100 static DEFINE_MUTEX(pmz_irq_mutex);
101
102 static struct uart_driver pmz_uart_reg = {
103 .owner = THIS_MODULE,
104 .driver_name = "ttyS",
105 .devfs_name = "tts/",
106 .dev_name = "ttyS",
107 .major = TTY_MAJOR,
108 };
109
110
111 /*
112 * Load all registers to reprogram the port
113 * This function must only be called when the TX is not busy. The UART
114 * port lock must be held and local interrupts disabled.
115 */
116 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
117 {
118 int i;
119
120 if (ZS_IS_ASLEEP(uap))
121 return;
122
123 /* Let pending transmits finish. */
124 for (i = 0; i < 1000; i++) {
125 unsigned char stat = read_zsreg(uap, R1);
126 if (stat & ALL_SNT)
127 break;
128 udelay(100);
129 }
130
131 ZS_CLEARERR(uap);
132 zssync(uap);
133 ZS_CLEARFIFO(uap);
134 zssync(uap);
135 ZS_CLEARERR(uap);
136
137 /* Disable all interrupts. */
138 write_zsreg(uap, R1,
139 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
140
141 /* Set parity, sync config, stop bits, and clock divisor. */
142 write_zsreg(uap, R4, regs[R4]);
143
144 /* Set misc. TX/RX control bits. */
145 write_zsreg(uap, R10, regs[R10]);
146
147 /* Set TX/RX controls sans the enable bits. */
148 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
149 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
150
151 /* now set R7 "prime" on ESCC */
152 write_zsreg(uap, R15, regs[R15] | EN85C30);
153 write_zsreg(uap, R7, regs[R7P]);
154
155 /* make sure we use R7 "non-prime" on ESCC */
156 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
157
158 /* Synchronous mode config. */
159 write_zsreg(uap, R6, regs[R6]);
160 write_zsreg(uap, R7, regs[R7]);
161
162 /* Disable baud generator. */
163 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
164
165 /* Clock mode control. */
166 write_zsreg(uap, R11, regs[R11]);
167
168 /* Lower and upper byte of baud rate generator divisor. */
169 write_zsreg(uap, R12, regs[R12]);
170 write_zsreg(uap, R13, regs[R13]);
171
172 /* Now rewrite R14, with BRENAB (if set). */
173 write_zsreg(uap, R14, regs[R14]);
174
175 /* Reset external status interrupts. */
176 write_zsreg(uap, R0, RES_EXT_INT);
177 write_zsreg(uap, R0, RES_EXT_INT);
178
179 /* Rewrite R3/R5, this time without enables masked. */
180 write_zsreg(uap, R3, regs[R3]);
181 write_zsreg(uap, R5, regs[R5]);
182
183 /* Rewrite R1, this time without IRQ enabled masked. */
184 write_zsreg(uap, R1, regs[R1]);
185
186 /* Enable interrupts */
187 write_zsreg(uap, R9, regs[R9]);
188 }
189
190 /*
191 * We do like sunzilog to avoid disrupting pending Tx
192 * Reprogram the Zilog channel HW registers with the copies found in the
193 * software state struct. If the transmitter is busy, we defer this update
194 * until the next TX complete interrupt. Else, we do it right now.
195 *
196 * The UART port lock must be held and local interrupts disabled.
197 */
198 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
199 {
200 if (!ZS_REGS_HELD(uap)) {
201 if (ZS_TX_ACTIVE(uap)) {
202 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
203 } else {
204 pmz_debug("pmz: maybe_update_regs: updating\n");
205 pmz_load_zsregs(uap, uap->curregs);
206 }
207 }
208 }
209
210 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
211 struct pt_regs *regs)
212 {
213 struct tty_struct *tty = NULL;
214 unsigned char ch, r1, drop, error, flag;
215 int loops = 0;
216
217 /* The interrupt can be enabled when the port isn't open, typically
218 * that happens when using one port is open and the other closed (stale
219 * interrupt) or when one port is used as a console.
220 */
221 if (!ZS_IS_OPEN(uap)) {
222 pmz_debug("pmz: draining input\n");
223 /* Port is closed, drain input data */
224 for (;;) {
225 if ((++loops) > 1000)
226 goto flood;
227 (void)read_zsreg(uap, R1);
228 write_zsreg(uap, R0, ERR_RES);
229 (void)read_zsdata(uap);
230 ch = read_zsreg(uap, R0);
231 if (!(ch & Rx_CH_AV))
232 break;
233 }
234 return NULL;
235 }
236
237 /* Sanity check, make sure the old bug is no longer happening */
238 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
239 WARN_ON(1);
240 (void)read_zsdata(uap);
241 return NULL;
242 }
243 tty = uap->port.info->tty;
244
245 while (1) {
246 error = 0;
247 drop = 0;
248
249 r1 = read_zsreg(uap, R1);
250 ch = read_zsdata(uap);
251
252 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
253 write_zsreg(uap, R0, ERR_RES);
254 zssync(uap);
255 }
256
257 ch &= uap->parity_mask;
258 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
259 uap->flags &= ~PMACZILOG_FLAG_BREAK;
260 }
261
262 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
263 #ifdef USE_CTRL_O_SYSRQ
264 /* Handle the SysRq ^O Hack */
265 if (ch == '\x0f') {
266 uap->port.sysrq = jiffies + HZ*5;
267 goto next_char;
268 }
269 #endif /* USE_CTRL_O_SYSRQ */
270 if (uap->port.sysrq) {
271 int swallow;
272 spin_unlock(&uap->port.lock);
273 swallow = uart_handle_sysrq_char(&uap->port, ch, regs);
274 spin_lock(&uap->port.lock);
275 if (swallow)
276 goto next_char;
277 }
278 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
279
280 /* A real serial line, record the character and status. */
281 if (drop)
282 goto next_char;
283
284 flag = TTY_NORMAL;
285 uap->port.icount.rx++;
286
287 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
288 error = 1;
289 if (r1 & BRK_ABRT) {
290 pmz_debug("pmz: got break !\n");
291 r1 &= ~(PAR_ERR | CRC_ERR);
292 uap->port.icount.brk++;
293 if (uart_handle_break(&uap->port))
294 goto next_char;
295 }
296 else if (r1 & PAR_ERR)
297 uap->port.icount.parity++;
298 else if (r1 & CRC_ERR)
299 uap->port.icount.frame++;
300 if (r1 & Rx_OVR)
301 uap->port.icount.overrun++;
302 r1 &= uap->port.read_status_mask;
303 if (r1 & BRK_ABRT)
304 flag = TTY_BREAK;
305 else if (r1 & PAR_ERR)
306 flag = TTY_PARITY;
307 else if (r1 & CRC_ERR)
308 flag = TTY_FRAME;
309 }
310
311 if (uap->port.ignore_status_mask == 0xff ||
312 (r1 & uap->port.ignore_status_mask) == 0) {
313 tty_insert_flip_char(tty, ch, flag);
314 }
315 if (r1 & Rx_OVR)
316 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
317 next_char:
318 /* We can get stuck in an infinite loop getting char 0 when the
319 * line is in a wrong HW state, we break that here.
320 * When that happens, I disable the receive side of the driver.
321 * Note that what I've been experiencing is a real irq loop where
322 * I'm getting flooded regardless of the actual port speed.
323 * Something stange is going on with the HW
324 */
325 if ((++loops) > 1000)
326 goto flood;
327 ch = read_zsreg(uap, R0);
328 if (!(ch & Rx_CH_AV))
329 break;
330 }
331
332 return tty;
333 flood:
334 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
335 write_zsreg(uap, R1, uap->curregs[R1]);
336 zssync(uap);
337 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
338 return tty;
339 }
340
341 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
342 {
343 unsigned char status;
344
345 status = read_zsreg(uap, R0);
346 write_zsreg(uap, R0, RES_EXT_INT);
347 zssync(uap);
348
349 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
350 if (status & SYNC_HUNT)
351 uap->port.icount.dsr++;
352
353 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
354 * But it does not tell us which bit has changed, we have to keep
355 * track of this ourselves.
356 * The CTS input is inverted for some reason. -- paulus
357 */
358 if ((status ^ uap->prev_status) & DCD)
359 uart_handle_dcd_change(&uap->port,
360 (status & DCD));
361 if ((status ^ uap->prev_status) & CTS)
362 uart_handle_cts_change(&uap->port,
363 !(status & CTS));
364
365 wake_up_interruptible(&uap->port.info->delta_msr_wait);
366 }
367
368 if (status & BRK_ABRT)
369 uap->flags |= PMACZILOG_FLAG_BREAK;
370
371 uap->prev_status = status;
372 }
373
374 static void pmz_transmit_chars(struct uart_pmac_port *uap)
375 {
376 struct circ_buf *xmit;
377
378 if (ZS_IS_ASLEEP(uap))
379 return;
380 if (ZS_IS_CONS(uap)) {
381 unsigned char status = read_zsreg(uap, R0);
382
383 /* TX still busy? Just wait for the next TX done interrupt.
384 *
385 * It can occur because of how we do serial console writes. It would
386 * be nice to transmit console writes just like we normally would for
387 * a TTY line. (ie. buffered and TX interrupt driven). That is not
388 * easy because console writes cannot sleep. One solution might be
389 * to poll on enough port->xmit space becomming free. -DaveM
390 */
391 if (!(status & Tx_BUF_EMP))
392 return;
393 }
394
395 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
396
397 if (ZS_REGS_HELD(uap)) {
398 pmz_load_zsregs(uap, uap->curregs);
399 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
400 }
401
402 if (ZS_TX_STOPPED(uap)) {
403 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
404 goto ack_tx_int;
405 }
406
407 if (uap->port.x_char) {
408 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
409 write_zsdata(uap, uap->port.x_char);
410 zssync(uap);
411 uap->port.icount.tx++;
412 uap->port.x_char = 0;
413 return;
414 }
415
416 if (uap->port.info == NULL)
417 goto ack_tx_int;
418 xmit = &uap->port.info->xmit;
419 if (uart_circ_empty(xmit)) {
420 uart_write_wakeup(&uap->port);
421 goto ack_tx_int;
422 }
423 if (uart_tx_stopped(&uap->port))
424 goto ack_tx_int;
425
426 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
427 write_zsdata(uap, xmit->buf[xmit->tail]);
428 zssync(uap);
429
430 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
431 uap->port.icount.tx++;
432
433 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
434 uart_write_wakeup(&uap->port);
435
436 return;
437
438 ack_tx_int:
439 write_zsreg(uap, R0, RES_Tx_P);
440 zssync(uap);
441 }
442
443 /* Hrm... we register that twice, fixme later.... */
444 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
445 {
446 struct uart_pmac_port *uap = dev_id;
447 struct uart_pmac_port *uap_a;
448 struct uart_pmac_port *uap_b;
449 int rc = IRQ_NONE;
450 struct tty_struct *tty;
451 u8 r3;
452
453 uap_a = pmz_get_port_A(uap);
454 uap_b = uap_a->mate;
455
456 spin_lock(&uap_a->port.lock);
457 r3 = read_zsreg(uap_a, R3);
458
459 #ifdef DEBUG_HARD
460 pmz_debug("irq, r3: %x\n", r3);
461 #endif
462 /* Channel A */
463 tty = NULL;
464 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
465 write_zsreg(uap_a, R0, RES_H_IUS);
466 zssync(uap_a);
467 if (r3 & CHAEXT)
468 pmz_status_handle(uap_a, regs);
469 if (r3 & CHARxIP)
470 tty = pmz_receive_chars(uap_a, regs);
471 if (r3 & CHATxIP)
472 pmz_transmit_chars(uap_a);
473 rc = IRQ_HANDLED;
474 }
475 spin_unlock(&uap_a->port.lock);
476 if (tty != NULL)
477 tty_flip_buffer_push(tty);
478
479 if (uap_b->node == NULL)
480 goto out;
481
482 spin_lock(&uap_b->port.lock);
483 tty = NULL;
484 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
485 write_zsreg(uap_b, R0, RES_H_IUS);
486 zssync(uap_b);
487 if (r3 & CHBEXT)
488 pmz_status_handle(uap_b, regs);
489 if (r3 & CHBRxIP)
490 tty = pmz_receive_chars(uap_b, regs);
491 if (r3 & CHBTxIP)
492 pmz_transmit_chars(uap_b);
493 rc = IRQ_HANDLED;
494 }
495 spin_unlock(&uap_b->port.lock);
496 if (tty != NULL)
497 tty_flip_buffer_push(tty);
498
499 out:
500 #ifdef DEBUG_HARD
501 pmz_debug("irq done.\n");
502 #endif
503 return rc;
504 }
505
506 /*
507 * Peek the status register, lock not held by caller
508 */
509 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
510 {
511 unsigned long flags;
512 u8 status;
513
514 spin_lock_irqsave(&uap->port.lock, flags);
515 status = read_zsreg(uap, R0);
516 spin_unlock_irqrestore(&uap->port.lock, flags);
517
518 return status;
519 }
520
521 /*
522 * Check if transmitter is empty
523 * The port lock is not held.
524 */
525 static unsigned int pmz_tx_empty(struct uart_port *port)
526 {
527 struct uart_pmac_port *uap = to_pmz(port);
528 unsigned char status;
529
530 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
531 return TIOCSER_TEMT;
532
533 status = pmz_peek_status(to_pmz(port));
534 if (status & Tx_BUF_EMP)
535 return TIOCSER_TEMT;
536 return 0;
537 }
538
539 /*
540 * Set Modem Control (RTS & DTR) bits
541 * The port lock is held and interrupts are disabled.
542 * Note: Shall we really filter out RTS on external ports or
543 * should that be dealt at higher level only ?
544 */
545 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
546 {
547 struct uart_pmac_port *uap = to_pmz(port);
548 unsigned char set_bits, clear_bits;
549
550 /* Do nothing for irda for now... */
551 if (ZS_IS_IRDA(uap))
552 return;
553 /* We get called during boot with a port not up yet */
554 if (ZS_IS_ASLEEP(uap) ||
555 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
556 return;
557
558 set_bits = clear_bits = 0;
559
560 if (ZS_IS_INTMODEM(uap)) {
561 if (mctrl & TIOCM_RTS)
562 set_bits |= RTS;
563 else
564 clear_bits |= RTS;
565 }
566 if (mctrl & TIOCM_DTR)
567 set_bits |= DTR;
568 else
569 clear_bits |= DTR;
570
571 /* NOTE: Not subject to 'transmitter active' rule. */
572 uap->curregs[R5] |= set_bits;
573 uap->curregs[R5] &= ~clear_bits;
574 if (ZS_IS_ASLEEP(uap))
575 return;
576 write_zsreg(uap, R5, uap->curregs[R5]);
577 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
578 set_bits, clear_bits, uap->curregs[R5]);
579 zssync(uap);
580 }
581
582 /*
583 * Get Modem Control bits (only the input ones, the core will
584 * or that with a cached value of the control ones)
585 * The port lock is held and interrupts are disabled.
586 */
587 static unsigned int pmz_get_mctrl(struct uart_port *port)
588 {
589 struct uart_pmac_port *uap = to_pmz(port);
590 unsigned char status;
591 unsigned int ret;
592
593 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
594 return 0;
595
596 status = read_zsreg(uap, R0);
597
598 ret = 0;
599 if (status & DCD)
600 ret |= TIOCM_CAR;
601 if (status & SYNC_HUNT)
602 ret |= TIOCM_DSR;
603 if (!(status & CTS))
604 ret |= TIOCM_CTS;
605
606 return ret;
607 }
608
609 /*
610 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
611 * though for DMA, we will have to do a bit more.
612 * The port lock is held and interrupts are disabled.
613 */
614 static void pmz_stop_tx(struct uart_port *port)
615 {
616 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
617 }
618
619 /*
620 * Kick the Tx side.
621 * The port lock is held and interrupts are disabled.
622 */
623 static void pmz_start_tx(struct uart_port *port)
624 {
625 struct uart_pmac_port *uap = to_pmz(port);
626 unsigned char status;
627
628 pmz_debug("pmz: start_tx()\n");
629
630 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
631 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
632
633 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
634 return;
635
636 status = read_zsreg(uap, R0);
637
638 /* TX busy? Just wait for the TX done interrupt. */
639 if (!(status & Tx_BUF_EMP))
640 return;
641
642 /* Send the first character to jump-start the TX done
643 * IRQ sending engine.
644 */
645 if (port->x_char) {
646 write_zsdata(uap, port->x_char);
647 zssync(uap);
648 port->icount.tx++;
649 port->x_char = 0;
650 } else {
651 struct circ_buf *xmit = &port->info->xmit;
652
653 write_zsdata(uap, xmit->buf[xmit->tail]);
654 zssync(uap);
655 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
656 port->icount.tx++;
657
658 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
659 uart_write_wakeup(&uap->port);
660 }
661 pmz_debug("pmz: start_tx() done.\n");
662 }
663
664 /*
665 * Stop Rx side, basically disable emitting of
666 * Rx interrupts on the port. We don't disable the rx
667 * side of the chip proper though
668 * The port lock is held.
669 */
670 static void pmz_stop_rx(struct uart_port *port)
671 {
672 struct uart_pmac_port *uap = to_pmz(port);
673
674 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
675 return;
676
677 pmz_debug("pmz: stop_rx()()\n");
678
679 /* Disable all RX interrupts. */
680 uap->curregs[R1] &= ~RxINT_MASK;
681 pmz_maybe_update_regs(uap);
682
683 pmz_debug("pmz: stop_rx() done.\n");
684 }
685
686 /*
687 * Enable modem status change interrupts
688 * The port lock is held.
689 */
690 static void pmz_enable_ms(struct uart_port *port)
691 {
692 struct uart_pmac_port *uap = to_pmz(port);
693 unsigned char new_reg;
694
695 if (ZS_IS_IRDA(uap) || uap->node == NULL)
696 return;
697 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
698 if (new_reg != uap->curregs[R15]) {
699 uap->curregs[R15] = new_reg;
700
701 if (ZS_IS_ASLEEP(uap))
702 return;
703 /* NOTE: Not subject to 'transmitter active' rule. */
704 write_zsreg(uap, R15, uap->curregs[R15]);
705 }
706 }
707
708 /*
709 * Control break state emission
710 * The port lock is not held.
711 */
712 static void pmz_break_ctl(struct uart_port *port, int break_state)
713 {
714 struct uart_pmac_port *uap = to_pmz(port);
715 unsigned char set_bits, clear_bits, new_reg;
716 unsigned long flags;
717
718 if (uap->node == NULL)
719 return;
720 set_bits = clear_bits = 0;
721
722 if (break_state)
723 set_bits |= SND_BRK;
724 else
725 clear_bits |= SND_BRK;
726
727 spin_lock_irqsave(&port->lock, flags);
728
729 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
730 if (new_reg != uap->curregs[R5]) {
731 uap->curregs[R5] = new_reg;
732
733 /* NOTE: Not subject to 'transmitter active' rule. */
734 if (ZS_IS_ASLEEP(uap))
735 return;
736 write_zsreg(uap, R5, uap->curregs[R5]);
737 }
738
739 spin_unlock_irqrestore(&port->lock, flags);
740 }
741
742 /*
743 * Turn power on or off to the SCC and associated stuff
744 * (port drivers, modem, IR port, etc.)
745 * Returns the number of milliseconds we should wait before
746 * trying to use the port.
747 */
748 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
749 {
750 int delay = 0;
751 int rc;
752
753 if (state) {
754 rc = pmac_call_feature(
755 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
756 pmz_debug("port power on result: %d\n", rc);
757 if (ZS_IS_INTMODEM(uap)) {
758 rc = pmac_call_feature(
759 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
760 delay = 2500; /* wait for 2.5s before using */
761 pmz_debug("modem power result: %d\n", rc);
762 }
763 } else {
764 /* TODO: Make that depend on a timer, don't power down
765 * immediately
766 */
767 if (ZS_IS_INTMODEM(uap)) {
768 rc = pmac_call_feature(
769 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
770 pmz_debug("port power off result: %d\n", rc);
771 }
772 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
773 }
774 return delay;
775 }
776
777 /*
778 * FixZeroBug....Works around a bug in the SCC receving channel.
779 * Inspired from Darwin code, 15 Sept. 2000 -DanM
780 *
781 * The following sequence prevents a problem that is seen with O'Hare ASICs
782 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
783 * at the input to the receiver becomes 'stuck' and locks up the receiver.
784 * This problem can occur as a result of a zero bit at the receiver input
785 * coincident with any of the following events:
786 *
787 * The SCC is initialized (hardware or software).
788 * A framing error is detected.
789 * The clocking option changes from synchronous or X1 asynchronous
790 * clocking to X16, X32, or X64 asynchronous clocking.
791 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
792 *
793 * This workaround attempts to recover from the lockup condition by placing
794 * the SCC in synchronous loopback mode with a fast clock before programming
795 * any of the asynchronous modes.
796 */
797 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
798 {
799 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
800 zssync(uap);
801 udelay(10);
802 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
803 zssync(uap);
804
805 write_zsreg(uap, 4, X1CLK | MONSYNC);
806 write_zsreg(uap, 3, Rx8);
807 write_zsreg(uap, 5, Tx8 | RTS);
808 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
809 write_zsreg(uap, 11, RCBR | TCBR);
810 write_zsreg(uap, 12, 0);
811 write_zsreg(uap, 13, 0);
812 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
813 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
814 write_zsreg(uap, 3, Rx8 | RxENABLE);
815 write_zsreg(uap, 0, RES_EXT_INT);
816 write_zsreg(uap, 0, RES_EXT_INT);
817 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
818
819 /* The channel should be OK now, but it is probably receiving
820 * loopback garbage.
821 * Switch to asynchronous mode, disable the receiver,
822 * and discard everything in the receive buffer.
823 */
824 write_zsreg(uap, 9, NV);
825 write_zsreg(uap, 4, X16CLK | SB_MASK);
826 write_zsreg(uap, 3, Rx8);
827
828 while (read_zsreg(uap, 0) & Rx_CH_AV) {
829 (void)read_zsreg(uap, 8);
830 write_zsreg(uap, 0, RES_EXT_INT);
831 write_zsreg(uap, 0, ERR_RES);
832 }
833 }
834
835 /*
836 * Real startup routine, powers up the hardware and sets up
837 * the SCC. Returns a delay in ms where you need to wait before
838 * actually using the port, this is typically the internal modem
839 * powerup delay. This routine expect the lock to be taken.
840 */
841 static int __pmz_startup(struct uart_pmac_port *uap)
842 {
843 int pwr_delay = 0;
844
845 memset(&uap->curregs, 0, sizeof(uap->curregs));
846
847 /* Power up the SCC & underlying hardware (modem/irda) */
848 pwr_delay = pmz_set_scc_power(uap, 1);
849
850 /* Nice buggy HW ... */
851 pmz_fix_zero_bug_scc(uap);
852
853 /* Reset the channel */
854 uap->curregs[R9] = 0;
855 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
856 zssync(uap);
857 udelay(10);
858 write_zsreg(uap, 9, 0);
859 zssync(uap);
860
861 /* Clear the interrupt registers */
862 write_zsreg(uap, R1, 0);
863 write_zsreg(uap, R0, ERR_RES);
864 write_zsreg(uap, R0, ERR_RES);
865 write_zsreg(uap, R0, RES_H_IUS);
866 write_zsreg(uap, R0, RES_H_IUS);
867
868 /* Setup some valid baud rate */
869 uap->curregs[R4] = X16CLK | SB1;
870 uap->curregs[R3] = Rx8;
871 uap->curregs[R5] = Tx8 | RTS;
872 if (!ZS_IS_IRDA(uap))
873 uap->curregs[R5] |= DTR;
874 uap->curregs[R12] = 0;
875 uap->curregs[R13] = 0;
876 uap->curregs[R14] = BRENAB;
877
878 /* Clear handshaking, enable BREAK interrupts */
879 uap->curregs[R15] = BRKIE;
880
881 /* Master interrupt enable */
882 uap->curregs[R9] |= NV | MIE;
883
884 pmz_load_zsregs(uap, uap->curregs);
885
886 /* Enable receiver and transmitter. */
887 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
888 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
889
890 /* Remember status for DCD/CTS changes */
891 uap->prev_status = read_zsreg(uap, R0);
892
893
894 return pwr_delay;
895 }
896
897 static void pmz_irda_reset(struct uart_pmac_port *uap)
898 {
899 uap->curregs[R5] |= DTR;
900 write_zsreg(uap, R5, uap->curregs[R5]);
901 zssync(uap);
902 mdelay(110);
903 uap->curregs[R5] &= ~DTR;
904 write_zsreg(uap, R5, uap->curregs[R5]);
905 zssync(uap);
906 mdelay(10);
907 }
908
909 /*
910 * This is the "normal" startup routine, using the above one
911 * wrapped with the lock and doing a schedule delay
912 */
913 static int pmz_startup(struct uart_port *port)
914 {
915 struct uart_pmac_port *uap = to_pmz(port);
916 unsigned long flags;
917 int pwr_delay = 0;
918
919 pmz_debug("pmz: startup()\n");
920
921 if (ZS_IS_ASLEEP(uap))
922 return -EAGAIN;
923 if (uap->node == NULL)
924 return -ENODEV;
925
926 mutex_lock(&pmz_irq_mutex);
927
928 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
929
930 /* A console is never powered down. Else, power up and
931 * initialize the chip
932 */
933 if (!ZS_IS_CONS(uap)) {
934 spin_lock_irqsave(&port->lock, flags);
935 pwr_delay = __pmz_startup(uap);
936 spin_unlock_irqrestore(&port->lock, flags);
937 }
938
939 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
940 if (request_irq(uap->port.irq, pmz_interrupt, SA_SHIRQ, "PowerMac Zilog", uap)) {
941 dev_err(&uap->dev->ofdev.dev,
942 "Unable to register zs interrupt handler.\n");
943 pmz_set_scc_power(uap, 0);
944 mutex_unlock(&pmz_irq_mutex);
945 return -ENXIO;
946 }
947
948 mutex_unlock(&pmz_irq_mutex);
949
950 /* Right now, we deal with delay by blocking here, I'll be
951 * smarter later on
952 */
953 if (pwr_delay != 0) {
954 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
955 msleep(pwr_delay);
956 }
957
958 /* IrDA reset is done now */
959 if (ZS_IS_IRDA(uap))
960 pmz_irda_reset(uap);
961
962 /* Enable interrupts emission from the chip */
963 spin_lock_irqsave(&port->lock, flags);
964 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
965 if (!ZS_IS_EXTCLK(uap))
966 uap->curregs[R1] |= EXT_INT_ENAB;
967 write_zsreg(uap, R1, uap->curregs[R1]);
968 spin_unlock_irqrestore(&port->lock, flags);
969
970 pmz_debug("pmz: startup() done.\n");
971
972 return 0;
973 }
974
975 static void pmz_shutdown(struct uart_port *port)
976 {
977 struct uart_pmac_port *uap = to_pmz(port);
978 unsigned long flags;
979
980 pmz_debug("pmz: shutdown()\n");
981
982 if (uap->node == NULL)
983 return;
984
985 mutex_lock(&pmz_irq_mutex);
986
987 /* Release interrupt handler */
988 free_irq(uap->port.irq, uap);
989
990 spin_lock_irqsave(&port->lock, flags);
991
992 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
993
994 if (!ZS_IS_OPEN(uap->mate))
995 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
996
997 /* Disable interrupts */
998 if (!ZS_IS_ASLEEP(uap)) {
999 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1000 write_zsreg(uap, R1, uap->curregs[R1]);
1001 zssync(uap);
1002 }
1003
1004 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1005 spin_unlock_irqrestore(&port->lock, flags);
1006 mutex_unlock(&pmz_irq_mutex);
1007 return;
1008 }
1009
1010 /* Disable receiver and transmitter. */
1011 uap->curregs[R3] &= ~RxENABLE;
1012 uap->curregs[R5] &= ~TxENABLE;
1013
1014 /* Disable all interrupts and BRK assertion. */
1015 uap->curregs[R5] &= ~SND_BRK;
1016 pmz_maybe_update_regs(uap);
1017
1018 /* Shut the chip down */
1019 pmz_set_scc_power(uap, 0);
1020
1021 spin_unlock_irqrestore(&port->lock, flags);
1022
1023 mutex_unlock(&pmz_irq_mutex);
1024
1025 pmz_debug("pmz: shutdown() done.\n");
1026 }
1027
1028 /* Shared by TTY driver and serial console setup. The port lock is held
1029 * and local interrupts are disabled.
1030 */
1031 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1032 unsigned int iflag, unsigned long baud)
1033 {
1034 int brg;
1035
1036
1037 /* Switch to external clocking for IrDA high clock rates. That
1038 * code could be re-used for Midi interfaces with different
1039 * multipliers
1040 */
1041 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1042 uap->curregs[R4] = X1CLK;
1043 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1044 uap->curregs[R14] = 0; /* BRG off */
1045 uap->curregs[R12] = 0;
1046 uap->curregs[R13] = 0;
1047 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1048 } else {
1049 switch (baud) {
1050 case ZS_CLOCK/16: /* 230400 */
1051 uap->curregs[R4] = X16CLK;
1052 uap->curregs[R11] = 0;
1053 uap->curregs[R14] = 0;
1054 break;
1055 case ZS_CLOCK/32: /* 115200 */
1056 uap->curregs[R4] = X32CLK;
1057 uap->curregs[R11] = 0;
1058 uap->curregs[R14] = 0;
1059 break;
1060 default:
1061 uap->curregs[R4] = X16CLK;
1062 uap->curregs[R11] = TCBR | RCBR;
1063 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1064 uap->curregs[R12] = (brg & 255);
1065 uap->curregs[R13] = ((brg >> 8) & 255);
1066 uap->curregs[R14] = BRENAB;
1067 }
1068 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1069 }
1070
1071 /* Character size, stop bits, and parity. */
1072 uap->curregs[3] &= ~RxN_MASK;
1073 uap->curregs[5] &= ~TxN_MASK;
1074
1075 switch (cflag & CSIZE) {
1076 case CS5:
1077 uap->curregs[3] |= Rx5;
1078 uap->curregs[5] |= Tx5;
1079 uap->parity_mask = 0x1f;
1080 break;
1081 case CS6:
1082 uap->curregs[3] |= Rx6;
1083 uap->curregs[5] |= Tx6;
1084 uap->parity_mask = 0x3f;
1085 break;
1086 case CS7:
1087 uap->curregs[3] |= Rx7;
1088 uap->curregs[5] |= Tx7;
1089 uap->parity_mask = 0x7f;
1090 break;
1091 case CS8:
1092 default:
1093 uap->curregs[3] |= Rx8;
1094 uap->curregs[5] |= Tx8;
1095 uap->parity_mask = 0xff;
1096 break;
1097 };
1098 uap->curregs[4] &= ~(SB_MASK);
1099 if (cflag & CSTOPB)
1100 uap->curregs[4] |= SB2;
1101 else
1102 uap->curregs[4] |= SB1;
1103 if (cflag & PARENB)
1104 uap->curregs[4] |= PAR_ENAB;
1105 else
1106 uap->curregs[4] &= ~PAR_ENAB;
1107 if (!(cflag & PARODD))
1108 uap->curregs[4] |= PAR_EVEN;
1109 else
1110 uap->curregs[4] &= ~PAR_EVEN;
1111
1112 uap->port.read_status_mask = Rx_OVR;
1113 if (iflag & INPCK)
1114 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1115 if (iflag & (BRKINT | PARMRK))
1116 uap->port.read_status_mask |= BRK_ABRT;
1117
1118 uap->port.ignore_status_mask = 0;
1119 if (iflag & IGNPAR)
1120 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1121 if (iflag & IGNBRK) {
1122 uap->port.ignore_status_mask |= BRK_ABRT;
1123 if (iflag & IGNPAR)
1124 uap->port.ignore_status_mask |= Rx_OVR;
1125 }
1126
1127 if ((cflag & CREAD) == 0)
1128 uap->port.ignore_status_mask = 0xff;
1129 }
1130
1131
1132 /*
1133 * Set the irda codec on the imac to the specified baud rate.
1134 */
1135 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1136 {
1137 u8 cmdbyte;
1138 int t, version;
1139
1140 switch (*baud) {
1141 /* SIR modes */
1142 case 2400:
1143 cmdbyte = 0x53;
1144 break;
1145 case 4800:
1146 cmdbyte = 0x52;
1147 break;
1148 case 9600:
1149 cmdbyte = 0x51;
1150 break;
1151 case 19200:
1152 cmdbyte = 0x50;
1153 break;
1154 case 38400:
1155 cmdbyte = 0x4f;
1156 break;
1157 case 57600:
1158 cmdbyte = 0x4e;
1159 break;
1160 case 115200:
1161 cmdbyte = 0x4d;
1162 break;
1163 /* The FIR modes aren't really supported at this point, how
1164 * do we select the speed ? via the FCR on KeyLargo ?
1165 */
1166 case 1152000:
1167 cmdbyte = 0;
1168 break;
1169 case 4000000:
1170 cmdbyte = 0;
1171 break;
1172 default: /* 9600 */
1173 cmdbyte = 0x51;
1174 *baud = 9600;
1175 break;
1176 }
1177
1178 /* Wait for transmitter to drain */
1179 t = 10000;
1180 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1181 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1182 if (--t <= 0) {
1183 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1184 return;
1185 }
1186 udelay(10);
1187 }
1188
1189 /* Drain the receiver too */
1190 t = 100;
1191 (void)read_zsdata(uap);
1192 (void)read_zsdata(uap);
1193 (void)read_zsdata(uap);
1194 mdelay(10);
1195 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1196 read_zsdata(uap);
1197 mdelay(10);
1198 if (--t <= 0) {
1199 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1200 return;
1201 }
1202 }
1203
1204 /* Switch to command mode */
1205 uap->curregs[R5] |= DTR;
1206 write_zsreg(uap, R5, uap->curregs[R5]);
1207 zssync(uap);
1208 mdelay(1);
1209
1210 /* Switch SCC to 19200 */
1211 pmz_convert_to_zs(uap, CS8, 0, 19200);
1212 pmz_load_zsregs(uap, uap->curregs);
1213 mdelay(1);
1214
1215 /* Write get_version command byte */
1216 write_zsdata(uap, 1);
1217 t = 5000;
1218 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1219 if (--t <= 0) {
1220 dev_err(&uap->dev->ofdev.dev,
1221 "irda_setup timed out on get_version byte\n");
1222 goto out;
1223 }
1224 udelay(10);
1225 }
1226 version = read_zsdata(uap);
1227
1228 if (version < 4) {
1229 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1230 version);
1231 goto out;
1232 }
1233
1234 /* Send speed mode */
1235 write_zsdata(uap, cmdbyte);
1236 t = 5000;
1237 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1238 if (--t <= 0) {
1239 dev_err(&uap->dev->ofdev.dev,
1240 "irda_setup timed out on speed mode byte\n");
1241 goto out;
1242 }
1243 udelay(10);
1244 }
1245 t = read_zsdata(uap);
1246 if (t != cmdbyte)
1247 dev_err(&uap->dev->ofdev.dev,
1248 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1249
1250 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1251 *baud, version);
1252
1253 (void)read_zsdata(uap);
1254 (void)read_zsdata(uap);
1255 (void)read_zsdata(uap);
1256
1257 out:
1258 /* Switch back to data mode */
1259 uap->curregs[R5] &= ~DTR;
1260 write_zsreg(uap, R5, uap->curregs[R5]);
1261 zssync(uap);
1262
1263 (void)read_zsdata(uap);
1264 (void)read_zsdata(uap);
1265 (void)read_zsdata(uap);
1266 }
1267
1268
1269 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1270 struct termios *old)
1271 {
1272 struct uart_pmac_port *uap = to_pmz(port);
1273 unsigned long baud;
1274
1275 pmz_debug("pmz: set_termios()\n");
1276
1277 if (ZS_IS_ASLEEP(uap))
1278 return;
1279
1280 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1281
1282 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1283 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1284 * about the FIR mode and high speed modes. So these are unused. For
1285 * implementing proper support for these, we should probably add some
1286 * DMA as well, at least on the Rx side, which isn't a simple thing
1287 * at this point.
1288 */
1289 if (ZS_IS_IRDA(uap)) {
1290 /* Calc baud rate */
1291 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1292 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1293 /* Cet the irda codec to the right rate */
1294 pmz_irda_setup(uap, &baud);
1295 /* Set final baud rate */
1296 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1297 pmz_load_zsregs(uap, uap->curregs);
1298 zssync(uap);
1299 } else {
1300 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1301 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1302 /* Make sure modem status interrupts are correctly configured */
1303 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1304 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1305 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1306 } else {
1307 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1308 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1309 }
1310
1311 /* Load registers to the chip */
1312 pmz_maybe_update_regs(uap);
1313 }
1314 uart_update_timeout(port, termios->c_cflag, baud);
1315
1316 pmz_debug("pmz: set_termios() done.\n");
1317 }
1318
1319 /* The port lock is not held. */
1320 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1321 struct termios *old)
1322 {
1323 struct uart_pmac_port *uap = to_pmz(port);
1324 unsigned long flags;
1325
1326 spin_lock_irqsave(&port->lock, flags);
1327
1328 /* Disable IRQs on the port */
1329 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1330 write_zsreg(uap, R1, uap->curregs[R1]);
1331
1332 /* Setup new port configuration */
1333 __pmz_set_termios(port, termios, old);
1334
1335 /* Re-enable IRQs on the port */
1336 if (ZS_IS_OPEN(uap)) {
1337 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1338 if (!ZS_IS_EXTCLK(uap))
1339 uap->curregs[R1] |= EXT_INT_ENAB;
1340 write_zsreg(uap, R1, uap->curregs[R1]);
1341 }
1342 spin_unlock_irqrestore(&port->lock, flags);
1343 }
1344
1345 static const char *pmz_type(struct uart_port *port)
1346 {
1347 struct uart_pmac_port *uap = to_pmz(port);
1348
1349 if (ZS_IS_IRDA(uap))
1350 return "Z85c30 ESCC - Infrared port";
1351 else if (ZS_IS_INTMODEM(uap))
1352 return "Z85c30 ESCC - Internal modem";
1353 return "Z85c30 ESCC - Serial port";
1354 }
1355
1356 /* We do not request/release mappings of the registers here, this
1357 * happens at early serial probe time.
1358 */
1359 static void pmz_release_port(struct uart_port *port)
1360 {
1361 }
1362
1363 static int pmz_request_port(struct uart_port *port)
1364 {
1365 return 0;
1366 }
1367
1368 /* These do not need to do anything interesting either. */
1369 static void pmz_config_port(struct uart_port *port, int flags)
1370 {
1371 }
1372
1373 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1374 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1375 {
1376 return -EINVAL;
1377 }
1378
1379 static struct uart_ops pmz_pops = {
1380 .tx_empty = pmz_tx_empty,
1381 .set_mctrl = pmz_set_mctrl,
1382 .get_mctrl = pmz_get_mctrl,
1383 .stop_tx = pmz_stop_tx,
1384 .start_tx = pmz_start_tx,
1385 .stop_rx = pmz_stop_rx,
1386 .enable_ms = pmz_enable_ms,
1387 .break_ctl = pmz_break_ctl,
1388 .startup = pmz_startup,
1389 .shutdown = pmz_shutdown,
1390 .set_termios = pmz_set_termios,
1391 .type = pmz_type,
1392 .release_port = pmz_release_port,
1393 .request_port = pmz_request_port,
1394 .config_port = pmz_config_port,
1395 .verify_port = pmz_verify_port,
1396 };
1397
1398 /*
1399 * Setup one port structure after probing, HW is down at this point,
1400 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1401 * register our console before uart_add_one_port() is called
1402 */
1403 static int __init pmz_init_port(struct uart_pmac_port *uap)
1404 {
1405 struct device_node *np = uap->node;
1406 char *conn;
1407 struct slot_names_prop {
1408 int count;
1409 char name[1];
1410 } *slots;
1411 int len;
1412 struct resource r_ports, r_rxdma, r_txdma;
1413
1414 /*
1415 * Request & map chip registers
1416 */
1417 if (of_address_to_resource(np, 0, &r_ports))
1418 return -ENODEV;
1419 uap->port.mapbase = r_ports.start;
1420 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1421
1422 uap->control_reg = uap->port.membase;
1423 uap->data_reg = uap->control_reg + 0x10;
1424
1425 /*
1426 * Request & map DBDMA registers
1427 */
1428 #ifdef HAS_DBDMA
1429 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1430 of_address_to_resource(np, 2, &r_rxdma) == 0)
1431 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1432 #else
1433 memset(&r_txdma, 0, sizeof(struct resource));
1434 memset(&r_rxdma, 0, sizeof(struct resource));
1435 #endif
1436 if (ZS_HAS_DMA(uap)) {
1437 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1438 if (uap->tx_dma_regs == NULL) {
1439 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1440 goto no_dma;
1441 }
1442 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1443 if (uap->rx_dma_regs == NULL) {
1444 iounmap(uap->tx_dma_regs);
1445 uap->tx_dma_regs = NULL;
1446 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1447 goto no_dma;
1448 }
1449 uap->tx_dma_irq = np->intrs[1].line;
1450 uap->rx_dma_irq = np->intrs[2].line;
1451 }
1452 no_dma:
1453
1454 /*
1455 * Detect port type
1456 */
1457 if (device_is_compatible(np, "cobalt"))
1458 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1459 conn = get_property(np, "AAPL,connector", &len);
1460 if (conn && (strcmp(conn, "infrared") == 0))
1461 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1462 uap->port_type = PMAC_SCC_ASYNC;
1463 /* 1999 Powerbook G3 has slot-names property instead */
1464 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
1465 if (slots && slots->count > 0) {
1466 if (strcmp(slots->name, "IrDA") == 0)
1467 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1468 else if (strcmp(slots->name, "Modem") == 0)
1469 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1470 }
1471 if (ZS_IS_IRDA(uap))
1472 uap->port_type = PMAC_SCC_IRDA;
1473 if (ZS_IS_INTMODEM(uap)) {
1474 struct device_node* i2c_modem = find_devices("i2c-modem");
1475 if (i2c_modem) {
1476 char* mid = get_property(i2c_modem, "modem-id", NULL);
1477 if (mid) switch(*mid) {
1478 case 0x04 :
1479 case 0x05 :
1480 case 0x07 :
1481 case 0x08 :
1482 case 0x0b :
1483 case 0x0c :
1484 uap->port_type = PMAC_SCC_I2S1;
1485 }
1486 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1487 mid ? (*mid) : 0);
1488 } else {
1489 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1490 }
1491 }
1492
1493 /*
1494 * Init remaining bits of "port" structure
1495 */
1496 uap->port.iotype = SERIAL_IO_MEM;
1497 uap->port.irq = np->intrs[0].line;
1498 uap->port.uartclk = ZS_CLOCK;
1499 uap->port.fifosize = 1;
1500 uap->port.ops = &pmz_pops;
1501 uap->port.type = PORT_PMAC_ZILOG;
1502 uap->port.flags = 0;
1503
1504 /* Setup some valid baud rate information in the register
1505 * shadows so we don't write crap there before baud rate is
1506 * first initialized.
1507 */
1508 pmz_convert_to_zs(uap, CS8, 0, 9600);
1509
1510 return 0;
1511 }
1512
1513 /*
1514 * Get rid of a port on module removal
1515 */
1516 static void pmz_dispose_port(struct uart_pmac_port *uap)
1517 {
1518 struct device_node *np;
1519
1520 np = uap->node;
1521 iounmap(uap->rx_dma_regs);
1522 iounmap(uap->tx_dma_regs);
1523 iounmap(uap->control_reg);
1524 uap->node = NULL;
1525 of_node_put(np);
1526 memset(uap, 0, sizeof(struct uart_pmac_port));
1527 }
1528
1529 /*
1530 * Called upon match with an escc node in the devive-tree.
1531 */
1532 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1533 {
1534 int i;
1535
1536 /* Iterate the pmz_ports array to find a matching entry
1537 */
1538 for (i = 0; i < MAX_ZS_PORTS; i++)
1539 if (pmz_ports[i].node == mdev->ofdev.node) {
1540 struct uart_pmac_port *uap = &pmz_ports[i];
1541
1542 uap->dev = mdev;
1543 dev_set_drvdata(&mdev->ofdev.dev, uap);
1544 if (macio_request_resources(uap->dev, "pmac_zilog"))
1545 printk(KERN_WARNING "%s: Failed to request resource"
1546 ", port still active\n",
1547 uap->node->name);
1548 else
1549 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1550 return 0;
1551 }
1552 return -ENODEV;
1553 }
1554
1555 /*
1556 * That one should not be called, macio isn't really a hotswap device,
1557 * we don't expect one of those serial ports to go away...
1558 */
1559 static int pmz_detach(struct macio_dev *mdev)
1560 {
1561 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1562
1563 if (!uap)
1564 return -ENODEV;
1565
1566 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1567 macio_release_resources(uap->dev);
1568 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1569 }
1570 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1571 uap->dev = NULL;
1572
1573 return 0;
1574 }
1575
1576
1577 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1578 {
1579 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1580 struct uart_state *state;
1581 unsigned long flags;
1582
1583 if (uap == NULL) {
1584 printk("HRM... pmz_suspend with NULL uap\n");
1585 return 0;
1586 }
1587
1588 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1589 return 0;
1590
1591 pmz_debug("suspend, switching to state %d\n", pm_state);
1592
1593 state = pmz_uart_reg.state + uap->port.line;
1594
1595 mutex_lock(&pmz_irq_mutex);
1596 down(&state->sem);
1597
1598 spin_lock_irqsave(&uap->port.lock, flags);
1599
1600 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1601 /* Disable receiver and transmitter. */
1602 uap->curregs[R3] &= ~RxENABLE;
1603 uap->curregs[R5] &= ~TxENABLE;
1604
1605 /* Disable all interrupts and BRK assertion. */
1606 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1607 uap->curregs[R5] &= ~SND_BRK;
1608 pmz_load_zsregs(uap, uap->curregs);
1609 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1610 mb();
1611 }
1612
1613 spin_unlock_irqrestore(&uap->port.lock, flags);
1614
1615 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1616 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1617 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1618 disable_irq(uap->port.irq);
1619 }
1620
1621 if (ZS_IS_CONS(uap))
1622 uap->port.cons->flags &= ~CON_ENABLED;
1623
1624 /* Shut the chip down */
1625 pmz_set_scc_power(uap, 0);
1626
1627 up(&state->sem);
1628 mutex_unlock(&pmz_irq_mutex);
1629
1630 pmz_debug("suspend, switching complete\n");
1631
1632 mdev->ofdev.dev.power.power_state = pm_state;
1633
1634 return 0;
1635 }
1636
1637
1638 static int pmz_resume(struct macio_dev *mdev)
1639 {
1640 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1641 struct uart_state *state;
1642 unsigned long flags;
1643 int pwr_delay = 0;
1644
1645 if (uap == NULL)
1646 return 0;
1647
1648 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1649 return 0;
1650
1651 pmz_debug("resume, switching to state 0\n");
1652
1653 state = pmz_uart_reg.state + uap->port.line;
1654
1655 mutex_lock(&pmz_irq_mutex);
1656 down(&state->sem);
1657
1658 spin_lock_irqsave(&uap->port.lock, flags);
1659 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1660 spin_unlock_irqrestore(&uap->port.lock, flags);
1661 goto bail;
1662 }
1663 pwr_delay = __pmz_startup(uap);
1664
1665 /* Take care of config that may have changed while asleep */
1666 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1667
1668 if (ZS_IS_OPEN(uap)) {
1669 /* Enable interrupts */
1670 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1671 if (!ZS_IS_EXTCLK(uap))
1672 uap->curregs[R1] |= EXT_INT_ENAB;
1673 write_zsreg(uap, R1, uap->curregs[R1]);
1674 }
1675
1676 spin_unlock_irqrestore(&uap->port.lock, flags);
1677
1678 if (ZS_IS_CONS(uap))
1679 uap->port.cons->flags |= CON_ENABLED;
1680
1681 /* Re-enable IRQ on the controller */
1682 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1683 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1684 enable_irq(uap->port.irq);
1685 }
1686
1687 bail:
1688 up(&state->sem);
1689 mutex_unlock(&pmz_irq_mutex);
1690
1691 /* Right now, we deal with delay by blocking here, I'll be
1692 * smarter later on
1693 */
1694 if (pwr_delay != 0) {
1695 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1696 msleep(pwr_delay);
1697 }
1698
1699 pmz_debug("resume, switching complete\n");
1700
1701 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1702
1703 return 0;
1704 }
1705
1706 /*
1707 * Probe all ports in the system and build the ports array, we register
1708 * with the serial layer at this point, the macio-type probing is only
1709 * used later to "attach" to the sysfs tree so we get power management
1710 * events
1711 */
1712 static int __init pmz_probe(void)
1713 {
1714 struct device_node *node_p, *node_a, *node_b, *np;
1715 int count = 0;
1716 int rc;
1717
1718 /*
1719 * Find all escc chips in the system
1720 */
1721 node_p = of_find_node_by_name(NULL, "escc");
1722 while (node_p) {
1723 /*
1724 * First get channel A/B node pointers
1725 *
1726 * TODO: Add routines with proper locking to do that...
1727 */
1728 node_a = node_b = NULL;
1729 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1730 if (strncmp(np->name, "ch-a", 4) == 0)
1731 node_a = of_node_get(np);
1732 else if (strncmp(np->name, "ch-b", 4) == 0)
1733 node_b = of_node_get(np);
1734 }
1735 if (!node_a && !node_b) {
1736 of_node_put(node_a);
1737 of_node_put(node_b);
1738 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1739 (!node_a) ? 'a' : 'b', node_p->full_name);
1740 goto next;
1741 }
1742
1743 /*
1744 * Fill basic fields in the port structures
1745 */
1746 pmz_ports[count].mate = &pmz_ports[count+1];
1747 pmz_ports[count+1].mate = &pmz_ports[count];
1748 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1749 pmz_ports[count].node = node_a;
1750 pmz_ports[count+1].node = node_b;
1751 pmz_ports[count].port.line = count;
1752 pmz_ports[count+1].port.line = count+1;
1753
1754 /*
1755 * Setup the ports for real
1756 */
1757 rc = pmz_init_port(&pmz_ports[count]);
1758 if (rc == 0 && node_b != NULL)
1759 rc = pmz_init_port(&pmz_ports[count+1]);
1760 if (rc != 0) {
1761 of_node_put(node_a);
1762 of_node_put(node_b);
1763 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1764 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1765 goto next;
1766 }
1767 count += 2;
1768 next:
1769 node_p = of_find_node_by_name(node_p, "escc");
1770 }
1771 pmz_ports_count = count;
1772
1773 return 0;
1774 }
1775
1776 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1777
1778 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1779 static int __init pmz_console_setup(struct console *co, char *options);
1780
1781 static struct console pmz_console = {
1782 .name = "ttyS",
1783 .write = pmz_console_write,
1784 .device = uart_console_device,
1785 .setup = pmz_console_setup,
1786 .flags = CON_PRINTBUFFER,
1787 .index = -1,
1788 .data = &pmz_uart_reg,
1789 };
1790
1791 #define PMACZILOG_CONSOLE &pmz_console
1792 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1793 #define PMACZILOG_CONSOLE (NULL)
1794 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1795
1796 /*
1797 * Register the driver, console driver and ports with the serial
1798 * core
1799 */
1800 static int __init pmz_register(void)
1801 {
1802 int i, rc;
1803
1804 pmz_uart_reg.nr = pmz_ports_count;
1805 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1806 pmz_uart_reg.minor = 64;
1807
1808 /*
1809 * Register this driver with the serial core
1810 */
1811 rc = uart_register_driver(&pmz_uart_reg);
1812 if (rc)
1813 return rc;
1814
1815 /*
1816 * Register each port with the serial core
1817 */
1818 for (i = 0; i < pmz_ports_count; i++) {
1819 struct uart_pmac_port *uport = &pmz_ports[i];
1820 /* NULL node may happen on wallstreet */
1821 if (uport->node != NULL)
1822 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1823 if (rc)
1824 goto err_out;
1825 }
1826
1827 return 0;
1828 err_out:
1829 while (i-- > 0) {
1830 struct uart_pmac_port *uport = &pmz_ports[i];
1831 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1832 }
1833 uart_unregister_driver(&pmz_uart_reg);
1834 return rc;
1835 }
1836
1837 static struct of_device_id pmz_match[] =
1838 {
1839 {
1840 .name = "ch-a",
1841 },
1842 {
1843 .name = "ch-b",
1844 },
1845 {},
1846 };
1847 MODULE_DEVICE_TABLE (of, pmz_match);
1848
1849 static struct macio_driver pmz_driver =
1850 {
1851 .name = "pmac_zilog",
1852 .match_table = pmz_match,
1853 .probe = pmz_attach,
1854 .remove = pmz_detach,
1855 .suspend = pmz_suspend,
1856 .resume = pmz_resume,
1857 };
1858
1859 static int __init init_pmz(void)
1860 {
1861 int rc, i;
1862 printk(KERN_INFO "%s\n", version);
1863
1864 /*
1865 * First, we need to do a direct OF-based probe pass. We
1866 * do that because we want serial console up before the
1867 * macio stuffs calls us back, and since that makes it
1868 * easier to pass the proper number of channels to
1869 * uart_register_driver()
1870 */
1871 if (pmz_ports_count == 0)
1872 pmz_probe();
1873
1874 /*
1875 * Bail early if no port found
1876 */
1877 if (pmz_ports_count == 0)
1878 return -ENODEV;
1879
1880 /*
1881 * Now we register with the serial layer
1882 */
1883 rc = pmz_register();
1884 if (rc) {
1885 printk(KERN_ERR
1886 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1887 "pmac_zilog: Did another serial driver already claim the minors?\n");
1888 /* effectively "pmz_unprobe()" */
1889 for (i=0; i < pmz_ports_count; i++)
1890 pmz_dispose_port(&pmz_ports[i]);
1891 return rc;
1892 }
1893
1894 /*
1895 * Then we register the macio driver itself
1896 */
1897 return macio_register_driver(&pmz_driver);
1898 }
1899
1900 static void __exit exit_pmz(void)
1901 {
1902 int i;
1903
1904 /* Get rid of macio-driver (detach from macio) */
1905 macio_unregister_driver(&pmz_driver);
1906
1907 for (i = 0; i < pmz_ports_count; i++) {
1908 struct uart_pmac_port *uport = &pmz_ports[i];
1909 if (uport->node != NULL) {
1910 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1911 pmz_dispose_port(uport);
1912 }
1913 }
1914 /* Unregister UART driver */
1915 uart_unregister_driver(&pmz_uart_reg);
1916 }
1917
1918 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1919
1920 /*
1921 * Print a string to the serial port trying not to disturb
1922 * any possible real use of the port...
1923 */
1924 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1925 {
1926 struct uart_pmac_port *uap = &pmz_ports[con->index];
1927 unsigned long flags;
1928 int i;
1929
1930 if (ZS_IS_ASLEEP(uap))
1931 return;
1932 spin_lock_irqsave(&uap->port.lock, flags);
1933
1934 /* Turn of interrupts and enable the transmitter. */
1935 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1936 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1937
1938 for (i = 0; i < count; i++) {
1939 /* Wait for the transmit buffer to empty. */
1940 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1941 udelay(5);
1942 write_zsdata(uap, s[i]);
1943 if (s[i] == 10) {
1944 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1945 udelay(5);
1946 write_zsdata(uap, R13);
1947 }
1948 }
1949
1950 /* Restore the values in the registers. */
1951 write_zsreg(uap, R1, uap->curregs[1]);
1952 /* Don't disable the transmitter. */
1953
1954 spin_unlock_irqrestore(&uap->port.lock, flags);
1955 }
1956
1957 /*
1958 * Setup the serial console
1959 */
1960 static int __init pmz_console_setup(struct console *co, char *options)
1961 {
1962 struct uart_pmac_port *uap;
1963 struct uart_port *port;
1964 int baud = 38400;
1965 int bits = 8;
1966 int parity = 'n';
1967 int flow = 'n';
1968 unsigned long pwr_delay;
1969
1970 /*
1971 * XServe's default to 57600 bps
1972 */
1973 if (machine_is_compatible("RackMac1,1")
1974 || machine_is_compatible("RackMac1,2")
1975 || machine_is_compatible("MacRISC4"))
1976 baud = 57600;
1977
1978 /*
1979 * Check whether an invalid uart number has been specified, and
1980 * if so, search for the first available port that does have
1981 * console support.
1982 */
1983 if (co->index >= pmz_ports_count)
1984 co->index = 0;
1985 uap = &pmz_ports[co->index];
1986 if (uap->node == NULL)
1987 return -ENODEV;
1988 port = &uap->port;
1989
1990 /*
1991 * Mark port as beeing a console
1992 */
1993 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1994
1995 /*
1996 * Temporary fix for uart layer who didn't setup the spinlock yet
1997 */
1998 spin_lock_init(&port->lock);
1999
2000 /*
2001 * Enable the hardware
2002 */
2003 pwr_delay = __pmz_startup(uap);
2004 if (pwr_delay)
2005 mdelay(pwr_delay);
2006
2007 if (options)
2008 uart_parse_options(options, &baud, &parity, &bits, &flow);
2009
2010 return uart_set_options(port, co, baud, parity, bits, flow);
2011 }
2012
2013 static int __init pmz_console_init(void)
2014 {
2015 /* Probe ports */
2016 pmz_probe();
2017
2018 /* TODO: Autoprobe console based on OF */
2019 /* pmz_console.index = i; */
2020 register_console(&pmz_console);
2021
2022 return 0;
2023
2024 }
2025 console_initcall(pmz_console_init);
2026 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2027
2028 module_init(init_pmz);
2029 module_exit(exit_pmz);
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