?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] Support register switch in nommu mode
[linux-2.6/verdex.git] / sound / pci / es1968.c
blob9ffb600321cbb78ffdedd4ebcf9f61e3e6dcb6b6
1 /*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97 #include <sound/driver.h>
98 #include <asm/io.h>
99 #include <linux/delay.h>
100 #include <linux/interrupt.h>
101 #include <linux/init.h>
102 #include <linux/pci.h>
103 #include <linux/slab.h>
104 #include <linux/gameport.h>
105 #include <linux/moduleparam.h>
106 #include <sound/core.h>
107 #include <sound/pcm.h>
108 #include <sound/mpu401.h>
109 #include <sound/ac97_codec.h>
110 #include <sound/initval.h>
111
112 #define CARD_NAME "ESS Maestro1/2"
113 #define DRIVER_NAME "ES1968"
114
115 MODULE_DESCRIPTION("ESS Maestro");
116 MODULE_LICENSE("GPL");
117 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
118 "{ESS,Maestro 2},"
119 "{ESS,Maestro 1},"
120 "{TerraTec,DMX}}");
121
122 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
123 #define SUPPORT_JOYSTICK 1
124 #endif
125
126 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
127 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
128 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
129 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
130 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
131 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
132 static int clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
133 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
134 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
135 #ifdef SUPPORT_JOYSTICK
136 static int joystick[SNDRV_CARDS];
137 #endif
138
139 module_param_array(index, int, NULL, 0444);
140 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
141 module_param_array(id, charp, NULL, 0444);
142 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
143 module_param_array(enable, bool, NULL, 0444);
144 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
145 module_param_array(total_bufsize, int, NULL, 0444);
146 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
147 module_param_array(pcm_substreams_p, int, NULL, 0444);
148 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
149 module_param_array(pcm_substreams_c, int, NULL, 0444);
150 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
151 module_param_array(clock, int, NULL, 0444);
152 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
153 module_param_array(use_pm, int, NULL, 0444);
154 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
155 module_param_array(enable_mpu, int, NULL, 0444);
156 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
157 #ifdef SUPPORT_JOYSTICK
158 module_param_array(joystick, bool, NULL, 0444);
159 MODULE_PARM_DESC(joystick, "Enable joystick.");
160 #endif
161
162
163 #define NR_APUS 64
164 #define NR_APU_REGS 16
165
166 /* NEC Versas ? */
167 #define NEC_VERSA_SUBID1 0x80581033
168 #define NEC_VERSA_SUBID2 0x803c1033
169
170 /* Mode Flags */
171 #define ESS_FMT_STEREO 0x01
172 #define ESS_FMT_16BIT 0x02
173
174 #define DAC_RUNNING 1
175 #define ADC_RUNNING 2
176
177 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
178
179 #define ESS_DISABLE_AUDIO 0x8000
180 #define ESS_ENABLE_SERIAL_IRQ 0x4000
181 #define IO_ADRESS_ALIAS 0x0020
182 #define MPU401_IRQ_ENABLE 0x0010
183 #define MPU401_IO_ENABLE 0x0008
184 #define GAME_IO_ENABLE 0x0004
185 #define FM_IO_ENABLE 0x0002
186 #define SB_IO_ENABLE 0x0001
187
188 /* Values for the ESM_CONFIG_A */
189
190 #define PIC_SNOOP1 0x4000
191 #define PIC_SNOOP2 0x2000
192 #define SAFEGUARD 0x0800
193 #define DMA_CLEAR 0x0700
194 #define DMA_DDMA 0x0000
195 #define DMA_TDMA 0x0100
196 #define DMA_PCPCI 0x0200
197 #define POST_WRITE 0x0080
198 #define PCI_TIMING 0x0040
199 #define SWAP_LR 0x0020
200 #define SUBTR_DECODE 0x0002
201
202 /* Values for the ESM_CONFIG_B */
203
204 #define SPDIF_CONFB 0x0100
205 #define HWV_CONFB 0x0080
206 #define DEBOUNCE 0x0040
207 #define GPIO_CONFB 0x0020
208 #define CHI_CONFB 0x0010
209 #define IDMA_CONFB 0x0008 /*undoc */
210 #define MIDI_FIX 0x0004 /*undoc */
211 #define IRQ_TO_ISA 0x0001 /*undoc */
212
213 /* Values for Ring Bus Control B */
214 #define RINGB_2CODEC_ID_MASK 0x0003
215 #define RINGB_DIS_VALIDATION 0x0008
216 #define RINGB_EN_SPDIF 0x0010
217 #define RINGB_EN_2CODEC 0x0020
218 #define RINGB_SING_BIT_DUAL 0x0040
219
220 /* ****Port Adresses**** */
221
222 /* Write & Read */
223 #define ESM_INDEX 0x02
224 #define ESM_DATA 0x00
225
226 /* AC97 + RingBus */
227 #define ESM_AC97_INDEX 0x30
228 #define ESM_AC97_DATA 0x32
229 #define ESM_RING_BUS_DEST 0x34
230 #define ESM_RING_BUS_CONTR_A 0x36
231 #define ESM_RING_BUS_CONTR_B 0x38
232 #define ESM_RING_BUS_SDO 0x3A
233
234 /* WaveCache*/
235 #define WC_INDEX 0x10
236 #define WC_DATA 0x12
237 #define WC_CONTROL 0x14
238
239 /* ASSP*/
240 #define ASSP_INDEX 0x80
241 #define ASSP_MEMORY 0x82
242 #define ASSP_DATA 0x84
243 #define ASSP_CONTROL_A 0xA2
244 #define ASSP_CONTROL_B 0xA4
245 #define ASSP_CONTROL_C 0xA6
246 #define ASSP_HOSTW_INDEX 0xA8
247 #define ASSP_HOSTW_DATA 0xAA
248 #define ASSP_HOSTW_IRQ 0xAC
249 /* Midi */
250 #define ESM_MPU401_PORT 0x98
251 /* Others */
252 #define ESM_PORT_HOST_IRQ 0x18
253
254 #define IDR0_DATA_PORT 0x00
255 #define IDR1_CRAM_POINTER 0x01
256 #define IDR2_CRAM_DATA 0x02
257 #define IDR3_WAVE_DATA 0x03
258 #define IDR4_WAVE_PTR_LOW 0x04
259 #define IDR5_WAVE_PTR_HI 0x05
260 #define IDR6_TIMER_CTRL 0x06
261 #define IDR7_WAVE_ROMRAM 0x07
262
263 #define WRITEABLE_MAP 0xEFFFFF
264 #define READABLE_MAP 0x64003F
265
266 /* PCI Register */
267
268 #define ESM_LEGACY_AUDIO_CONTROL 0x40
269 #define ESM_ACPI_COMMAND 0x54
270 #define ESM_CONFIG_A 0x50
271 #define ESM_CONFIG_B 0x52
272 #define ESM_DDMA 0x60
273
274 /* Bob Bits */
275 #define ESM_BOB_ENABLE 0x0001
276 #define ESM_BOB_START 0x0001
277
278 /* Host IRQ Control Bits */
279 #define ESM_RESET_MAESTRO 0x8000
280 #define ESM_RESET_DIRECTSOUND 0x4000
281 #define ESM_HIRQ_ClkRun 0x0100
282 #define ESM_HIRQ_HW_VOLUME 0x0040
283 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
284 #define ESM_HIRQ_ASSP 0x0010
285 #define ESM_HIRQ_DSIE 0x0004
286 #define ESM_HIRQ_MPU401 0x0002
287 #define ESM_HIRQ_SB 0x0001
288
289 /* Host IRQ Status Bits */
290 #define ESM_MPU401_IRQ 0x02
291 #define ESM_SB_IRQ 0x01
292 #define ESM_SOUND_IRQ 0x04
293 #define ESM_ASSP_IRQ 0x10
294 #define ESM_HWVOL_IRQ 0x40
295
296 #define ESS_SYSCLK 50000000
297 #define ESM_BOB_FREQ 200
298 #define ESM_BOB_FREQ_MAX 800
299
300 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
301 #define ESM_FREQ_ESM2 (50000000L / 1024L)
302
303 /* APU Modes: reg 0x00, bit 4-7 */
304 #define ESM_APU_MODE_SHIFT 4
305 #define ESM_APU_MODE_MASK (0xf << 4)
306 #define ESM_APU_OFF 0x00
307 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
308 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
309 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
310 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
311 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
312 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
313 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
314 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
315 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
316 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
317 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
318 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
319 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
320 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
321 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
322
323 /* reg 0x00 */
324 #define ESM_APU_FILTER_Q_SHIFT 0
325 #define ESM_APU_FILTER_Q_MASK (3 << 0)
326 /* APU Filtey Q Control */
327 #define ESM_APU_FILTER_LESSQ 0x00
328 #define ESM_APU_FILTER_MOREQ 0x03
329
330 #define ESM_APU_FILTER_TYPE_SHIFT 2
331 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
332 #define ESM_APU_ENV_TYPE_SHIFT 8
333 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
334 #define ESM_APU_ENV_STATE_SHIFT 10
335 #define ESM_APU_ENV_STATE_MASK (3 << 10)
336 #define ESM_APU_END_CURVE (1 << 12)
337 #define ESM_APU_INT_ON_LOOP (1 << 13)
338 #define ESM_APU_DMA_ENABLE (1 << 14)
339
340 /* reg 0x02 */
341 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
342 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
343 #define ESM_APU_SUBMIX_MODE (1 << 3)
344 #define ESM_APU_6dB (1 << 4)
345 #define ESM_APU_DUAL_EFFECT (1 << 5)
346 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
347 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
348
349 /* reg 0x03 */
350 #define ESM_APU_STEP_SIZE_MASK 0x0fff
351
352 /* reg 0x04 */
353 #define ESM_APU_PHASE_SHIFT 0
354 #define ESM_APU_PHASE_MASK (0xff << 0)
355 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
356 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
357
358 /* reg 0x05 - wave start offset */
359 /* reg 0x06 - wave end offset */
360 /* reg 0x07 - wave loop length */
361
362 /* reg 0x08 */
363 #define ESM_APU_EFFECT_GAIN_SHIFT 0
364 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
365 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
366 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
367 #define ESM_APU_TREMOLO_RATE_SHIFT 12
368 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
369
370 /* reg 0x09 */
371 /* bit 0-7 amplitude dest? */
372 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
373 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
374
375 /* reg 0x0a */
376 #define ESM_APU_POLAR_PAN_SHIFT 0
377 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
378 /* Polar Pan Control */
379 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
380 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
381 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
382
383 #define ESM_APU_FILTER_TUNING_SHIFT 8
384 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
385
386 /* reg 0x0b */
387 #define ESM_APU_DATA_SRC_A_SHIFT 0
388 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
389 #define ESM_APU_INV_POL_A (1 << 7)
390 #define ESM_APU_DATA_SRC_B_SHIFT 8
391 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
392 #define ESM_APU_INV_POL_B (1 << 15)
393
394 #define ESM_APU_VIBRATO_RATE_SHIFT 0
395 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
396 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
397 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
398 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
399 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
400
401 /* reg 0x0c */
402 #define ESM_APU_RADIUS_SELECT (1 << 6)
403
404 /* APU Filter Control */
405 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
406 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
407 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
408 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
409 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
410 #define ESM_APU_FILTER_OFF 0x05
411
412 /* APU ATFP Type */
413 #define ESM_APU_ATFP_AMPLITUDE 0x00
414 #define ESM_APU_ATFP_TREMELO 0x01
415 #define ESM_APU_ATFP_FILTER 0x02
416 #define ESM_APU_ATFP_PAN 0x03
417
418 /* APU ATFP Flags */
419 #define ESM_APU_ATFP_FLG_OFF 0x00
420 #define ESM_APU_ATFP_FLG_WAIT 0x01
421 #define ESM_APU_ATFP_FLG_DONE 0x02
422 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
423
424
425 /* capture mixing buffer size */
426 #define ESM_MEM_ALIGN 0x1000
427 #define ESM_MIXBUF_SIZE 0x400
428
429 #define ESM_MODE_PLAY 0
430 #define ESM_MODE_CAPTURE 1
431
432 /* acpi states */
433 enum {
434 ACPI_D0=0,
435 ACPI_D1,
436 ACPI_D2,
437 ACPI_D3
438 };
439
440 /* bits in the acpi masks */
441 #define ACPI_12MHZ ( 1 << 15)
442 #define ACPI_24MHZ ( 1 << 14)
443 #define ACPI_978 ( 1 << 13)
444 #define ACPI_SPDIF ( 1 << 12)
445 #define ACPI_GLUE ( 1 << 11)
446 #define ACPI__10 ( 1 << 10) /* reserved */
447 #define ACPI_PCIINT ( 1 << 9)
448 #define ACPI_HV ( 1 << 8) /* hardware volume */
449 #define ACPI_GPIO ( 1 << 7)
450 #define ACPI_ASSP ( 1 << 6)
451 #define ACPI_SB ( 1 << 5) /* sb emul */
452 #define ACPI_FM ( 1 << 4) /* fm emul */
453 #define ACPI_RB ( 1 << 3) /* ringbus / aclink */
454 #define ACPI_MIDI ( 1 << 2)
455 #define ACPI_GP ( 1 << 1) /* game port */
456 #define ACPI_WP ( 1 << 0) /* wave processor */
457
458 #define ACPI_ALL (0xffff)
459 #define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \
460 ACPI_MIDI|ACPI_GP|ACPI_WP))
461 #define ACPI_NONE (ACPI__10)
462
463 /* these masks indicate which units we care about at
464 which states */
465 static u16 acpi_state_mask[] = {
466 [ACPI_D0] = ACPI_ALL,
467 [ACPI_D1] = ACPI_SLEEP,
468 [ACPI_D2] = ACPI_SLEEP,
469 [ACPI_D3] = ACPI_NONE
470 };
471
472
473 /* APU use in the driver */
474 enum snd_enum_apu_type {
475 ESM_APU_PCM_PLAY,
476 ESM_APU_PCM_CAPTURE,
477 ESM_APU_PCM_RATECONV,
478 ESM_APU_FREE
479 };
480
481 /* chip type */
482 enum {
483 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
484 };
485
486 /* DMA Hack! */
487 struct esm_memory {
488 struct snd_dma_buffer buf;
489 int empty; /* status */
490 struct list_head list;
491 };
492
493 /* Playback Channel */
494 struct esschan {
495 int running;
496
497 u8 apu[4];
498 u8 apu_mode[4];
499
500 /* playback/capture pcm buffer */
501 struct esm_memory *memory;
502 /* capture mixer buffer */
503 struct esm_memory *mixbuf;
504
505 unsigned int hwptr; /* current hw pointer in bytes */
506 unsigned int count; /* sample counter in bytes */
507 unsigned int dma_size; /* total buffer size in bytes */
508 unsigned int frag_size; /* period size in bytes */
509 unsigned int wav_shift;
510 u16 base[4]; /* offset for ptr */
511
512 /* stereo/16bit flag */
513 unsigned char fmt;
514 int mode; /* playback / capture */
515
516 int bob_freq; /* required timer frequency */
517
518 struct snd_pcm_substream *substream;
519
520 /* linked list */
521 struct list_head list;
522
523 #ifdef CONFIG_PM
524 u16 wc_map[4];
525 #endif
526 };
527
528 struct es1968 {
529 /* Module Config */
530 int total_bufsize; /* in bytes */
531
532 int playback_streams, capture_streams;
533
534 unsigned int clock; /* clock */
535 /* for clock measurement */
536 unsigned int in_measurement: 1;
537 unsigned int measure_apu;
538 unsigned int measure_lastpos;
539 unsigned int measure_count;
540
541 /* buffer */
542 struct snd_dma_buffer dma;
543
544 /* Resources... */
545 int irq;
546 unsigned long io_port;
547 int type;
548 struct pci_dev *pci;
549 struct snd_card *card;
550 struct snd_pcm *pcm;
551 int do_pm; /* power-management enabled */
552
553 /* DMA memory block */
554 struct list_head buf_list;
555
556 /* ALSA Stuff */
557 struct snd_ac97 *ac97;
558 struct snd_kcontrol *master_switch; /* for h/w volume control */
559 struct snd_kcontrol *master_volume;
560
561 struct snd_rawmidi *rmidi;
562
563 spinlock_t reg_lock;
564 spinlock_t ac97_lock;
565 struct tasklet_struct hwvol_tq;
566 unsigned int in_suspend;
567
568 /* Maestro Stuff */
569 u16 maestro_map[32];
570 int bobclient; /* active timer instancs */
571 int bob_freq; /* timer frequency */
572 struct semaphore memory_mutex; /* memory lock */
573
574 /* APU states */
575 unsigned char apu[NR_APUS];
576
577 /* active substreams */
578 struct list_head substream_list;
579 spinlock_t substream_lock;
580
581 #ifdef CONFIG_PM
582 u16 apu_map[NR_APUS][NR_APU_REGS];
583 #endif
584
585 #ifdef SUPPORT_JOYSTICK
586 struct gameport *gameport;
587 #endif
588 };
589
590 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs);
591
592 static struct pci_device_id snd_es1968_ids[] = {
593 /* Maestro 1 */
594 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
595 /* Maestro 2 */
596 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
597 /* Maestro 2E */
598 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
599 { 0, }
600 };
601
602 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
603
604 /* *********************
605 * Low Level Funcs! *
606 *********************/
607
608 /* no spinlock */
609 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
610 {
611 outw(reg, chip->io_port + ESM_INDEX);
612 outw(data, chip->io_port + ESM_DATA);
613 chip->maestro_map[reg] = data;
614 }
615
616 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
617 {
618 unsigned long flags;
619 spin_lock_irqsave(&chip->reg_lock, flags);
620 __maestro_write(chip, reg, data);
621 spin_unlock_irqrestore(&chip->reg_lock, flags);
622 }
623
624 /* no spinlock */
625 static u16 __maestro_read(struct es1968 *chip, u16 reg)
626 {
627 if (READABLE_MAP & (1 << reg)) {
628 outw(reg, chip->io_port + ESM_INDEX);
629 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
630 }
631 return chip->maestro_map[reg];
632 }
633
634 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
635 {
636 unsigned long flags;
637 u16 result;
638 spin_lock_irqsave(&chip->reg_lock, flags);
639 result = __maestro_read(chip, reg);
640 spin_unlock_irqrestore(&chip->reg_lock, flags);
641 return result;
642 }
643
644 /* Wait for the codec bus to be free */
645 static int snd_es1968_ac97_wait(struct es1968 *chip)
646 {
647 int timeout = 100000;
648
649 while (timeout-- > 0) {
650 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
651 return 0;
652 cond_resched();
653 }
654 snd_printd("es1968: ac97 timeout\n");
655 return 1; /* timeout */
656 }
657
658 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
659 {
660 struct es1968 *chip = ac97->private_data;
661 unsigned long flags;
662
663 snd_es1968_ac97_wait(chip);
664
665 /* Write the bus */
666 spin_lock_irqsave(&chip->ac97_lock, flags);
667 outw(val, chip->io_port + ESM_AC97_DATA);
668 /*msleep(1);*/
669 outb(reg, chip->io_port + ESM_AC97_INDEX);
670 /*msleep(1);*/
671 spin_unlock_irqrestore(&chip->ac97_lock, flags);
672 }
673
674 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
675 {
676 u16 data = 0;
677 struct es1968 *chip = ac97->private_data;
678 unsigned long flags;
679
680 snd_es1968_ac97_wait(chip);
681
682 spin_lock_irqsave(&chip->ac97_lock, flags);
683 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
684 /*msleep(1);*/
685
686 if (! snd_es1968_ac97_wait(chip)) {
687 data = inw(chip->io_port + ESM_AC97_DATA);
688 /*msleep(1);*/
689 }
690 spin_unlock_irqrestore(&chip->ac97_lock, flags);
691
692 return data;
693 }
694
695 /* no spinlock */
696 static void apu_index_set(struct es1968 *chip, u16 index)
697 {
698 int i;
699 __maestro_write(chip, IDR1_CRAM_POINTER, index);
700 for (i = 0; i < 1000; i++)
701 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
702 return;
703 snd_printd("es1968: APU register select failed. (Timeout)\n");
704 }
705
706 /* no spinlock */
707 static void apu_data_set(struct es1968 *chip, u16 data)
708 {
709 int i;
710 for (i = 0; i < 1000; i++) {
711 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
712 return;
713 __maestro_write(chip, IDR0_DATA_PORT, data);
714 }
715 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
716 }
717
718 /* no spinlock */
719 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
720 {
721 snd_assert(channel < NR_APUS, return);
722 #ifdef CONFIG_PM
723 chip->apu_map[channel][reg] = data;
724 #endif
725 reg |= (channel << 4);
726 apu_index_set(chip, reg);
727 apu_data_set(chip, data);
728 }
729
730 static inline void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
731 {
732 unsigned long flags;
733 spin_lock_irqsave(&chip->reg_lock, flags);
734 __apu_set_register(chip, channel, reg, data);
735 spin_unlock_irqrestore(&chip->reg_lock, flags);
736 }
737
738 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
739 {
740 snd_assert(channel < NR_APUS, return 0);
741 reg |= (channel << 4);
742 apu_index_set(chip, reg);
743 return __maestro_read(chip, IDR0_DATA_PORT);
744 }
745
746 static inline u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
747 {
748 unsigned long flags;
749 u16 v;
750 spin_lock_irqsave(&chip->reg_lock, flags);
751 v = __apu_get_register(chip, channel, reg);
752 spin_unlock_irqrestore(&chip->reg_lock, flags);
753 return v;
754 }
755
756 #if 0 /* ASSP is not supported */
757
758 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
759 {
760 unsigned long flags;
761
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 outl(reg, chip->io_port + ASSP_INDEX);
764 outl(value, chip->io_port + ASSP_DATA);
765 spin_unlock_irqrestore(&chip->reg_lock, flags);
766 }
767
768 static u32 assp_get_register(struct es1968 *chip, u32 reg)
769 {
770 unsigned long flags;
771 u32 value;
772
773 spin_lock_irqsave(&chip->reg_lock, flags);
774 outl(reg, chip->io_port + ASSP_INDEX);
775 value = inl(chip->io_port + ASSP_DATA);
776 spin_unlock_irqrestore(&chip->reg_lock, flags);
777
778 return value;
779 }
780
781 #endif
782
783 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
784 {
785 unsigned long flags;
786
787 spin_lock_irqsave(&chip->reg_lock, flags);
788 outw(reg, chip->io_port + WC_INDEX);
789 outw(value, chip->io_port + WC_DATA);
790 spin_unlock_irqrestore(&chip->reg_lock, flags);
791 }
792
793 static u16 wave_get_register(struct es1968 *chip, u16 reg)
794 {
795 unsigned long flags;
796 u16 value;
797
798 spin_lock_irqsave(&chip->reg_lock, flags);
799 outw(reg, chip->io_port + WC_INDEX);
800 value = inw(chip->io_port + WC_DATA);
801 spin_unlock_irqrestore(&chip->reg_lock, flags);
802
803 return value;
804 }
805
806 /* *******************
807 * Bob the Timer! *
808 *******************/
809
810 static void snd_es1968_bob_stop(struct es1968 *chip)
811 {
812 u16 reg;
813
814 reg = __maestro_read(chip, 0x11);
815 reg &= ~ESM_BOB_ENABLE;
816 __maestro_write(chip, 0x11, reg);
817 reg = __maestro_read(chip, 0x17);
818 reg &= ~ESM_BOB_START;
819 __maestro_write(chip, 0x17, reg);
820 }
821
822 static void snd_es1968_bob_start(struct es1968 *chip)
823 {
824 int prescale;
825 int divide;
826
827 /* compute ideal interrupt frequency for buffer size & play rate */
828 /* first, find best prescaler value to match freq */
829 for (prescale = 5; prescale < 12; prescale++)
830 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
831 break;
832
833 /* next, back off prescaler whilst getting divider into optimum range */
834 divide = 1;
835 while ((prescale > 5) && (divide < 32)) {
836 prescale--;
837 divide <<= 1;
838 }
839 divide >>= 1;
840
841 /* now fine-tune the divider for best match */
842 for (; divide < 31; divide++)
843 if (chip->bob_freq >
844 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
845
846 /* divide = 0 is illegal, but don't let prescale = 4! */
847 if (divide == 0) {
848 divide++;
849 if (prescale > 5)
850 prescale--;
851 } else if (divide > 1)
852 divide--;
853
854 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
855
856 /* Now set IDR 11/17 */
857 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
858 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
859 }
860
861 /* call with substream spinlock */
862 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
863 {
864 chip->bobclient++;
865 if (chip->bobclient == 1) {
866 chip->bob_freq = freq;
867 snd_es1968_bob_start(chip);
868 } else if (chip->bob_freq < freq) {
869 snd_es1968_bob_stop(chip);
870 chip->bob_freq = freq;
871 snd_es1968_bob_start(chip);
872 }
873 }
874
875 /* call with substream spinlock */
876 static void snd_es1968_bob_dec(struct es1968 *chip)
877 {
878 chip->bobclient--;
879 if (chip->bobclient <= 0)
880 snd_es1968_bob_stop(chip);
881 else if (chip->bob_freq > ESM_BOB_FREQ) {
882 /* check reduction of timer frequency */
883 struct list_head *p;
884 int max_freq = ESM_BOB_FREQ;
885 list_for_each(p, &chip->substream_list) {
886 struct esschan *es = list_entry(p, struct esschan, list);
887 if (max_freq < es->bob_freq)
888 max_freq = es->bob_freq;
889 }
890 if (max_freq != chip->bob_freq) {
891 snd_es1968_bob_stop(chip);
892 chip->bob_freq = max_freq;
893 snd_es1968_bob_start(chip);
894 }
895 }
896 }
897
898 static int
899 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
900 struct snd_pcm_runtime *runtime)
901 {
902 /* we acquire 4 interrupts per period for precise control.. */
903 int freq = runtime->rate * 4;
904 if (es->fmt & ESS_FMT_STEREO)
905 freq <<= 1;
906 if (es->fmt & ESS_FMT_16BIT)
907 freq <<= 1;
908 freq /= es->frag_size;
909 if (freq < ESM_BOB_FREQ)
910 freq = ESM_BOB_FREQ;
911 else if (freq > ESM_BOB_FREQ_MAX)
912 freq = ESM_BOB_FREQ_MAX;
913 return freq;
914 }
915
916
917 /*************
918 * PCM Part *
919 *************/
920
921 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
922 {
923 u32 rate = (freq << 16) / chip->clock;
924 #if 0 /* XXX: do we need this? */
925 if (rate > 0x10000)
926 rate = 0x10000;
927 #endif
928 return rate;
929 }
930
931 /* get current pointer */
932 static inline unsigned int
933 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
934 {
935 unsigned int offset;
936
937 offset = apu_get_register(chip, es->apu[0], 5);
938
939 offset -= es->base[0];
940
941 return (offset & 0xFFFE); /* hardware is in words */
942 }
943
944 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
945 {
946 apu_set_register(chip, apu, 2,
947 (apu_get_register(chip, apu, 2) & 0x00FF) |
948 ((freq & 0xff) << 8) | 0x10);
949 apu_set_register(chip, apu, 3, freq >> 8);
950 }
951
952 /* spin lock held */
953 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
954 {
955 /* set the APU mode */
956 __apu_set_register(esm, apu, 0,
957 (__apu_get_register(esm, apu, 0) & 0xff0f) |
958 (mode << 4));
959 }
960
961 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
962 {
963 spin_lock(&chip->reg_lock);
964 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
965 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
966 if (es->mode == ESM_MODE_CAPTURE) {
967 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
968 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
969 }
970 if (es->fmt & ESS_FMT_STEREO) {
971 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
972 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
973 if (es->mode == ESM_MODE_CAPTURE) {
974 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
975 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
976 }
977 }
978 spin_unlock(&chip->reg_lock);
979 }
980
981 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
982 {
983 spin_lock(&chip->reg_lock);
984 snd_es1968_trigger_apu(chip, es->apu[0], 0);
985 snd_es1968_trigger_apu(chip, es->apu[1], 0);
986 if (es->mode == ESM_MODE_CAPTURE) {
987 snd_es1968_trigger_apu(chip, es->apu[2], 0);
988 snd_es1968_trigger_apu(chip, es->apu[3], 0);
989 }
990 spin_unlock(&chip->reg_lock);
991 }
992
993 /* set the wavecache control reg */
994 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
995 int channel, u32 addr, int capture)
996 {
997 u32 tmpval = (addr - 0x10) & 0xFFF8;
998
999 if (! capture) {
1000 if (!(es->fmt & ESS_FMT_16BIT))
1001 tmpval |= 4; /* 8bit */
1002 if (es->fmt & ESS_FMT_STEREO)
1003 tmpval |= 2; /* stereo */
1004 }
1005
1006 /* set the wavecache control reg */
1007 wave_set_register(chip, es->apu[channel] << 3, tmpval);
1008
1009 #ifdef CONFIG_PM
1010 es->wc_map[channel] = tmpval;
1011 #endif
1012 }
1013
1014
1015 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
1016 struct snd_pcm_runtime *runtime)
1017 {
1018 u32 pa;
1019 int high_apu = 0;
1020 int channel, apu;
1021 int i, size;
1022 unsigned long flags;
1023 u32 freq;
1024
1025 size = es->dma_size >> es->wav_shift;
1026
1027 if (es->fmt & ESS_FMT_STEREO)
1028 high_apu++;
1029
1030 for (channel = 0; channel <= high_apu; channel++) {
1031 apu = es->apu[channel];
1032
1033 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1034
1035 /* Offset to PCMBAR */
1036 pa = es->memory->buf.addr;
1037 pa -= chip->dma.addr;
1038 pa >>= 1; /* words */
1039
1040 pa |= 0x00400000; /* System RAM (Bit 22) */
1041
1042 if (es->fmt & ESS_FMT_STEREO) {
1043 /* Enable stereo */
1044 if (channel)
1045 pa |= 0x00800000; /* (Bit 23) */
1046 if (es->fmt & ESS_FMT_16BIT)
1047 pa >>= 1;
1048 }
1049
1050 /* base offset of dma calcs when reading the pointer
1051 on this left one */
1052 es->base[channel] = pa & 0xFFFF;
1053
1054 for (i = 0; i < 16; i++)
1055 apu_set_register(chip, apu, i, 0x0000);
1056
1057 /* Load the buffer into the wave engine */
1058 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1059 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1060 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1061 /* setting loop == sample len */
1062 apu_set_register(chip, apu, 7, size);
1063
1064 /* clear effects/env.. */
1065 apu_set_register(chip, apu, 8, 0x0000);
1066 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1067 apu_set_register(chip, apu, 9, 0xD000);
1068
1069 /* clear routing stuff */
1070 apu_set_register(chip, apu, 11, 0x0000);
1071 /* dma on, no envelopes, filter to all 1s) */
1072 apu_set_register(chip, apu, 0, 0x400F);
1073
1074 if (es->fmt & ESS_FMT_16BIT)
1075 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1076 else
1077 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1078
1079 if (es->fmt & ESS_FMT_STEREO) {
1080 /* set panning: left or right */
1081 /* Check: different panning. On my Canyon 3D Chipset the
1082 Channels are swapped. I don't know, about the output
1083 to the SPDif Link. Perhaps you have to change this
1084 and not the APU Regs 4-5. */
1085 apu_set_register(chip, apu, 10,
1086 0x8F00 | (channel ? 0 : 0x10));
1087 es->apu_mode[channel] += 1; /* stereo */
1088 } else
1089 apu_set_register(chip, apu, 10, 0x8F08);
1090 }
1091
1092 spin_lock_irqsave(&chip->reg_lock, flags);
1093 /* clear WP interrupts */
1094 outw(1, chip->io_port + 0x04);
1095 /* enable WP ints */
1096 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1097 spin_unlock_irqrestore(&chip->reg_lock, flags);
1098
1099 freq = runtime->rate;
1100 /* set frequency */
1101 if (freq > 48000)
1102 freq = 48000;
1103 if (freq < 4000)
1104 freq = 4000;
1105
1106 /* hmmm.. */
1107 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1108 freq >>= 1;
1109
1110 freq = snd_es1968_compute_rate(chip, freq);
1111
1112 /* Load the frequency, turn on 6dB */
1113 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1114 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1115 }
1116
1117
1118 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1119 unsigned int pa, unsigned int bsize,
1120 int mode, int route)
1121 {
1122 int i, apu = es->apu[channel];
1123
1124 es->apu_mode[channel] = mode;
1125
1126 /* set the wavecache control reg */
1127 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1128
1129 /* Offset to PCMBAR */
1130 pa -= chip->dma.addr;
1131 pa >>= 1; /* words */
1132
1133 /* base offset of dma calcs when reading the pointer
1134 on this left one */
1135 es->base[channel] = pa & 0xFFFF;
1136 pa |= 0x00400000; /* bit 22 -> System RAM */
1137
1138 /* Begin loading the APU */
1139 for (i = 0; i < 16; i++)
1140 apu_set_register(chip, apu, i, 0x0000);
1141
1142 /* need to enable subgroups.. and we should probably
1143 have different groups for different /dev/dsps.. */
1144 apu_set_register(chip, apu, 2, 0x8);
1145
1146 /* Load the buffer into the wave engine */
1147 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1148 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1149 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1150 apu_set_register(chip, apu, 7, bsize);
1151 /* clear effects/env.. */
1152 apu_set_register(chip, apu, 8, 0x00F0);
1153 /* amplitude now? sure. why not. */
1154 apu_set_register(chip, apu, 9, 0x0000);
1155 /* set filter tune, radius, polar pan */
1156 apu_set_register(chip, apu, 10, 0x8F08);
1157 /* route input */
1158 apu_set_register(chip, apu, 11, route);
1159 /* dma on, no envelopes, filter to all 1s) */
1160 apu_set_register(chip, apu, 0, 0x400F);
1161 }
1162
1163 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1164 struct snd_pcm_runtime *runtime)
1165 {
1166 int size;
1167 u32 freq;
1168 unsigned long flags;
1169
1170 size = es->dma_size >> es->wav_shift;
1171
1172 /* APU assignments:
1173 0 = mono/left SRC
1174 1 = right SRC
1175 2 = mono/left Input Mixer
1176 3 = right Input Mixer
1177 */
1178 /* data seems to flow from the codec, through an apu into
1179 the 'mixbuf' bit of page, then through the SRC apu
1180 and out to the real 'buffer'. ok. sure. */
1181
1182 /* input mixer (left/mono) */
1183 /* parallel in crap, see maestro reg 0xC [8-11] */
1184 init_capture_apu(chip, es, 2,
1185 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1186 ESM_APU_INPUTMIXER, 0x14);
1187 /* SRC (left/mono); get input from inputing apu */
1188 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1189 ESM_APU_SRCONVERTOR, es->apu[2]);
1190 if (es->fmt & ESS_FMT_STEREO) {
1191 /* input mixer (right) */
1192 init_capture_apu(chip, es, 3,
1193 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1194 ESM_MIXBUF_SIZE/4, /* in words */
1195 ESM_APU_INPUTMIXER, 0x15);
1196 /* SRC (right) */
1197 init_capture_apu(chip, es, 1,
1198 es->memory->buf.addr + size*2, size,
1199 ESM_APU_SRCONVERTOR, es->apu[3]);
1200 }
1201
1202 freq = runtime->rate;
1203 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1204 if (freq > 47999)
1205 freq = 47999;
1206 if (freq < 4000)
1207 freq = 4000;
1208
1209 freq = snd_es1968_compute_rate(chip, freq);
1210
1211 /* Load the frequency, turn on 6dB */
1212 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1213 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1214
1215 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1216 freq = 0x10000;
1217 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1218 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1219
1220 spin_lock_irqsave(&chip->reg_lock, flags);
1221 /* clear WP interrupts */
1222 outw(1, chip->io_port + 0x04);
1223 /* enable WP ints */
1224 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1225 spin_unlock_irqrestore(&chip->reg_lock, flags);
1226 }
1227
1228 /*******************
1229 * ALSA Interface *
1230 *******************/
1231
1232 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1233 {
1234 struct es1968 *chip = snd_pcm_substream_chip(substream);
1235 struct snd_pcm_runtime *runtime = substream->runtime;
1236 struct esschan *es = runtime->private_data;
1237
1238 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1239 es->frag_size = snd_pcm_lib_period_bytes(substream);
1240
1241 es->wav_shift = 1; /* maestro handles always 16bit */
1242 es->fmt = 0;
1243 if (snd_pcm_format_width(runtime->format) == 16)
1244 es->fmt |= ESS_FMT_16BIT;
1245 if (runtime->channels > 1) {
1246 es->fmt |= ESS_FMT_STEREO;
1247 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1248 es->wav_shift++;
1249 }
1250 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1251
1252 switch (es->mode) {
1253 case ESM_MODE_PLAY:
1254 snd_es1968_playback_setup(chip, es, runtime);
1255 break;
1256 case ESM_MODE_CAPTURE:
1257 snd_es1968_capture_setup(chip, es, runtime);
1258 break;
1259 }
1260
1261 return 0;
1262 }
1263
1264 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1265 {
1266 struct es1968 *chip = snd_pcm_substream_chip(substream);
1267 struct esschan *es = substream->runtime->private_data;
1268
1269 spin_lock(&chip->substream_lock);
1270 switch (cmd) {
1271 case SNDRV_PCM_TRIGGER_START:
1272 case SNDRV_PCM_TRIGGER_RESUME:
1273 if (es->running)
1274 break;
1275 snd_es1968_bob_inc(chip, es->bob_freq);
1276 es->count = 0;
1277 es->hwptr = 0;
1278 snd_es1968_pcm_start(chip, es);
1279 es->running = 1;
1280 break;
1281 case SNDRV_PCM_TRIGGER_STOP:
1282 case SNDRV_PCM_TRIGGER_SUSPEND:
1283 if (! es->running)
1284 break;
1285 snd_es1968_pcm_stop(chip, es);
1286 es->running = 0;
1287 snd_es1968_bob_dec(chip);
1288 break;
1289 }
1290 spin_unlock(&chip->substream_lock);
1291 return 0;
1292 }
1293
1294 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1295 {
1296 struct es1968 *chip = snd_pcm_substream_chip(substream);
1297 struct esschan *es = substream->runtime->private_data;
1298 unsigned int ptr;
1299
1300 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1301
1302 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1303 }
1304
1305 static struct snd_pcm_hardware snd_es1968_playback = {
1306 .info = (SNDRV_PCM_INFO_MMAP |
1307 SNDRV_PCM_INFO_MMAP_VALID |
1308 SNDRV_PCM_INFO_INTERLEAVED |
1309 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1310 /*SNDRV_PCM_INFO_PAUSE |*/
1311 SNDRV_PCM_INFO_RESUME),
1312 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1313 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1314 .rate_min = 4000,
1315 .rate_max = 48000,
1316 .channels_min = 1,
1317 .channels_max = 2,
1318 .buffer_bytes_max = 65536,
1319 .period_bytes_min = 256,
1320 .period_bytes_max = 65536,
1321 .periods_min = 1,
1322 .periods_max = 1024,
1323 .fifo_size = 0,
1324 };
1325
1326 static struct snd_pcm_hardware snd_es1968_capture = {
1327 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1328 SNDRV_PCM_INFO_MMAP |
1329 SNDRV_PCM_INFO_MMAP_VALID |
1330 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1331 /*SNDRV_PCM_INFO_PAUSE |*/
1332 SNDRV_PCM_INFO_RESUME),
1333 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1334 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1335 .rate_min = 4000,
1336 .rate_max = 48000,
1337 .channels_min = 1,
1338 .channels_max = 2,
1339 .buffer_bytes_max = 65536,
1340 .period_bytes_min = 256,
1341 .period_bytes_max = 65536,
1342 .periods_min = 1,
1343 .periods_max = 1024,
1344 .fifo_size = 0,
1345 };
1346
1347 /* *************************
1348 * DMA memory management *
1349 *************************/
1350
1351 /* Because the Maestro can only take addresses relative to the PCM base address
1352 register :( */
1353
1354 static int calc_available_memory_size(struct es1968 *chip)
1355 {
1356 struct list_head *p;
1357 int max_size = 0;
1358
1359 down(&chip->memory_mutex);
1360 list_for_each(p, &chip->buf_list) {
1361 struct esm_memory *buf = list_entry(p, struct esm_memory, list);
1362 if (buf->empty && buf->buf.bytes > max_size)
1363 max_size = buf->buf.bytes;
1364 }
1365 up(&chip->memory_mutex);
1366 if (max_size >= 128*1024)
1367 max_size = 127*1024;
1368 return max_size;
1369 }
1370
1371 /* allocate a new memory chunk with the specified size */
1372 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1373 {
1374 struct esm_memory *buf;
1375 struct list_head *p;
1376
1377 size = ((size + ESM_MEM_ALIGN - 1) / ESM_MEM_ALIGN) * ESM_MEM_ALIGN;
1378 down(&chip->memory_mutex);
1379 list_for_each(p, &chip->buf_list) {
1380 buf = list_entry(p, struct esm_memory, list);
1381 if (buf->empty && buf->buf.bytes >= size)
1382 goto __found;
1383 }
1384 up(&chip->memory_mutex);
1385 return NULL;
1386
1387 __found:
1388 if (buf->buf.bytes > size) {
1389 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1390 if (chunk == NULL) {
1391 up(&chip->memory_mutex);
1392 return NULL;
1393 }
1394 chunk->buf = buf->buf;
1395 chunk->buf.bytes -= size;
1396 chunk->buf.area += size;
1397 chunk->buf.addr += size;
1398 chunk->empty = 1;
1399 buf->buf.bytes = size;
1400 list_add(&chunk->list, &buf->list);
1401 }
1402 buf->empty = 0;
1403 up(&chip->memory_mutex);
1404 return buf;
1405 }
1406
1407 /* free a memory chunk */
1408 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1409 {
1410 struct esm_memory *chunk;
1411
1412 down(&chip->memory_mutex);
1413 buf->empty = 1;
1414 if (buf->list.prev != &chip->buf_list) {
1415 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1416 if (chunk->empty) {
1417 chunk->buf.bytes += buf->buf.bytes;
1418 list_del(&buf->list);
1419 kfree(buf);
1420 buf = chunk;
1421 }
1422 }
1423 if (buf->list.next != &chip->buf_list) {
1424 chunk = list_entry(buf->list.next, struct esm_memory, list);
1425 if (chunk->empty) {
1426 buf->buf.bytes += chunk->buf.bytes;
1427 list_del(&chunk->list);
1428 kfree(chunk);
1429 }
1430 }
1431 up(&chip->memory_mutex);
1432 }
1433
1434 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1435 {
1436 struct list_head *p;
1437
1438 if (! chip->dma.area)
1439 return;
1440 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1441 while ((p = chip->buf_list.next) != &chip->buf_list) {
1442 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1443 list_del(p);
1444 kfree(chunk);
1445 }
1446 }
1447
1448 static int __devinit
1449 snd_es1968_init_dmabuf(struct es1968 *chip)
1450 {
1451 int err;
1452 struct esm_memory *chunk;
1453
1454 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1455 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1456 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1457 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1458 snd_dma_pci_data(chip->pci),
1459 chip->total_bufsize, &chip->dma);
1460 if (err < 0 || ! chip->dma.area) {
1461 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1462 chip->total_bufsize);
1463 return -ENOMEM;
1464 }
1465 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1466 snd_dma_free_pages(&chip->dma);
1467 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1468 return -ENOMEM;
1469 }
1470 }
1471
1472 INIT_LIST_HEAD(&chip->buf_list);
1473 /* allocate an empty chunk */
1474 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1475 if (chunk == NULL) {
1476 snd_es1968_free_dmabuf(chip);
1477 return -ENOMEM;
1478 }
1479 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1480 chunk->buf = chip->dma;
1481 chunk->buf.area += ESM_MEM_ALIGN;
1482 chunk->buf.addr += ESM_MEM_ALIGN;
1483 chunk->buf.bytes -= ESM_MEM_ALIGN;
1484 chunk->empty = 1;
1485 list_add(&chunk->list, &chip->buf_list);
1486
1487 return 0;
1488 }
1489
1490 /* setup the dma_areas */
1491 /* buffer is extracted from the pre-allocated memory chunk */
1492 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1493 struct snd_pcm_hw_params *hw_params)
1494 {
1495 struct es1968 *chip = snd_pcm_substream_chip(substream);
1496 struct snd_pcm_runtime *runtime = substream->runtime;
1497 struct esschan *chan = runtime->private_data;
1498 int size = params_buffer_bytes(hw_params);
1499
1500 if (chan->memory) {
1501 if (chan->memory->buf.bytes >= size) {
1502 runtime->dma_bytes = size;
1503 return 0;
1504 }
1505 snd_es1968_free_memory(chip, chan->memory);
1506 }
1507 chan->memory = snd_es1968_new_memory(chip, size);
1508 if (chan->memory == NULL) {
1509 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1510 return -ENOMEM;
1511 }
1512 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1513 return 1; /* area was changed */
1514 }
1515
1516 /* remove dma areas if allocated */
1517 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1518 {
1519 struct es1968 *chip = snd_pcm_substream_chip(substream);
1520 struct snd_pcm_runtime *runtime = substream->runtime;
1521 struct esschan *chan;
1522
1523 if (runtime->private_data == NULL)
1524 return 0;
1525 chan = runtime->private_data;
1526 if (chan->memory) {
1527 snd_es1968_free_memory(chip, chan->memory);
1528 chan->memory = NULL;
1529 }
1530 return 0;
1531 }
1532
1533
1534 /*
1535 * allocate APU pair
1536 */
1537 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1538 {
1539 int apu;
1540
1541 for (apu = 0; apu < NR_APUS; apu += 2) {
1542 if (chip->apu[apu] == ESM_APU_FREE &&
1543 chip->apu[apu + 1] == ESM_APU_FREE) {
1544 chip->apu[apu] = chip->apu[apu + 1] = type;
1545 return apu;
1546 }
1547 }
1548 return -EBUSY;
1549 }
1550
1551 /*
1552 * release APU pair
1553 */
1554 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1555 {
1556 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1557 }
1558
1559
1560 /******************
1561 * PCM open/close *
1562 ******************/
1563
1564 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1565 {
1566 struct es1968 *chip = snd_pcm_substream_chip(substream);
1567 struct snd_pcm_runtime *runtime = substream->runtime;
1568 struct esschan *es;
1569 int apu1;
1570
1571 /* search 2 APUs */
1572 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1573 if (apu1 < 0)
1574 return apu1;
1575
1576 es = kzalloc(sizeof(*es), GFP_KERNEL);
1577 if (!es) {
1578 snd_es1968_free_apu_pair(chip, apu1);
1579 return -ENOMEM;
1580 }
1581
1582 es->apu[0] = apu1;
1583 es->apu[1] = apu1 + 1;
1584 es->apu_mode[0] = 0;
1585 es->apu_mode[1] = 0;
1586 es->running = 0;
1587 es->substream = substream;
1588 es->mode = ESM_MODE_PLAY;
1589
1590 runtime->private_data = es;
1591 runtime->hw = snd_es1968_playback;
1592 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1593 calc_available_memory_size(chip);
1594 #if 0
1595 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1596 1024);
1597 #endif
1598 spin_lock_irq(&chip->substream_lock);
1599 list_add(&es->list, &chip->substream_list);
1600 spin_unlock_irq(&chip->substream_lock);
1601
1602 return 0;
1603 }
1604
1605 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1606 {
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct es1968 *chip = snd_pcm_substream_chip(substream);
1609 struct esschan *es;
1610 int apu1, apu2;
1611
1612 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1613 if (apu1 < 0)
1614 return apu1;
1615 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1616 if (apu2 < 0) {
1617 snd_es1968_free_apu_pair(chip, apu1);
1618 return apu2;
1619 }
1620
1621 es = kzalloc(sizeof(*es), GFP_KERNEL);
1622 if (!es) {
1623 snd_es1968_free_apu_pair(chip, apu1);
1624 snd_es1968_free_apu_pair(chip, apu2);
1625 return -ENOMEM;
1626 }
1627
1628 es->apu[0] = apu1;
1629 es->apu[1] = apu1 + 1;
1630 es->apu[2] = apu2;
1631 es->apu[3] = apu2 + 1;
1632 es->apu_mode[0] = 0;
1633 es->apu_mode[1] = 0;
1634 es->apu_mode[2] = 0;
1635 es->apu_mode[3] = 0;
1636 es->running = 0;
1637 es->substream = substream;
1638 es->mode = ESM_MODE_CAPTURE;
1639
1640 /* get mixbuffer */
1641 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1642 snd_es1968_free_apu_pair(chip, apu1);
1643 snd_es1968_free_apu_pair(chip, apu2);
1644 kfree(es);
1645 return -ENOMEM;
1646 }
1647 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1648
1649 runtime->private_data = es;
1650 runtime->hw = snd_es1968_capture;
1651 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1652 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1653 #if 0
1654 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1655 1024);
1656 #endif
1657 spin_lock_irq(&chip->substream_lock);
1658 list_add(&es->list, &chip->substream_list);
1659 spin_unlock_irq(&chip->substream_lock);
1660
1661 return 0;
1662 }
1663
1664 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1665 {
1666 struct es1968 *chip = snd_pcm_substream_chip(substream);
1667 struct esschan *es;
1668
1669 if (substream->runtime->private_data == NULL)
1670 return 0;
1671 es = substream->runtime->private_data;
1672 spin_lock_irq(&chip->substream_lock);
1673 list_del(&es->list);
1674 spin_unlock_irq(&chip->substream_lock);
1675 snd_es1968_free_apu_pair(chip, es->apu[0]);
1676 kfree(es);
1677
1678 return 0;
1679 }
1680
1681 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1682 {
1683 struct es1968 *chip = snd_pcm_substream_chip(substream);
1684 struct esschan *es;
1685
1686 if (substream->runtime->private_data == NULL)
1687 return 0;
1688 es = substream->runtime->private_data;
1689 spin_lock_irq(&chip->substream_lock);
1690 list_del(&es->list);
1691 spin_unlock_irq(&chip->substream_lock);
1692 snd_es1968_free_memory(chip, es->mixbuf);
1693 snd_es1968_free_apu_pair(chip, es->apu[0]);
1694 snd_es1968_free_apu_pair(chip, es->apu[2]);
1695 kfree(es);
1696
1697 return 0;
1698 }
1699
1700 static struct snd_pcm_ops snd_es1968_playback_ops = {
1701 .open = snd_es1968_playback_open,
1702 .close = snd_es1968_playback_close,
1703 .ioctl = snd_pcm_lib_ioctl,
1704 .hw_params = snd_es1968_hw_params,
1705 .hw_free = snd_es1968_hw_free,
1706 .prepare = snd_es1968_pcm_prepare,
1707 .trigger = snd_es1968_pcm_trigger,
1708 .pointer = snd_es1968_pcm_pointer,
1709 };
1710
1711 static struct snd_pcm_ops snd_es1968_capture_ops = {
1712 .open = snd_es1968_capture_open,
1713 .close = snd_es1968_capture_close,
1714 .ioctl = snd_pcm_lib_ioctl,
1715 .hw_params = snd_es1968_hw_params,
1716 .hw_free = snd_es1968_hw_free,
1717 .prepare = snd_es1968_pcm_prepare,
1718 .trigger = snd_es1968_pcm_trigger,
1719 .pointer = snd_es1968_pcm_pointer,
1720 };
1721
1722
1723 /*
1724 * measure clock
1725 */
1726 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1727
1728 static void __devinit es1968_measure_clock(struct es1968 *chip)
1729 {
1730 int i, apu;
1731 unsigned int pa, offset, t;
1732 struct esm_memory *memory;
1733 struct timeval start_time, stop_time;
1734
1735 if (chip->clock == 0)
1736 chip->clock = 48000; /* default clock value */
1737
1738 /* search 2 APUs (although one apu is enough) */
1739 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1740 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1741 return;
1742 }
1743 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1744 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1745 snd_es1968_free_apu_pair(chip, apu);
1746 return;
1747 }
1748
1749 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1750
1751 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1752
1753 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1754 pa |= 0x00400000; /* System RAM (Bit 22) */
1755
1756 /* initialize apu */
1757 for (i = 0; i < 16; i++)
1758 apu_set_register(chip, apu, i, 0x0000);
1759
1760 apu_set_register(chip, apu, 0, 0x400f);
1761 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1762 apu_set_register(chip, apu, 5, pa & 0xffff);
1763 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1764 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1765 apu_set_register(chip, apu, 8, 0x0000);
1766 apu_set_register(chip, apu, 9, 0xD000);
1767 apu_set_register(chip, apu, 10, 0x8F08);
1768 apu_set_register(chip, apu, 11, 0x0000);
1769 spin_lock_irq(&chip->reg_lock);
1770 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1771 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1772 spin_unlock_irq(&chip->reg_lock);
1773
1774 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1775
1776 chip->in_measurement = 1;
1777 chip->measure_apu = apu;
1778 spin_lock_irq(&chip->reg_lock);
1779 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1780 __apu_set_register(chip, apu, 5, pa & 0xffff);
1781 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1782 do_gettimeofday(&start_time);
1783 spin_unlock_irq(&chip->reg_lock);
1784 msleep(50);
1785 spin_lock_irq(&chip->reg_lock);
1786 offset = __apu_get_register(chip, apu, 5);
1787 do_gettimeofday(&stop_time);
1788 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1789 snd_es1968_bob_dec(chip);
1790 chip->in_measurement = 0;
1791 spin_unlock_irq(&chip->reg_lock);
1792
1793 /* check the current position */
1794 offset -= (pa & 0xffff);
1795 offset &= 0xfffe;
1796 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1797
1798 t = stop_time.tv_sec - start_time.tv_sec;
1799 t *= 1000000;
1800 if (stop_time.tv_usec < start_time.tv_usec)
1801 t -= start_time.tv_usec - stop_time.tv_usec;
1802 else
1803 t += stop_time.tv_usec - start_time.tv_usec;
1804 if (t == 0) {
1805 snd_printk(KERN_ERR "?? calculation error..\n");
1806 } else {
1807 offset *= 1000;
1808 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1809 if (offset < 47500 || offset > 48500) {
1810 if (offset >= 40000 && offset <= 50000)
1811 chip->clock = (chip->clock * offset) / 48000;
1812 }
1813 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1814 }
1815 snd_es1968_free_memory(chip, memory);
1816 snd_es1968_free_apu_pair(chip, apu);
1817 }
1818
1819
1820 /*
1821 */
1822
1823 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1824 {
1825 struct es1968 *esm = pcm->private_data;
1826 snd_es1968_free_dmabuf(esm);
1827 esm->pcm = NULL;
1828 }
1829
1830 static int __devinit
1831 snd_es1968_pcm(struct es1968 *chip, int device)
1832 {
1833 struct snd_pcm *pcm;
1834 int err;
1835
1836 /* get DMA buffer */
1837 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1838 return err;
1839
1840 /* set PCMBAR */
1841 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1842 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1843 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1844 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1845
1846 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1847 chip->playback_streams,
1848 chip->capture_streams, &pcm)) < 0)
1849 return err;
1850
1851 pcm->private_data = chip;
1852 pcm->private_free = snd_es1968_pcm_free;
1853
1854 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1855 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1856
1857 pcm->info_flags = 0;
1858
1859 strcpy(pcm->name, "ESS Maestro");
1860
1861 chip->pcm = pcm;
1862
1863 return 0;
1864 }
1865
1866 /*
1867 * update pointer
1868 */
1869 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1870 {
1871 unsigned int hwptr;
1872 unsigned int diff;
1873 struct snd_pcm_substream *subs = es->substream;
1874
1875 if (subs == NULL || !es->running)
1876 return;
1877
1878 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1879 hwptr %= es->dma_size;
1880
1881 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1882
1883 es->hwptr = hwptr;
1884 es->count += diff;
1885
1886 if (es->count > es->frag_size) {
1887 spin_unlock(&chip->substream_lock);
1888 snd_pcm_period_elapsed(subs);
1889 spin_lock(&chip->substream_lock);
1890 es->count %= es->frag_size;
1891 }
1892 }
1893
1894 /*
1895 */
1896 static void es1968_update_hw_volume(unsigned long private_data)
1897 {
1898 struct es1968 *chip = (struct es1968 *) private_data;
1899 int x, val;
1900 unsigned long flags;
1901
1902 /* Figure out which volume control button was pushed,
1903 based on differences from the default register
1904 values. */
1905 x = inb(chip->io_port + 0x1c);
1906 /* Reset the volume control registers. */
1907 outb(0x88, chip->io_port + 0x1c);
1908 outb(0x88, chip->io_port + 0x1d);
1909 outb(0x88, chip->io_port + 0x1e);
1910 outb(0x88, chip->io_port + 0x1f);
1911
1912 if (chip->in_suspend)
1913 return;
1914
1915 if (! chip->master_switch || ! chip->master_volume)
1916 return;
1917
1918 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1919 spin_lock_irqsave(&chip->ac97_lock, flags);
1920 val = chip->ac97->regs[AC97_MASTER];
1921 if (x & 1) {
1922 /* mute */
1923 val ^= 0x8000;
1924 chip->ac97->regs[AC97_MASTER] = val;
1925 outw(val, chip->io_port + ESM_AC97_DATA);
1926 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1927 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1928 &chip->master_switch->id);
1929 } else {
1930 val &= 0x7fff;
1931 if (((x>>1) & 7) > 4) {
1932 /* volume up */
1933 if ((val & 0xff) > 0)
1934 val--;
1935 if ((val & 0xff00) > 0)
1936 val -= 0x0100;
1937 } else {
1938 /* volume down */
1939 if ((val & 0xff) < 0x1f)
1940 val++;
1941 if ((val & 0xff00) < 0x1f00)
1942 val += 0x0100;
1943 }
1944 chip->ac97->regs[AC97_MASTER] = val;
1945 outw(val, chip->io_port + ESM_AC97_DATA);
1946 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1947 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1948 &chip->master_volume->id);
1949 }
1950 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1951 }
1952
1953 /*
1954 * interrupt handler
1955 */
1956 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1957 {
1958 struct es1968 *chip = dev_id;
1959 u32 event;
1960
1961 if (!(event = inb(chip->io_port + 0x1A)))
1962 return IRQ_NONE;
1963
1964 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1965
1966 if (event & ESM_HWVOL_IRQ)
1967 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1968
1969 /* else ack 'em all, i imagine */
1970 outb(0xFF, chip->io_port + 0x1A);
1971
1972 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1973 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1974 }
1975
1976 if (event & ESM_SOUND_IRQ) {
1977 struct list_head *p;
1978 spin_lock(&chip->substream_lock);
1979 list_for_each(p, &chip->substream_list) {
1980 struct esschan *es = list_entry(p, struct esschan, list);
1981 if (es->running)
1982 snd_es1968_update_pcm(chip, es);
1983 }
1984 spin_unlock(&chip->substream_lock);
1985 if (chip->in_measurement) {
1986 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1987 if (curp < chip->measure_lastpos)
1988 chip->measure_count++;
1989 chip->measure_lastpos = curp;
1990 }
1991 }
1992
1993 return IRQ_HANDLED;
1994 }
1995
1996 /*
1997 * Mixer stuff
1998 */
1999
2000 static int __devinit
2001 snd_es1968_mixer(struct es1968 *chip)
2002 {
2003 struct snd_ac97_bus *pbus;
2004 struct snd_ac97_template ac97;
2005 struct snd_ctl_elem_id id;
2006 int err;
2007 static struct snd_ac97_bus_ops ops = {
2008 .write = snd_es1968_ac97_write,
2009 .read = snd_es1968_ac97_read,
2010 };
2011
2012 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2013 return err;
2014 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2015
2016 memset(&ac97, 0, sizeof(ac97));
2017 ac97.private_data = chip;
2018 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2019 return err;
2020
2021 /* attach master switch / volumes for h/w volume control */
2022 memset(&id, 0, sizeof(id));
2023 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2024 strcpy(id.name, "Master Playback Switch");
2025 chip->master_switch = snd_ctl_find_id(chip->card, &id);
2026 memset(&id, 0, sizeof(id));
2027 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2028 strcpy(id.name, "Master Playback Volume");
2029 chip->master_volume = snd_ctl_find_id(chip->card, &id);
2030
2031 return 0;
2032 }
2033
2034 /*
2035 * reset ac97 codec
2036 */
2037
2038 static void snd_es1968_ac97_reset(struct es1968 *chip)
2039 {
2040 unsigned long ioaddr = chip->io_port;
2041
2042 unsigned short save_ringbus_a;
2043 unsigned short save_68;
2044 unsigned short w;
2045 unsigned int vend;
2046
2047 /* save configuration */
2048 save_ringbus_a = inw(ioaddr + 0x36);
2049
2050 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2051 /* set command/status address i/o to 1st codec */
2052 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2053 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2054
2055 /* disable ac link */
2056 outw(0x0000, ioaddr + 0x36);
2057 save_68 = inw(ioaddr + 0x68);
2058 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2059 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2060 if (w & 1)
2061 save_68 |= 0x10;
2062 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2063 outw(0x0001, ioaddr + 0x68); /* gpio write */
2064 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2065 udelay(20);
2066 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2067 msleep(20);
2068
2069 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2070 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2071 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2072 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2073
2074 /* now the second codec */
2075 /* disable ac link */
2076 outw(0x0000, ioaddr + 0x36);
2077 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2078 save_68 = inw(ioaddr + 0x68);
2079 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2080 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2081 udelay(20);
2082 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2083 msleep(500);
2084 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2085 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2086 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2087
2088 #if 0 /* the loop here needs to be much better if we want it.. */
2089 snd_printk(KERN_INFO "trying software reset\n");
2090 /* try and do a software reset */
2091 outb(0x80 | 0x7c, ioaddr + 0x30);
2092 for (w = 0;; w++) {
2093 if ((inw(ioaddr + 0x30) & 1) == 0) {
2094 if (inb(ioaddr + 0x32) != 0)
2095 break;
2096
2097 outb(0x80 | 0x7d, ioaddr + 0x30);
2098 if (((inw(ioaddr + 0x30) & 1) == 0)
2099 && (inb(ioaddr + 0x32) != 0))
2100 break;
2101 outb(0x80 | 0x7f, ioaddr + 0x30);
2102 if (((inw(ioaddr + 0x30) & 1) == 0)
2103 && (inb(ioaddr + 0x32) != 0))
2104 break;
2105 }
2106
2107 if (w > 10000) {
2108 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2109 msleep(500); /* oh my.. */
2110 outb(inb(ioaddr + 0x37) & ~0x08,
2111 ioaddr + 0x37);
2112 udelay(1);
2113 outw(0x80, ioaddr + 0x30);
2114 for (w = 0; w < 10000; w++) {
2115 if ((inw(ioaddr + 0x30) & 1) == 0)
2116 break;
2117 }
2118 }
2119 }
2120 #endif
2121 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2122 /* turn on external amp? */
2123 outw(0xf9ff, ioaddr + 0x64);
2124 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2125 outw(0x0209, ioaddr + 0x60);
2126 }
2127
2128 /* restore.. */
2129 outw(save_ringbus_a, ioaddr + 0x36);
2130
2131 /* Turn on the 978 docking chip.
2132 First frob the "master output enable" bit,
2133 then set most of the playback volume control registers to max. */
2134 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2135 outb(0xff, ioaddr+0xc3);
2136 outb(0xff, ioaddr+0xc4);
2137 outb(0xff, ioaddr+0xc6);
2138 outb(0xff, ioaddr+0xc8);
2139 outb(0x3f, ioaddr+0xcf);
2140 outb(0x3f, ioaddr+0xd0);
2141 }
2142
2143 static void snd_es1968_reset(struct es1968 *chip)
2144 {
2145 /* Reset */
2146 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2147 chip->io_port + ESM_PORT_HOST_IRQ);
2148 udelay(10);
2149 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2150 udelay(10);
2151 }
2152
2153 /*
2154 * power management
2155 */
2156 static void snd_es1968_set_acpi(struct es1968 *chip, int state)
2157 {
2158 u16 active_mask = acpi_state_mask[state];
2159
2160 pci_set_power_state(chip->pci, state);
2161 /* make sure the units we care about are on
2162 XXX we might want to do this before state flipping? */
2163 pci_write_config_word(chip->pci, 0x54, ~ active_mask);
2164 pci_write_config_word(chip->pci, 0x56, ~ active_mask);
2165 }
2166
2167
2168 /*
2169 * initialize maestro chip
2170 */
2171 static void snd_es1968_chip_init(struct es1968 *chip)
2172 {
2173 struct pci_dev *pci = chip->pci;
2174 int i;
2175 unsigned long iobase = chip->io_port;
2176 u16 w;
2177 u32 n;
2178
2179 /* We used to muck around with pci config space that
2180 * we had no business messing with. We don't know enough
2181 * about the machine to know which DMA mode is appropriate,
2182 * etc. We were guessing wrong on some machines and making
2183 * them unhappy. We now trust in the BIOS to do things right,
2184 * which almost certainly means a new host of problems will
2185 * arise with broken BIOS implementations. screw 'em.
2186 * We're already intolerant of machines that don't assign
2187 * IRQs.
2188 */
2189
2190 /* do config work at full power */
2191 snd_es1968_set_acpi(chip, ACPI_D0);
2192
2193 /* Config Reg A */
2194 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2195
2196 w &= ~DMA_CLEAR; /* Clear DMA bits */
2197 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2198 w &= ~SAFEGUARD; /* Safeguard off */
2199 w |= POST_WRITE; /* Posted write */
2200 w |= PCI_TIMING; /* PCI timing on */
2201 /* XXX huh? claims to be reserved.. */
2202 w &= ~SWAP_LR; /* swap left/right
2203 seems to only have effect on SB
2204 Emulation */
2205 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2206
2207 pci_write_config_word(pci, ESM_CONFIG_A, w);
2208
2209 /* Config Reg B */
2210
2211 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2212
2213 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2214 /* XXX how do we know which to use? */
2215 w &= ~(1 << 14); /* External clock */
2216
2217 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2218 w |= HWV_CONFB; /* HWV on */
2219 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2220 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2221 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2222 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2223 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2224 w &= ~(1 << 1); /* reserved, always write 0 */
2225 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2226
2227 pci_write_config_word(pci, ESM_CONFIG_B, w);
2228
2229 /* DDMA off */
2230
2231 pci_read_config_word(pci, ESM_DDMA, &w);
2232 w &= ~(1 << 0);
2233 pci_write_config_word(pci, ESM_DDMA, w);
2234
2235 /*
2236 * Legacy mode
2237 */
2238
2239 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2240
2241 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2242 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2243 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2244
2245 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2246
2247 /* Set up 978 docking control chip. */
2248 pci_read_config_word(pci, 0x58, &w);
2249 w|=1<<2; /* Enable 978. */
2250 w|=1<<3; /* Turn on 978 hardware volume control. */
2251 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2252 pci_write_config_word(pci, 0x58, w);
2253
2254 /* Sound Reset */
2255
2256 snd_es1968_reset(chip);
2257
2258 /*
2259 * Ring Bus Setup
2260 */
2261
2262 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2263 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2264 udelay(20);
2265 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2266 udelay(20);
2267
2268 /*
2269 * Reset the CODEC
2270 */
2271
2272 snd_es1968_ac97_reset(chip);
2273
2274 /* Ring Bus Control B */
2275
2276 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2277 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2278 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2279 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2280
2281 /* Set hardware volume control registers to midpoints.
2282 We can tell which button was pushed based on how they change. */
2283 outb(0x88, iobase+0x1c);
2284 outb(0x88, iobase+0x1d);
2285 outb(0x88, iobase+0x1e);
2286 outb(0x88, iobase+0x1f);
2287
2288 /* it appears some maestros (dell 7500) only work if these are set,
2289 regardless of wether we use the assp or not. */
2290
2291 outb(0, iobase + ASSP_CONTROL_B);
2292 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2293 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2294
2295 /*
2296 * set up wavecache
2297 */
2298 for (i = 0; i < 16; i++) {
2299 /* Write 0 into the buffer area 0x1E0->1EF */
2300 outw(0x01E0 + i, iobase + WC_INDEX);
2301 outw(0x0000, iobase + WC_DATA);
2302
2303 /* The 1.10 test program seem to write 0 into the buffer area
2304 * 0x1D0-0x1DF too.*/
2305 outw(0x01D0 + i, iobase + WC_INDEX);
2306 outw(0x0000, iobase + WC_DATA);
2307 }
2308 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2309 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2310 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2311 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2312 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2313 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2314 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2315 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2316
2317
2318 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2319 /* Now back to the DirectSound stuff */
2320 /* audio serial configuration.. ? */
2321 maestro_write(chip, 0x08, 0xB004);
2322 maestro_write(chip, 0x09, 0x001B);
2323 maestro_write(chip, 0x0A, 0x8000);
2324 maestro_write(chip, 0x0B, 0x3F37);
2325 maestro_write(chip, 0x0C, 0x0098);
2326
2327 /* parallel in, has something to do with recording :) */
2328 maestro_write(chip, 0x0C,
2329 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2330 /* parallel out */
2331 maestro_write(chip, 0x0C,
2332 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2333
2334 maestro_write(chip, 0x0D, 0x7632);
2335
2336 /* Wave cache control on - test off, sg off,
2337 enable, enable extra chans 1Mb */
2338
2339 w = inw(iobase + WC_CONTROL);
2340
2341 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2342 w |= 0xA000; /* reserved... I don't know */
2343 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2344 Seems to crash the Computer if enabled... */
2345 w |= 0x0100; /* Wave Cache Operation Enabled */
2346 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2347 w &= ~0x0060; /* Clear Wavtable Size */
2348 w |= 0x0020; /* Wavetable Size : 1MB */
2349 /* Bit 4 is reserved */
2350 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2351 /* Bit 1 is reserved */
2352 w &= ~0x0001; /* Test Mode off */
2353
2354 outw(w, iobase + WC_CONTROL);
2355
2356 /* Now clear the APU control ram */
2357 for (i = 0; i < NR_APUS; i++) {
2358 for (w = 0; w < NR_APU_REGS; w++)
2359 apu_set_register(chip, i, w, 0);
2360
2361 }
2362 }
2363
2364 /* Enable IRQ's */
2365 static void snd_es1968_start_irq(struct es1968 *chip)
2366 {
2367 unsigned short w;
2368 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2369 if (chip->rmidi)
2370 w |= ESM_HIRQ_MPU401;
2371 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2372 }
2373
2374 #ifdef CONFIG_PM
2375 /*
2376 * PM support
2377 */
2378 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2379 {
2380 struct snd_card *card = pci_get_drvdata(pci);
2381 struct es1968 *chip = card->private_data;
2382
2383 if (! chip->do_pm)
2384 return 0;
2385
2386 chip->in_suspend = 1;
2387 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2388 snd_pcm_suspend_all(chip->pcm);
2389 snd_ac97_suspend(chip->ac97);
2390 snd_es1968_bob_stop(chip);
2391 snd_es1968_set_acpi(chip, ACPI_D3);
2392 pci_disable_device(pci);
2393 pci_save_state(pci);
2394 return 0;
2395 }
2396
2397 static int es1968_resume(struct pci_dev *pci)
2398 {
2399 struct snd_card *card = pci_get_drvdata(pci);
2400 struct es1968 *chip = card->private_data;
2401 struct list_head *p;
2402
2403 if (! chip->do_pm)
2404 return 0;
2405
2406 /* restore all our config */
2407 pci_restore_state(pci);
2408 pci_enable_device(pci);
2409 pci_set_master(pci);
2410 snd_es1968_chip_init(chip);
2411
2412 /* need to restore the base pointers.. */
2413 if (chip->dma.addr) {
2414 /* set PCMBAR */
2415 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2416 }
2417
2418 snd_es1968_start_irq(chip);
2419
2420 /* restore ac97 state */
2421 snd_ac97_resume(chip->ac97);
2422
2423 list_for_each(p, &chip->substream_list) {
2424 struct esschan *es = list_entry(p, struct esschan, list);
2425 switch (es->mode) {
2426 case ESM_MODE_PLAY:
2427 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2428 break;
2429 case ESM_MODE_CAPTURE:
2430 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2431 break;
2432 }
2433 }
2434
2435 /* start timer again */
2436 if (chip->bobclient)
2437 snd_es1968_bob_start(chip);
2438
2439 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2440 chip->in_suspend = 0;
2441 return 0;
2442 }
2443 #endif /* CONFIG_PM */
2444
2445 #ifdef SUPPORT_JOYSTICK
2446 #define JOYSTICK_ADDR 0x200
2447 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2448 {
2449 struct gameport *gp;
2450 struct resource *r;
2451 u16 val;
2452
2453 if (!joystick[dev])
2454 return -ENODEV;
2455
2456 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2457 if (!r)
2458 return -EBUSY;
2459
2460 chip->gameport = gp = gameport_allocate_port();
2461 if (!gp) {
2462 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2463 release_and_free_resource(r);
2464 return -ENOMEM;
2465 }
2466
2467 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2468 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2469
2470 gameport_set_name(gp, "ES1968 Gameport");
2471 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2472 gameport_set_dev_parent(gp, &chip->pci->dev);
2473 gp->io = JOYSTICK_ADDR;
2474 gameport_set_port_data(gp, r);
2475
2476 gameport_register_port(gp);
2477
2478 return 0;
2479 }
2480
2481 static void snd_es1968_free_gameport(struct es1968 *chip)
2482 {
2483 if (chip->gameport) {
2484 struct resource *r = gameport_get_port_data(chip->gameport);
2485
2486 gameport_unregister_port(chip->gameport);
2487 chip->gameport = NULL;
2488
2489 release_and_free_resource(r);
2490 }
2491 }
2492 #else
2493 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2494 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2495 #endif
2496
2497 static int snd_es1968_free(struct es1968 *chip)
2498 {
2499 if (chip->io_port) {
2500 synchronize_irq(chip->irq);
2501 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2502 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2503 }
2504
2505 if (chip->irq >= 0)
2506 free_irq(chip->irq, (void *)chip);
2507 snd_es1968_free_gameport(chip);
2508 snd_es1968_set_acpi(chip, ACPI_D3);
2509 chip->master_switch = NULL;
2510 chip->master_volume = NULL;
2511 pci_release_regions(chip->pci);
2512 pci_disable_device(chip->pci);
2513 kfree(chip);
2514 return 0;
2515 }
2516
2517 static int snd_es1968_dev_free(struct snd_device *device)
2518 {
2519 struct es1968 *chip = device->device_data;
2520 return snd_es1968_free(chip);
2521 }
2522
2523 struct ess_device_list {
2524 unsigned short type; /* chip type */
2525 unsigned short vendor; /* subsystem vendor id */
2526 };
2527
2528 static struct ess_device_list pm_whitelist[] __devinitdata = {
2529 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2530 { TYPE_MAESTRO2E, 0x1028 },
2531 { TYPE_MAESTRO2E, 0x103c },
2532 { TYPE_MAESTRO2E, 0x1179 },
2533 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2534 { TYPE_MAESTRO2E, 0x1558 },
2535 };
2536
2537 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2538 { TYPE_MAESTRO2, 0x125d },
2539 };
2540
2541 static int __devinit snd_es1968_create(struct snd_card *card,
2542 struct pci_dev *pci,
2543 int total_bufsize,
2544 int play_streams,
2545 int capt_streams,
2546 int chip_type,
2547 int do_pm,
2548 struct es1968 **chip_ret)
2549 {
2550 static struct snd_device_ops ops = {
2551 .dev_free = snd_es1968_dev_free,
2552 };
2553 struct es1968 *chip;
2554 int i, err;
2555
2556 *chip_ret = NULL;
2557
2558 /* enable PCI device */
2559 if ((err = pci_enable_device(pci)) < 0)
2560 return err;
2561 /* check, if we can restrict PCI DMA transfers to 28 bits */
2562 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2563 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2564 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2565 pci_disable_device(pci);
2566 return -ENXIO;
2567 }
2568
2569 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2570 if (! chip) {
2571 pci_disable_device(pci);
2572 return -ENOMEM;
2573 }
2574
2575 /* Set Vars */
2576 chip->type = chip_type;
2577 spin_lock_init(&chip->reg_lock);
2578 spin_lock_init(&chip->substream_lock);
2579 INIT_LIST_HEAD(&chip->buf_list);
2580 INIT_LIST_HEAD(&chip->substream_list);
2581 spin_lock_init(&chip->ac97_lock);
2582 init_MUTEX(&chip->memory_mutex);
2583 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2584 chip->card = card;
2585 chip->pci = pci;
2586 chip->irq = -1;
2587 chip->total_bufsize = total_bufsize; /* in bytes */
2588 chip->playback_streams = play_streams;
2589 chip->capture_streams = capt_streams;
2590
2591 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2592 kfree(chip);
2593 pci_disable_device(pci);
2594 return err;
2595 }
2596 chip->io_port = pci_resource_start(pci, 0);
2597 if (request_irq(pci->irq, snd_es1968_interrupt, SA_INTERRUPT|SA_SHIRQ,
2598 "ESS Maestro", (void*)chip)) {
2599 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2600 snd_es1968_free(chip);
2601 return -EBUSY;
2602 }
2603 chip->irq = pci->irq;
2604
2605 /* Clear Maestro_map */
2606 for (i = 0; i < 32; i++)
2607 chip->maestro_map[i] = 0;
2608
2609 /* Clear Apu Map */
2610 for (i = 0; i < NR_APUS; i++)
2611 chip->apu[i] = ESM_APU_FREE;
2612
2613 /* just to be sure */
2614 pci_set_master(pci);
2615
2616 if (do_pm > 1) {
2617 /* disable power-management if not on the whitelist */
2618 unsigned short vend;
2619 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2620 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2621 if (chip->type == pm_whitelist[i].type &&
2622 vend == pm_whitelist[i].vendor) {
2623 do_pm = 1;
2624 break;
2625 }
2626 }
2627 if (do_pm > 1) {
2628 /* not matched; disabling pm */
2629 printk(KERN_INFO "es1968: not attempting power management.\n");
2630 do_pm = 0;
2631 }
2632 }
2633 chip->do_pm = do_pm;
2634
2635 snd_es1968_chip_init(chip);
2636
2637 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2638 snd_es1968_free(chip);
2639 return err;
2640 }
2641
2642 snd_card_set_dev(card, &pci->dev);
2643
2644 *chip_ret = chip;
2645
2646 return 0;
2647 }
2648
2649
2650 /*
2651 */
2652 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2653 const struct pci_device_id *pci_id)
2654 {
2655 static int dev;
2656 struct snd_card *card;
2657 struct es1968 *chip;
2658 unsigned int i;
2659 int err;
2660
2661 if (dev >= SNDRV_CARDS)
2662 return -ENODEV;
2663 if (!enable[dev]) {
2664 dev++;
2665 return -ENOENT;
2666 }
2667
2668 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2669 if (!card)
2670 return -ENOMEM;
2671
2672 if (total_bufsize[dev] < 128)
2673 total_bufsize[dev] = 128;
2674 if (total_bufsize[dev] > 4096)
2675 total_bufsize[dev] = 4096;
2676 if ((err = snd_es1968_create(card, pci,
2677 total_bufsize[dev] * 1024, /* in bytes */
2678 pcm_substreams_p[dev],
2679 pcm_substreams_c[dev],
2680 pci_id->driver_data,
2681 use_pm[dev],
2682 &chip)) < 0) {
2683 snd_card_free(card);
2684 return err;
2685 }
2686 card->private_data = chip;
2687
2688 switch (chip->type) {
2689 case TYPE_MAESTRO2E:
2690 strcpy(card->driver, "ES1978");
2691 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2692 break;
2693 case TYPE_MAESTRO2:
2694 strcpy(card->driver, "ES1968");
2695 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2696 break;
2697 case TYPE_MAESTRO:
2698 strcpy(card->driver, "ESM1");
2699 strcpy(card->shortname, "ESS Maestro 1");
2700 break;
2701 }
2702
2703 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2704 snd_card_free(card);
2705 return err;
2706 }
2707
2708 if ((err = snd_es1968_mixer(chip)) < 0) {
2709 snd_card_free(card);
2710 return err;
2711 }
2712
2713 if (enable_mpu[dev] == 2) {
2714 /* check the black list */
2715 unsigned short vend;
2716 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2717 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2718 if (chip->type == mpu_blacklist[i].type &&
2719 vend == mpu_blacklist[i].vendor) {
2720 enable_mpu[dev] = 0;
2721 break;
2722 }
2723 }
2724 }
2725 if (enable_mpu[dev]) {
2726 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2727 chip->io_port + ESM_MPU401_PORT, 1,
2728 chip->irq, 0, &chip->rmidi)) < 0) {
2729 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2730 }
2731 }
2732
2733 snd_es1968_create_gameport(chip, dev);
2734
2735 snd_es1968_start_irq(chip);
2736
2737 chip->clock = clock[dev];
2738 if (! chip->clock)
2739 es1968_measure_clock(chip);
2740
2741 sprintf(card->longname, "%s at 0x%lx, irq %i",
2742 card->shortname, chip->io_port, chip->irq);
2743
2744 if ((err = snd_card_register(card)) < 0) {
2745 snd_card_free(card);
2746 return err;
2747 }
2748 pci_set_drvdata(pci, card);
2749 dev++;
2750 return 0;
2751 }
2752
2753 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2754 {
2755 snd_card_free(pci_get_drvdata(pci));
2756 pci_set_drvdata(pci, NULL);
2757 }
2758
2759 static struct pci_driver driver = {
2760 .name = "ES1968 (ESS Maestro)",
2761 .id_table = snd_es1968_ids,
2762 .probe = snd_es1968_probe,
2763 .remove = __devexit_p(snd_es1968_remove),
2764 #ifdef CONFIG_PM
2765 .suspend = es1968_suspend,
2766 .resume = es1968_resume,
2767 #endif
2768 };
2769
2770 static int __init alsa_card_es1968_init(void)
2771 {
2772 return pci_register_driver(&driver);
2773 }
2774
2775 static void __exit alsa_card_es1968_exit(void)
2776 {
2777 pci_unregister_driver(&driver);
2778 }
2779
2780 module_init(alsa_card_es1968_init)
2781 module_exit(alsa_card_es1968_exit)
Verdex Pro support