5 #include <asm/desc_defs.h>
10 static inline void fill_ldt(struct desc_struct
*desc
,
11 const struct user_desc
*info
)
13 desc
->limit0
= info
->limit
& 0x0ffff;
14 desc
->base0
= info
->base_addr
& 0x0000ffff;
16 desc
->base1
= (info
->base_addr
& 0x00ff0000) >> 16;
17 desc
->type
= (info
->read_exec_only
^ 1) << 1;
18 desc
->type
|= info
->contents
<< 2;
21 desc
->p
= info
->seg_not_present
^ 1;
22 desc
->limit
= (info
->limit
& 0xf0000) >> 16;
23 desc
->avl
= info
->useable
;
24 desc
->d
= info
->seg_32bit
;
25 desc
->g
= info
->limit_in_pages
;
26 desc
->base2
= (info
->base_addr
& 0xff000000) >> 24;
29 extern struct desc_ptr idt_descr
;
30 extern gate_desc idt_table
[];
33 struct desc_struct gdt
[GDT_ENTRIES
];
34 } __attribute__((aligned(PAGE_SIZE
)));
35 DECLARE_PER_CPU(struct gdt_page
, gdt_page
);
37 static inline struct desc_struct
*get_cpu_gdt_table(unsigned int cpu
)
39 return per_cpu(gdt_page
, cpu
).gdt
;
44 static inline void pack_gate(gate_desc
*gate
, unsigned type
, unsigned long func
,
45 unsigned dpl
, unsigned ist
, unsigned seg
)
47 gate
->offset_low
= PTR_LOW(func
);
48 gate
->segment
= __KERNEL_CS
;
55 gate
->offset_middle
= PTR_MIDDLE(func
);
56 gate
->offset_high
= PTR_HIGH(func
);
60 static inline void pack_gate(gate_desc
*gate
, unsigned char type
,
61 unsigned long base
, unsigned dpl
, unsigned flags
,
64 gate
->a
= (seg
<< 16) | (base
& 0xffff);
65 gate
->b
= (base
& 0xffff0000) |
66 (((0x80 | type
| (dpl
<< 5)) & 0xff) << 8);
71 static inline int desc_empty(const void *ptr
)
73 const u32
*desc
= ptr
;
74 return !(desc
[0] | desc
[1]);
77 #ifdef CONFIG_PARAVIRT
78 #include <asm/paravirt.h>
80 #define load_TR_desc() native_load_tr_desc()
81 #define load_gdt(dtr) native_load_gdt(dtr)
82 #define load_idt(dtr) native_load_idt(dtr)
83 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
84 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
86 #define store_gdt(dtr) native_store_gdt(dtr)
87 #define store_idt(dtr) native_store_idt(dtr)
88 #define store_tr(tr) (tr = native_store_tr())
89 #define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
91 #define load_TLS(t, cpu) native_load_tls(t, cpu)
92 #define set_ldt native_set_ldt
94 #define write_ldt_entry(dt, entry, desc) \
95 native_write_ldt_entry(dt, entry, desc)
96 #define write_gdt_entry(dt, entry, desc, type) \
97 native_write_gdt_entry(dt, entry, desc, type)
98 #define write_idt_entry(dt, entry, g) \
99 native_write_idt_entry(dt, entry, g)
102 static inline void native_write_idt_entry(gate_desc
*idt
, int entry
,
103 const gate_desc
*gate
)
105 memcpy(&idt
[entry
], gate
, sizeof(*gate
));
108 static inline void native_write_ldt_entry(struct desc_struct
*ldt
, int entry
,
111 memcpy(&ldt
[entry
], desc
, 8);
114 static inline void native_write_gdt_entry(struct desc_struct
*gdt
, int entry
,
115 const void *desc
, int type
)
120 size
= sizeof(tss_desc
);
123 size
= sizeof(ldt_desc
);
126 size
= sizeof(struct desc_struct
);
129 memcpy(&gdt
[entry
], desc
, size
);
132 static inline void pack_descriptor(struct desc_struct
*desc
, unsigned long base
,
133 unsigned long limit
, unsigned char type
,
136 desc
->a
= ((base
& 0xffff) << 16) | (limit
& 0xffff);
137 desc
->b
= (base
& 0xff000000) | ((base
& 0xff0000) >> 16) |
138 (limit
& 0x000f0000) | ((type
& 0xff) << 8) |
139 ((flags
& 0xf) << 20);
144 static inline void set_tssldt_descriptor(void *d
, unsigned long addr
,
145 unsigned type
, unsigned size
)
148 struct ldttss_desc64
*desc
= d
;
149 memset(desc
, 0, sizeof(*desc
));
150 desc
->limit0
= size
& 0xFFFF;
151 desc
->base0
= PTR_LOW(addr
);
152 desc
->base1
= PTR_MIDDLE(addr
) & 0xFF;
155 desc
->limit1
= (size
>> 16) & 0xF;
156 desc
->base2
= (PTR_MIDDLE(addr
) >> 8) & 0xFF;
157 desc
->base3
= PTR_HIGH(addr
);
159 pack_descriptor((struct desc_struct
*)d
, addr
, size
, 0x80 | type
, 0);
163 static inline void __set_tss_desc(unsigned cpu
, unsigned int entry
, void *addr
)
165 struct desc_struct
*d
= get_cpu_gdt_table(cpu
);
169 * sizeof(unsigned long) coming from an extra "long" at the end
170 * of the iobitmap. See tss_struct definition in processor.h
172 * -1? seg base+limit should be pointing to the address of the
175 set_tssldt_descriptor(&tss
, (unsigned long)addr
, DESC_TSS
,
176 IO_BITMAP_OFFSET
+ IO_BITMAP_BYTES
+
177 sizeof(unsigned long) - 1);
178 write_gdt_entry(d
, entry
, &tss
, DESC_TSS
);
181 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
183 static inline void native_set_ldt(const void *addr
, unsigned int entries
)
185 if (likely(entries
== 0))
186 asm volatile("lldt %w0"::"q" (0));
188 unsigned cpu
= smp_processor_id();
191 set_tssldt_descriptor(&ldt
, (unsigned long)addr
, DESC_LDT
,
192 entries
* LDT_ENTRY_SIZE
- 1);
193 write_gdt_entry(get_cpu_gdt_table(cpu
), GDT_ENTRY_LDT
,
195 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT
*8));
199 static inline void native_load_tr_desc(void)
201 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS
*8));
204 static inline void native_load_gdt(const struct desc_ptr
*dtr
)
206 asm volatile("lgdt %0"::"m" (*dtr
));
209 static inline void native_load_idt(const struct desc_ptr
*dtr
)
211 asm volatile("lidt %0"::"m" (*dtr
));
214 static inline void native_store_gdt(struct desc_ptr
*dtr
)
216 asm volatile("sgdt %0":"=m" (*dtr
));
219 static inline void native_store_idt(struct desc_ptr
*dtr
)
221 asm volatile("sidt %0":"=m" (*dtr
));
224 static inline unsigned long native_store_tr(void)
227 asm volatile("str %0":"=r" (tr
));
231 static inline void native_load_tls(struct thread_struct
*t
, unsigned int cpu
)
234 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
236 for (i
= 0; i
< GDT_ENTRY_TLS_ENTRIES
; i
++)
237 gdt
[GDT_ENTRY_TLS_MIN
+ i
] = t
->tls_array
[i
];
240 #define _LDT_empty(info) \
241 ((info)->base_addr == 0 && \
242 (info)->limit == 0 && \
243 (info)->contents == 0 && \
244 (info)->read_exec_only == 1 && \
245 (info)->seg_32bit == 0 && \
246 (info)->limit_in_pages == 0 && \
247 (info)->seg_not_present == 1 && \
248 (info)->useable == 0)
251 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
253 #define LDT_empty(info) (_LDT_empty(info))
256 static inline void clear_LDT(void)
262 * load one particular LDT into the current CPU
264 static inline void load_LDT_nolock(mm_context_t
*pc
)
266 set_ldt(pc
->ldt
, pc
->size
);
269 static inline void load_LDT(mm_context_t
*pc
)
276 static inline unsigned long get_desc_base(const struct desc_struct
*desc
)
278 return desc
->base0
| ((desc
->base1
) << 16) | ((desc
->base2
) << 24);
281 static inline unsigned long get_desc_limit(const struct desc_struct
*desc
)
283 return desc
->limit0
| (desc
->limit
<< 16);
286 static inline void _set_gate(int gate
, unsigned type
, void *addr
,
287 unsigned dpl
, unsigned ist
, unsigned seg
)
290 pack_gate(&s
, type
, (unsigned long)addr
, dpl
, ist
, seg
);
292 * does not need to be atomic because it is only done once at
295 write_idt_entry(idt_table
, gate
, &s
);
299 * This needs to use 'idt_table' rather than 'idt', and
300 * thus use the _nonmapped_ version of the IDT, as the
301 * Pentium F0 0F bugfix can have resulted in the mapped
302 * IDT being write-protected.
304 static inline void set_intr_gate(unsigned int n
, void *addr
)
306 BUG_ON((unsigned)n
> 0xFF);
307 _set_gate(n
, GATE_INTERRUPT
, addr
, 0, 0, __KERNEL_CS
);
310 #define SYS_VECTOR_FREE 0
311 #define SYS_VECTOR_ALLOCED 1
313 extern int first_system_vector
;
314 extern char system_vectors
[];
316 static inline void alloc_system_vector(int vector
)
318 if (system_vectors
[vector
] == SYS_VECTOR_FREE
) {
319 system_vectors
[vector
] = SYS_VECTOR_ALLOCED
;
320 if (first_system_vector
> vector
)
321 first_system_vector
= vector
;
326 static inline void alloc_intr_gate(unsigned int n
, void *addr
)
328 alloc_system_vector(n
);
329 set_intr_gate(n
, addr
);
333 * This routine sets up an interrupt gate at directory privilege level 3.
335 static inline void set_system_intr_gate(unsigned int n
, void *addr
)
337 BUG_ON((unsigned)n
> 0xFF);
338 _set_gate(n
, GATE_INTERRUPT
, addr
, 0x3, 0, __KERNEL_CS
);
341 static inline void set_trap_gate(unsigned int n
, void *addr
)
343 BUG_ON((unsigned)n
> 0xFF);
344 _set_gate(n
, GATE_TRAP
, addr
, 0, 0, __KERNEL_CS
);
347 static inline void set_system_gate(unsigned int n
, void *addr
)
349 BUG_ON((unsigned)n
> 0xFF);
351 _set_gate(n
, GATE_TRAP
, addr
, 0x3, 0, __KERNEL_CS
);
353 _set_gate(n
, GATE_INTERRUPT
, addr
, 0x3, 0, __KERNEL_CS
);
357 static inline void set_task_gate(unsigned int n
, unsigned int gdt_entry
)
359 BUG_ON((unsigned)n
> 0xFF);
360 _set_gate(n
, GATE_TASK
, (void *)0, 0, 0, (gdt_entry
<<3));
363 static inline void set_intr_gate_ist(int n
, void *addr
, unsigned ist
)
365 BUG_ON((unsigned)n
> 0xFF);
366 _set_gate(n
, GATE_INTERRUPT
, addr
, 0, ist
, __KERNEL_CS
);
369 static inline void set_system_gate_ist(int n
, void *addr
, unsigned ist
)
371 BUG_ON((unsigned)n
> 0xFF);
372 _set_gate(n
, GATE_INTERRUPT
, addr
, 0x3, ist
, __KERNEL_CS
);
377 * GET_DESC_BASE reads the descriptor base of the specified segment.
380 * idx - descriptor index
382 * base - 32bit register to which the base will be written
383 * lo_w - lo word of the "base" register
384 * lo_b - lo byte of the "base" register
385 * hi_b - hi byte of the low word of the "base" register
388 * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
389 * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
391 #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
392 movb idx * 8 + 4(gdt), lo_b; \
393 movb idx * 8 + 7(gdt), hi_b; \
395 movw idx * 8 + 2(gdt), lo_w;
398 #endif /* __ASSEMBLY__ */