?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] x86_64: Fix wrong PCI ID for ALI M1695 AGP bridge
[linux-2.6/verdex.git] / drivers / char / agp / amd64-agp.c
blob7c6c7268e236afb231b084a9c6c06aa1e35d7941
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/agp_backend.h>
16 #include <linux/mmzone.h>
17 #include <asm/page.h> /* PAGE_SIZE */
18 #include "agp.h"
19
20 /* Will need to be increased if AMD64 ever goes >8-way. */
21 #define MAX_HAMMER_GARTS 8
22
23 /* PTE bits. */
24 #define GPTE_VALID 1
25 #define GPTE_COHERENT 2
26
27 /* Aperture control register bits. */
28 #define GARTEN (1<<0)
29 #define DISGARTCPU (1<<4)
30 #define DISGARTIO (1<<5)
31
32 /* GART cache control register bits. */
33 #define INVGART (1<<0)
34 #define GARTPTEERR (1<<1)
35
36 /* K8 On-cpu GART registers */
37 #define AMD64_GARTAPERTURECTL 0x90
38 #define AMD64_GARTAPERTUREBASE 0x94
39 #define AMD64_GARTTABLEBASE 0x98
40 #define AMD64_GARTCACHECTL 0x9c
41 #define AMD64_GARTEN (1<<0)
42
43 /* NVIDIA K8 registers */
44 #define NVIDIA_X86_64_0_APBASE 0x10
45 #define NVIDIA_X86_64_1_APBASE1 0x50
46 #define NVIDIA_X86_64_1_APLIMIT1 0x54
47 #define NVIDIA_X86_64_1_APSIZE 0xa8
48 #define NVIDIA_X86_64_1_APBASE2 0xd8
49 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
50
51 /* ULi K8 registers */
52 #define ULI_X86_64_BASE_ADDR 0x10
53 #define ULI_X86_64_HTT_FEA_REG 0x50
54 #define ULI_X86_64_ENU_SCR_REG 0x54
55
56 static int nr_garts;
57 static struct pci_dev * hammers[MAX_HAMMER_GARTS];
58
59 static struct resource *aperture_resource;
60 static int __initdata agp_try_unsupported = 1;
61
62 #define for_each_nb() for(gart_iterator=0;gart_iterator<nr_garts;gart_iterator++)
63
64 static void flush_amd64_tlb(struct pci_dev *dev)
65 {
66 u32 tmp;
67
68 pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp);
69 tmp |= INVGART;
70 pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp);
71 }
72
73 static void amd64_tlbflush(struct agp_memory *temp)
74 {
75 int gart_iterator;
76 for_each_nb()
77 flush_amd64_tlb(hammers[gart_iterator]);
78 }
79
80 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
81 {
82 int i, j, num_entries;
83 long long tmp;
84 u32 pte;
85
86 num_entries = agp_num_entries();
87
88 if (type != 0 || mem->type != 0)
89 return -EINVAL;
90
91 /* Make sure we can fit the range in the gatt table. */
92 /* FIXME: could wrap */
93 if (((unsigned long)pg_start + mem->page_count) > num_entries)
94 return -EINVAL;
95
96 j = pg_start;
97
98 /* gatt table should be empty. */
99 while (j < (pg_start + mem->page_count)) {
100 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
101 return -EBUSY;
102 j++;
103 }
104
105 if (mem->is_flushed == FALSE) {
106 global_cache_flush();
107 mem->is_flushed = TRUE;
108 }
109
110 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
111 tmp = agp_bridge->driver->mask_memory(agp_bridge,
112 mem->memory[i], mem->type);
113
114 BUG_ON(tmp & 0xffffff0000000ffcULL);
115 pte = (tmp & 0x000000ff00000000ULL) >> 28;
116 pte |=(tmp & 0x00000000fffff000ULL);
117 pte |= GPTE_VALID | GPTE_COHERENT;
118
119 writel(pte, agp_bridge->gatt_table+j);
120 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
121 }
122 amd64_tlbflush(mem);
123 return 0;
124 }
125
126 /*
127 * This hack alters the order element according
128 * to the size of a long. It sucks. I totally disown this, even
129 * though it does appear to work for the most part.
130 */
131 static struct aper_size_info_32 amd64_aperture_sizes[7] =
132 {
133 {32, 8192, 3+(sizeof(long)/8), 0 },
134 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
135 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
136 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
137 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
138 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
139 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
140 };
141
142
143 /*
144 * Get the current Aperture size from the x86-64.
145 * Note, that there may be multiple x86-64's, but we just return
146 * the value from the first one we find. The set_size functions
147 * keep the rest coherent anyway. Or at least should do.
148 */
149 static int amd64_fetch_size(void)
150 {
151 struct pci_dev *dev;
152 int i;
153 u32 temp;
154 struct aper_size_info_32 *values;
155
156 dev = hammers[0];
157 if (dev==NULL)
158 return 0;
159
160 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
161 temp = (temp & 0xe);
162 values = A_SIZE_32(amd64_aperture_sizes);
163
164 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
165 if (temp == values[i].size_value) {
166 agp_bridge->previous_size =
167 agp_bridge->current_size = (void *) (values + i);
168
169 agp_bridge->aperture_size_idx = i;
170 return values[i].size;
171 }
172 }
173 return 0;
174 }
175
176 /*
177 * In a multiprocessor x86-64 system, this function gets
178 * called once for each CPU.
179 */
180 static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
181 {
182 u64 aperturebase;
183 u32 tmp;
184 u64 addr, aper_base;
185
186 /* Address to map to */
187 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
188 aperturebase = tmp << 25;
189 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
190
191 /* address of the mappings table */
192 addr = (u64) gatt_table;
193 addr >>= 12;
194 tmp = (u32) addr<<4;
195 tmp &= ~0xf;
196 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
197
198 /* Enable GART translation for this hammer. */
199 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
200 tmp |= GARTEN;
201 tmp &= ~(DISGARTCPU | DISGARTIO);
202 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
203
204 /* keep CPU's coherent. */
205 flush_amd64_tlb (hammer);
206
207 return aper_base;
208 }
209
210
211 static struct aper_size_info_32 amd_8151_sizes[7] =
212 {
213 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
214 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
215 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
216 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
217 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
218 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
219 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
220 };
221
222 static int amd_8151_configure(void)
223 {
224 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
225 int gart_iterator;
226
227 /* Configure AGP regs in each x86-64 host bridge. */
228 for_each_nb() {
229 agp_bridge->gart_bus_addr =
230 amd64_configure(hammers[gart_iterator],gatt_bus);
231 }
232 return 0;
233 }
234
235
236 static void amd64_cleanup(void)
237 {
238 u32 tmp;
239 int gart_iterator;
240 for_each_nb() {
241 /* disable gart translation */
242 pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp);
243 tmp &= ~AMD64_GARTEN;
244 pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp);
245 }
246 }
247
248
249 static struct agp_bridge_driver amd_8151_driver = {
250 .owner = THIS_MODULE,
251 .aperture_sizes = amd_8151_sizes,
252 .size_type = U32_APER_SIZE,
253 .num_aperture_sizes = 7,
254 .configure = amd_8151_configure,
255 .fetch_size = amd64_fetch_size,
256 .cleanup = amd64_cleanup,
257 .tlb_flush = amd64_tlbflush,
258 .mask_memory = agp_generic_mask_memory,
259 .masks = NULL,
260 .agp_enable = agp_generic_enable,
261 .cache_flush = global_cache_flush,
262 .create_gatt_table = agp_generic_create_gatt_table,
263 .free_gatt_table = agp_generic_free_gatt_table,
264 .insert_memory = amd64_insert_memory,
265 .remove_memory = agp_generic_remove_memory,
266 .alloc_by_type = agp_generic_alloc_by_type,
267 .free_by_type = agp_generic_free_by_type,
268 .agp_alloc_page = agp_generic_alloc_page,
269 .agp_destroy_page = agp_generic_destroy_page,
270 };
271
272 /* Some basic sanity checks for the aperture. */
273 static int __devinit aperture_valid(u64 aper, u32 size)
274 {
275 u32 pfn, c;
276 if (aper == 0) {
277 printk(KERN_ERR PFX "No aperture\n");
278 return 0;
279 }
280 if (size < 32*1024*1024) {
281 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
282 return 0;
283 }
284 if (aper + size > 0xffffffff) {
285 printk(KERN_ERR PFX "Aperture out of bounds\n");
286 return 0;
287 }
288 pfn = aper >> PAGE_SHIFT;
289 for (c = 0; c < size/PAGE_SIZE; c++) {
290 if (!pfn_valid(pfn + c))
291 break;
292 if (!PageReserved(pfn_to_page(pfn + c))) {
293 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
294 return 0;
295 }
296 }
297
298 /* Request the Aperture. This catches cases when someone else
299 already put a mapping in there - happens with some very broken BIOS
300
301 Maybe better to use pci_assign_resource/pci_enable_device instead
302 trusting the bridges? */
303 if (!aperture_resource &&
304 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
305 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
306 return 0;
307 }
308 return 1;
309 }
310
311 /*
312 * W*s centric BIOS sometimes only set up the aperture in the AGP
313 * bridge, not the northbridge. On AMD64 this is handled early
314 * in aperture.c, but when GART_IOMMU is not enabled or we run
315 * on a 32bit kernel this needs to be redone.
316 * Unfortunately it is impossible to fix the aperture here because it's too late
317 * to allocate that much memory. But at least error out cleanly instead of
318 * crashing.
319 */
320 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
321 u16 cap)
322 {
323 u32 aper_low, aper_hi;
324 u64 aper, nb_aper;
325 int order = 0;
326 u32 nb_order, nb_base;
327 u16 apsize;
328
329 pci_read_config_dword(nb, 0x90, &nb_order);
330 nb_order = (nb_order >> 1) & 7;
331 pci_read_config_dword(nb, 0x94, &nb_base);
332 nb_aper = nb_base << 25;
333 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
334 return 0;
335 }
336
337 /* Northbridge seems to contain crap. Try the AGP bridge. */
338
339 pci_read_config_word(agp, cap+0x14, &apsize);
340 if (apsize == 0xffff)
341 return -1;
342
343 apsize &= 0xfff;
344 /* Some BIOS use weird encodings not in the AGPv3 table. */
345 if (apsize & 0xff)
346 apsize |= 0xf00;
347 order = 7 - hweight16(apsize);
348
349 pci_read_config_dword(agp, 0x10, &aper_low);
350 pci_read_config_dword(agp, 0x14, &aper_hi);
351 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
352 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
353 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
354 return -1;
355
356 pci_write_config_dword(nb, 0x90, order << 1);
357 pci_write_config_dword(nb, 0x94, aper >> 25);
358
359 return 0;
360 }
361
362 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
363 {
364 struct pci_dev *loop_dev = NULL;
365 int i = 0;
366
367 /* cache pci_devs of northbridges. */
368 while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev))
369 != NULL) {
370 if (i == MAX_HAMMER_GARTS) {
371 printk(KERN_ERR PFX "Too many northbridges for AGP\n");
372 return -1;
373 }
374 if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) {
375 printk(KERN_ERR PFX "No usable aperture found.\n");
376 #ifdef __x86_64__
377 /* should port this to i386 */
378 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
379 #endif
380 return -1;
381 }
382 hammers[i++] = loop_dev;
383 }
384 nr_garts = i;
385 return i == 0 ? -1 : 0;
386 }
387
388 /* Handle AMD 8151 quirks */
389 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
390 {
391 char *revstring;
392 u8 rev_id;
393
394 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
395 switch (rev_id) {
396 case 0x01: revstring="A0"; break;
397 case 0x02: revstring="A1"; break;
398 case 0x11: revstring="B0"; break;
399 case 0x12: revstring="B1"; break;
400 case 0x13: revstring="B2"; break;
401 case 0x14: revstring="B3"; break;
402 default: revstring="??"; break;
403 }
404
405 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
406
407 /*
408 * Work around errata.
409 * Chips before B2 stepping incorrectly reporting v3.5
410 */
411 if (rev_id < 0x13) {
412 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
413 bridge->major_version = 3;
414 bridge->minor_version = 0;
415 }
416 }
417
418
419 static const struct aper_size_info_32 uli_sizes[7] =
420 {
421 {256, 65536, 6, 10},
422 {128, 32768, 5, 9},
423 {64, 16384, 4, 8},
424 {32, 8192, 3, 7},
425 {16, 4096, 2, 6},
426 {8, 2048, 1, 4},
427 {4, 1024, 0, 3}
428 };
429 static int __devinit uli_agp_init(struct pci_dev *pdev)
430 {
431 u32 httfea,baseaddr,enuscr;
432 struct pci_dev *dev1;
433 int i;
434 unsigned size = amd64_fetch_size();
435 printk(KERN_INFO "Setting up ULi AGP.\n");
436 dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0));
437 if (dev1 == NULL) {
438 printk(KERN_INFO PFX "Detected a ULi chipset, "
439 "but could not fine the secondary device.\n");
440 return -ENODEV;
441 }
442
443 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
444 if (uli_sizes[i].size == size)
445 break;
446
447 if (i == ARRAY_SIZE(uli_sizes)) {
448 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
449 return -ENODEV;
450 }
451
452 /* shadow x86-64 registers into ULi registers */
453 pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea);
454
455 /* if x86-64 aperture base is beyond 4G, exit here */
456 if ((httfea & 0x7fff) >> (32 - 25))
457 return -ENODEV;
458
459 httfea = (httfea& 0x7fff) << 25;
460
461 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
462 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
463 baseaddr|= httfea;
464 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
465
466 enuscr= httfea+ (size * 1024 * 1024) - 1;
467 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
468 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
469 return 0;
470 }
471
472
473 static const struct aper_size_info_32 nforce3_sizes[5] =
474 {
475 {512, 131072, 7, 0x00000000 },
476 {256, 65536, 6, 0x00000008 },
477 {128, 32768, 5, 0x0000000C },
478 {64, 16384, 4, 0x0000000E },
479 {32, 8192, 3, 0x0000000F }
480 };
481
482 /* Handle shadow device of the Nvidia NForce3 */
483 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
484 static int __devinit nforce3_agp_init(struct pci_dev *pdev)
485 {
486 u32 tmp, apbase, apbar, aplimit;
487 struct pci_dev *dev1;
488 int i;
489 unsigned size = amd64_fetch_size();
490
491 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
492
493 dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0));
494 if (dev1 == NULL) {
495 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
496 "nForce3 chipset, but could not find "
497 "the secondary device.\n");
498 return -ENODEV;
499 }
500
501 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
502 if (nforce3_sizes[i].size == size)
503 break;
504
505 if (i == ARRAY_SIZE(nforce3_sizes)) {
506 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
507 return -ENODEV;
508 }
509
510 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
511 tmp &= ~(0xf);
512 tmp |= nforce3_sizes[i].size_value;
513 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
514
515 /* shadow x86-64 registers into NVIDIA registers */
516 pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase);
517
518 /* if x86-64 aperture base is beyond 4G, exit here */
519 if ( (apbase & 0x7fff) >> (32 - 25) ) {
520 printk(KERN_INFO PFX "aperture base > 4G\n");
521 return -ENODEV;
522 }
523
524 apbase = (apbase & 0x7fff) << 25;
525
526 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
527 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
528 apbar |= apbase;
529 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
530
531 aplimit = apbase + (size * 1024 * 1024) - 1;
532 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
533 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
534 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
535 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
536
537 return 0;
538 }
539
540 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
541 const struct pci_device_id *ent)
542 {
543 struct agp_bridge_data *bridge;
544 u8 cap_ptr;
545
546 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
547 if (!cap_ptr)
548 return -ENODEV;
549
550 /* Could check for AGPv3 here */
551
552 bridge = agp_alloc_bridge();
553 if (!bridge)
554 return -ENOMEM;
555
556 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
557 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
558 amd8151_init(pdev, bridge);
559 } else {
560 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
561 }
562
563 bridge->driver = &amd_8151_driver;
564 bridge->dev = pdev;
565 bridge->capndx = cap_ptr;
566
567 /* Fill in the mode register */
568 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
569
570 if (cache_nbs(pdev, cap_ptr) == -1) {
571 agp_put_bridge(bridge);
572 return -ENODEV;
573 }
574
575 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
576 int ret = nforce3_agp_init(pdev);
577 if (ret) {
578 agp_put_bridge(bridge);
579 return ret;
580 }
581 }
582
583 if (pdev->vendor == PCI_VENDOR_ID_AL) {
584 int ret = uli_agp_init(pdev);
585 if (ret) {
586 agp_put_bridge(bridge);
587 return ret;
588 }
589 }
590
591 pci_set_drvdata(pdev, bridge);
592 return agp_add_bridge(bridge);
593 }
594
595 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
596 {
597 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
598
599 release_mem_region(virt_to_gart(bridge->gatt_table_real),
600 amd64_aperture_sizes[bridge->aperture_size_idx].size);
601 agp_remove_bridge(bridge);
602 agp_put_bridge(bridge);
603 }
604
605 #ifdef CONFIG_PM
606
607 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
608 {
609 pci_save_state(pdev);
610 pci_set_power_state(pdev, pci_choose_state(pdev, state));
611
612 return 0;
613 }
614
615 static int agp_amd64_resume(struct pci_dev *pdev)
616 {
617 pci_set_power_state(pdev, PCI_D0);
618 pci_restore_state(pdev);
619
620 return amd_8151_configure();
621 }
622
623 #endif /* CONFIG_PM */
624
625 static struct pci_device_id agp_amd64_pci_table[] = {
626 {
627 .class = (PCI_CLASS_BRIDGE_HOST << 8),
628 .class_mask = ~0,
629 .vendor = PCI_VENDOR_ID_AMD,
630 .device = PCI_DEVICE_ID_AMD_8151_0,
631 .subvendor = PCI_ANY_ID,
632 .subdevice = PCI_ANY_ID,
633 },
634 /* ULi M1689 */
635 {
636 .class = (PCI_CLASS_BRIDGE_HOST << 8),
637 .class_mask = ~0,
638 .vendor = PCI_VENDOR_ID_AL,
639 .device = PCI_DEVICE_ID_AL_M1689,
640 .subvendor = PCI_ANY_ID,
641 .subdevice = PCI_ANY_ID,
642 },
643 /* VIA K8T800Pro */
644 {
645 .class = (PCI_CLASS_BRIDGE_HOST << 8),
646 .class_mask = ~0,
647 .vendor = PCI_VENDOR_ID_VIA,
648 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 },
652 /* VIA K8T800 */
653 {
654 .class = (PCI_CLASS_BRIDGE_HOST << 8),
655 .class_mask = ~0,
656 .vendor = PCI_VENDOR_ID_VIA,
657 .device = PCI_DEVICE_ID_VIA_8385_0,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 },
661 /* VIA K8M800 / K8N800 */
662 {
663 .class = (PCI_CLASS_BRIDGE_HOST << 8),
664 .class_mask = ~0,
665 .vendor = PCI_VENDOR_ID_VIA,
666 .device = PCI_DEVICE_ID_VIA_8380_0,
667 .subvendor = PCI_ANY_ID,
668 .subdevice = PCI_ANY_ID,
669 },
670 /* VIA K8T890 */
671 {
672 .class = (PCI_CLASS_BRIDGE_HOST << 8),
673 .class_mask = ~0,
674 .vendor = PCI_VENDOR_ID_VIA,
675 .device = PCI_DEVICE_ID_VIA_3238_0,
676 .subvendor = PCI_ANY_ID,
677 .subdevice = PCI_ANY_ID,
678 },
679 /* VIA K8T800/K8M800/K8N800 */
680 {
681 .class = (PCI_CLASS_BRIDGE_HOST << 8),
682 .class_mask = ~0,
683 .vendor = PCI_VENDOR_ID_VIA,
684 .device = PCI_DEVICE_ID_VIA_838X_1,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = PCI_ANY_ID,
687 },
688 /* NForce3 */
689 {
690 .class = (PCI_CLASS_BRIDGE_HOST << 8),
691 .class_mask = ~0,
692 .vendor = PCI_VENDOR_ID_NVIDIA,
693 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
694 .subvendor = PCI_ANY_ID,
695 .subdevice = PCI_ANY_ID,
696 },
697 {
698 .class = (PCI_CLASS_BRIDGE_HOST << 8),
699 .class_mask = ~0,
700 .vendor = PCI_VENDOR_ID_NVIDIA,
701 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
702 .subvendor = PCI_ANY_ID,
703 .subdevice = PCI_ANY_ID,
704 },
705 /* SIS 755 */
706 {
707 .class = (PCI_CLASS_BRIDGE_HOST << 8),
708 .class_mask = ~0,
709 .vendor = PCI_VENDOR_ID_SI,
710 .device = PCI_DEVICE_ID_SI_755,
711 .subvendor = PCI_ANY_ID,
712 .subdevice = PCI_ANY_ID,
713 },
714 /* SIS 760 */
715 {
716 .class = (PCI_CLASS_BRIDGE_HOST << 8),
717 .class_mask = ~0,
718 .vendor = PCI_VENDOR_ID_SI,
719 .device = PCI_DEVICE_ID_SI_760,
720 .subvendor = PCI_ANY_ID,
721 .subdevice = PCI_ANY_ID,
722 },
723 /* ALI/ULI M1695 */
724 {
725 .class = (PCI_CLASS_BRIDGE_HOST << 8),
726 .class_mask = ~0,
727 .vendor = PCI_VENDOR_ID_AL,
728 .device = 0x1695,
729 .subvendor = PCI_ANY_ID,
730 .subdevice = PCI_ANY_ID,
731 },
732
733 { }
734 };
735
736 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
737
738 static struct pci_driver agp_amd64_pci_driver = {
739 .name = "agpgart-amd64",
740 .id_table = agp_amd64_pci_table,
741 .probe = agp_amd64_probe,
742 .remove = agp_amd64_remove,
743 #ifdef CONFIG_PM
744 .suspend = agp_amd64_suspend,
745 .resume = agp_amd64_resume,
746 #endif
747 };
748
749
750 /* Not static due to IOMMU code calling it early. */
751 int __init agp_amd64_init(void)
752 {
753 int err = 0;
754 static struct pci_device_id amd64nb[] = {
755 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
756 { },
757 };
758
759 if (agp_off)
760 return -EINVAL;
761 if (pci_register_driver(&agp_amd64_pci_driver) > 0) {
762 struct pci_dev *dev;
763 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
764 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
765 #ifdef MODULE
766 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
767 #else
768 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
769 #endif
770 return -ENODEV;
771 }
772
773 /* First check that we have at least one AMD64 NB */
774 if (!pci_dev_present(amd64nb))
775 return -ENODEV;
776
777 /* Look for any AGP bridge */
778 dev = NULL;
779 err = -ENODEV;
780 for_each_pci_dev(dev) {
781 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
782 continue;
783 /* Only one bridge supported right now */
784 if (agp_amd64_probe(dev, NULL) == 0) {
785 err = 0;
786 break;
787 }
788 }
789 }
790 return err;
791 }
792
793 static void __exit agp_amd64_cleanup(void)
794 {
795 if (aperture_resource)
796 release_resource(aperture_resource);
797 pci_unregister_driver(&agp_amd64_pci_driver);
798 }
799
800 /* On AMD64 the PCI driver needs to initialize this driver early
801 for the IOMMU, so it has to be called via a backdoor. */
802 #ifndef CONFIG_GART_IOMMU
803 module_init(agp_amd64_init);
804 module_exit(agp_amd64_cleanup);
805 #endif
806
807 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
808 module_param(agp_try_unsupported, bool, 0);
809 MODULE_LICENSE("GPL");
Verdex Pro support