include/asm-ia64/sn/rw_mmr.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_RW_MMR_H
   9 #define _ASM_IA64_SN_RW_MMR_H
  10
  11
  12 /*
  13  * This file contains macros used to access MMR registers via
  14  * uncached physical addresses.
  15  *      pio_phys_read_mmr  - read an MMR
  16  *      pio_phys_write_mmr - write an MMR
  17  *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
  18  *              Second MMR will be skipped if address is NULL
  19  *
  20  * Addresses passed to these routines should be uncached physical addresses
  21  * ie., 0x80000....
  22  */
  23
  24
  25 extern inline long
  26 pio_phys_read_mmr(volatile long *mmr)
  27 {
  28         long val;
  29         asm volatile
  30             ("mov r2=psr;;"
  31              "rsm psr.i | psr.dt;;"
  32              "srlz.i;;"
  33              "ld8.acq %0=[%1];;"
  34              "mov psr.l=r2;;"
  35              "srlz.i;;"
  36              : "=r"(val)
  37              : "r"(mmr)
  38              : "r2");
  39         return val;
  40 }
  41
  42
  43
  44 extern inline void
  45 pio_phys_write_mmr(volatile long *mmr, long val)
  46 {
  47         asm volatile
  48             ("mov r2=psr;;"
  49              "rsm psr.i | psr.dt;;"
  50              "srlz.i;;"
  51              "st8.rel [%0]=%1;;"
  52              "mov psr.l=r2;;"
  53              "srlz.i;;"
  54              :: "r"(mmr), "r"(val)
  55              : "r2", "memory");
  56 }
  57
  58 extern inline void
  59 pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2)
  60 {
  61         asm volatile
  62             ("mov r2=psr;;"
  63              "rsm psr.i | psr.dt | psr.ic;;"
  64              "cmp.ne p9,p0=%2,r0;"
  65              "srlz.i;;"
  66              "st8.rel [%0]=%1;"
  67              "(p9) st8.rel [%2]=%3;;"
  68              "mov psr.l=r2;;"
  69              "srlz.i;;"
  70              :: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)
  71              : "p9", "r2", "memory");
  72 }
  73
  74 #endif /* _ASM_IA64_SN_RW_MMR_H */