arch/ppc/syslib/ppc85xx_setup.c

   1 /*
   2  * arch/ppc/syslib/ppc85xx_setup.c
   3  *
   4  * MPC85XX common board code
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>  /* for linux/serial_core.h */
  23 #include <linux/serial_core.h>
  24 #include <linux/serial_8250.h>
  25
  26 #include <asm/time.h>
  27 #include <asm/mpc85xx.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ppc_sys.h>
  31 #include <asm/kgdb.h>
  32
  33 #include <syslib/ppc85xx_setup.h>
  34
  35 extern void abort(void);
  36
  37 /* Return the amount of memory */
  38 unsigned long __init
  39 mpc85xx_find_end_of_memory(void)
  40 {
  41         bd_t *binfo;
  42
  43         binfo = (bd_t *) __res;
  44
  45         return binfo->bi_memsize;
  46 }
  47
  48 /* The decrementer counts at the system (internal) clock freq divided by 8 */
  49 void __init
  50 mpc85xx_calibrate_decr(void)
  51 {
  52         bd_t *binfo = (bd_t *) __res;
  53         unsigned int freq, divisor;
  54
  55         /* get the core frequency */
  56         freq = binfo->bi_busfreq;
  57
  58         /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
  59         divisor = 8;
  60         tb_ticks_per_jiffy = freq / divisor / HZ;
  61         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  62
  63         /* Set the time base to zero */
  64         mtspr(SPRN_TBWL, 0);
  65         mtspr(SPRN_TBWU, 0);
  66
  67         /* Clear any pending timer interrupts */
  68         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  69
  70         /* Enable decrementer interrupt */
  71         mtspr(SPRN_TCR, TCR_DIE);
  72 }
  73
  74 #ifdef CONFIG_SERIAL_8250
  75 void __init
  76 mpc85xx_early_serial_map(void)
  77 {
  78 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  79         struct uart_port serial_req;
  80 #endif
  81         struct plat_serial8250_port *pdata;
  82         bd_t *binfo = (bd_t *) __res;
  83         pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
  84
  85         /* Setup serial port access */
  86         pdata[0].uartclk = binfo->bi_busfreq;
  87         pdata[0].mapbase += binfo->bi_immr_base;
  88         pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
  89
  90 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  91         memset(&serial_req, 0, sizeof (serial_req));
  92         serial_req.iotype = SERIAL_IO_MEM;
  93         serial_req.mapbase = pdata[0].mapbase;
  94         serial_req.membase = pdata[0].membase;
  95         serial_req.regshift = 0;
  96
  97         gen550_init(0, &serial_req);
  98 #endif
  99
 100         pdata[1].uartclk = binfo->bi_busfreq;
 101         pdata[1].mapbase += binfo->bi_immr_base;
 102         pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
 103
 104 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 105         /* Assume gen550_init() doesn't modify serial_req */
 106         serial_req.mapbase = pdata[1].mapbase;
 107         serial_req.membase = pdata[1].membase;
 108
 109         gen550_init(1, &serial_req);
 110 #endif
 111 }
 112 #endif
 113
 114 void
 115 mpc85xx_restart(char *cmd)
 116 {
 117         local_irq_disable();
 118         abort();
 119 }
 120
 121 void
 122 mpc85xx_power_off(void)
 123 {
 124         local_irq_disable();
 125         for(;;);
 126 }
 127
 128 void
 129 mpc85xx_halt(void)
 130 {
 131         local_irq_disable();
 132         for(;;);
 133 }
 134
 135 #ifdef CONFIG_PCI
 136
 137 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 138 extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
 139 extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
 140 #endif
 141
 142 static void __init
 143 mpc85xx_setup_pci1(struct pci_controller *hose)
 144 {
 145         volatile struct ccsr_pci *pci;
 146         volatile struct ccsr_guts *guts;
 147         unsigned short temps;
 148         bd_t *binfo = (bd_t *) __res;
 149
 150         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
 151                     MPC85xx_PCI1_SIZE);
 152
 153         guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
 154                     MPC85xx_GUTS_SIZE);
 155
 156         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 157         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 158         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 159
 160 #define PORDEVSR_PCI    (0x00800000)    /* PCI Mode */
 161         if (guts->pordevsr & PORDEVSR_PCI) {
 162                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 163         } else {
 164                 /* PCI-X init */
 165                 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 166                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 167                 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
 168         }
 169
 170         /* Disable all windows (except powar0 since its ignored) */
 171         pci->powar1 = 0;
 172         pci->powar2 = 0;
 173         pci->powar3 = 0;
 174         pci->powar4 = 0;
 175         pci->piwar1 = 0;
 176         pci->piwar2 = 0;
 177         pci->piwar3 = 0;
 178
 179         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
 180         pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 181         pci->potear1 = 0x00000000;
 182         pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 183         /* Enable, Mem R/W */
 184         pci->powar1 = 0x80044000 |
 185            (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
 186
 187         /* Setup outboud IO windows @ MPC85XX_PCI1_IO_BASE */
 188         pci->potar2 = 0x00000000;
 189         pci->potear2 = 0x00000000;
 190         pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
 191         /* Enable, IO R/W */
 192         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
 193
 194         /* Setup 2G inbound Memory Window @ 0 */
 195         pci->pitar1 = 0x00000000;
 196         pci->piwbar1 = 0x00000000;
 197         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 198                                            Mem, Snoop R/W, 2G */
 199 }
 200
 201
 202 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
 203 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
 204
 205 #ifdef CONFIG_85xx_PCI2
 206 static void __init
 207 mpc85xx_setup_pci2(struct pci_controller *hose)
 208 {
 209         volatile struct ccsr_pci *pci;
 210         unsigned short temps;
 211         bd_t *binfo = (bd_t *) __res;
 212
 213         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
 214                     MPC85xx_PCI2_SIZE);
 215
 216         early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
 217         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 218         early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
 219         early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
 220
 221         /* Disable all windows (except powar0 since its ignored) */
 222         pci->powar1 = 0;
 223         pci->powar2 = 0;
 224         pci->powar3 = 0;
 225         pci->powar4 = 0;
 226         pci->piwar1 = 0;
 227         pci->piwar2 = 0;
 228         pci->piwar3 = 0;
 229
 230         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
 231         pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 232         pci->potear1 = 0x00000000;
 233         pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 234         /* Enable, Mem R/W */
 235         pci->powar1 = 0x80044000 |
 236            (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
 237
 238         /* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
 239         pci->potar2 = 0x00000000;
 240         pci->potear2 = 0x00000000;
 241         pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 242         /* Enable, IO R/W */
 243         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
 244
 245         /* Setup 2G inbound Memory Window @ 0 */
 246         pci->pitar1 = 0x00000000;
 247         pci->piwbar1 = 0x00000000;
 248         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 249                                            Mem, Snoop R/W, 2G */
 250 }
 251 #endif /* CONFIG_85xx_PCI2 */
 252
 253 int mpc85xx_pci1_last_busno = 0;
 254
 255 void __init
 256 mpc85xx_setup_hose(void)
 257 {
 258         struct pci_controller *hose_a;
 259 #ifdef CONFIG_85xx_PCI2
 260         struct pci_controller *hose_b;
 261 #endif
 262         bd_t *binfo = (bd_t *) __res;
 263
 264         hose_a = pcibios_alloc_controller();
 265
 266         if (!hose_a)
 267                 return;
 268
 269         ppc_md.pci_swizzle = common_swizzle;
 270         ppc_md.pci_map_irq = mpc85xx_map_irq;
 271
 272         hose_a->first_busno = 0;
 273         hose_a->bus_offset = 0;
 274         hose_a->last_busno = 0xff;
 275
 276         setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 277                            binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 278         hose_a->set_cfg_type = 1;
 279
 280         mpc85xx_setup_pci1(hose_a);
 281
 282         hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
 283         hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
 284         hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
 285
 286         hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
 287         hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
 288         hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
 289 #ifdef CONFIG_85xx_PCI2
 290         hose_a->io_base_virt =  ioremap(MPC85XX_PCI1_IO_BASE,
 291                                         MPC85XX_PCI1_IO_SIZE +
 292                                         MPC85XX_PCI2_IO_SIZE);
 293 #else
 294         hose_a->io_base_virt =  ioremap(MPC85XX_PCI1_IO_BASE,
 295                                         MPC85XX_PCI1_IO_SIZE);
 296 #endif
 297         isa_io_base = (unsigned long)hose_a->io_base_virt;
 298
 299         /* setup resources */
 300         pci_init_resource(&hose_a->mem_resources[0],
 301                         MPC85XX_PCI1_LOWER_MEM,
 302                         MPC85XX_PCI1_UPPER_MEM,
 303                         IORESOURCE_MEM, "PCI1 host bridge");
 304
 305         pci_init_resource(&hose_a->io_resource,
 306                         MPC85XX_PCI1_LOWER_IO,
 307                         MPC85XX_PCI1_UPPER_IO,
 308                         IORESOURCE_IO, "PCI1 host bridge");
 309
 310         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 311
 312 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 313         /* Pre pciauto_bus_scan VIA init */
 314         mpc85xx_cds_enable_via(hose_a);
 315 #endif
 316
 317         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 318
 319 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 320         /* Post pciauto_bus_scan VIA fixup */
 321         mpc85xx_cds_fixup_via(hose_a);
 322 #endif
 323
 324 #ifdef CONFIG_85xx_PCI2
 325         hose_b = pcibios_alloc_controller();
 326
 327         if (!hose_b)
 328                 return;
 329
 330         hose_b->bus_offset = hose_a->last_busno + 1;
 331         hose_b->first_busno = hose_a->last_busno + 1;
 332         hose_b->last_busno = 0xff;
 333
 334         setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 335                            binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 336         hose_b->set_cfg_type = 1;
 337
 338         mpc85xx_setup_pci2(hose_b);
 339
 340         hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
 341         hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
 342         hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
 343
 344         hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
 345         hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
 346         hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
 347         hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
 348
 349         /* setup resources */
 350         pci_init_resource(&hose_b->mem_resources[0],
 351                         MPC85XX_PCI2_LOWER_MEM,
 352                         MPC85XX_PCI2_UPPER_MEM,
 353                         IORESOURCE_MEM, "PCI2 host bridge");
 354
 355         pci_init_resource(&hose_b->io_resource,
 356                         MPC85XX_PCI2_LOWER_IO,
 357                         MPC85XX_PCI2_UPPER_IO,
 358                         IORESOURCE_IO, "PCI2 host bridge");
 359
 360         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 361
 362         /* let board code know what the last bus number was on PCI1 */
 363         mpc85xx_pci1_last_busno = hose_a->last_busno;
 364 #endif
 365         return;
 366 }
 367 #endif /* CONFIG_PCI */
 368
 369