arch/ia64/sn/pci/pcibr/pcibr_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/pci.h>
  11 #include <asm/sn/addrs.h>
  12 #include <asm/sn/geo.h>
  13 #include <asm/sn/pcibr_provider.h>
  14 #include <asm/sn/pcibus_provider_defs.h>
  15 #include <asm/sn/pcidev.h>
  16 #include <asm/sn/pic.h>
  17 #include <asm/sn/sn_sal.h>
  18 #include <asm/sn/tiocp.h>
  19 #include "tio.h"
  20 #include "xtalk/xwidgetdev.h"
  21 #include "xtalk/hubdev.h"
  22
  23 extern int sn_ioif_inited;
  24
  25 /* =====================================================================
  26  *    DMA MANAGEMENT
  27  *
  28  *      The Bridge ASIC provides three methods of doing DMA: via a "direct map"
  29  *      register available in 32-bit PCI space (which selects a contiguous 2G
  30  *      address space on some other widget), via "direct" addressing via 64-bit
  31  *      PCI space (all destination information comes from the PCI address,
  32  *      including transfer attributes), and via a "mapped" region that allows
  33  *      a bunch of different small mappings to be established with the PMU.
  34  *
  35  *      For efficiency, we most prefer to use the 32bit direct mapping facility,
  36  *      since it requires no resource allocations. The advantage of using the
  37  *      PMU over the 64-bit direct is that single-cycle PCI addressing can be
  38  *      used; the advantage of using 64-bit direct over PMU addressing is that
  39  *      we do not have to allocate entries in the PMU.
  40  */
  41
  42 static dma_addr_t
  43 pcibr_dmamap_ate32(struct pcidev_info *info,
  44                    uint64_t paddr, size_t req_size, uint64_t flags)
  45 {
  46
  47         struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
  48         struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
  49             pdi_pcibus_info;
  50         uint8_t internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
  51                                             pdi_linux_pcidev->devfn)) - 1;
  52         int ate_count;
  53         int ate_index;
  54         uint64_t ate_flags = flags | PCI32_ATE_V;
  55         uint64_t ate;
  56         uint64_t pci_addr;
  57         uint64_t xio_addr;
  58         uint64_t offset;
  59
  60         /* PIC in PCI-X mode does not supports 32bit PageMap mode */
  61         if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
  62                 return 0;
  63         }
  64
  65         /* Calculate the number of ATEs needed. */
  66         if (!(MINIMAL_ATE_FLAG(paddr, req_size))) {
  67                 ate_count = IOPG((IOPGSIZE - 1) /* worst case start offset */
  68                                  +req_size      /* max mapping bytes */
  69                                  - 1) + 1;      /* round UP */
  70         } else {                /* assume requested target is page aligned */
  71                 ate_count = IOPG(req_size       /* max mapping bytes */
  72                                  - 1) + 1;      /* round UP */
  73         }
  74
  75         /* Get the number of ATEs required. */
  76         ate_index = pcibr_ate_alloc(pcibus_info, ate_count);
  77         if (ate_index < 0)
  78                 return 0;
  79
  80         /* In PCI-X mode, Prefetch not supported */
  81         if (IS_PCIX(pcibus_info))
  82                 ate_flags &= ~(PCI32_ATE_PREF);
  83
  84         xio_addr =
  85             IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
  86             PHYS_TO_TIODMA(paddr);
  87         offset = IOPGOFF(xio_addr);
  88         ate = ate_flags | (xio_addr - offset);
  89
  90         /* If PIC, put the targetid in the ATE */
  91         if (IS_PIC_SOFT(pcibus_info)) {
  92                 ate |= (pcibus_info->pbi_hub_xid << PIC_ATE_TARGETID_SHFT);
  93         }
  94         ate_write(pcibus_info, ate_index, ate_count, ate);
  95
  96         /*
  97          * Set up the DMA mapped Address.
  98          */
  99         pci_addr = PCI32_MAPPED_BASE + offset + IOPGSIZE * ate_index;
 100
 101         /*
 102          * If swap was set in device in pcibr_endian_set()
 103          * we need to turn swapping on.
 104          */
 105         if (pcibus_info->pbi_devreg[internal_device] & PCIBR_DEV_SWAP_DIR)
 106                 ATE_SWAP_ON(pci_addr);
 107
 108         return pci_addr;
 109 }
 110
 111 static dma_addr_t
 112 pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
 113                         uint64_t dma_attributes)
 114 {
 115         struct pcibus_info *pcibus_info = (struct pcibus_info *)
 116             ((info->pdi_host_pcidev_info)->pdi_pcibus_info);
 117         uint64_t pci_addr;
 118
 119         /* Translate to Crosstalk View of Physical Address */
 120         pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
 121                     PHYS_TO_TIODMA(paddr)) | dma_attributes;
 122
 123         /* Handle Bus mode */
 124         if (IS_PCIX(pcibus_info))
 125                 pci_addr &= ~PCI64_ATTR_PREF;
 126
 127         /* Handle Bridge Chipset differences */
 128         if (IS_PIC_SOFT(pcibus_info)) {
 129                 pci_addr |=
 130                     ((uint64_t) pcibus_info->
 131                      pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
 132         } else
 133                 pci_addr |= TIOCP_PCI64_CMDTYPE_MEM;
 134
 135         /* If PCI mode, func zero uses VCHAN0, every other func uses VCHAN1 */
 136         if (!IS_PCIX(pcibus_info) && PCI_FUNC(info->pdi_linux_pcidev->devfn))
 137                 pci_addr |= PCI64_ATTR_VIRTUAL;
 138
 139         return pci_addr;
 140
 141 }
 142
 143 static dma_addr_t
 144 pcibr_dmatrans_direct32(struct pcidev_info * info,
 145                         uint64_t paddr, size_t req_size, uint64_t flags)
 146 {
 147
 148         struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
 149         struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
 150             pdi_pcibus_info;
 151         uint64_t xio_addr;
 152
 153         uint64_t xio_base;
 154         uint64_t offset;
 155         uint64_t endoff;
 156
 157         if (IS_PCIX(pcibus_info)) {
 158                 return 0;
 159         }
 160
 161         xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
 162             PHYS_TO_TIODMA(paddr);
 163
 164         xio_base = pcibus_info->pbi_dir_xbase;
 165         offset = xio_addr - xio_base;
 166         endoff = req_size + offset;
 167         if ((req_size > (1ULL << 31)) ||        /* Too Big */
 168             (xio_addr < xio_base) ||    /* Out of range for mappings */
 169             (endoff > (1ULL << 31))) {  /* Too Big */
 170                 return 0;
 171         }
 172
 173         return PCI32_DIRECT_BASE | offset;
 174
 175 }
 176
 177 /*
 178  * Wrapper routine for free'ing DMA maps
 179  * DMA mappings for Direct 64 and 32 do not have any DMA maps.
 180  */
 181 void
 182 pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
 183 {
 184         struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
 185         struct pcibus_info *pcibus_info =
 186             (struct pcibus_info *)pcidev_info->pdi_pcibus_info;
 187
 188         if (IS_PCI32_MAPPED(dma_handle)) {
 189                 int ate_index;
 190
 191                 ate_index =
 192                     IOPG((ATE_SWAP_OFF(dma_handle) - PCI32_MAPPED_BASE));
 193                 pcibr_ate_free(pcibus_info, ate_index);
 194         }
 195 }
 196
 197 /*
 198  * On SN systems there is a race condition between a PIO read response and
 199  * DMA's.  In rare cases, the read response may beat the DMA, causing the
 200  * driver to think that data in memory is complete and meaningful.  This code
 201  * eliminates that race.  This routine is called by the PIO read routines
 202  * after doing the read.  For PIC this routine then forces a fake interrupt
 203  * on another line, which is logically associated with the slot that the PIO
 204  * is addressed to.  It then spins while watching the memory location that
 205  * the interrupt is targetted to.  When the interrupt response arrives, we
 206  * are sure that the DMA has landed in memory and it is safe for the driver
 207  * to proceed.  For TIOCP use the Device(x) Write Request Buffer Flush
 208  * Bridge register since it ensures the data has entered the coherence domain,
 209  * unlike the PIC Device(x) Write Request Buffer Flush register.
 210  */
 211
 212 void sn_dma_flush(uint64_t addr)
 213 {
 214         nasid_t nasid;
 215         int is_tio;
 216         int wid_num;
 217         int i, j;
 218         int bwin;
 219         uint64_t flags;
 220         struct hubdev_info *hubinfo;
 221         volatile struct sn_flush_device_list *p;
 222         struct sn_flush_nasid_entry *flush_nasid_list;
 223
 224         if (!sn_ioif_inited)
 225                 return;
 226
 227         nasid = NASID_GET(addr);
 228         if (-1 == nasid_to_cnodeid(nasid))
 229                 return;
 230
 231         hubinfo = (NODEPDA(nasid_to_cnodeid(nasid)))->pdinfo;
 232
 233         if (!hubinfo) {
 234                 BUG();
 235         }
 236         is_tio = (nasid & 1);
 237         if (is_tio) {
 238                 wid_num = TIO_SWIN_WIDGETNUM(addr);
 239                 bwin = TIO_BWIN_WINDOWNUM(addr);
 240         } else {
 241                 wid_num = SWIN_WIDGETNUM(addr);
 242                 bwin = BWIN_WINDOWNUM(addr);
 243         }
 244
 245         flush_nasid_list = &hubinfo->hdi_flush_nasid_list;
 246         if (flush_nasid_list->widget_p == NULL)
 247                 return;
 248         if (bwin > 0) {
 249                 uint64_t itte = flush_nasid_list->iio_itte[bwin];
 250
 251                 if (is_tio) {
 252                         wid_num = (itte >> TIO_ITTE_WIDGET_SHIFT) &
 253                             TIO_ITTE_WIDGET_MASK;
 254                 } else {
 255                         wid_num = (itte >> IIO_ITTE_WIDGET_SHIFT) &
 256                             IIO_ITTE_WIDGET_MASK;
 257                 }
 258         }
 259         if (flush_nasid_list->widget_p == NULL)
 260                 return;
 261         if (flush_nasid_list->widget_p[wid_num] == NULL)
 262                 return;
 263         p = &flush_nasid_list->widget_p[wid_num][0];
 264
 265         /* find a matching BAR */
 266         for (i = 0; i < DEV_PER_WIDGET; i++) {
 267                 for (j = 0; j < PCI_ROM_RESOURCE; j++) {
 268                         if (p->sfdl_bar_list[j].start == 0)
 269                                 break;
 270                         if (addr >= p->sfdl_bar_list[j].start
 271                             && addr <= p->sfdl_bar_list[j].end)
 272                                 break;
 273                 }
 274                 if (j < PCI_ROM_RESOURCE && p->sfdl_bar_list[j].start != 0)
 275                         break;
 276                 p++;
 277         }
 278
 279         /* if no matching BAR, return without doing anything. */
 280         if (i == DEV_PER_WIDGET)
 281                 return;
 282
 283         /*
 284          * For TIOCP use the Device(x) Write Request Buffer Flush Bridge
 285          * register since it ensures the data has entered the coherence
 286          * domain, unlike PIC
 287          */
 288         if (is_tio) {
 289                 uint32_t tio_id = REMOTE_HUB_L(nasid, TIO_NODE_ID);
 290                 uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id);
 291
 292                 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
 293                 if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
 294                         return;
 295                 } else {
 296                         pcireg_wrb_flush_get(p->sfdl_pcibus_info,
 297                                              (p->sfdl_slot - 1));
 298                 }
 299         } else {
 300                 spin_lock_irqsave(&((struct sn_flush_device_list *)p)->
 301                                   sfdl_flush_lock, flags);
 302
 303                 *p->sfdl_flush_addr = 0;
 304
 305                 /* force an interrupt. */
 306                 *(volatile uint32_t *)(p->sfdl_force_int_addr) = 1;
 307
 308                 /* wait for the interrupt to come back. */
 309                 while (*(p->sfdl_flush_addr) != 0x10f) ;
 310
 311                 /* okay, everything is synched up. */
 312                 spin_unlock_irqrestore((spinlock_t *)&p->sfdl_flush_lock, flags);
 313         }
 314         return;
 315 }
 316
 317 /*
 318  * DMA interfaces.  Called from pci_dma.c routines.
 319  */
 320
 321 dma_addr_t
 322 pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size)
 323 {
 324         dma_addr_t dma_handle;
 325         struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
 326
 327         /* SN cannot support DMA addresses smaller than 32 bits. */
 328         if (hwdev->dma_mask < 0x7fffffff) {
 329                 return 0;
 330         }
 331
 332         if (hwdev->dma_mask == ~0UL) {
 333                 /*
 334                  * Handle the most common case: 64 bit cards.  This
 335                  * call should always succeed.
 336                  */
 337
 338                 dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
 339                                                      PCI64_ATTR_PREF);
 340         } else {
 341                 /* Handle 32-63 bit cards via direct mapping */
 342                 dma_handle = pcibr_dmatrans_direct32(pcidev_info, phys_addr,
 343                                                      size, 0);
 344                 if (!dma_handle) {
 345                         /*
 346                          * It is a 32 bit card and we cannot do direct mapping,
 347                          * so we use an ATE.
 348                          */
 349
 350                         dma_handle = pcibr_dmamap_ate32(pcidev_info, phys_addr,
 351                                                         size, PCI32_ATE_PREF);
 352                 }
 353         }
 354
 355         return dma_handle;
 356 }
 357
 358 dma_addr_t
 359 pcibr_dma_map_consistent(struct pci_dev * hwdev, unsigned long phys_addr,
 360                          size_t size)
 361 {
 362         dma_addr_t dma_handle;
 363         struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
 364
 365         if (hwdev->dev.coherent_dma_mask == ~0UL) {
 366                 dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
 367                                             PCI64_ATTR_BAR);
 368         } else {
 369                 dma_handle = (dma_addr_t) pcibr_dmamap_ate32(pcidev_info,
 370                                                     phys_addr, size,
 371                                                     PCI32_ATE_BAR);
 372         }
 373
 374         return dma_handle;
 375 }
 376
 377 EXPORT_SYMBOL(sn_dma_flush);