include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 #include <asm/machvec.h>
   5 #include <asm/ptrace.h>         /* for pt_regs */
   6
   7 /* NR_IRQS is made from three components:
   8  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
   9  *   2. PINT_NR_IRQS   - number of PINT interrupts
  10  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
  11  */
  12
  13 /* 1. ONCHIP_NR_IRQS */
  14 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
  15 # define ONCHIP_NR_IRQS 24      // Actually 21
  16 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
  17 # define ONCHIP_NR_IRQS 64
  18 # define PINT_NR_IRQS   16
  19 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
  20 # define ONCHIP_NR_IRQS 32
  21 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  22       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  23       defined(CONFIG_CPU_SUBTYPE_SH7705)
  24 # define ONCHIP_NR_IRQS 64      // Actually 61
  25 # define PINT_NR_IRQS   16
  26 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
  27 # define ONCHIP_NR_IRQS 104
  28 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
  29 # define ONCHIP_NR_IRQS 48      // Actually 44
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
  31 # define ONCHIP_NR_IRQS 72
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  33 # define ONCHIP_NR_IRQS 112     /* XXX */
  34 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  35 # define ONCHIP_NR_IRQS 72
  36 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
  37 # define ONCHIP_NR_IRQS 144
  38 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
  39       defined(CONFIG_CPU_SUBTYPE_SH73180) || \
  40       defined(CONFIG_CPU_SUBTYPE_SH7343)
  41 # define ONCHIP_NR_IRQS 109
  42 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  43 # define ONCHIP_NR_IRQS 111
  44 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
  45 # define ONCHIP_NR_IRQS 256
  46 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  47 # define ONCHIP_NR_IRQS 128
  48 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
  49 # define ONCHIP_NR_IRQS 144
  50 #endif
  51
  52 /* 2. PINT_NR_IRQS */
  53 #ifdef CONFIG_SH_UNKNOWN
  54 # define PINT_NR_IRQS 16
  55 #else
  56 # ifndef PINT_NR_IRQS
  57 #  define PINT_NR_IRQS 0
  58 # endif
  59 #endif
  60
  61 #if PINT_NR_IRQS > 0
  62 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
  63 #endif
  64
  65 /* 3. OFFCHIP_NR_IRQS */
  66 #if defined(CONFIG_HD64461)
  67 # define OFFCHIP_NR_IRQS 18
  68 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
  69 # define OFFCHIP_NR_IRQS 48
  70 #elif defined(CONFIG_HD64465)
  71 # define OFFCHIP_NR_IRQS 16
  72 #elif defined (CONFIG_SH_EC3104)
  73 # define OFFCHIP_NR_IRQS 16
  74 #elif defined (CONFIG_SH_DREAMCAST)
  75 # define OFFCHIP_NR_IRQS 96
  76 #elif defined (CONFIG_SH_TITAN)
  77 # define OFFCHIP_NR_IRQS 4
  78 #elif defined(CONFIG_SH_R7780RP)
  79 # define OFFCHIP_NR_IRQS 16
  80 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
  81 # define OFFCHIP_NR_IRQS 12
  82 #elif defined(CONFIG_SH_UNKNOWN)
  83 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
  84 #else
  85 # define OFFCHIP_NR_IRQS 0
  86 #endif
  87
  88 #if OFFCHIP_NR_IRQS > 0
  89 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
  90 #endif
  91
  92 /* NR_IRQS. 1+2+3 */
  93 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
  94
  95 /*
  96  * Convert back and forth between INTEVT and IRQ values.
  97  */
  98 #define evt2irq(evt)            (((evt) >> 5) - 16)
  99 #define irq2evt(irq)            (((irq) + 16) << 5)
 100
 101 /*
 102  * Simple Mask Register Support
 103  */
 104 extern void make_maskreg_irq(unsigned int irq);
 105 extern unsigned short *irq_mask_register;
 106
 107 /*
 108  * PINT IRQs
 109  */
 110 void init_IRQ_pint(void);
 111
 112 /*
 113  * The shift value is now the number of bits to shift, not the number of
 114  * bits/4. This is to make it easier to read the value directly from the
 115  * datasheets. The IPR address, addr, will be set from ipr_idx via the
 116  * map_ipridx_to_addr function.
 117  */
 118 struct ipr_data {
 119         unsigned int irq;
 120         int ipr_idx;            /* Index for the IPR registered */
 121         int shift;              /* Number of bits to shift the data */
 122         int priority;           /* The priority */
 123         unsigned int addr;      /* Address of Interrupt Priority Register */
 124 };
 125
 126 /*
 127  * Given an IPR IDX, map the value to an IPR register address.
 128  */
 129 unsigned int map_ipridx_to_addr(int idx);
 130
 131 /*
 132  * Enable individual interrupt mode for external IPR IRQs.
 133  */
 134 void ipr_irq_enable_irlm(void);
 135
 136 /*
 137  * Function for "on chip support modules".
 138  */
 139 void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
 140 void make_imask_irq(unsigned int irq);
 141 void init_IRQ_ipr(void);
 142
 143 struct intc2_data {
 144         unsigned short irq;
 145         unsigned char ipr_offset, ipr_shift;
 146         unsigned char msk_offset, msk_shift;
 147         unsigned char priority;
 148 };
 149
 150 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
 151 void init_IRQ_intc2(void);
 152
 153 static inline int generic_irq_demux(int irq)
 154 {
 155         return irq;
 156 }
 157
 158 #define irq_canonicalize(irq)   (irq)
 159 #define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
 160
 161 #ifdef CONFIG_4KSTACKS
 162 extern void irq_ctx_init(int cpu);
 163 extern void irq_ctx_exit(int cpu);
 164 # define __ARCH_HAS_DO_SOFTIRQ
 165 #else
 166 # define irq_ctx_init(cpu) do { } while (0)
 167 # define irq_ctx_exit(cpu) do { } while (0)
 168 #endif
 169
 170 #endif /* __ASM_SH_IRQ_H */