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b43: Change schedule for old-fw support removal
[linux-2.6/verdex.git] / drivers / net / wireless / b43 / main.c
blob5ca55dcd0345562401d2b4d266e0f3bdb44b9dd8
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy_common.h"
48 #include "phy_g.h"
49 #include "phy_n.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
91
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
102 SSB_DEVTABLE_END
103 };
104
105 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
106
107 /* Channel and ratetables are shared for all devices.
108 * They can't be const, because ieee80211 puts some precalculated
109 * data in there. This data is the same for all devices, so we don't
110 * get concurrency issues */
111 #define RATETAB_ENT(_rateid, _flags) \
112 { \
113 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
114 .hw_value = (_rateid), \
115 .flags = (_flags), \
116 }
117
118 /*
119 * NOTE: When changing this, sync with xmit.c's
120 * b43_plcp_get_bitrate_idx_* functions!
121 */
122 static struct ieee80211_rate __b43_ratetable[] = {
123 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
124 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
126 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
127 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 };
136
137 #define b43_a_ratetable (__b43_ratetable + 4)
138 #define b43_a_ratetable_size 8
139 #define b43_b_ratetable (__b43_ratetable + 0)
140 #define b43_b_ratetable_size 4
141 #define b43_g_ratetable (__b43_ratetable + 0)
142 #define b43_g_ratetable_size 12
143
144 #define CHAN4G(_channel, _freq, _flags) { \
145 .band = IEEE80211_BAND_2GHZ, \
146 .center_freq = (_freq), \
147 .hw_value = (_channel), \
148 .flags = (_flags), \
149 .max_antenna_gain = 0, \
150 .max_power = 30, \
151 }
152 static struct ieee80211_channel b43_2ghz_chantable[] = {
153 CHAN4G(1, 2412, 0),
154 CHAN4G(2, 2417, 0),
155 CHAN4G(3, 2422, 0),
156 CHAN4G(4, 2427, 0),
157 CHAN4G(5, 2432, 0),
158 CHAN4G(6, 2437, 0),
159 CHAN4G(7, 2442, 0),
160 CHAN4G(8, 2447, 0),
161 CHAN4G(9, 2452, 0),
162 CHAN4G(10, 2457, 0),
163 CHAN4G(11, 2462, 0),
164 CHAN4G(12, 2467, 0),
165 CHAN4G(13, 2472, 0),
166 CHAN4G(14, 2484, 0),
167 };
168 #undef CHAN4G
169
170 #define CHAN5G(_channel, _flags) { \
171 .band = IEEE80211_BAND_5GHZ, \
172 .center_freq = 5000 + (5 * (_channel)), \
173 .hw_value = (_channel), \
174 .flags = (_flags), \
175 .max_antenna_gain = 0, \
176 .max_power = 30, \
177 }
178 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
179 CHAN5G(32, 0), CHAN5G(34, 0),
180 CHAN5G(36, 0), CHAN5G(38, 0),
181 CHAN5G(40, 0), CHAN5G(42, 0),
182 CHAN5G(44, 0), CHAN5G(46, 0),
183 CHAN5G(48, 0), CHAN5G(50, 0),
184 CHAN5G(52, 0), CHAN5G(54, 0),
185 CHAN5G(56, 0), CHAN5G(58, 0),
186 CHAN5G(60, 0), CHAN5G(62, 0),
187 CHAN5G(64, 0), CHAN5G(66, 0),
188 CHAN5G(68, 0), CHAN5G(70, 0),
189 CHAN5G(72, 0), CHAN5G(74, 0),
190 CHAN5G(76, 0), CHAN5G(78, 0),
191 CHAN5G(80, 0), CHAN5G(82, 0),
192 CHAN5G(84, 0), CHAN5G(86, 0),
193 CHAN5G(88, 0), CHAN5G(90, 0),
194 CHAN5G(92, 0), CHAN5G(94, 0),
195 CHAN5G(96, 0), CHAN5G(98, 0),
196 CHAN5G(100, 0), CHAN5G(102, 0),
197 CHAN5G(104, 0), CHAN5G(106, 0),
198 CHAN5G(108, 0), CHAN5G(110, 0),
199 CHAN5G(112, 0), CHAN5G(114, 0),
200 CHAN5G(116, 0), CHAN5G(118, 0),
201 CHAN5G(120, 0), CHAN5G(122, 0),
202 CHAN5G(124, 0), CHAN5G(126, 0),
203 CHAN5G(128, 0), CHAN5G(130, 0),
204 CHAN5G(132, 0), CHAN5G(134, 0),
205 CHAN5G(136, 0), CHAN5G(138, 0),
206 CHAN5G(140, 0), CHAN5G(142, 0),
207 CHAN5G(144, 0), CHAN5G(145, 0),
208 CHAN5G(146, 0), CHAN5G(147, 0),
209 CHAN5G(148, 0), CHAN5G(149, 0),
210 CHAN5G(150, 0), CHAN5G(151, 0),
211 CHAN5G(152, 0), CHAN5G(153, 0),
212 CHAN5G(154, 0), CHAN5G(155, 0),
213 CHAN5G(156, 0), CHAN5G(157, 0),
214 CHAN5G(158, 0), CHAN5G(159, 0),
215 CHAN5G(160, 0), CHAN5G(161, 0),
216 CHAN5G(162, 0), CHAN5G(163, 0),
217 CHAN5G(164, 0), CHAN5G(165, 0),
218 CHAN5G(166, 0), CHAN5G(168, 0),
219 CHAN5G(170, 0), CHAN5G(172, 0),
220 CHAN5G(174, 0), CHAN5G(176, 0),
221 CHAN5G(178, 0), CHAN5G(180, 0),
222 CHAN5G(182, 0), CHAN5G(184, 0),
223 CHAN5G(186, 0), CHAN5G(188, 0),
224 CHAN5G(190, 0), CHAN5G(192, 0),
225 CHAN5G(194, 0), CHAN5G(196, 0),
226 CHAN5G(198, 0), CHAN5G(200, 0),
227 CHAN5G(202, 0), CHAN5G(204, 0),
228 CHAN5G(206, 0), CHAN5G(208, 0),
229 CHAN5G(210, 0), CHAN5G(212, 0),
230 CHAN5G(214, 0), CHAN5G(216, 0),
231 CHAN5G(218, 0), CHAN5G(220, 0),
232 CHAN5G(222, 0), CHAN5G(224, 0),
233 CHAN5G(226, 0), CHAN5G(228, 0),
234 };
235
236 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
237 CHAN5G(34, 0), CHAN5G(36, 0),
238 CHAN5G(38, 0), CHAN5G(40, 0),
239 CHAN5G(42, 0), CHAN5G(44, 0),
240 CHAN5G(46, 0), CHAN5G(48, 0),
241 CHAN5G(52, 0), CHAN5G(56, 0),
242 CHAN5G(60, 0), CHAN5G(64, 0),
243 CHAN5G(100, 0), CHAN5G(104, 0),
244 CHAN5G(108, 0), CHAN5G(112, 0),
245 CHAN5G(116, 0), CHAN5G(120, 0),
246 CHAN5G(124, 0), CHAN5G(128, 0),
247 CHAN5G(132, 0), CHAN5G(136, 0),
248 CHAN5G(140, 0), CHAN5G(149, 0),
249 CHAN5G(153, 0), CHAN5G(157, 0),
250 CHAN5G(161, 0), CHAN5G(165, 0),
251 CHAN5G(184, 0), CHAN5G(188, 0),
252 CHAN5G(192, 0), CHAN5G(196, 0),
253 CHAN5G(200, 0), CHAN5G(204, 0),
254 CHAN5G(208, 0), CHAN5G(212, 0),
255 CHAN5G(216, 0),
256 };
257 #undef CHAN5G
258
259 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
260 .band = IEEE80211_BAND_5GHZ,
261 .channels = b43_5ghz_nphy_chantable,
262 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
263 .bitrates = b43_a_ratetable,
264 .n_bitrates = b43_a_ratetable_size,
265 };
266
267 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
268 .band = IEEE80211_BAND_5GHZ,
269 .channels = b43_5ghz_aphy_chantable,
270 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
271 .bitrates = b43_a_ratetable,
272 .n_bitrates = b43_a_ratetable_size,
273 };
274
275 static struct ieee80211_supported_band b43_band_2GHz = {
276 .band = IEEE80211_BAND_2GHZ,
277 .channels = b43_2ghz_chantable,
278 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
279 .bitrates = b43_g_ratetable,
280 .n_bitrates = b43_g_ratetable_size,
281 };
282
283 static void b43_wireless_core_exit(struct b43_wldev *dev);
284 static int b43_wireless_core_init(struct b43_wldev *dev);
285 static void b43_wireless_core_stop(struct b43_wldev *dev);
286 static int b43_wireless_core_start(struct b43_wldev *dev);
287
288 static int b43_ratelimit(struct b43_wl *wl)
289 {
290 if (!wl || !wl->current_dev)
291 return 1;
292 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
293 return 1;
294 /* We are up and running.
295 * Ratelimit the messages to avoid DoS over the net. */
296 return net_ratelimit();
297 }
298
299 void b43info(struct b43_wl *wl, const char *fmt, ...)
300 {
301 va_list args;
302
303 if (!b43_ratelimit(wl))
304 return;
305 va_start(args, fmt);
306 printk(KERN_INFO "b43-%s: ",
307 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
308 vprintk(fmt, args);
309 va_end(args);
310 }
311
312 void b43err(struct b43_wl *wl, const char *fmt, ...)
313 {
314 va_list args;
315
316 if (!b43_ratelimit(wl))
317 return;
318 va_start(args, fmt);
319 printk(KERN_ERR "b43-%s ERROR: ",
320 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
321 vprintk(fmt, args);
322 va_end(args);
323 }
324
325 void b43warn(struct b43_wl *wl, const char *fmt, ...)
326 {
327 va_list args;
328
329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_WARNING "b43-%s warning: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336 }
337
338 #if B43_DEBUG
339 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
340 {
341 va_list args;
342
343 va_start(args, fmt);
344 printk(KERN_DEBUG "b43-%s debug: ",
345 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
346 vprintk(fmt, args);
347 va_end(args);
348 }
349 #endif /* DEBUG */
350
351 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
352 {
353 u32 macctl;
354
355 B43_WARN_ON(offset % 4 != 0);
356
357 macctl = b43_read32(dev, B43_MMIO_MACCTL);
358 if (macctl & B43_MACCTL_BE)
359 val = swab32(val);
360
361 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
362 mmiowb();
363 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 }
365
366 static inline void b43_shm_control_word(struct b43_wldev *dev,
367 u16 routing, u16 offset)
368 {
369 u32 control;
370
371 /* "offset" is the WORD offset. */
372 control = routing;
373 control <<= 16;
374 control |= offset;
375 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 }
377
378 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
379 {
380 u32 ret;
381
382 if (routing == B43_SHM_SHARED) {
383 B43_WARN_ON(offset & 0x0001);
384 if (offset & 0x0003) {
385 /* Unaligned access */
386 b43_shm_control_word(dev, routing, offset >> 2);
387 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
388 ret <<= 16;
389 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
390 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
391
392 goto out;
393 }
394 offset >>= 2;
395 }
396 b43_shm_control_word(dev, routing, offset);
397 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
398 out:
399 return ret;
400 }
401
402 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
403 {
404 struct b43_wl *wl = dev->wl;
405 unsigned long flags;
406 u32 ret;
407
408 spin_lock_irqsave(&wl->shm_lock, flags);
409 ret = __b43_shm_read32(dev, routing, offset);
410 spin_unlock_irqrestore(&wl->shm_lock, flags);
411
412 return ret;
413 }
414
415 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
416 {
417 u16 ret;
418
419 if (routing == B43_SHM_SHARED) {
420 B43_WARN_ON(offset & 0x0001);
421 if (offset & 0x0003) {
422 /* Unaligned access */
423 b43_shm_control_word(dev, routing, offset >> 2);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
425
426 goto out;
427 }
428 offset >>= 2;
429 }
430 b43_shm_control_word(dev, routing, offset);
431 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
432 out:
433 return ret;
434 }
435
436 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
437 {
438 struct b43_wl *wl = dev->wl;
439 unsigned long flags;
440 u16 ret;
441
442 spin_lock_irqsave(&wl->shm_lock, flags);
443 ret = __b43_shm_read16(dev, routing, offset);
444 spin_unlock_irqrestore(&wl->shm_lock, flags);
445
446 return ret;
447 }
448
449 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
450 {
451 if (routing == B43_SHM_SHARED) {
452 B43_WARN_ON(offset & 0x0001);
453 if (offset & 0x0003) {
454 /* Unaligned access */
455 b43_shm_control_word(dev, routing, offset >> 2);
456 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
457 (value >> 16) & 0xffff);
458 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
459 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
460 return;
461 }
462 offset >>= 2;
463 }
464 b43_shm_control_word(dev, routing, offset);
465 b43_write32(dev, B43_MMIO_SHM_DATA, value);
466 }
467
468 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
469 {
470 struct b43_wl *wl = dev->wl;
471 unsigned long flags;
472
473 spin_lock_irqsave(&wl->shm_lock, flags);
474 __b43_shm_write32(dev, routing, offset, value);
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
476 }
477
478 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
479 {
480 if (routing == B43_SHM_SHARED) {
481 B43_WARN_ON(offset & 0x0001);
482 if (offset & 0x0003) {
483 /* Unaligned access */
484 b43_shm_control_word(dev, routing, offset >> 2);
485 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
486 return;
487 }
488 offset >>= 2;
489 }
490 b43_shm_control_word(dev, routing, offset);
491 b43_write16(dev, B43_MMIO_SHM_DATA, value);
492 }
493
494 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
495 {
496 struct b43_wl *wl = dev->wl;
497 unsigned long flags;
498
499 spin_lock_irqsave(&wl->shm_lock, flags);
500 __b43_shm_write16(dev, routing, offset, value);
501 spin_unlock_irqrestore(&wl->shm_lock, flags);
502 }
503
504 /* Read HostFlags */
505 u64 b43_hf_read(struct b43_wldev * dev)
506 {
507 u64 ret;
508
509 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
510 ret <<= 16;
511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
512 ret <<= 16;
513 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
514
515 return ret;
516 }
517
518 /* Write HostFlags */
519 void b43_hf_write(struct b43_wldev *dev, u64 value)
520 {
521 u16 lo, mi, hi;
522
523 lo = (value & 0x00000000FFFFULL);
524 mi = (value & 0x0000FFFF0000ULL) >> 16;
525 hi = (value & 0xFFFF00000000ULL) >> 32;
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
527 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
528 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
529 }
530
531 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
532 {
533 u32 low, high;
534
535 B43_WARN_ON(dev->dev->id.revision < 3);
536
537 /* The hardware guarantees us an atomic read, if we
538 * read the low register first. */
539 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
540 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
541
542 *tsf = high;
543 *tsf <<= 32;
544 *tsf |= low;
545 }
546
547 static void b43_time_lock(struct b43_wldev *dev)
548 {
549 u32 macctl;
550
551 macctl = b43_read32(dev, B43_MMIO_MACCTL);
552 macctl |= B43_MACCTL_TBTTHOLD;
553 b43_write32(dev, B43_MMIO_MACCTL, macctl);
554 /* Commit the write */
555 b43_read32(dev, B43_MMIO_MACCTL);
556 }
557
558 static void b43_time_unlock(struct b43_wldev *dev)
559 {
560 u32 macctl;
561
562 macctl = b43_read32(dev, B43_MMIO_MACCTL);
563 macctl &= ~B43_MACCTL_TBTTHOLD;
564 b43_write32(dev, B43_MMIO_MACCTL, macctl);
565 /* Commit the write */
566 b43_read32(dev, B43_MMIO_MACCTL);
567 }
568
569 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
570 {
571 u32 low, high;
572
573 B43_WARN_ON(dev->dev->id.revision < 3);
574
575 low = tsf;
576 high = (tsf >> 32);
577 /* The hardware guarantees us an atomic write, if we
578 * write the low register first. */
579 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
580 mmiowb();
581 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
582 mmiowb();
583 }
584
585 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
586 {
587 b43_time_lock(dev);
588 b43_tsf_write_locked(dev, tsf);
589 b43_time_unlock(dev);
590 }
591
592 static
593 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
594 {
595 static const u8 zero_addr[ETH_ALEN] = { 0 };
596 u16 data;
597
598 if (!mac)
599 mac = zero_addr;
600
601 offset |= 0x0020;
602 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
603
604 data = mac[0];
605 data |= mac[1] << 8;
606 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
607 data = mac[2];
608 data |= mac[3] << 8;
609 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
610 data = mac[4];
611 data |= mac[5] << 8;
612 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
613 }
614
615 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
616 {
617 const u8 *mac;
618 const u8 *bssid;
619 u8 mac_bssid[ETH_ALEN * 2];
620 int i;
621 u32 tmp;
622
623 bssid = dev->wl->bssid;
624 mac = dev->wl->mac_addr;
625
626 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
627
628 memcpy(mac_bssid, mac, ETH_ALEN);
629 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
630
631 /* Write our MAC address and BSSID to template ram */
632 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
633 tmp = (u32) (mac_bssid[i + 0]);
634 tmp |= (u32) (mac_bssid[i + 1]) << 8;
635 tmp |= (u32) (mac_bssid[i + 2]) << 16;
636 tmp |= (u32) (mac_bssid[i + 3]) << 24;
637 b43_ram_write(dev, 0x20 + i, tmp);
638 }
639 }
640
641 static void b43_upload_card_macaddress(struct b43_wldev *dev)
642 {
643 b43_write_mac_bssid_templates(dev);
644 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
645 }
646
647 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
648 {
649 /* slot_time is in usec. */
650 if (dev->phy.type != B43_PHYTYPE_G)
651 return;
652 b43_write16(dev, 0x684, 510 + slot_time);
653 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
654 }
655
656 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
657 {
658 b43_set_slot_time(dev, 9);
659 }
660
661 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
662 {
663 b43_set_slot_time(dev, 20);
664 }
665
666 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
667 * Returns the _previously_ enabled IRQ mask.
668 */
669 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
670 {
671 u32 old_mask;
672
673 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
674 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
675
676 return old_mask;
677 }
678
679 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
680 * Returns the _previously_ enabled IRQ mask.
681 */
682 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
683 {
684 u32 old_mask;
685
686 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
687 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
688
689 return old_mask;
690 }
691
692 /* Synchronize IRQ top- and bottom-half.
693 * IRQs must be masked before calling this.
694 * This must not be called with the irq_lock held.
695 */
696 static void b43_synchronize_irq(struct b43_wldev *dev)
697 {
698 synchronize_irq(dev->dev->irq);
699 tasklet_kill(&dev->isr_tasklet);
700 }
701
702 /* DummyTransmission function, as documented on
703 * http://bcm-specs.sipsolutions.net/DummyTransmission
704 */
705 void b43_dummy_transmission(struct b43_wldev *dev)
706 {
707 struct b43_wl *wl = dev->wl;
708 struct b43_phy *phy = &dev->phy;
709 unsigned int i, max_loop;
710 u16 value;
711 u32 buffer[5] = {
712 0x00000000,
713 0x00D40000,
714 0x00000000,
715 0x01000000,
716 0x00000000,
717 };
718
719 switch (phy->type) {
720 case B43_PHYTYPE_A:
721 max_loop = 0x1E;
722 buffer[0] = 0x000201CC;
723 break;
724 case B43_PHYTYPE_B:
725 case B43_PHYTYPE_G:
726 max_loop = 0xFA;
727 buffer[0] = 0x000B846E;
728 break;
729 default:
730 B43_WARN_ON(1);
731 return;
732 }
733
734 spin_lock_irq(&wl->irq_lock);
735 write_lock(&wl->tx_lock);
736
737 for (i = 0; i < 5; i++)
738 b43_ram_write(dev, i * 4, buffer[i]);
739
740 /* Commit writes */
741 b43_read32(dev, B43_MMIO_MACCTL);
742
743 b43_write16(dev, 0x0568, 0x0000);
744 b43_write16(dev, 0x07C0, 0x0000);
745 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
746 b43_write16(dev, 0x050C, value);
747 b43_write16(dev, 0x0508, 0x0000);
748 b43_write16(dev, 0x050A, 0x0000);
749 b43_write16(dev, 0x054C, 0x0000);
750 b43_write16(dev, 0x056A, 0x0014);
751 b43_write16(dev, 0x0568, 0x0826);
752 b43_write16(dev, 0x0500, 0x0000);
753 b43_write16(dev, 0x0502, 0x0030);
754
755 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
756 b43_radio_write16(dev, 0x0051, 0x0017);
757 for (i = 0x00; i < max_loop; i++) {
758 value = b43_read16(dev, 0x050E);
759 if (value & 0x0080)
760 break;
761 udelay(10);
762 }
763 for (i = 0x00; i < 0x0A; i++) {
764 value = b43_read16(dev, 0x050E);
765 if (value & 0x0400)
766 break;
767 udelay(10);
768 }
769 for (i = 0x00; i < 0x19; i++) {
770 value = b43_read16(dev, 0x0690);
771 if (!(value & 0x0100))
772 break;
773 udelay(10);
774 }
775 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
776 b43_radio_write16(dev, 0x0051, 0x0037);
777
778 write_unlock(&wl->tx_lock);
779 spin_unlock_irq(&wl->irq_lock);
780 }
781
782 static void key_write(struct b43_wldev *dev,
783 u8 index, u8 algorithm, const u8 * key)
784 {
785 unsigned int i;
786 u32 offset;
787 u16 value;
788 u16 kidx;
789
790 /* Key index/algo block */
791 kidx = b43_kidx_to_fw(dev, index);
792 value = ((kidx << 4) | algorithm);
793 b43_shm_write16(dev, B43_SHM_SHARED,
794 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
795
796 /* Write the key to the Key Table Pointer offset */
797 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
798 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
799 value = key[i];
800 value |= (u16) (key[i + 1]) << 8;
801 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
802 }
803 }
804
805 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
806 {
807 u32 addrtmp[2] = { 0, 0, };
808 u8 per_sta_keys_start = 8;
809
810 if (b43_new_kidx_api(dev))
811 per_sta_keys_start = 4;
812
813 B43_WARN_ON(index < per_sta_keys_start);
814 /* We have two default TX keys and possibly two default RX keys.
815 * Physical mac 0 is mapped to physical key 4 or 8, depending
816 * on the firmware version.
817 * So we must adjust the index here.
818 */
819 index -= per_sta_keys_start;
820
821 if (addr) {
822 addrtmp[0] = addr[0];
823 addrtmp[0] |= ((u32) (addr[1]) << 8);
824 addrtmp[0] |= ((u32) (addr[2]) << 16);
825 addrtmp[0] |= ((u32) (addr[3]) << 24);
826 addrtmp[1] = addr[4];
827 addrtmp[1] |= ((u32) (addr[5]) << 8);
828 }
829
830 if (dev->dev->id.revision >= 5) {
831 /* Receive match transmitter address mechanism */
832 b43_shm_write32(dev, B43_SHM_RCMTA,
833 (index * 2) + 0, addrtmp[0]);
834 b43_shm_write16(dev, B43_SHM_RCMTA,
835 (index * 2) + 1, addrtmp[1]);
836 } else {
837 /* RXE (Receive Engine) and
838 * PSM (Programmable State Machine) mechanism
839 */
840 if (index < 8) {
841 /* TODO write to RCM 16, 19, 22 and 25 */
842 } else {
843 b43_shm_write32(dev, B43_SHM_SHARED,
844 B43_SHM_SH_PSM + (index * 6) + 0,
845 addrtmp[0]);
846 b43_shm_write16(dev, B43_SHM_SHARED,
847 B43_SHM_SH_PSM + (index * 6) + 4,
848 addrtmp[1]);
849 }
850 }
851 }
852
853 static void do_key_write(struct b43_wldev *dev,
854 u8 index, u8 algorithm,
855 const u8 * key, size_t key_len, const u8 * mac_addr)
856 {
857 u8 buf[B43_SEC_KEYSIZE] = { 0, };
858 u8 per_sta_keys_start = 8;
859
860 if (b43_new_kidx_api(dev))
861 per_sta_keys_start = 4;
862
863 B43_WARN_ON(index >= dev->max_nr_keys);
864 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
865
866 if (index >= per_sta_keys_start)
867 keymac_write(dev, index, NULL); /* First zero out mac. */
868 if (key)
869 memcpy(buf, key, key_len);
870 key_write(dev, index, algorithm, buf);
871 if (index >= per_sta_keys_start)
872 keymac_write(dev, index, mac_addr);
873
874 dev->key[index].algorithm = algorithm;
875 }
876
877 static int b43_key_write(struct b43_wldev *dev,
878 int index, u8 algorithm,
879 const u8 * key, size_t key_len,
880 const u8 * mac_addr,
881 struct ieee80211_key_conf *keyconf)
882 {
883 int i;
884 int sta_keys_start;
885
886 if (key_len > B43_SEC_KEYSIZE)
887 return -EINVAL;
888 for (i = 0; i < dev->max_nr_keys; i++) {
889 /* Check that we don't already have this key. */
890 B43_WARN_ON(dev->key[i].keyconf == keyconf);
891 }
892 if (index < 0) {
893 /* Pairwise key. Get an empty slot for the key. */
894 if (b43_new_kidx_api(dev))
895 sta_keys_start = 4;
896 else
897 sta_keys_start = 8;
898 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
899 if (!dev->key[i].keyconf) {
900 /* found empty */
901 index = i;
902 break;
903 }
904 }
905 if (index < 0) {
906 b43warn(dev->wl, "Out of hardware key memory\n");
907 return -ENOSPC;
908 }
909 } else
910 B43_WARN_ON(index > 3);
911
912 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
913 if ((index <= 3) && !b43_new_kidx_api(dev)) {
914 /* Default RX key */
915 B43_WARN_ON(mac_addr);
916 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
917 }
918 keyconf->hw_key_idx = index;
919 dev->key[index].keyconf = keyconf;
920
921 return 0;
922 }
923
924 static int b43_key_clear(struct b43_wldev *dev, int index)
925 {
926 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
927 return -EINVAL;
928 do_key_write(dev, index, B43_SEC_ALGO_NONE,
929 NULL, B43_SEC_KEYSIZE, NULL);
930 if ((index <= 3) && !b43_new_kidx_api(dev)) {
931 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
932 NULL, B43_SEC_KEYSIZE, NULL);
933 }
934 dev->key[index].keyconf = NULL;
935
936 return 0;
937 }
938
939 static void b43_clear_keys(struct b43_wldev *dev)
940 {
941 int i;
942
943 for (i = 0; i < dev->max_nr_keys; i++)
944 b43_key_clear(dev, i);
945 }
946
947 static void b43_dump_keymemory(struct b43_wldev *dev)
948 {
949 unsigned int i, index, offset;
950 DECLARE_MAC_BUF(macbuf);
951 u8 mac[ETH_ALEN];
952 u16 algo;
953 u32 rcmta0;
954 u16 rcmta1;
955 u64 hf;
956 struct b43_key *key;
957
958 if (!b43_debug(dev, B43_DBG_KEYS))
959 return;
960
961 hf = b43_hf_read(dev);
962 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
963 !!(hf & B43_HF_USEDEFKEYS));
964 for (index = 0; index < dev->max_nr_keys; index++) {
965 key = &(dev->key[index]);
966 printk(KERN_DEBUG "Key slot %02u: %s",
967 index, (key->keyconf == NULL) ? " " : "*");
968 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
969 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
970 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
971 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
972 }
973
974 algo = b43_shm_read16(dev, B43_SHM_SHARED,
975 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
976 printk(" Algo: %04X/%02X", algo, key->algorithm);
977
978 if (index >= 4) {
979 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
980 ((index - 4) * 2) + 0);
981 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
982 ((index - 4) * 2) + 1);
983 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
984 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
985 printk(" MAC: %s",
986 print_mac(macbuf, mac));
987 } else
988 printk(" DEFAULT KEY");
989 printk("\n");
990 }
991 }
992
993 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
994 {
995 u32 macctl;
996 u16 ucstat;
997 bool hwps;
998 bool awake;
999 int i;
1000
1001 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1002 (ps_flags & B43_PS_DISABLED));
1003 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1004
1005 if (ps_flags & B43_PS_ENABLED) {
1006 hwps = 1;
1007 } else if (ps_flags & B43_PS_DISABLED) {
1008 hwps = 0;
1009 } else {
1010 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1011 // and thus is not an AP and we are associated, set bit 25
1012 }
1013 if (ps_flags & B43_PS_AWAKE) {
1014 awake = 1;
1015 } else if (ps_flags & B43_PS_ASLEEP) {
1016 awake = 0;
1017 } else {
1018 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1019 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1020 // successful, set bit26
1021 }
1022
1023 /* FIXME: For now we force awake-on and hwps-off */
1024 hwps = 0;
1025 awake = 1;
1026
1027 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1028 if (hwps)
1029 macctl |= B43_MACCTL_HWPS;
1030 else
1031 macctl &= ~B43_MACCTL_HWPS;
1032 if (awake)
1033 macctl |= B43_MACCTL_AWAKE;
1034 else
1035 macctl &= ~B43_MACCTL_AWAKE;
1036 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1037 /* Commit write */
1038 b43_read32(dev, B43_MMIO_MACCTL);
1039 if (awake && dev->dev->id.revision >= 5) {
1040 /* Wait for the microcode to wake up. */
1041 for (i = 0; i < 100; i++) {
1042 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1043 B43_SHM_SH_UCODESTAT);
1044 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1045 break;
1046 udelay(10);
1047 }
1048 }
1049 }
1050
1051 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1052 {
1053 u32 tmslow;
1054 u32 macctl;
1055
1056 flags |= B43_TMSLOW_PHYCLKEN;
1057 flags |= B43_TMSLOW_PHYRESET;
1058 ssb_device_enable(dev->dev, flags);
1059 msleep(2); /* Wait for the PLL to turn on. */
1060
1061 /* Now take the PHY out of Reset again */
1062 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1063 tmslow |= SSB_TMSLOW_FGC;
1064 tmslow &= ~B43_TMSLOW_PHYRESET;
1065 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1066 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1067 msleep(1);
1068 tmslow &= ~SSB_TMSLOW_FGC;
1069 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1070 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1071 msleep(1);
1072
1073 /* Turn Analog ON, but only if we already know the PHY-type.
1074 * This protects against very early setup where we don't know the
1075 * PHY-type, yet. wireless_core_reset will be called once again later,
1076 * when we know the PHY-type. */
1077 if (dev->phy.ops)
1078 dev->phy.ops->switch_analog(dev, 1);
1079
1080 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1081 macctl &= ~B43_MACCTL_GMODE;
1082 if (flags & B43_TMSLOW_GMODE)
1083 macctl |= B43_MACCTL_GMODE;
1084 macctl |= B43_MACCTL_IHR_ENABLED;
1085 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1086 }
1087
1088 static void handle_irq_transmit_status(struct b43_wldev *dev)
1089 {
1090 u32 v0, v1;
1091 u16 tmp;
1092 struct b43_txstatus stat;
1093
1094 while (1) {
1095 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1096 if (!(v0 & 0x00000001))
1097 break;
1098 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1099
1100 stat.cookie = (v0 >> 16);
1101 stat.seq = (v1 & 0x0000FFFF);
1102 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1103 tmp = (v0 & 0x0000FFFF);
1104 stat.frame_count = ((tmp & 0xF000) >> 12);
1105 stat.rts_count = ((tmp & 0x0F00) >> 8);
1106 stat.supp_reason = ((tmp & 0x001C) >> 2);
1107 stat.pm_indicated = !!(tmp & 0x0080);
1108 stat.intermediate = !!(tmp & 0x0040);
1109 stat.for_ampdu = !!(tmp & 0x0020);
1110 stat.acked = !!(tmp & 0x0002);
1111
1112 b43_handle_txstatus(dev, &stat);
1113 }
1114 }
1115
1116 static void drain_txstatus_queue(struct b43_wldev *dev)
1117 {
1118 u32 dummy;
1119
1120 if (dev->dev->id.revision < 5)
1121 return;
1122 /* Read all entries from the microcode TXstatus FIFO
1123 * and throw them away.
1124 */
1125 while (1) {
1126 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1127 if (!(dummy & 0x00000001))
1128 break;
1129 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1130 }
1131 }
1132
1133 static u32 b43_jssi_read(struct b43_wldev *dev)
1134 {
1135 u32 val = 0;
1136
1137 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1138 val <<= 16;
1139 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1140
1141 return val;
1142 }
1143
1144 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1145 {
1146 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1147 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1148 }
1149
1150 static void b43_generate_noise_sample(struct b43_wldev *dev)
1151 {
1152 b43_jssi_write(dev, 0x7F7F7F7F);
1153 b43_write32(dev, B43_MMIO_MACCMD,
1154 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1155 }
1156
1157 static void b43_calculate_link_quality(struct b43_wldev *dev)
1158 {
1159 /* Top half of Link Quality calculation. */
1160
1161 if (dev->phy.type != B43_PHYTYPE_G)
1162 return;
1163 if (dev->noisecalc.calculation_running)
1164 return;
1165 dev->noisecalc.calculation_running = 1;
1166 dev->noisecalc.nr_samples = 0;
1167
1168 b43_generate_noise_sample(dev);
1169 }
1170
1171 static void handle_irq_noise(struct b43_wldev *dev)
1172 {
1173 struct b43_phy_g *phy = dev->phy.g;
1174 u16 tmp;
1175 u8 noise[4];
1176 u8 i, j;
1177 s32 average;
1178
1179 /* Bottom half of Link Quality calculation. */
1180
1181 if (dev->phy.type != B43_PHYTYPE_G)
1182 return;
1183
1184 /* Possible race condition: It might be possible that the user
1185 * changed to a different channel in the meantime since we
1186 * started the calculation. We ignore that fact, since it's
1187 * not really that much of a problem. The background noise is
1188 * an estimation only anyway. Slightly wrong results will get damped
1189 * by the averaging of the 8 sample rounds. Additionally the
1190 * value is shortlived. So it will be replaced by the next noise
1191 * calculation round soon. */
1192
1193 B43_WARN_ON(!dev->noisecalc.calculation_running);
1194 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1195 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1196 noise[2] == 0x7F || noise[3] == 0x7F)
1197 goto generate_new;
1198
1199 /* Get the noise samples. */
1200 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1201 i = dev->noisecalc.nr_samples;
1202 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1203 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1204 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1205 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1206 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1207 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1208 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1209 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1210 dev->noisecalc.nr_samples++;
1211 if (dev->noisecalc.nr_samples == 8) {
1212 /* Calculate the Link Quality by the noise samples. */
1213 average = 0;
1214 for (i = 0; i < 8; i++) {
1215 for (j = 0; j < 4; j++)
1216 average += dev->noisecalc.samples[i][j];
1217 }
1218 average /= (8 * 4);
1219 average *= 125;
1220 average += 64;
1221 average /= 128;
1222 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1223 tmp = (tmp / 128) & 0x1F;
1224 if (tmp >= 8)
1225 average += 2;
1226 else
1227 average -= 25;
1228 if (tmp == 8)
1229 average -= 72;
1230 else
1231 average -= 48;
1232
1233 dev->stats.link_noise = average;
1234 dev->noisecalc.calculation_running = 0;
1235 return;
1236 }
1237 generate_new:
1238 b43_generate_noise_sample(dev);
1239 }
1240
1241 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1242 {
1243 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1244 ///TODO: PS TBTT
1245 } else {
1246 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1247 b43_power_saving_ctl_bits(dev, 0);
1248 }
1249 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1250 dev->dfq_valid = 1;
1251 }
1252
1253 static void handle_irq_atim_end(struct b43_wldev *dev)
1254 {
1255 if (dev->dfq_valid) {
1256 b43_write32(dev, B43_MMIO_MACCMD,
1257 b43_read32(dev, B43_MMIO_MACCMD)
1258 | B43_MACCMD_DFQ_VALID);
1259 dev->dfq_valid = 0;
1260 }
1261 }
1262
1263 static void handle_irq_pmq(struct b43_wldev *dev)
1264 {
1265 u32 tmp;
1266
1267 //TODO: AP mode.
1268
1269 while (1) {
1270 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1271 if (!(tmp & 0x00000008))
1272 break;
1273 }
1274 /* 16bit write is odd, but correct. */
1275 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1276 }
1277
1278 static void b43_write_template_common(struct b43_wldev *dev,
1279 const u8 * data, u16 size,
1280 u16 ram_offset,
1281 u16 shm_size_offset, u8 rate)
1282 {
1283 u32 i, tmp;
1284 struct b43_plcp_hdr4 plcp;
1285
1286 plcp.data = 0;
1287 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1288 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1289 ram_offset += sizeof(u32);
1290 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1291 * So leave the first two bytes of the next write blank.
1292 */
1293 tmp = (u32) (data[0]) << 16;
1294 tmp |= (u32) (data[1]) << 24;
1295 b43_ram_write(dev, ram_offset, tmp);
1296 ram_offset += sizeof(u32);
1297 for (i = 2; i < size; i += sizeof(u32)) {
1298 tmp = (u32) (data[i + 0]);
1299 if (i + 1 < size)
1300 tmp |= (u32) (data[i + 1]) << 8;
1301 if (i + 2 < size)
1302 tmp |= (u32) (data[i + 2]) << 16;
1303 if (i + 3 < size)
1304 tmp |= (u32) (data[i + 3]) << 24;
1305 b43_ram_write(dev, ram_offset + i - 2, tmp);
1306 }
1307 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1308 size + sizeof(struct b43_plcp_hdr6));
1309 }
1310
1311 /* Check if the use of the antenna that ieee80211 told us to
1312 * use is possible. This will fall back to DEFAULT.
1313 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1314 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1315 u8 antenna_nr)
1316 {
1317 u8 antenna_mask;
1318
1319 if (antenna_nr == 0) {
1320 /* Zero means "use default antenna". That's always OK. */
1321 return 0;
1322 }
1323
1324 /* Get the mask of available antennas. */
1325 if (dev->phy.gmode)
1326 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1327 else
1328 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1329
1330 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1331 /* This antenna is not available. Fall back to default. */
1332 return 0;
1333 }
1334
1335 return antenna_nr;
1336 }
1337
1338 /* Convert a b43 antenna number value to the PHY TX control value. */
1339 static u16 b43_antenna_to_phyctl(int antenna)
1340 {
1341 switch (antenna) {
1342 case B43_ANTENNA0:
1343 return B43_TXH_PHY_ANT0;
1344 case B43_ANTENNA1:
1345 return B43_TXH_PHY_ANT1;
1346 case B43_ANTENNA2:
1347 return B43_TXH_PHY_ANT2;
1348 case B43_ANTENNA3:
1349 return B43_TXH_PHY_ANT3;
1350 case B43_ANTENNA_AUTO:
1351 return B43_TXH_PHY_ANT01AUTO;
1352 }
1353 B43_WARN_ON(1);
1354 return 0;
1355 }
1356
1357 static void b43_write_beacon_template(struct b43_wldev *dev,
1358 u16 ram_offset,
1359 u16 shm_size_offset)
1360 {
1361 unsigned int i, len, variable_len;
1362 const struct ieee80211_mgmt *bcn;
1363 const u8 *ie;
1364 bool tim_found = 0;
1365 unsigned int rate;
1366 u16 ctl;
1367 int antenna;
1368 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1369
1370 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1371 len = min((size_t) dev->wl->current_beacon->len,
1372 0x200 - sizeof(struct b43_plcp_hdr6));
1373 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1374
1375 b43_write_template_common(dev, (const u8 *)bcn,
1376 len, ram_offset, shm_size_offset, rate);
1377
1378 /* Write the PHY TX control parameters. */
1379 antenna = B43_ANTENNA_DEFAULT;
1380 antenna = b43_antenna_to_phyctl(antenna);
1381 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1382 /* We can't send beacons with short preamble. Would get PHY errors. */
1383 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1384 ctl &= ~B43_TXH_PHY_ANT;
1385 ctl &= ~B43_TXH_PHY_ENC;
1386 ctl |= antenna;
1387 if (b43_is_cck_rate(rate))
1388 ctl |= B43_TXH_PHY_ENC_CCK;
1389 else
1390 ctl |= B43_TXH_PHY_ENC_OFDM;
1391 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1392
1393 /* Find the position of the TIM and the DTIM_period value
1394 * and write them to SHM. */
1395 ie = bcn->u.beacon.variable;
1396 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1397 for (i = 0; i < variable_len - 2; ) {
1398 uint8_t ie_id, ie_len;
1399
1400 ie_id = ie[i];
1401 ie_len = ie[i + 1];
1402 if (ie_id == 5) {
1403 u16 tim_position;
1404 u16 dtim_period;
1405 /* This is the TIM Information Element */
1406
1407 /* Check whether the ie_len is in the beacon data range. */
1408 if (variable_len < ie_len + 2 + i)
1409 break;
1410 /* A valid TIM is at least 4 bytes long. */
1411 if (ie_len < 4)
1412 break;
1413 tim_found = 1;
1414
1415 tim_position = sizeof(struct b43_plcp_hdr6);
1416 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1417 tim_position += i;
1418
1419 dtim_period = ie[i + 3];
1420
1421 b43_shm_write16(dev, B43_SHM_SHARED,
1422 B43_SHM_SH_TIMBPOS, tim_position);
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1424 B43_SHM_SH_DTIMPER, dtim_period);
1425 break;
1426 }
1427 i += ie_len + 2;
1428 }
1429 if (!tim_found) {
1430 /*
1431 * If ucode wants to modify TIM do it behind the beacon, this
1432 * will happen, for example, when doing mesh networking.
1433 */
1434 b43_shm_write16(dev, B43_SHM_SHARED,
1435 B43_SHM_SH_TIMBPOS,
1436 len + sizeof(struct b43_plcp_hdr6));
1437 b43_shm_write16(dev, B43_SHM_SHARED,
1438 B43_SHM_SH_DTIMPER, 0);
1439 }
1440 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1441 }
1442
1443 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1444 u16 shm_offset, u16 size,
1445 struct ieee80211_rate *rate)
1446 {
1447 struct b43_plcp_hdr4 plcp;
1448 u32 tmp;
1449 __le16 dur;
1450
1451 plcp.data = 0;
1452 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1453 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1454 dev->wl->vif, size,
1455 rate);
1456 /* Write PLCP in two parts and timing for packet transfer */
1457 tmp = le32_to_cpu(plcp.data);
1458 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1459 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1461 }
1462
1463 /* Instead of using custom probe response template, this function
1464 * just patches custom beacon template by:
1465 * 1) Changing packet type
1466 * 2) Patching duration field
1467 * 3) Stripping TIM
1468 */
1469 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1470 u16 *dest_size,
1471 struct ieee80211_rate *rate)
1472 {
1473 const u8 *src_data;
1474 u8 *dest_data;
1475 u16 src_size, elem_size, src_pos, dest_pos;
1476 __le16 dur;
1477 struct ieee80211_hdr *hdr;
1478 size_t ie_start;
1479
1480 src_size = dev->wl->current_beacon->len;
1481 src_data = (const u8 *)dev->wl->current_beacon->data;
1482
1483 /* Get the start offset of the variable IEs in the packet. */
1484 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1485 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1486
1487 if (B43_WARN_ON(src_size < ie_start))
1488 return NULL;
1489
1490 dest_data = kmalloc(src_size, GFP_ATOMIC);
1491 if (unlikely(!dest_data))
1492 return NULL;
1493
1494 /* Copy the static data and all Information Elements, except the TIM. */
1495 memcpy(dest_data, src_data, ie_start);
1496 src_pos = ie_start;
1497 dest_pos = ie_start;
1498 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1499 elem_size = src_data[src_pos + 1] + 2;
1500 if (src_data[src_pos] == 5) {
1501 /* This is the TIM. */
1502 continue;
1503 }
1504 memcpy(dest_data + dest_pos, src_data + src_pos,
1505 elem_size);
1506 dest_pos += elem_size;
1507 }
1508 *dest_size = dest_pos;
1509 hdr = (struct ieee80211_hdr *)dest_data;
1510
1511 /* Set the frame control. */
1512 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1513 IEEE80211_STYPE_PROBE_RESP);
1514 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1515 dev->wl->vif, *dest_size,
1516 rate);
1517 hdr->duration_id = dur;
1518
1519 return dest_data;
1520 }
1521
1522 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1523 u16 ram_offset,
1524 u16 shm_size_offset,
1525 struct ieee80211_rate *rate)
1526 {
1527 const u8 *probe_resp_data;
1528 u16 size;
1529
1530 size = dev->wl->current_beacon->len;
1531 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1532 if (unlikely(!probe_resp_data))
1533 return;
1534
1535 /* Looks like PLCP headers plus packet timings are stored for
1536 * all possible basic rates
1537 */
1538 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1539 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1540 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1541 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1542
1543 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1544 b43_write_template_common(dev, probe_resp_data,
1545 size, ram_offset, shm_size_offset,
1546 rate->hw_value);
1547 kfree(probe_resp_data);
1548 }
1549
1550 static void b43_upload_beacon0(struct b43_wldev *dev)
1551 {
1552 struct b43_wl *wl = dev->wl;
1553
1554 if (wl->beacon0_uploaded)
1555 return;
1556 b43_write_beacon_template(dev, 0x68, 0x18);
1557 /* FIXME: Probe resp upload doesn't really belong here,
1558 * but we don't use that feature anyway. */
1559 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1560 &__b43_ratetable[3]);
1561 wl->beacon0_uploaded = 1;
1562 }
1563
1564 static void b43_upload_beacon1(struct b43_wldev *dev)
1565 {
1566 struct b43_wl *wl = dev->wl;
1567
1568 if (wl->beacon1_uploaded)
1569 return;
1570 b43_write_beacon_template(dev, 0x468, 0x1A);
1571 wl->beacon1_uploaded = 1;
1572 }
1573
1574 static void handle_irq_beacon(struct b43_wldev *dev)
1575 {
1576 struct b43_wl *wl = dev->wl;
1577 u32 cmd, beacon0_valid, beacon1_valid;
1578
1579 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1580 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1581 return;
1582
1583 /* This is the bottom half of the asynchronous beacon update. */
1584
1585 /* Ignore interrupt in the future. */
1586 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1587
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1590 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1591
1592 /* Schedule interrupt manually, if busy. */
1593 if (beacon0_valid && beacon1_valid) {
1594 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1595 dev->irq_savedstate |= B43_IRQ_BEACON;
1596 return;
1597 }
1598
1599 if (unlikely(wl->beacon_templates_virgin)) {
1600 /* We never uploaded a beacon before.
1601 * Upload both templates now, but only mark one valid. */
1602 wl->beacon_templates_virgin = 0;
1603 b43_upload_beacon0(dev);
1604 b43_upload_beacon1(dev);
1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON0_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1608 } else {
1609 if (!beacon0_valid) {
1610 b43_upload_beacon0(dev);
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 cmd |= B43_MACCMD_BEACON0_VALID;
1613 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1614 } else if (!beacon1_valid) {
1615 b43_upload_beacon1(dev);
1616 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1617 cmd |= B43_MACCMD_BEACON1_VALID;
1618 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1619 }
1620 }
1621 }
1622
1623 static void b43_beacon_update_trigger_work(struct work_struct *work)
1624 {
1625 struct b43_wl *wl = container_of(work, struct b43_wl,
1626 beacon_update_trigger);
1627 struct b43_wldev *dev;
1628
1629 mutex_lock(&wl->mutex);
1630 dev = wl->current_dev;
1631 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1632 spin_lock_irq(&wl->irq_lock);
1633 /* update beacon right away or defer to irq */
1634 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1635 handle_irq_beacon(dev);
1636 /* The handler might have updated the IRQ mask. */
1637 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1638 dev->irq_savedstate);
1639 mmiowb();
1640 spin_unlock_irq(&wl->irq_lock);
1641 }
1642 mutex_unlock(&wl->mutex);
1643 }
1644
1645 /* Asynchronously update the packet templates in template RAM.
1646 * Locking: Requires wl->irq_lock to be locked. */
1647 static void b43_update_templates(struct b43_wl *wl)
1648 {
1649 struct sk_buff *beacon;
1650
1651 /* This is the top half of the ansynchronous beacon update.
1652 * The bottom half is the beacon IRQ.
1653 * Beacon update must be asynchronous to avoid sending an
1654 * invalid beacon. This can happen for example, if the firmware
1655 * transmits a beacon while we are updating it. */
1656
1657 /* We could modify the existing beacon and set the aid bit in
1658 * the TIM field, but that would probably require resizing and
1659 * moving of data within the beacon template.
1660 * Simply request a new beacon and let mac80211 do the hard work. */
1661 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1662 if (unlikely(!beacon))
1663 return;
1664
1665 if (wl->current_beacon)
1666 dev_kfree_skb_any(wl->current_beacon);
1667 wl->current_beacon = beacon;
1668 wl->beacon0_uploaded = 0;
1669 wl->beacon1_uploaded = 0;
1670 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1671 }
1672
1673 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1674 {
1675 b43_time_lock(dev);
1676 if (dev->dev->id.revision >= 3) {
1677 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1678 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1679 } else {
1680 b43_write16(dev, 0x606, (beacon_int >> 6));
1681 b43_write16(dev, 0x610, beacon_int);
1682 }
1683 b43_time_unlock(dev);
1684 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1685 }
1686
1687 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1688 {
1689 u16 reason;
1690
1691 /* Read the register that contains the reason code for the panic. */
1692 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1693 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1694
1695 switch (reason) {
1696 default:
1697 b43dbg(dev->wl, "The panic reason is unknown.\n");
1698 /* fallthrough */
1699 case B43_FWPANIC_DIE:
1700 /* Do not restart the controller or firmware.
1701 * The device is nonfunctional from now on.
1702 * Restarting would result in this panic to trigger again,
1703 * so we avoid that recursion. */
1704 break;
1705 case B43_FWPANIC_RESTART:
1706 b43_controller_restart(dev, "Microcode panic");
1707 break;
1708 }
1709 }
1710
1711 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1712 {
1713 unsigned int i, cnt;
1714 u16 reason, marker_id, marker_line;
1715 __le16 *buf;
1716
1717 /* The proprietary firmware doesn't have this IRQ. */
1718 if (!dev->fw.opensource)
1719 return;
1720
1721 /* Read the register that contains the reason code for this IRQ. */
1722 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1723
1724 switch (reason) {
1725 case B43_DEBUGIRQ_PANIC:
1726 b43_handle_firmware_panic(dev);
1727 break;
1728 case B43_DEBUGIRQ_DUMP_SHM:
1729 if (!B43_DEBUG)
1730 break; /* Only with driver debugging enabled. */
1731 buf = kmalloc(4096, GFP_ATOMIC);
1732 if (!buf) {
1733 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1734 goto out;
1735 }
1736 for (i = 0; i < 4096; i += 2) {
1737 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1738 buf[i / 2] = cpu_to_le16(tmp);
1739 }
1740 b43info(dev->wl, "Shared memory dump:\n");
1741 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1742 16, 2, buf, 4096, 1);
1743 kfree(buf);
1744 break;
1745 case B43_DEBUGIRQ_DUMP_REGS:
1746 if (!B43_DEBUG)
1747 break; /* Only with driver debugging enabled. */
1748 b43info(dev->wl, "Microcode register dump:\n");
1749 for (i = 0, cnt = 0; i < 64; i++) {
1750 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1751 if (cnt == 0)
1752 printk(KERN_INFO);
1753 printk("r%02u: 0x%04X ", i, tmp);
1754 cnt++;
1755 if (cnt == 6) {
1756 printk("\n");
1757 cnt = 0;
1758 }
1759 }
1760 printk("\n");
1761 break;
1762 case B43_DEBUGIRQ_MARKER:
1763 if (!B43_DEBUG)
1764 break; /* Only with driver debugging enabled. */
1765 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1766 B43_MARKER_ID_REG);
1767 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1768 B43_MARKER_LINE_REG);
1769 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1770 "at line number %u\n",
1771 marker_id, marker_line);
1772 break;
1773 default:
1774 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1775 reason);
1776 }
1777 out:
1778 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1779 b43_shm_write16(dev, B43_SHM_SCRATCH,
1780 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1781 }
1782
1783 /* Interrupt handler bottom-half */
1784 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1785 {
1786 u32 reason;
1787 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1788 u32 merged_dma_reason = 0;
1789 int i;
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1793
1794 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1795
1796 reason = dev->irq_reason;
1797 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1798 dma_reason[i] = dev->dma_reason[i];
1799 merged_dma_reason |= dma_reason[i];
1800 }
1801
1802 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1803 b43err(dev->wl, "MAC transmission error\n");
1804
1805 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1806 b43err(dev->wl, "PHY transmission error\n");
1807 rmb();
1808 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1809 atomic_set(&dev->phy.txerr_cnt,
1810 B43_PHY_TX_BADNESS_LIMIT);
1811 b43err(dev->wl, "Too many PHY TX errors, "
1812 "restarting the controller\n");
1813 b43_controller_restart(dev, "PHY TX errors");
1814 }
1815 }
1816
1817 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1818 B43_DMAIRQ_NONFATALMASK))) {
1819 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1820 b43err(dev->wl, "Fatal DMA error: "
1821 "0x%08X, 0x%08X, 0x%08X, "
1822 "0x%08X, 0x%08X, 0x%08X\n",
1823 dma_reason[0], dma_reason[1],
1824 dma_reason[2], dma_reason[3],
1825 dma_reason[4], dma_reason[5]);
1826 b43_controller_restart(dev, "DMA error");
1827 mmiowb();
1828 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1829 return;
1830 }
1831 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1832 b43err(dev->wl, "DMA error: "
1833 "0x%08X, 0x%08X, 0x%08X, "
1834 "0x%08X, 0x%08X, 0x%08X\n",
1835 dma_reason[0], dma_reason[1],
1836 dma_reason[2], dma_reason[3],
1837 dma_reason[4], dma_reason[5]);
1838 }
1839 }
1840
1841 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1842 handle_irq_ucode_debug(dev);
1843 if (reason & B43_IRQ_TBTT_INDI)
1844 handle_irq_tbtt_indication(dev);
1845 if (reason & B43_IRQ_ATIM_END)
1846 handle_irq_atim_end(dev);
1847 if (reason & B43_IRQ_BEACON)
1848 handle_irq_beacon(dev);
1849 if (reason & B43_IRQ_PMQ)
1850 handle_irq_pmq(dev);
1851 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1852 ;/* TODO */
1853 if (reason & B43_IRQ_NOISESAMPLE_OK)
1854 handle_irq_noise(dev);
1855
1856 /* Check the DMA reason registers for received data. */
1857 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1858 if (b43_using_pio_transfers(dev))
1859 b43_pio_rx(dev->pio.rx_queue);
1860 else
1861 b43_dma_rx(dev->dma.rx_ring);
1862 }
1863 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1864 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1865 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1866 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1867 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1868
1869 if (reason & B43_IRQ_TX_OK)
1870 handle_irq_transmit_status(dev);
1871
1872 b43_interrupt_enable(dev, dev->irq_savedstate);
1873 mmiowb();
1874 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1875 }
1876
1877 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1878 {
1879 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1880
1881 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1882 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1883 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1884 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1885 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1886 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1887 }
1888
1889 /* Interrupt handler top-half */
1890 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1891 {
1892 irqreturn_t ret = IRQ_NONE;
1893 struct b43_wldev *dev = dev_id;
1894 u32 reason;
1895
1896 if (!dev)
1897 return IRQ_NONE;
1898
1899 spin_lock(&dev->wl->irq_lock);
1900
1901 if (b43_status(dev) < B43_STAT_STARTED)
1902 goto out;
1903 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1904 if (reason == 0xffffffff) /* shared IRQ */
1905 goto out;
1906 ret = IRQ_HANDLED;
1907 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1908 if (!reason)
1909 goto out;
1910
1911 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1912 & 0x0001DC00;
1913 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1914 & 0x0000DC00;
1915 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1916 & 0x0000DC00;
1917 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1918 & 0x0001DC00;
1919 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1920 & 0x0000DC00;
1921 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1922 & 0x0000DC00;
1923
1924 b43_interrupt_ack(dev, reason);
1925 /* disable all IRQs. They are enabled again in the bottom half. */
1926 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1927 /* save the reason code and call our bottom half. */
1928 dev->irq_reason = reason;
1929 tasklet_schedule(&dev->isr_tasklet);
1930 out:
1931 mmiowb();
1932 spin_unlock(&dev->wl->irq_lock);
1933
1934 return ret;
1935 }
1936
1937 static void do_release_fw(struct b43_firmware_file *fw)
1938 {
1939 release_firmware(fw->data);
1940 fw->data = NULL;
1941 fw->filename = NULL;
1942 }
1943
1944 static void b43_release_firmware(struct b43_wldev *dev)
1945 {
1946 do_release_fw(&dev->fw.ucode);
1947 do_release_fw(&dev->fw.pcm);
1948 do_release_fw(&dev->fw.initvals);
1949 do_release_fw(&dev->fw.initvals_band);
1950 }
1951
1952 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1953 {
1954 const char *text;
1955
1956 text = "You must go to "
1957 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware "
1958 "and download the correct firmware for this driver version. "
1959 "Please carefully read all instructions on this website.\n";
1960 if (error)
1961 b43err(wl, text);
1962 else
1963 b43warn(wl, text);
1964 }
1965
1966 static int do_request_fw(struct b43_wldev *dev,
1967 const char *name,
1968 struct b43_firmware_file *fw,
1969 bool silent)
1970 {
1971 char path[sizeof(modparam_fwpostfix) + 32];
1972 const struct firmware *blob;
1973 struct b43_fw_header *hdr;
1974 u32 size;
1975 int err;
1976
1977 if (!name) {
1978 /* Don't fetch anything. Free possibly cached firmware. */
1979 do_release_fw(fw);
1980 return 0;
1981 }
1982 if (fw->filename) {
1983 if (strcmp(fw->filename, name) == 0)
1984 return 0; /* Already have this fw. */
1985 /* Free the cached firmware first. */
1986 do_release_fw(fw);
1987 }
1988
1989 snprintf(path, ARRAY_SIZE(path),
1990 "b43%s/%s.fw",
1991 modparam_fwpostfix, name);
1992 err = request_firmware(&blob, path, dev->dev->dev);
1993 if (err == -ENOENT) {
1994 if (!silent) {
1995 b43err(dev->wl, "Firmware file \"%s\" not found\n",
1996 path);
1997 }
1998 return err;
1999 } else if (err) {
2000 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2001 path, err);
2002 return err;
2003 }
2004 if (blob->size < sizeof(struct b43_fw_header))
2005 goto err_format;
2006 hdr = (struct b43_fw_header *)(blob->data);
2007 switch (hdr->type) {
2008 case B43_FW_TYPE_UCODE:
2009 case B43_FW_TYPE_PCM:
2010 size = be32_to_cpu(hdr->size);
2011 if (size != blob->size - sizeof(struct b43_fw_header))
2012 goto err_format;
2013 /* fallthrough */
2014 case B43_FW_TYPE_IV:
2015 if (hdr->ver != 1)
2016 goto err_format;
2017 break;
2018 default:
2019 goto err_format;
2020 }
2021
2022 fw->data = blob;
2023 fw->filename = name;
2024
2025 return 0;
2026
2027 err_format:
2028 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
2029 release_firmware(blob);
2030
2031 return -EPROTO;
2032 }
2033
2034 static int b43_request_firmware(struct b43_wldev *dev)
2035 {
2036 struct b43_firmware *fw = &dev->fw;
2037 const u8 rev = dev->dev->id.revision;
2038 const char *filename;
2039 u32 tmshigh;
2040 int err;
2041
2042 /* Get microcode */
2043 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2044 if ((rev >= 5) && (rev <= 10))
2045 filename = "ucode5";
2046 else if ((rev >= 11) && (rev <= 12))
2047 filename = "ucode11";
2048 else if (rev >= 13)
2049 filename = "ucode13";
2050 else
2051 goto err_no_ucode;
2052 err = do_request_fw(dev, filename, &fw->ucode, 0);
2053 if (err)
2054 goto err_load;
2055
2056 /* Get PCM code */
2057 if ((rev >= 5) && (rev <= 10))
2058 filename = "pcm5";
2059 else if (rev >= 11)
2060 filename = NULL;
2061 else
2062 goto err_no_pcm;
2063 fw->pcm_request_failed = 0;
2064 err = do_request_fw(dev, filename, &fw->pcm, 1);
2065 if (err == -ENOENT) {
2066 /* We did not find a PCM file? Not fatal, but
2067 * core rev <= 10 must do without hwcrypto then. */
2068 fw->pcm_request_failed = 1;
2069 } else if (err)
2070 goto err_load;
2071
2072 /* Get initvals */
2073 switch (dev->phy.type) {
2074 case B43_PHYTYPE_A:
2075 if ((rev >= 5) && (rev <= 10)) {
2076 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2077 filename = "a0g1initvals5";
2078 else
2079 filename = "a0g0initvals5";
2080 } else
2081 goto err_no_initvals;
2082 break;
2083 case B43_PHYTYPE_G:
2084 if ((rev >= 5) && (rev <= 10))
2085 filename = "b0g0initvals5";
2086 else if (rev >= 13)
2087 filename = "b0g0initvals13";
2088 else
2089 goto err_no_initvals;
2090 break;
2091 case B43_PHYTYPE_N:
2092 if ((rev >= 11) && (rev <= 12))
2093 filename = "n0initvals11";
2094 else
2095 goto err_no_initvals;
2096 break;
2097 default:
2098 goto err_no_initvals;
2099 }
2100 err = do_request_fw(dev, filename, &fw->initvals, 0);
2101 if (err)
2102 goto err_load;
2103
2104 /* Get bandswitch initvals */
2105 switch (dev->phy.type) {
2106 case B43_PHYTYPE_A:
2107 if ((rev >= 5) && (rev <= 10)) {
2108 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2109 filename = "a0g1bsinitvals5";
2110 else
2111 filename = "a0g0bsinitvals5";
2112 } else if (rev >= 11)
2113 filename = NULL;
2114 else
2115 goto err_no_initvals;
2116 break;
2117 case B43_PHYTYPE_G:
2118 if ((rev >= 5) && (rev <= 10))
2119 filename = "b0g0bsinitvals5";
2120 else if (rev >= 11)
2121 filename = NULL;
2122 else
2123 goto err_no_initvals;
2124 break;
2125 case B43_PHYTYPE_N:
2126 if ((rev >= 11) && (rev <= 12))
2127 filename = "n0bsinitvals11";
2128 else
2129 goto err_no_initvals;
2130 break;
2131 default:
2132 goto err_no_initvals;
2133 }
2134 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2135 if (err)
2136 goto err_load;
2137
2138 return 0;
2139
2140 err_load:
2141 b43_print_fw_helptext(dev->wl, 1);
2142 goto error;
2143
2144 err_no_ucode:
2145 err = -ENODEV;
2146 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2147 goto error;
2148
2149 err_no_pcm:
2150 err = -ENODEV;
2151 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2152 goto error;
2153
2154 err_no_initvals:
2155 err = -ENODEV;
2156 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2157 "core rev %u\n", dev->phy.type, rev);
2158 goto error;
2159
2160 error:
2161 b43_release_firmware(dev);
2162 return err;
2163 }
2164
2165 static int b43_upload_microcode(struct b43_wldev *dev)
2166 {
2167 const size_t hdr_len = sizeof(struct b43_fw_header);
2168 const __be32 *data;
2169 unsigned int i, len;
2170 u16 fwrev, fwpatch, fwdate, fwtime;
2171 u32 tmp, macctl;
2172 int err = 0;
2173
2174 /* Jump the microcode PSM to offset 0 */
2175 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2176 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2177 macctl |= B43_MACCTL_PSM_JMP0;
2178 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2179 /* Zero out all microcode PSM registers and shared memory. */
2180 for (i = 0; i < 64; i++)
2181 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2182 for (i = 0; i < 4096; i += 2)
2183 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2184
2185 /* Upload Microcode. */
2186 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2187 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2188 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2189 for (i = 0; i < len; i++) {
2190 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2191 udelay(10);
2192 }
2193
2194 if (dev->fw.pcm.data) {
2195 /* Upload PCM data. */
2196 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2197 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2198 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2199 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2200 /* No need for autoinc bit in SHM_HW */
2201 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2202 for (i = 0; i < len; i++) {
2203 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2204 udelay(10);
2205 }
2206 }
2207
2208 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2209
2210 /* Start the microcode PSM */
2211 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2212 macctl &= ~B43_MACCTL_PSM_JMP0;
2213 macctl |= B43_MACCTL_PSM_RUN;
2214 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2215
2216 /* Wait for the microcode to load and respond */
2217 i = 0;
2218 while (1) {
2219 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2220 if (tmp == B43_IRQ_MAC_SUSPENDED)
2221 break;
2222 i++;
2223 if (i >= 20) {
2224 b43err(dev->wl, "Microcode not responding\n");
2225 b43_print_fw_helptext(dev->wl, 1);
2226 err = -ENODEV;
2227 goto error;
2228 }
2229 msleep_interruptible(50);
2230 if (signal_pending(current)) {
2231 err = -EINTR;
2232 goto error;
2233 }
2234 }
2235 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2236
2237 /* Get and check the revisions. */
2238 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2239 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2240 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2241 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2242
2243 if (fwrev <= 0x128) {
2244 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2245 "binary drivers older than version 4.x is unsupported. "
2246 "You must upgrade your firmware files.\n");
2247 b43_print_fw_helptext(dev->wl, 1);
2248 err = -EOPNOTSUPP;
2249 goto error;
2250 }
2251 dev->fw.rev = fwrev;
2252 dev->fw.patch = fwpatch;
2253 dev->fw.opensource = (fwdate == 0xFFFF);
2254
2255 if (dev->fw.opensource) {
2256 /* Patchlevel info is encoded in the "time" field. */
2257 dev->fw.patch = fwtime;
2258 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2259 dev->fw.rev, dev->fw.patch,
2260 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2261 } else {
2262 b43info(dev->wl, "Loading firmware version %u.%u "
2263 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2264 fwrev, fwpatch,
2265 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2266 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2267 if (dev->fw.pcm_request_failed) {
2268 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2269 "Hardware accelerated cryptography is disabled.\n");
2270 b43_print_fw_helptext(dev->wl, 0);
2271 }
2272 }
2273
2274 if (b43_is_old_txhdr_format(dev)) {
2275 /* We're over the deadline, but we keep support for old fw
2276 * until it turns out to be in major conflict with something new. */
2277 b43warn(dev->wl, "You are using an old firmware image. "
2278 "Support for old firmware will be removed soon "
2279 "(official deadline was July 2008).\n");
2280 b43_print_fw_helptext(dev->wl, 0);
2281 }
2282
2283 return 0;
2284
2285 error:
2286 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2287 macctl &= ~B43_MACCTL_PSM_RUN;
2288 macctl |= B43_MACCTL_PSM_JMP0;
2289 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2290
2291 return err;
2292 }
2293
2294 static int b43_write_initvals(struct b43_wldev *dev,
2295 const struct b43_iv *ivals,
2296 size_t count,
2297 size_t array_size)
2298 {
2299 const struct b43_iv *iv;
2300 u16 offset;
2301 size_t i;
2302 bool bit32;
2303
2304 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2305 iv = ivals;
2306 for (i = 0; i < count; i++) {
2307 if (array_size < sizeof(iv->offset_size))
2308 goto err_format;
2309 array_size -= sizeof(iv->offset_size);
2310 offset = be16_to_cpu(iv->offset_size);
2311 bit32 = !!(offset & B43_IV_32BIT);
2312 offset &= B43_IV_OFFSET_MASK;
2313 if (offset >= 0x1000)
2314 goto err_format;
2315 if (bit32) {
2316 u32 value;
2317
2318 if (array_size < sizeof(iv->data.d32))
2319 goto err_format;
2320 array_size -= sizeof(iv->data.d32);
2321
2322 value = get_unaligned_be32(&iv->data.d32);
2323 b43_write32(dev, offset, value);
2324
2325 iv = (const struct b43_iv *)((const uint8_t *)iv +
2326 sizeof(__be16) +
2327 sizeof(__be32));
2328 } else {
2329 u16 value;
2330
2331 if (array_size < sizeof(iv->data.d16))
2332 goto err_format;
2333 array_size -= sizeof(iv->data.d16);
2334
2335 value = be16_to_cpu(iv->data.d16);
2336 b43_write16(dev, offset, value);
2337
2338 iv = (const struct b43_iv *)((const uint8_t *)iv +
2339 sizeof(__be16) +
2340 sizeof(__be16));
2341 }
2342 }
2343 if (array_size)
2344 goto err_format;
2345
2346 return 0;
2347
2348 err_format:
2349 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2350 b43_print_fw_helptext(dev->wl, 1);
2351
2352 return -EPROTO;
2353 }
2354
2355 static int b43_upload_initvals(struct b43_wldev *dev)
2356 {
2357 const size_t hdr_len = sizeof(struct b43_fw_header);
2358 const struct b43_fw_header *hdr;
2359 struct b43_firmware *fw = &dev->fw;
2360 const struct b43_iv *ivals;
2361 size_t count;
2362 int err;
2363
2364 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2365 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2366 count = be32_to_cpu(hdr->size);
2367 err = b43_write_initvals(dev, ivals, count,
2368 fw->initvals.data->size - hdr_len);
2369 if (err)
2370 goto out;
2371 if (fw->initvals_band.data) {
2372 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2373 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2374 count = be32_to_cpu(hdr->size);
2375 err = b43_write_initvals(dev, ivals, count,
2376 fw->initvals_band.data->size - hdr_len);
2377 if (err)
2378 goto out;
2379 }
2380 out:
2381
2382 return err;
2383 }
2384
2385 /* Initialize the GPIOs
2386 * http://bcm-specs.sipsolutions.net/GPIO
2387 */
2388 static int b43_gpio_init(struct b43_wldev *dev)
2389 {
2390 struct ssb_bus *bus = dev->dev->bus;
2391 struct ssb_device *gpiodev, *pcidev = NULL;
2392 u32 mask, set;
2393
2394 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2395 & ~B43_MACCTL_GPOUTSMSK);
2396
2397 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2398 | 0x000F);
2399
2400 mask = 0x0000001F;
2401 set = 0x0000000F;
2402 if (dev->dev->bus->chip_id == 0x4301) {
2403 mask |= 0x0060;
2404 set |= 0x0060;
2405 }
2406 if (0 /* FIXME: conditional unknown */ ) {
2407 b43_write16(dev, B43_MMIO_GPIO_MASK,
2408 b43_read16(dev, B43_MMIO_GPIO_MASK)
2409 | 0x0100);
2410 mask |= 0x0180;
2411 set |= 0x0180;
2412 }
2413 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2414 b43_write16(dev, B43_MMIO_GPIO_MASK,
2415 b43_read16(dev, B43_MMIO_GPIO_MASK)
2416 | 0x0200);
2417 mask |= 0x0200;
2418 set |= 0x0200;
2419 }
2420 if (dev->dev->id.revision >= 2)
2421 mask |= 0x0010; /* FIXME: This is redundant. */
2422
2423 #ifdef CONFIG_SSB_DRIVER_PCICORE
2424 pcidev = bus->pcicore.dev;
2425 #endif
2426 gpiodev = bus->chipco.dev ? : pcidev;
2427 if (!gpiodev)
2428 return 0;
2429 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2430 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2431 & mask) | set);
2432
2433 return 0;
2434 }
2435
2436 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2437 static void b43_gpio_cleanup(struct b43_wldev *dev)
2438 {
2439 struct ssb_bus *bus = dev->dev->bus;
2440 struct ssb_device *gpiodev, *pcidev = NULL;
2441
2442 #ifdef CONFIG_SSB_DRIVER_PCICORE
2443 pcidev = bus->pcicore.dev;
2444 #endif
2445 gpiodev = bus->chipco.dev ? : pcidev;
2446 if (!gpiodev)
2447 return;
2448 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2449 }
2450
2451 /* http://bcm-specs.sipsolutions.net/EnableMac */
2452 void b43_mac_enable(struct b43_wldev *dev)
2453 {
2454 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2455 u16 fwstate;
2456
2457 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2458 B43_SHM_SH_UCODESTAT);
2459 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2460 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2461 b43err(dev->wl, "b43_mac_enable(): The firmware "
2462 "should be suspended, but current state is %u\n",
2463 fwstate);
2464 }
2465 }
2466
2467 dev->mac_suspended--;
2468 B43_WARN_ON(dev->mac_suspended < 0);
2469 if (dev->mac_suspended == 0) {
2470 b43_write32(dev, B43_MMIO_MACCTL,
2471 b43_read32(dev, B43_MMIO_MACCTL)
2472 | B43_MACCTL_ENABLED);
2473 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2474 B43_IRQ_MAC_SUSPENDED);
2475 /* Commit writes */
2476 b43_read32(dev, B43_MMIO_MACCTL);
2477 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2478 b43_power_saving_ctl_bits(dev, 0);
2479 }
2480 }
2481
2482 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2483 void b43_mac_suspend(struct b43_wldev *dev)
2484 {
2485 int i;
2486 u32 tmp;
2487
2488 might_sleep();
2489 B43_WARN_ON(dev->mac_suspended < 0);
2490
2491 if (dev->mac_suspended == 0) {
2492 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2493 b43_write32(dev, B43_MMIO_MACCTL,
2494 b43_read32(dev, B43_MMIO_MACCTL)
2495 & ~B43_MACCTL_ENABLED);
2496 /* force pci to flush the write */
2497 b43_read32(dev, B43_MMIO_MACCTL);
2498 for (i = 35; i; i--) {
2499 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2500 if (tmp & B43_IRQ_MAC_SUSPENDED)
2501 goto out;
2502 udelay(10);
2503 }
2504 /* Hm, it seems this will take some time. Use msleep(). */
2505 for (i = 40; i; i--) {
2506 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2507 if (tmp & B43_IRQ_MAC_SUSPENDED)
2508 goto out;
2509 msleep(1);
2510 }
2511 b43err(dev->wl, "MAC suspend failed\n");
2512 }
2513 out:
2514 dev->mac_suspended++;
2515 }
2516
2517 static void b43_adjust_opmode(struct b43_wldev *dev)
2518 {
2519 struct b43_wl *wl = dev->wl;
2520 u32 ctl;
2521 u16 cfp_pretbtt;
2522
2523 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2524 /* Reset status to STA infrastructure mode. */
2525 ctl &= ~B43_MACCTL_AP;
2526 ctl &= ~B43_MACCTL_KEEP_CTL;
2527 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2528 ctl &= ~B43_MACCTL_KEEP_BAD;
2529 ctl &= ~B43_MACCTL_PROMISC;
2530 ctl &= ~B43_MACCTL_BEACPROMISC;
2531 ctl |= B43_MACCTL_INFRA;
2532
2533 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2534 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2535 ctl |= B43_MACCTL_AP;
2536 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2537 ctl &= ~B43_MACCTL_INFRA;
2538
2539 if (wl->filter_flags & FIF_CONTROL)
2540 ctl |= B43_MACCTL_KEEP_CTL;
2541 if (wl->filter_flags & FIF_FCSFAIL)
2542 ctl |= B43_MACCTL_KEEP_BAD;
2543 if (wl->filter_flags & FIF_PLCPFAIL)
2544 ctl |= B43_MACCTL_KEEP_BADPLCP;
2545 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2546 ctl |= B43_MACCTL_PROMISC;
2547 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2548 ctl |= B43_MACCTL_BEACPROMISC;
2549
2550 /* Workaround: On old hardware the HW-MAC-address-filter
2551 * doesn't work properly, so always run promisc in filter
2552 * it in software. */
2553 if (dev->dev->id.revision <= 4)
2554 ctl |= B43_MACCTL_PROMISC;
2555
2556 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2557
2558 cfp_pretbtt = 2;
2559 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2560 if (dev->dev->bus->chip_id == 0x4306 &&
2561 dev->dev->bus->chip_rev == 3)
2562 cfp_pretbtt = 100;
2563 else
2564 cfp_pretbtt = 50;
2565 }
2566 b43_write16(dev, 0x612, cfp_pretbtt);
2567 }
2568
2569 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2570 {
2571 u16 offset;
2572
2573 if (is_ofdm) {
2574 offset = 0x480;
2575 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2576 } else {
2577 offset = 0x4C0;
2578 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2579 }
2580 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2581 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2582 }
2583
2584 static void b43_rate_memory_init(struct b43_wldev *dev)
2585 {
2586 switch (dev->phy.type) {
2587 case B43_PHYTYPE_A:
2588 case B43_PHYTYPE_G:
2589 case B43_PHYTYPE_N:
2590 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2591 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2592 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2593 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2594 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2595 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2596 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2597 if (dev->phy.type == B43_PHYTYPE_A)
2598 break;
2599 /* fallthrough */
2600 case B43_PHYTYPE_B:
2601 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2602 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2603 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2604 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2605 break;
2606 default:
2607 B43_WARN_ON(1);
2608 }
2609 }
2610
2611 /* Set the default values for the PHY TX Control Words. */
2612 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2613 {
2614 u16 ctl = 0;
2615
2616 ctl |= B43_TXH_PHY_ENC_CCK;
2617 ctl |= B43_TXH_PHY_ANT01AUTO;
2618 ctl |= B43_TXH_PHY_TXPWR;
2619
2620 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2621 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2622 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2623 }
2624
2625 /* Set the TX-Antenna for management frames sent by firmware. */
2626 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2627 {
2628 u16 ant;
2629 u16 tmp;
2630
2631 ant = b43_antenna_to_phyctl(antenna);
2632
2633 /* For ACK/CTS */
2634 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2635 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2636 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2637 /* For Probe Resposes */
2638 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2639 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2640 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2641 }
2642
2643 /* This is the opposite of b43_chip_init() */
2644 static void b43_chip_exit(struct b43_wldev *dev)
2645 {
2646 b43_phy_exit(dev);
2647 b43_gpio_cleanup(dev);
2648 /* firmware is released later */
2649 }
2650
2651 /* Initialize the chip
2652 * http://bcm-specs.sipsolutions.net/ChipInit
2653 */
2654 static int b43_chip_init(struct b43_wldev *dev)
2655 {
2656 struct b43_phy *phy = &dev->phy;
2657 int err;
2658 u32 value32, macctl;
2659 u16 value16;
2660
2661 /* Initialize the MAC control */
2662 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2663 if (dev->phy.gmode)
2664 macctl |= B43_MACCTL_GMODE;
2665 macctl |= B43_MACCTL_INFRA;
2666 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2667
2668 err = b43_request_firmware(dev);
2669 if (err)
2670 goto out;
2671 err = b43_upload_microcode(dev);
2672 if (err)
2673 goto out; /* firmware is released later */
2674
2675 err = b43_gpio_init(dev);
2676 if (err)
2677 goto out; /* firmware is released later */
2678
2679 err = b43_upload_initvals(dev);
2680 if (err)
2681 goto err_gpio_clean;
2682
2683 /* Turn the Analog on and initialize the PHY. */
2684 phy->ops->switch_analog(dev, 1);
2685 err = b43_phy_init(dev);
2686 if (err)
2687 goto err_gpio_clean;
2688
2689 /* Disable Interference Mitigation. */
2690 if (phy->ops->interf_mitigation)
2691 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2692
2693 /* Select the antennae */
2694 if (phy->ops->set_rx_antenna)
2695 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2696 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2697
2698 if (phy->type == B43_PHYTYPE_B) {
2699 value16 = b43_read16(dev, 0x005E);
2700 value16 |= 0x0004;
2701 b43_write16(dev, 0x005E, value16);
2702 }
2703 b43_write32(dev, 0x0100, 0x01000000);
2704 if (dev->dev->id.revision < 5)
2705 b43_write32(dev, 0x010C, 0x01000000);
2706
2707 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2708 & ~B43_MACCTL_INFRA);
2709 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2710 | B43_MACCTL_INFRA);
2711
2712 /* Probe Response Timeout value */
2713 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2714 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2715
2716 /* Initially set the wireless operation mode. */
2717 b43_adjust_opmode(dev);
2718
2719 if (dev->dev->id.revision < 3) {
2720 b43_write16(dev, 0x060E, 0x0000);
2721 b43_write16(dev, 0x0610, 0x8000);
2722 b43_write16(dev, 0x0604, 0x0000);
2723 b43_write16(dev, 0x0606, 0x0200);
2724 } else {
2725 b43_write32(dev, 0x0188, 0x80000000);
2726 b43_write32(dev, 0x018C, 0x02000000);
2727 }
2728 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2729 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2730 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2731 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2732 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2733 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2734 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2735
2736 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2737 value32 |= 0x00100000;
2738 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2739
2740 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2741 dev->dev->bus->chipco.fast_pwrup_delay);
2742
2743 err = 0;
2744 b43dbg(dev->wl, "Chip initialized\n");
2745 out:
2746 return err;
2747
2748 err_gpio_clean:
2749 b43_gpio_cleanup(dev);
2750 return err;
2751 }
2752
2753 static void b43_periodic_every60sec(struct b43_wldev *dev)
2754 {
2755 const struct b43_phy_operations *ops = dev->phy.ops;
2756
2757 if (ops->pwork_60sec)
2758 ops->pwork_60sec(dev);
2759
2760 /* Force check the TX power emission now. */
2761 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2762 }
2763
2764 static void b43_periodic_every30sec(struct b43_wldev *dev)
2765 {
2766 /* Update device statistics. */
2767 b43_calculate_link_quality(dev);
2768 }
2769
2770 static void b43_periodic_every15sec(struct b43_wldev *dev)
2771 {
2772 struct b43_phy *phy = &dev->phy;
2773 u16 wdr;
2774
2775 if (dev->fw.opensource) {
2776 /* Check if the firmware is still alive.
2777 * It will reset the watchdog counter to 0 in its idle loop. */
2778 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2779 if (unlikely(wdr)) {
2780 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2781 b43_controller_restart(dev, "Firmware watchdog");
2782 return;
2783 } else {
2784 b43_shm_write16(dev, B43_SHM_SCRATCH,
2785 B43_WATCHDOG_REG, 1);
2786 }
2787 }
2788
2789 if (phy->ops->pwork_15sec)
2790 phy->ops->pwork_15sec(dev);
2791
2792 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2793 wmb();
2794 }
2795
2796 static void do_periodic_work(struct b43_wldev *dev)
2797 {
2798 unsigned int state;
2799
2800 state = dev->periodic_state;
2801 if (state % 4 == 0)
2802 b43_periodic_every60sec(dev);
2803 if (state % 2 == 0)
2804 b43_periodic_every30sec(dev);
2805 b43_periodic_every15sec(dev);
2806 }
2807
2808 /* Periodic work locking policy:
2809 * The whole periodic work handler is protected by
2810 * wl->mutex. If another lock is needed somewhere in the
2811 * pwork callchain, it's aquired in-place, where it's needed.
2812 */
2813 static void b43_periodic_work_handler(struct work_struct *work)
2814 {
2815 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2816 periodic_work.work);
2817 struct b43_wl *wl = dev->wl;
2818 unsigned long delay;
2819
2820 mutex_lock(&wl->mutex);
2821
2822 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2823 goto out;
2824 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2825 goto out_requeue;
2826
2827 do_periodic_work(dev);
2828
2829 dev->periodic_state++;
2830 out_requeue:
2831 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2832 delay = msecs_to_jiffies(50);
2833 else
2834 delay = round_jiffies_relative(HZ * 15);
2835 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2836 out:
2837 mutex_unlock(&wl->mutex);
2838 }
2839
2840 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2841 {
2842 struct delayed_work *work = &dev->periodic_work;
2843
2844 dev->periodic_state = 0;
2845 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2846 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2847 }
2848
2849 /* Check if communication with the device works correctly. */
2850 static int b43_validate_chipaccess(struct b43_wldev *dev)
2851 {
2852 u32 v, backup;
2853
2854 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2855
2856 /* Check for read/write and endianness problems. */
2857 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2858 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2859 goto error;
2860 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2861 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2862 goto error;
2863
2864 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2865
2866 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2867 /* The 32bit register shadows the two 16bit registers
2868 * with update sideeffects. Validate this. */
2869 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2870 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2871 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2872 goto error;
2873 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2874 goto error;
2875 }
2876 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2877
2878 v = b43_read32(dev, B43_MMIO_MACCTL);
2879 v |= B43_MACCTL_GMODE;
2880 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2881 goto error;
2882
2883 return 0;
2884 error:
2885 b43err(dev->wl, "Failed to validate the chipaccess\n");
2886 return -ENODEV;
2887 }
2888
2889 static void b43_security_init(struct b43_wldev *dev)
2890 {
2891 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2892 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2893 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2894 /* KTP is a word address, but we address SHM bytewise.
2895 * So multiply by two.
2896 */
2897 dev->ktp *= 2;
2898 if (dev->dev->id.revision >= 5) {
2899 /* Number of RCMTA address slots */
2900 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2901 }
2902 b43_clear_keys(dev);
2903 }
2904
2905 static int b43_rng_read(struct hwrng *rng, u32 * data)
2906 {
2907 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2908 unsigned long flags;
2909
2910 /* Don't take wl->mutex here, as it could deadlock with
2911 * hwrng internal locking. It's not needed to take
2912 * wl->mutex here, anyway. */
2913
2914 spin_lock_irqsave(&wl->irq_lock, flags);
2915 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2916 spin_unlock_irqrestore(&wl->irq_lock, flags);
2917
2918 return (sizeof(u16));
2919 }
2920
2921 static void b43_rng_exit(struct b43_wl *wl)
2922 {
2923 if (wl->rng_initialized)
2924 hwrng_unregister(&wl->rng);
2925 }
2926
2927 static int b43_rng_init(struct b43_wl *wl)
2928 {
2929 int err;
2930
2931 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2932 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2933 wl->rng.name = wl->rng_name;
2934 wl->rng.data_read = b43_rng_read;
2935 wl->rng.priv = (unsigned long)wl;
2936 wl->rng_initialized = 1;
2937 err = hwrng_register(&wl->rng);
2938 if (err) {
2939 wl->rng_initialized = 0;
2940 b43err(wl, "Failed to register the random "
2941 "number generator (%d)\n", err);
2942 }
2943
2944 return err;
2945 }
2946
2947 static int b43_op_tx(struct ieee80211_hw *hw,
2948 struct sk_buff *skb)
2949 {
2950 struct b43_wl *wl = hw_to_b43_wl(hw);
2951 struct b43_wldev *dev = wl->current_dev;
2952 unsigned long flags;
2953 int err;
2954
2955 if (unlikely(skb->len < 2 + 2 + 6)) {
2956 /* Too short, this can't be a valid frame. */
2957 goto drop_packet;
2958 }
2959 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2960 if (unlikely(!dev))
2961 goto drop_packet;
2962
2963 /* Transmissions on seperate queues can run concurrently. */
2964 read_lock_irqsave(&wl->tx_lock, flags);
2965
2966 err = -ENODEV;
2967 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2968 if (b43_using_pio_transfers(dev))
2969 err = b43_pio_tx(dev, skb);
2970 else
2971 err = b43_dma_tx(dev, skb);
2972 }
2973
2974 read_unlock_irqrestore(&wl->tx_lock, flags);
2975
2976 if (unlikely(err))
2977 goto drop_packet;
2978 return NETDEV_TX_OK;
2979
2980 drop_packet:
2981 /* We can not transmit this packet. Drop it. */
2982 dev_kfree_skb_any(skb);
2983 return NETDEV_TX_OK;
2984 }
2985
2986 /* Locking: wl->irq_lock */
2987 static void b43_qos_params_upload(struct b43_wldev *dev,
2988 const struct ieee80211_tx_queue_params *p,
2989 u16 shm_offset)
2990 {
2991 u16 params[B43_NR_QOSPARAMS];
2992 int bslots, tmp;
2993 unsigned int i;
2994
2995 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
2996
2997 memset(&params, 0, sizeof(params));
2998
2999 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3000 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3001 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3002 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3003 params[B43_QOSPARAM_AIFS] = p->aifs;
3004 params[B43_QOSPARAM_BSLOTS] = bslots;
3005 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3006
3007 for (i = 0; i < ARRAY_SIZE(params); i++) {
3008 if (i == B43_QOSPARAM_STATUS) {
3009 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3010 shm_offset + (i * 2));
3011 /* Mark the parameters as updated. */
3012 tmp |= 0x100;
3013 b43_shm_write16(dev, B43_SHM_SHARED,
3014 shm_offset + (i * 2),
3015 tmp);
3016 } else {
3017 b43_shm_write16(dev, B43_SHM_SHARED,
3018 shm_offset + (i * 2),
3019 params[i]);
3020 }
3021 }
3022 }
3023
3024 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3025 static const u16 b43_qos_shm_offsets[] = {
3026 /* [mac80211-queue-nr] = SHM_OFFSET, */
3027 [0] = B43_QOS_VOICE,
3028 [1] = B43_QOS_VIDEO,
3029 [2] = B43_QOS_BESTEFFORT,
3030 [3] = B43_QOS_BACKGROUND,
3031 };
3032
3033 /* Update all QOS parameters in hardware. */
3034 static void b43_qos_upload_all(struct b43_wldev *dev)
3035 {
3036 struct b43_wl *wl = dev->wl;
3037 struct b43_qos_params *params;
3038 unsigned int i;
3039
3040 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3041 ARRAY_SIZE(wl->qos_params));
3042
3043 b43_mac_suspend(dev);
3044 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3045 params = &(wl->qos_params[i]);
3046 b43_qos_params_upload(dev, &(params->p),
3047 b43_qos_shm_offsets[i]);
3048 }
3049 b43_mac_enable(dev);
3050 }
3051
3052 static void b43_qos_clear(struct b43_wl *wl)
3053 {
3054 struct b43_qos_params *params;
3055 unsigned int i;
3056
3057 /* Initialize QoS parameters to sane defaults. */
3058
3059 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3060 ARRAY_SIZE(wl->qos_params));
3061
3062 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3063 params = &(wl->qos_params[i]);
3064
3065 switch (b43_qos_shm_offsets[i]) {
3066 case B43_QOS_VOICE:
3067 params->p.txop = 0;
3068 params->p.aifs = 2;
3069 params->p.cw_min = 0x0001;
3070 params->p.cw_max = 0x0001;
3071 break;
3072 case B43_QOS_VIDEO:
3073 params->p.txop = 0;
3074 params->p.aifs = 2;
3075 params->p.cw_min = 0x0001;
3076 params->p.cw_max = 0x0001;
3077 break;
3078 case B43_QOS_BESTEFFORT:
3079 params->p.txop = 0;
3080 params->p.aifs = 3;
3081 params->p.cw_min = 0x0001;
3082 params->p.cw_max = 0x03FF;
3083 break;
3084 case B43_QOS_BACKGROUND:
3085 params->p.txop = 0;
3086 params->p.aifs = 7;
3087 params->p.cw_min = 0x0001;
3088 params->p.cw_max = 0x03FF;
3089 break;
3090 default:
3091 B43_WARN_ON(1);
3092 }
3093 }
3094 }
3095
3096 /* Initialize the core's QOS capabilities */
3097 static void b43_qos_init(struct b43_wldev *dev)
3098 {
3099 /* Upload the current QOS parameters. */
3100 b43_qos_upload_all(dev);
3101
3102 /* Enable QOS support. */
3103 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3104 b43_write16(dev, B43_MMIO_IFSCTL,
3105 b43_read16(dev, B43_MMIO_IFSCTL)
3106 | B43_MMIO_IFSCTL_USE_EDCF);
3107 }
3108
3109 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3110 const struct ieee80211_tx_queue_params *params)
3111 {
3112 struct b43_wl *wl = hw_to_b43_wl(hw);
3113 struct b43_wldev *dev;
3114 unsigned int queue = (unsigned int)_queue;
3115 int err = -ENODEV;
3116
3117 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3118 /* Queue not available or don't support setting
3119 * params on this queue. Return success to not
3120 * confuse mac80211. */
3121 return 0;
3122 }
3123 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3124 ARRAY_SIZE(wl->qos_params));
3125
3126 mutex_lock(&wl->mutex);
3127 dev = wl->current_dev;
3128 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3129 goto out_unlock;
3130
3131 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3132 b43_mac_suspend(dev);
3133 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3134 b43_qos_shm_offsets[queue]);
3135 b43_mac_enable(dev);
3136 err = 0;
3137
3138 out_unlock:
3139 mutex_unlock(&wl->mutex);
3140
3141 return err;
3142 }
3143
3144 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3145 struct ieee80211_tx_queue_stats *stats)
3146 {
3147 struct b43_wl *wl = hw_to_b43_wl(hw);
3148 struct b43_wldev *dev = wl->current_dev;
3149 unsigned long flags;
3150 int err = -ENODEV;
3151
3152 if (!dev)
3153 goto out;
3154 spin_lock_irqsave(&wl->irq_lock, flags);
3155 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3156 if (b43_using_pio_transfers(dev))
3157 b43_pio_get_tx_stats(dev, stats);
3158 else
3159 b43_dma_get_tx_stats(dev, stats);
3160 err = 0;
3161 }
3162 spin_unlock_irqrestore(&wl->irq_lock, flags);
3163 out:
3164 return err;
3165 }
3166
3167 static int b43_op_get_stats(struct ieee80211_hw *hw,
3168 struct ieee80211_low_level_stats *stats)
3169 {
3170 struct b43_wl *wl = hw_to_b43_wl(hw);
3171 unsigned long flags;
3172
3173 spin_lock_irqsave(&wl->irq_lock, flags);
3174 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3175 spin_unlock_irqrestore(&wl->irq_lock, flags);
3176
3177 return 0;
3178 }
3179
3180 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3181 {
3182 struct ssb_device *sdev = dev->dev;
3183 u32 tmslow;
3184
3185 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3186 tmslow &= ~B43_TMSLOW_GMODE;
3187 tmslow |= B43_TMSLOW_PHYRESET;
3188 tmslow |= SSB_TMSLOW_FGC;
3189 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3190 msleep(1);
3191
3192 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3193 tmslow &= ~SSB_TMSLOW_FGC;
3194 tmslow |= B43_TMSLOW_PHYRESET;
3195 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3196 msleep(1);
3197 }
3198
3199 static const char * band_to_string(enum ieee80211_band band)
3200 {
3201 switch (band) {
3202 case IEEE80211_BAND_5GHZ:
3203 return "5";
3204 case IEEE80211_BAND_2GHZ:
3205 return "2.4";
3206 default:
3207 break;
3208 }
3209 B43_WARN_ON(1);
3210 return "";
3211 }
3212
3213 /* Expects wl->mutex locked */
3214 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3215 {
3216 struct b43_wldev *up_dev = NULL;
3217 struct b43_wldev *down_dev;
3218 struct b43_wldev *d;
3219 int err;
3220 bool uninitialized_var(gmode);
3221 int prev_status;
3222
3223 /* Find a device and PHY which supports the band. */
3224 list_for_each_entry(d, &wl->devlist, list) {
3225 switch (chan->band) {
3226 case IEEE80211_BAND_5GHZ:
3227 if (d->phy.supports_5ghz) {
3228 up_dev = d;
3229 gmode = 0;
3230 }
3231 break;
3232 case IEEE80211_BAND_2GHZ:
3233 if (d->phy.supports_2ghz) {
3234 up_dev = d;
3235 gmode = 1;
3236 }
3237 break;
3238 default:
3239 B43_WARN_ON(1);
3240 return -EINVAL;
3241 }
3242 if (up_dev)
3243 break;
3244 }
3245 if (!up_dev) {
3246 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3247 band_to_string(chan->band));
3248 return -ENODEV;
3249 }
3250 if ((up_dev == wl->current_dev) &&
3251 (!!wl->current_dev->phy.gmode == !!gmode)) {
3252 /* This device is already running. */
3253 return 0;
3254 }
3255 b43dbg(wl, "Switching to %s-GHz band\n",
3256 band_to_string(chan->band));
3257 down_dev = wl->current_dev;
3258
3259 prev_status = b43_status(down_dev);
3260 /* Shutdown the currently running core. */
3261 if (prev_status >= B43_STAT_STARTED)
3262 b43_wireless_core_stop(down_dev);
3263 if (prev_status >= B43_STAT_INITIALIZED)
3264 b43_wireless_core_exit(down_dev);
3265
3266 if (down_dev != up_dev) {
3267 /* We switch to a different core, so we put PHY into
3268 * RESET on the old core. */
3269 b43_put_phy_into_reset(down_dev);
3270 }
3271
3272 /* Now start the new core. */
3273 up_dev->phy.gmode = gmode;
3274 if (prev_status >= B43_STAT_INITIALIZED) {
3275 err = b43_wireless_core_init(up_dev);
3276 if (err) {
3277 b43err(wl, "Fatal: Could not initialize device for "
3278 "selected %s-GHz band\n",
3279 band_to_string(chan->band));
3280 goto init_failure;
3281 }
3282 }
3283 if (prev_status >= B43_STAT_STARTED) {
3284 err = b43_wireless_core_start(up_dev);
3285 if (err) {
3286 b43err(wl, "Fatal: Coult not start device for "
3287 "selected %s-GHz band\n",
3288 band_to_string(chan->band));
3289 b43_wireless_core_exit(up_dev);
3290 goto init_failure;
3291 }
3292 }
3293 B43_WARN_ON(b43_status(up_dev) != prev_status);
3294
3295 wl->current_dev = up_dev;
3296
3297 return 0;
3298 init_failure:
3299 /* Whoops, failed to init the new core. No core is operating now. */
3300 wl->current_dev = NULL;
3301 return err;
3302 }
3303
3304 /* Write the short and long frame retry limit values. */
3305 static void b43_set_retry_limits(struct b43_wldev *dev,
3306 unsigned int short_retry,
3307 unsigned int long_retry)
3308 {
3309 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3310 * the chip-internal counter. */
3311 short_retry = min(short_retry, (unsigned int)0xF);
3312 long_retry = min(long_retry, (unsigned int)0xF);
3313
3314 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3315 short_retry);
3316 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3317 long_retry);
3318 }
3319
3320 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3321 {
3322 struct b43_wl *wl = hw_to_b43_wl(hw);
3323 struct b43_wldev *dev;
3324 struct b43_phy *phy;
3325 struct ieee80211_conf *conf = &hw->conf;
3326 unsigned long flags;
3327 int antenna;
3328 int err = 0;
3329
3330 mutex_lock(&wl->mutex);
3331
3332 /* Switch the band (if necessary). This might change the active core. */
3333 err = b43_switch_band(wl, conf->channel);
3334 if (err)
3335 goto out_unlock_mutex;
3336 dev = wl->current_dev;
3337 phy = &dev->phy;
3338
3339 b43_mac_suspend(dev);
3340
3341 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3342 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3343 conf->long_frame_max_tx_count);
3344 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3345 if (!changed)
3346 goto out_mac_enable;
3347
3348 /* Switch to the requested channel.
3349 * The firmware takes care of races with the TX handler. */
3350 if (conf->channel->hw_value != phy->channel)
3351 b43_switch_channel(dev, conf->channel->hw_value);
3352
3353 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3354
3355 /* Adjust the desired TX power level. */
3356 if (conf->power_level != 0) {
3357 spin_lock_irqsave(&wl->irq_lock, flags);
3358 if (conf->power_level != phy->desired_txpower) {
3359 phy->desired_txpower = conf->power_level;
3360 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3361 B43_TXPWR_IGNORE_TSSI);
3362 }
3363 spin_unlock_irqrestore(&wl->irq_lock, flags);
3364 }
3365
3366 /* Antennas for RX and management frame TX. */
3367 antenna = B43_ANTENNA_DEFAULT;
3368 b43_mgmtframe_txantenna(dev, antenna);
3369 antenna = B43_ANTENNA_DEFAULT;
3370 if (phy->ops->set_rx_antenna)
3371 phy->ops->set_rx_antenna(dev, antenna);
3372
3373 /* Update templates for AP/mesh mode. */
3374 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3375 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3376 b43_set_beacon_int(dev, conf->beacon_int);
3377
3378 if (!!conf->radio_enabled != phy->radio_on) {
3379 if (conf->radio_enabled) {
3380 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3381 b43info(dev->wl, "Radio turned on by software\n");
3382 if (!dev->radio_hw_enable) {
3383 b43info(dev->wl, "The hardware RF-kill button "
3384 "still turns the radio physically off. "
3385 "Press the button to turn it on.\n");
3386 }
3387 } else {
3388 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3389 b43info(dev->wl, "Radio turned off by software\n");
3390 }
3391 }
3392
3393 out_mac_enable:
3394 b43_mac_enable(dev);
3395 out_unlock_mutex:
3396 mutex_unlock(&wl->mutex);
3397
3398 return err;
3399 }
3400
3401 static void b43_update_basic_rates(struct b43_wldev *dev, u64 brates)
3402 {
3403 struct ieee80211_supported_band *sband =
3404 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3405 struct ieee80211_rate *rate;
3406 int i;
3407 u16 basic, direct, offset, basic_offset, rateptr;
3408
3409 for (i = 0; i < sband->n_bitrates; i++) {
3410 rate = &sband->bitrates[i];
3411
3412 if (b43_is_cck_rate(rate->hw_value)) {
3413 direct = B43_SHM_SH_CCKDIRECT;
3414 basic = B43_SHM_SH_CCKBASIC;
3415 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3416 offset &= 0xF;
3417 } else {
3418 direct = B43_SHM_SH_OFDMDIRECT;
3419 basic = B43_SHM_SH_OFDMBASIC;
3420 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3421 offset &= 0xF;
3422 }
3423
3424 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3425
3426 if (b43_is_cck_rate(rate->hw_value)) {
3427 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3428 basic_offset &= 0xF;
3429 } else {
3430 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3431 basic_offset &= 0xF;
3432 }
3433
3434 /*
3435 * Get the pointer that we need to point to
3436 * from the direct map
3437 */
3438 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3439 direct + 2 * basic_offset);
3440 /* and write it to the basic map */
3441 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3442 rateptr);
3443 }
3444 }
3445
3446 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3447 struct ieee80211_vif *vif,
3448 struct ieee80211_bss_conf *conf,
3449 u32 changed)
3450 {
3451 struct b43_wl *wl = hw_to_b43_wl(hw);
3452 struct b43_wldev *dev;
3453
3454 mutex_lock(&wl->mutex);
3455
3456 dev = wl->current_dev;
3457 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3458 goto out_unlock_mutex;
3459 b43_mac_suspend(dev);
3460
3461 if (changed & BSS_CHANGED_BASIC_RATES)
3462 b43_update_basic_rates(dev, conf->basic_rates);
3463
3464 if (changed & BSS_CHANGED_ERP_SLOT) {
3465 if (conf->use_short_slot)
3466 b43_short_slot_timing_enable(dev);
3467 else
3468 b43_short_slot_timing_disable(dev);
3469 }
3470
3471 b43_mac_enable(dev);
3472 out_unlock_mutex:
3473 mutex_unlock(&wl->mutex);
3474
3475 return;
3476 }
3477
3478 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3479 const u8 *local_addr, const u8 *addr,
3480 struct ieee80211_key_conf *key)
3481 {
3482 struct b43_wl *wl = hw_to_b43_wl(hw);
3483 struct b43_wldev *dev;
3484 u8 algorithm;
3485 u8 index;
3486 int err;
3487
3488 if (modparam_nohwcrypt)
3489 return -ENOSPC; /* User disabled HW-crypto */
3490
3491 mutex_lock(&wl->mutex);
3492 spin_lock_irq(&wl->irq_lock);
3493 write_lock(&wl->tx_lock);
3494 /* Why do we need all this locking here?
3495 * mutex -> Every config operation must take it.
3496 * irq_lock -> We modify the dev->key array, which is accessed
3497 * in the IRQ handlers.
3498 * tx_lock -> We modify the dev->key array, which is accessed
3499 * in the TX handler.
3500 */
3501
3502 dev = wl->current_dev;
3503 err = -ENODEV;
3504 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3505 goto out_unlock;
3506
3507 if (dev->fw.pcm_request_failed) {
3508 /* We don't have firmware for the crypto engine.
3509 * Must use software-crypto. */
3510 err = -EOPNOTSUPP;
3511 goto out_unlock;
3512 }
3513
3514 err = -EINVAL;
3515 switch (key->alg) {
3516 case ALG_WEP:
3517 if (key->keylen == LEN_WEP40)
3518 algorithm = B43_SEC_ALGO_WEP40;
3519 else
3520 algorithm = B43_SEC_ALGO_WEP104;
3521 break;
3522 case ALG_TKIP:
3523 algorithm = B43_SEC_ALGO_TKIP;
3524 break;
3525 case ALG_CCMP:
3526 algorithm = B43_SEC_ALGO_AES;
3527 break;
3528 default:
3529 B43_WARN_ON(1);
3530 goto out_unlock;
3531 }
3532 index = (u8) (key->keyidx);
3533 if (index > 3)
3534 goto out_unlock;
3535
3536 switch (cmd) {
3537 case SET_KEY:
3538 if (algorithm == B43_SEC_ALGO_TKIP) {
3539 /* FIXME: No TKIP hardware encryption for now. */
3540 err = -EOPNOTSUPP;
3541 goto out_unlock;
3542 }
3543
3544 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3545 /* Pairwise key with an assigned MAC address. */
3546 err = b43_key_write(dev, -1, algorithm,
3547 key->key, key->keylen, addr, key);
3548 } else {
3549 /* Group key */
3550 err = b43_key_write(dev, index, algorithm,
3551 key->key, key->keylen, NULL, key);
3552 }
3553 if (err)
3554 goto out_unlock;
3555
3556 if (algorithm == B43_SEC_ALGO_WEP40 ||
3557 algorithm == B43_SEC_ALGO_WEP104) {
3558 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3559 } else {
3560 b43_hf_write(dev,
3561 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3562 }
3563 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3564 break;
3565 case DISABLE_KEY: {
3566 err = b43_key_clear(dev, key->hw_key_idx);
3567 if (err)
3568 goto out_unlock;
3569 break;
3570 }
3571 default:
3572 B43_WARN_ON(1);
3573 }
3574
3575 out_unlock:
3576 if (!err) {
3577 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3578 "mac: %pM\n",
3579 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3580 addr);
3581 b43_dump_keymemory(dev);
3582 }
3583 write_unlock(&wl->tx_lock);
3584 spin_unlock_irq(&wl->irq_lock);
3585 mutex_unlock(&wl->mutex);
3586
3587 return err;
3588 }
3589
3590 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3591 unsigned int changed, unsigned int *fflags,
3592 int mc_count, struct dev_addr_list *mc_list)
3593 {
3594 struct b43_wl *wl = hw_to_b43_wl(hw);
3595 struct b43_wldev *dev = wl->current_dev;
3596 unsigned long flags;
3597
3598 if (!dev) {
3599 *fflags = 0;
3600 return;
3601 }
3602
3603 spin_lock_irqsave(&wl->irq_lock, flags);
3604 *fflags &= FIF_PROMISC_IN_BSS |
3605 FIF_ALLMULTI |
3606 FIF_FCSFAIL |
3607 FIF_PLCPFAIL |
3608 FIF_CONTROL |
3609 FIF_OTHER_BSS |
3610 FIF_BCN_PRBRESP_PROMISC;
3611
3612 changed &= FIF_PROMISC_IN_BSS |
3613 FIF_ALLMULTI |
3614 FIF_FCSFAIL |
3615 FIF_PLCPFAIL |
3616 FIF_CONTROL |
3617 FIF_OTHER_BSS |
3618 FIF_BCN_PRBRESP_PROMISC;
3619
3620 wl->filter_flags = *fflags;
3621
3622 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3623 b43_adjust_opmode(dev);
3624 spin_unlock_irqrestore(&wl->irq_lock, flags);
3625 }
3626
3627 static int b43_op_config_interface(struct ieee80211_hw *hw,
3628 struct ieee80211_vif *vif,
3629 struct ieee80211_if_conf *conf)
3630 {
3631 struct b43_wl *wl = hw_to_b43_wl(hw);
3632 struct b43_wldev *dev = wl->current_dev;
3633 unsigned long flags;
3634
3635 if (!dev)
3636 return -ENODEV;
3637 mutex_lock(&wl->mutex);
3638 spin_lock_irqsave(&wl->irq_lock, flags);
3639 B43_WARN_ON(wl->vif != vif);
3640 if (conf->bssid)
3641 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3642 else
3643 memset(wl->bssid, 0, ETH_ALEN);
3644 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3645 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3646 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
3647 B43_WARN_ON(vif->type != wl->if_type);
3648 if (conf->changed & IEEE80211_IFCC_BEACON)
3649 b43_update_templates(wl);
3650 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
3651 if (conf->changed & IEEE80211_IFCC_BEACON)
3652 b43_update_templates(wl);
3653 }
3654 b43_write_mac_bssid_templates(dev);
3655 }
3656 spin_unlock_irqrestore(&wl->irq_lock, flags);
3657 mutex_unlock(&wl->mutex);
3658
3659 return 0;
3660 }
3661
3662 /* Locking: wl->mutex */
3663 static void b43_wireless_core_stop(struct b43_wldev *dev)
3664 {
3665 struct b43_wl *wl = dev->wl;
3666 unsigned long flags;
3667
3668 if (b43_status(dev) < B43_STAT_STARTED)
3669 return;
3670
3671 /* Disable and sync interrupts. We must do this before than
3672 * setting the status to INITIALIZED, as the interrupt handler
3673 * won't care about IRQs then. */
3674 spin_lock_irqsave(&wl->irq_lock, flags);
3675 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3676 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3677 spin_unlock_irqrestore(&wl->irq_lock, flags);
3678 b43_synchronize_irq(dev);
3679
3680 write_lock_irqsave(&wl->tx_lock, flags);
3681 b43_set_status(dev, B43_STAT_INITIALIZED);
3682 write_unlock_irqrestore(&wl->tx_lock, flags);
3683
3684 b43_pio_stop(dev);
3685 mutex_unlock(&wl->mutex);
3686 /* Must unlock as it would otherwise deadlock. No races here.
3687 * Cancel the possibly running self-rearming periodic work. */
3688 cancel_delayed_work_sync(&dev->periodic_work);
3689 mutex_lock(&wl->mutex);
3690
3691 b43_mac_suspend(dev);
3692 free_irq(dev->dev->irq, dev);
3693 b43dbg(wl, "Wireless interface stopped\n");
3694 }
3695
3696 /* Locking: wl->mutex */
3697 static int b43_wireless_core_start(struct b43_wldev *dev)
3698 {
3699 int err;
3700
3701 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3702
3703 drain_txstatus_queue(dev);
3704 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3705 IRQF_SHARED, KBUILD_MODNAME, dev);
3706 if (err) {
3707 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3708 goto out;
3709 }
3710
3711 /* We are ready to run. */
3712 b43_set_status(dev, B43_STAT_STARTED);
3713
3714 /* Start data flow (TX/RX). */
3715 b43_mac_enable(dev);
3716 b43_interrupt_enable(dev, dev->irq_savedstate);
3717
3718 /* Start maintainance work */
3719 b43_periodic_tasks_setup(dev);
3720
3721 b43dbg(dev->wl, "Wireless interface started\n");
3722 out:
3723 return err;
3724 }
3725
3726 /* Get PHY and RADIO versioning numbers */
3727 static int b43_phy_versioning(struct b43_wldev *dev)
3728 {
3729 struct b43_phy *phy = &dev->phy;
3730 u32 tmp;
3731 u8 analog_type;
3732 u8 phy_type;
3733 u8 phy_rev;
3734 u16 radio_manuf;
3735 u16 radio_ver;
3736 u16 radio_rev;
3737 int unsupported = 0;
3738
3739 /* Get PHY versioning */
3740 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3741 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3742 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3743 phy_rev = (tmp & B43_PHYVER_VERSION);
3744 switch (phy_type) {
3745 case B43_PHYTYPE_A:
3746 if (phy_rev >= 4)
3747 unsupported = 1;
3748 break;
3749 case B43_PHYTYPE_B:
3750 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3751 && phy_rev != 7)
3752 unsupported = 1;
3753 break;
3754 case B43_PHYTYPE_G:
3755 if (phy_rev > 9)
3756 unsupported = 1;
3757 break;
3758 #ifdef CONFIG_B43_NPHY
3759 case B43_PHYTYPE_N:
3760 if (phy_rev > 4)
3761 unsupported = 1;
3762 break;
3763 #endif
3764 #ifdef CONFIG_B43_PHY_LP
3765 case B43_PHYTYPE_LP:
3766 if (phy_rev > 1)
3767 unsupported = 1;
3768 break;
3769 #endif
3770 default:
3771 unsupported = 1;
3772 };
3773 if (unsupported) {
3774 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3775 "(Analog %u, Type %u, Revision %u)\n",
3776 analog_type, phy_type, phy_rev);
3777 return -EOPNOTSUPP;
3778 }
3779 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3780 analog_type, phy_type, phy_rev);
3781
3782 /* Get RADIO versioning */
3783 if (dev->dev->bus->chip_id == 0x4317) {
3784 if (dev->dev->bus->chip_rev == 0)
3785 tmp = 0x3205017F;
3786 else if (dev->dev->bus->chip_rev == 1)
3787 tmp = 0x4205017F;
3788 else
3789 tmp = 0x5205017F;
3790 } else {
3791 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3792 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3793 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3794 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3795 }
3796 radio_manuf = (tmp & 0x00000FFF);
3797 radio_ver = (tmp & 0x0FFFF000) >> 12;
3798 radio_rev = (tmp & 0xF0000000) >> 28;
3799 if (radio_manuf != 0x17F /* Broadcom */)
3800 unsupported = 1;
3801 switch (phy_type) {
3802 case B43_PHYTYPE_A:
3803 if (radio_ver != 0x2060)
3804 unsupported = 1;
3805 if (radio_rev != 1)
3806 unsupported = 1;
3807 if (radio_manuf != 0x17F)
3808 unsupported = 1;
3809 break;
3810 case B43_PHYTYPE_B:
3811 if ((radio_ver & 0xFFF0) != 0x2050)
3812 unsupported = 1;
3813 break;
3814 case B43_PHYTYPE_G:
3815 if (radio_ver != 0x2050)
3816 unsupported = 1;
3817 break;
3818 case B43_PHYTYPE_N:
3819 if (radio_ver != 0x2055 && radio_ver != 0x2056)
3820 unsupported = 1;
3821 break;
3822 case B43_PHYTYPE_LP:
3823 if (radio_ver != 0x2062)
3824 unsupported = 1;
3825 break;
3826 default:
3827 B43_WARN_ON(1);
3828 }
3829 if (unsupported) {
3830 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3831 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3832 radio_manuf, radio_ver, radio_rev);
3833 return -EOPNOTSUPP;
3834 }
3835 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3836 radio_manuf, radio_ver, radio_rev);
3837
3838 phy->radio_manuf = radio_manuf;
3839 phy->radio_ver = radio_ver;
3840 phy->radio_rev = radio_rev;
3841
3842 phy->analog = analog_type;
3843 phy->type = phy_type;
3844 phy->rev = phy_rev;
3845
3846 return 0;
3847 }
3848
3849 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3850 struct b43_phy *phy)
3851 {
3852 phy->hardware_power_control = !!modparam_hwpctl;
3853 phy->next_txpwr_check_time = jiffies;
3854 /* PHY TX errors counter. */
3855 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3856 }
3857
3858 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3859 {
3860 dev->dfq_valid = 0;
3861
3862 /* Assume the radio is enabled. If it's not enabled, the state will
3863 * immediately get fixed on the first periodic work run. */
3864 dev->radio_hw_enable = 1;
3865
3866 /* Stats */
3867 memset(&dev->stats, 0, sizeof(dev->stats));
3868
3869 setup_struct_phy_for_init(dev, &dev->phy);
3870
3871 /* IRQ related flags */
3872 dev->irq_reason = 0;
3873 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3874 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3875
3876 dev->mac_suspended = 1;
3877
3878 /* Noise calculation context */
3879 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3880 }
3881
3882 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3883 {
3884 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3885 u64 hf;
3886
3887 if (!modparam_btcoex)
3888 return;
3889 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3890 return;
3891 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3892 return;
3893
3894 hf = b43_hf_read(dev);
3895 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3896 hf |= B43_HF_BTCOEXALT;
3897 else
3898 hf |= B43_HF_BTCOEX;
3899 b43_hf_write(dev, hf);
3900 }
3901
3902 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3903 {
3904 if (!modparam_btcoex)
3905 return;
3906 //TODO
3907 }
3908
3909 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3910 {
3911 #ifdef CONFIG_SSB_DRIVER_PCICORE
3912 struct ssb_bus *bus = dev->dev->bus;
3913 u32 tmp;
3914
3915 if (bus->pcicore.dev &&
3916 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3917 bus->pcicore.dev->id.revision <= 5) {
3918 /* IMCFGLO timeouts workaround. */
3919 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3920 tmp &= ~SSB_IMCFGLO_REQTO;
3921 tmp &= ~SSB_IMCFGLO_SERTO;
3922 switch (bus->bustype) {
3923 case SSB_BUSTYPE_PCI:
3924 case SSB_BUSTYPE_PCMCIA:
3925 tmp |= 0x32;
3926 break;
3927 case SSB_BUSTYPE_SSB:
3928 tmp |= 0x53;
3929 break;
3930 }
3931 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3932 }
3933 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3934 }
3935
3936 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3937 {
3938 u16 pu_delay;
3939
3940 /* The time value is in microseconds. */
3941 if (dev->phy.type == B43_PHYTYPE_A)
3942 pu_delay = 3700;
3943 else
3944 pu_delay = 1050;
3945 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3946 pu_delay = 500;
3947 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3948 pu_delay = max(pu_delay, (u16)2400);
3949
3950 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3951 }
3952
3953 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3954 static void b43_set_pretbtt(struct b43_wldev *dev)
3955 {
3956 u16 pretbtt;
3957
3958 /* The time value is in microseconds. */
3959 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
3960 pretbtt = 2;
3961 } else {
3962 if (dev->phy.type == B43_PHYTYPE_A)
3963 pretbtt = 120;
3964 else
3965 pretbtt = 250;
3966 }
3967 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3968 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3969 }
3970
3971 /* Shutdown a wireless core */
3972 /* Locking: wl->mutex */
3973 static void b43_wireless_core_exit(struct b43_wldev *dev)
3974 {
3975 u32 macctl;
3976
3977 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3978 if (b43_status(dev) != B43_STAT_INITIALIZED)
3979 return;
3980 b43_set_status(dev, B43_STAT_UNINIT);
3981
3982 /* Stop the microcode PSM. */
3983 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3984 macctl &= ~B43_MACCTL_PSM_RUN;
3985 macctl |= B43_MACCTL_PSM_JMP0;
3986 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3987
3988 if (!dev->suspend_in_progress) {
3989 b43_leds_exit(dev);
3990 b43_rng_exit(dev->wl);
3991 }
3992 b43_dma_free(dev);
3993 b43_pio_free(dev);
3994 b43_chip_exit(dev);
3995 dev->phy.ops->switch_analog(dev, 0);
3996 if (dev->wl->current_beacon) {
3997 dev_kfree_skb_any(dev->wl->current_beacon);
3998 dev->wl->current_beacon = NULL;
3999 }
4000
4001 ssb_device_disable(dev->dev, 0);
4002 ssb_bus_may_powerdown(dev->dev->bus);
4003 }
4004
4005 /* Initialize a wireless core */
4006 static int b43_wireless_core_init(struct b43_wldev *dev)
4007 {
4008 struct b43_wl *wl = dev->wl;
4009 struct ssb_bus *bus = dev->dev->bus;
4010 struct ssb_sprom *sprom = &bus->sprom;
4011 struct b43_phy *phy = &dev->phy;
4012 int err;
4013 u64 hf;
4014 u32 tmp;
4015
4016 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4017
4018 err = ssb_bus_powerup(bus, 0);
4019 if (err)
4020 goto out;
4021 if (!ssb_device_is_enabled(dev->dev)) {
4022 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4023 b43_wireless_core_reset(dev, tmp);
4024 }
4025
4026 /* Reset all data structures. */
4027 setup_struct_wldev_for_init(dev);
4028 phy->ops->prepare_structs(dev);
4029
4030 /* Enable IRQ routing to this device. */
4031 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4032
4033 b43_imcfglo_timeouts_workaround(dev);
4034 b43_bluetooth_coext_disable(dev);
4035 if (phy->ops->prepare_hardware) {
4036 err = phy->ops->prepare_hardware(dev);
4037 if (err)
4038 goto err_busdown;
4039 }
4040 err = b43_chip_init(dev);
4041 if (err)
4042 goto err_busdown;
4043 b43_shm_write16(dev, B43_SHM_SHARED,
4044 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4045 hf = b43_hf_read(dev);
4046 if (phy->type == B43_PHYTYPE_G) {
4047 hf |= B43_HF_SYMW;
4048 if (phy->rev == 1)
4049 hf |= B43_HF_GDCW;
4050 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4051 hf |= B43_HF_OFDMPABOOST;
4052 } else if (phy->type == B43_PHYTYPE_B) {
4053 hf |= B43_HF_SYMW;
4054 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4055 hf &= ~B43_HF_GDCW;
4056 }
4057 b43_hf_write(dev, hf);
4058
4059 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4060 B43_DEFAULT_LONG_RETRY_LIMIT);
4061 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4062 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4063
4064 /* Disable sending probe responses from firmware.
4065 * Setting the MaxTime to one usec will always trigger
4066 * a timeout, so we never send any probe resp.
4067 * A timeout of zero is infinite. */
4068 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4069
4070 b43_rate_memory_init(dev);
4071 b43_set_phytxctl_defaults(dev);
4072
4073 /* Minimum Contention Window */
4074 if (phy->type == B43_PHYTYPE_B) {
4075 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4076 } else {
4077 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4078 }
4079 /* Maximum Contention Window */
4080 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4081
4082 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4083 dev->__using_pio_transfers = 1;
4084 err = b43_pio_init(dev);
4085 } else {
4086 dev->__using_pio_transfers = 0;
4087 err = b43_dma_init(dev);
4088 }
4089 if (err)
4090 goto err_chip_exit;
4091 b43_qos_init(dev);
4092 b43_set_synth_pu_delay(dev, 1);
4093 b43_bluetooth_coext_enable(dev);
4094
4095 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4096 b43_upload_card_macaddress(dev);
4097 b43_security_init(dev);
4098 if (!dev->suspend_in_progress)
4099 b43_rng_init(wl);
4100
4101 b43_set_status(dev, B43_STAT_INITIALIZED);
4102
4103 if (!dev->suspend_in_progress)
4104 b43_leds_init(dev);
4105 out:
4106 return err;
4107
4108 err_chip_exit:
4109 b43_chip_exit(dev);
4110 err_busdown:
4111 ssb_bus_may_powerdown(bus);
4112 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4113 return err;
4114 }
4115
4116 static int b43_op_add_interface(struct ieee80211_hw *hw,
4117 struct ieee80211_if_init_conf *conf)
4118 {
4119 struct b43_wl *wl = hw_to_b43_wl(hw);
4120 struct b43_wldev *dev;
4121 unsigned long flags;
4122 int err = -EOPNOTSUPP;
4123
4124 /* TODO: allow WDS/AP devices to coexist */
4125
4126 if (conf->type != NL80211_IFTYPE_AP &&
4127 conf->type != NL80211_IFTYPE_MESH_POINT &&
4128 conf->type != NL80211_IFTYPE_STATION &&
4129 conf->type != NL80211_IFTYPE_WDS &&
4130 conf->type != NL80211_IFTYPE_ADHOC)
4131 return -EOPNOTSUPP;
4132
4133 mutex_lock(&wl->mutex);
4134 if (wl->operating)
4135 goto out_mutex_unlock;
4136
4137 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4138
4139 dev = wl->current_dev;
4140 wl->operating = 1;
4141 wl->vif = conf->vif;
4142 wl->if_type = conf->type;
4143 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4144
4145 spin_lock_irqsave(&wl->irq_lock, flags);
4146 b43_adjust_opmode(dev);
4147 b43_set_pretbtt(dev);
4148 b43_set_synth_pu_delay(dev, 0);
4149 b43_upload_card_macaddress(dev);
4150 spin_unlock_irqrestore(&wl->irq_lock, flags);
4151
4152 err = 0;
4153 out_mutex_unlock:
4154 mutex_unlock(&wl->mutex);
4155
4156 return err;
4157 }
4158
4159 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4160 struct ieee80211_if_init_conf *conf)
4161 {
4162 struct b43_wl *wl = hw_to_b43_wl(hw);
4163 struct b43_wldev *dev = wl->current_dev;
4164 unsigned long flags;
4165
4166 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4167
4168 mutex_lock(&wl->mutex);
4169
4170 B43_WARN_ON(!wl->operating);
4171 B43_WARN_ON(wl->vif != conf->vif);
4172 wl->vif = NULL;
4173
4174 wl->operating = 0;
4175
4176 spin_lock_irqsave(&wl->irq_lock, flags);
4177 b43_adjust_opmode(dev);
4178 memset(wl->mac_addr, 0, ETH_ALEN);
4179 b43_upload_card_macaddress(dev);
4180 spin_unlock_irqrestore(&wl->irq_lock, flags);
4181
4182 mutex_unlock(&wl->mutex);
4183 }
4184
4185 static int b43_op_start(struct ieee80211_hw *hw)
4186 {
4187 struct b43_wl *wl = hw_to_b43_wl(hw);
4188 struct b43_wldev *dev = wl->current_dev;
4189 int did_init = 0;
4190 int err = 0;
4191 bool do_rfkill_exit = 0;
4192
4193 /* Kill all old instance specific information to make sure
4194 * the card won't use it in the short timeframe between start
4195 * and mac80211 reconfiguring it. */
4196 memset(wl->bssid, 0, ETH_ALEN);
4197 memset(wl->mac_addr, 0, ETH_ALEN);
4198 wl->filter_flags = 0;
4199 wl->radiotap_enabled = 0;
4200 b43_qos_clear(wl);
4201 wl->beacon0_uploaded = 0;
4202 wl->beacon1_uploaded = 0;
4203 wl->beacon_templates_virgin = 1;
4204
4205 /* First register RFkill.
4206 * LEDs that are registered later depend on it. */
4207 b43_rfkill_init(dev);
4208
4209 mutex_lock(&wl->mutex);
4210
4211 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4212 err = b43_wireless_core_init(dev);
4213 if (err) {
4214 do_rfkill_exit = 1;
4215 goto out_mutex_unlock;
4216 }
4217 did_init = 1;
4218 }
4219
4220 if (b43_status(dev) < B43_STAT_STARTED) {
4221 err = b43_wireless_core_start(dev);
4222 if (err) {
4223 if (did_init)
4224 b43_wireless_core_exit(dev);
4225 do_rfkill_exit = 1;
4226 goto out_mutex_unlock;
4227 }
4228 }
4229
4230 out_mutex_unlock:
4231 mutex_unlock(&wl->mutex);
4232
4233 if (do_rfkill_exit)
4234 b43_rfkill_exit(dev);
4235
4236 return err;
4237 }
4238
4239 static void b43_op_stop(struct ieee80211_hw *hw)
4240 {
4241 struct b43_wl *wl = hw_to_b43_wl(hw);
4242 struct b43_wldev *dev = wl->current_dev;
4243
4244 b43_rfkill_exit(dev);
4245 cancel_work_sync(&(wl->beacon_update_trigger));
4246
4247 mutex_lock(&wl->mutex);
4248 if (b43_status(dev) >= B43_STAT_STARTED)
4249 b43_wireless_core_stop(dev);
4250 b43_wireless_core_exit(dev);
4251 mutex_unlock(&wl->mutex);
4252
4253 cancel_work_sync(&(wl->txpower_adjust_work));
4254 }
4255
4256 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4257 struct ieee80211_sta *sta, bool set)
4258 {
4259 struct b43_wl *wl = hw_to_b43_wl(hw);
4260 unsigned long flags;
4261
4262 spin_lock_irqsave(&wl->irq_lock, flags);
4263 b43_update_templates(wl);
4264 spin_unlock_irqrestore(&wl->irq_lock, flags);
4265
4266 return 0;
4267 }
4268
4269 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4270 struct ieee80211_vif *vif,
4271 enum sta_notify_cmd notify_cmd,
4272 struct ieee80211_sta *sta)
4273 {
4274 struct b43_wl *wl = hw_to_b43_wl(hw);
4275
4276 B43_WARN_ON(!vif || wl->vif != vif);
4277 }
4278
4279 static const struct ieee80211_ops b43_hw_ops = {
4280 .tx = b43_op_tx,
4281 .conf_tx = b43_op_conf_tx,
4282 .add_interface = b43_op_add_interface,
4283 .remove_interface = b43_op_remove_interface,
4284 .config = b43_op_config,
4285 .bss_info_changed = b43_op_bss_info_changed,
4286 .config_interface = b43_op_config_interface,
4287 .configure_filter = b43_op_configure_filter,
4288 .set_key = b43_op_set_key,
4289 .get_stats = b43_op_get_stats,
4290 .get_tx_stats = b43_op_get_tx_stats,
4291 .start = b43_op_start,
4292 .stop = b43_op_stop,
4293 .set_tim = b43_op_beacon_set_tim,
4294 .sta_notify = b43_op_sta_notify,
4295 };
4296
4297 /* Hard-reset the chip. Do not call this directly.
4298 * Use b43_controller_restart()
4299 */
4300 static void b43_chip_reset(struct work_struct *work)
4301 {
4302 struct b43_wldev *dev =
4303 container_of(work, struct b43_wldev, restart_work);
4304 struct b43_wl *wl = dev->wl;
4305 int err = 0;
4306 int prev_status;
4307
4308 mutex_lock(&wl->mutex);
4309
4310 prev_status = b43_status(dev);
4311 /* Bring the device down... */
4312 if (prev_status >= B43_STAT_STARTED)
4313 b43_wireless_core_stop(dev);
4314 if (prev_status >= B43_STAT_INITIALIZED)
4315 b43_wireless_core_exit(dev);
4316
4317 /* ...and up again. */
4318 if (prev_status >= B43_STAT_INITIALIZED) {
4319 err = b43_wireless_core_init(dev);
4320 if (err)
4321 goto out;
4322 }
4323 if (prev_status >= B43_STAT_STARTED) {
4324 err = b43_wireless_core_start(dev);
4325 if (err) {
4326 b43_wireless_core_exit(dev);
4327 goto out;
4328 }
4329 }
4330 out:
4331 if (err)
4332 wl->current_dev = NULL; /* Failed to init the dev. */
4333 mutex_unlock(&wl->mutex);
4334 if (err)
4335 b43err(wl, "Controller restart FAILED\n");
4336 else
4337 b43info(wl, "Controller restarted\n");
4338 }
4339
4340 static int b43_setup_bands(struct b43_wldev *dev,
4341 bool have_2ghz_phy, bool have_5ghz_phy)
4342 {
4343 struct ieee80211_hw *hw = dev->wl->hw;
4344
4345 if (have_2ghz_phy)
4346 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4347 if (dev->phy.type == B43_PHYTYPE_N) {
4348 if (have_5ghz_phy)
4349 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4350 } else {
4351 if (have_5ghz_phy)
4352 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4353 }
4354
4355 dev->phy.supports_2ghz = have_2ghz_phy;
4356 dev->phy.supports_5ghz = have_5ghz_phy;
4357
4358 return 0;
4359 }
4360
4361 static void b43_wireless_core_detach(struct b43_wldev *dev)
4362 {
4363 /* We release firmware that late to not be required to re-request
4364 * is all the time when we reinit the core. */
4365 b43_release_firmware(dev);
4366 b43_phy_free(dev);
4367 }
4368
4369 static int b43_wireless_core_attach(struct b43_wldev *dev)
4370 {
4371 struct b43_wl *wl = dev->wl;
4372 struct ssb_bus *bus = dev->dev->bus;
4373 struct pci_dev *pdev = bus->host_pci;
4374 int err;
4375 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4376 u32 tmp;
4377
4378 /* Do NOT do any device initialization here.
4379 * Do it in wireless_core_init() instead.
4380 * This function is for gathering basic information about the HW, only.
4381 * Also some structs may be set up here. But most likely you want to have
4382 * that in core_init(), too.
4383 */
4384
4385 err = ssb_bus_powerup(bus, 0);
4386 if (err) {
4387 b43err(wl, "Bus powerup failed\n");
4388 goto out;
4389 }
4390 /* Get the PHY type. */
4391 if (dev->dev->id.revision >= 5) {
4392 u32 tmshigh;
4393
4394 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4395 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4396 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4397 } else
4398 B43_WARN_ON(1);
4399
4400 dev->phy.gmode = have_2ghz_phy;
4401 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4402 b43_wireless_core_reset(dev, tmp);
4403
4404 err = b43_phy_versioning(dev);
4405 if (err)
4406 goto err_powerdown;
4407 /* Check if this device supports multiband. */
4408 if (!pdev ||
4409 (pdev->device != 0x4312 &&
4410 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4411 /* No multiband support. */
4412 have_2ghz_phy = 0;
4413 have_5ghz_phy = 0;
4414 switch (dev->phy.type) {
4415 case B43_PHYTYPE_A:
4416 have_5ghz_phy = 1;
4417 break;
4418 case B43_PHYTYPE_G:
4419 case B43_PHYTYPE_N:
4420 case B43_PHYTYPE_LP:
4421 have_2ghz_phy = 1;
4422 break;
4423 default:
4424 B43_WARN_ON(1);
4425 }
4426 }
4427 if (dev->phy.type == B43_PHYTYPE_A) {
4428 /* FIXME */
4429 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4430 err = -EOPNOTSUPP;
4431 goto err_powerdown;
4432 }
4433 if (1 /* disable A-PHY */) {
4434 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4435 if (dev->phy.type != B43_PHYTYPE_N) {
4436 have_2ghz_phy = 1;
4437 have_5ghz_phy = 0;
4438 }
4439 }
4440
4441 err = b43_phy_allocate(dev);
4442 if (err)
4443 goto err_powerdown;
4444
4445 dev->phy.gmode = have_2ghz_phy;
4446 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4447 b43_wireless_core_reset(dev, tmp);
4448
4449 err = b43_validate_chipaccess(dev);
4450 if (err)
4451 goto err_phy_free;
4452 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4453 if (err)
4454 goto err_phy_free;
4455
4456 /* Now set some default "current_dev" */
4457 if (!wl->current_dev)
4458 wl->current_dev = dev;
4459 INIT_WORK(&dev->restart_work, b43_chip_reset);
4460
4461 dev->phy.ops->switch_analog(dev, 0);
4462 ssb_device_disable(dev->dev, 0);
4463 ssb_bus_may_powerdown(bus);
4464
4465 out:
4466 return err;
4467
4468 err_phy_free:
4469 b43_phy_free(dev);
4470 err_powerdown:
4471 ssb_bus_may_powerdown(bus);
4472 return err;
4473 }
4474
4475 static void b43_one_core_detach(struct ssb_device *dev)
4476 {
4477 struct b43_wldev *wldev;
4478 struct b43_wl *wl;
4479
4480 /* Do not cancel ieee80211-workqueue based work here.
4481 * See comment in b43_remove(). */
4482
4483 wldev = ssb_get_drvdata(dev);
4484 wl = wldev->wl;
4485 b43_debugfs_remove_device(wldev);
4486 b43_wireless_core_detach(wldev);
4487 list_del(&wldev->list);
4488 wl->nr_devs--;
4489 ssb_set_drvdata(dev, NULL);
4490 kfree(wldev);
4491 }
4492
4493 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4494 {
4495 struct b43_wldev *wldev;
4496 struct pci_dev *pdev;
4497 int err = -ENOMEM;
4498
4499 if (!list_empty(&wl->devlist)) {
4500 /* We are not the first core on this chip. */
4501 pdev = dev->bus->host_pci;
4502 /* Only special chips support more than one wireless
4503 * core, although some of the other chips have more than
4504 * one wireless core as well. Check for this and
4505 * bail out early.
4506 */
4507 if (!pdev ||
4508 ((pdev->device != 0x4321) &&
4509 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4510 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4511 return -ENODEV;
4512 }
4513 }
4514
4515 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4516 if (!wldev)
4517 goto out;
4518
4519 wldev->dev = dev;
4520 wldev->wl = wl;
4521 b43_set_status(wldev, B43_STAT_UNINIT);
4522 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4523 tasklet_init(&wldev->isr_tasklet,
4524 (void (*)(unsigned long))b43_interrupt_tasklet,
4525 (unsigned long)wldev);
4526 INIT_LIST_HEAD(&wldev->list);
4527
4528 err = b43_wireless_core_attach(wldev);
4529 if (err)
4530 goto err_kfree_wldev;
4531
4532 list_add(&wldev->list, &wl->devlist);
4533 wl->nr_devs++;
4534 ssb_set_drvdata(dev, wldev);
4535 b43_debugfs_add_device(wldev);
4536
4537 out:
4538 return err;
4539
4540 err_kfree_wldev:
4541 kfree(wldev);
4542 return err;
4543 }
4544
4545 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4546 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4547 (pdev->device == _device) && \
4548 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4549 (pdev->subsystem_device == _subdevice) )
4550
4551 static void b43_sprom_fixup(struct ssb_bus *bus)
4552 {
4553 struct pci_dev *pdev;
4554
4555 /* boardflags workarounds */
4556 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4557 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4558 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4559 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4560 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4561 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4562 if (bus->bustype == SSB_BUSTYPE_PCI) {
4563 pdev = bus->host_pci;
4564 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4565 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4566 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4567 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4568 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4569 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4570 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4571 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4572 }
4573 }
4574
4575 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4576 {
4577 struct ieee80211_hw *hw = wl->hw;
4578
4579 ssb_set_devtypedata(dev, NULL);
4580 ieee80211_free_hw(hw);
4581 }
4582
4583 static int b43_wireless_init(struct ssb_device *dev)
4584 {
4585 struct ssb_sprom *sprom = &dev->bus->sprom;
4586 struct ieee80211_hw *hw;
4587 struct b43_wl *wl;
4588 int err = -ENOMEM;
4589
4590 b43_sprom_fixup(dev->bus);
4591
4592 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4593 if (!hw) {
4594 b43err(NULL, "Could not allocate ieee80211 device\n");
4595 goto out;
4596 }
4597
4598 /* fill hw info */
4599 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4600 IEEE80211_HW_SIGNAL_DBM |
4601 IEEE80211_HW_NOISE_DBM;
4602
4603 hw->wiphy->interface_modes =
4604 BIT(NL80211_IFTYPE_AP) |
4605 BIT(NL80211_IFTYPE_MESH_POINT) |
4606 BIT(NL80211_IFTYPE_STATION) |
4607 BIT(NL80211_IFTYPE_WDS) |
4608 BIT(NL80211_IFTYPE_ADHOC);
4609
4610 hw->queues = b43_modparam_qos ? 4 : 1;
4611 hw->max_rates = 2;
4612 SET_IEEE80211_DEV(hw, dev->dev);
4613 if (is_valid_ether_addr(sprom->et1mac))
4614 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4615 else
4616 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4617
4618 /* Get and initialize struct b43_wl */
4619 wl = hw_to_b43_wl(hw);
4620 memset(wl, 0, sizeof(*wl));
4621 wl->hw = hw;
4622 spin_lock_init(&wl->irq_lock);
4623 rwlock_init(&wl->tx_lock);
4624 spin_lock_init(&wl->leds_lock);
4625 spin_lock_init(&wl->shm_lock);
4626 mutex_init(&wl->mutex);
4627 INIT_LIST_HEAD(&wl->devlist);
4628 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4629 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4630
4631 ssb_set_devtypedata(dev, wl);
4632 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4633 err = 0;
4634 out:
4635 return err;
4636 }
4637
4638 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4639 {
4640 struct b43_wl *wl;
4641 int err;
4642 int first = 0;
4643
4644 wl = ssb_get_devtypedata(dev);
4645 if (!wl) {
4646 /* Probing the first core. Must setup common struct b43_wl */
4647 first = 1;
4648 err = b43_wireless_init(dev);
4649 if (err)
4650 goto out;
4651 wl = ssb_get_devtypedata(dev);
4652 B43_WARN_ON(!wl);
4653 }
4654 err = b43_one_core_attach(dev, wl);
4655 if (err)
4656 goto err_wireless_exit;
4657
4658 if (first) {
4659 err = ieee80211_register_hw(wl->hw);
4660 if (err)
4661 goto err_one_core_detach;
4662 }
4663
4664 out:
4665 return err;
4666
4667 err_one_core_detach:
4668 b43_one_core_detach(dev);
4669 err_wireless_exit:
4670 if (first)
4671 b43_wireless_exit(dev, wl);
4672 return err;
4673 }
4674
4675 static void b43_remove(struct ssb_device *dev)
4676 {
4677 struct b43_wl *wl = ssb_get_devtypedata(dev);
4678 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4679
4680 /* We must cancel any work here before unregistering from ieee80211,
4681 * as the ieee80211 unreg will destroy the workqueue. */
4682 cancel_work_sync(&wldev->restart_work);
4683
4684 B43_WARN_ON(!wl);
4685 if (wl->current_dev == wldev)
4686 ieee80211_unregister_hw(wl->hw);
4687
4688 b43_one_core_detach(dev);
4689
4690 if (list_empty(&wl->devlist)) {
4691 /* Last core on the chip unregistered.
4692 * We can destroy common struct b43_wl.
4693 */
4694 b43_wireless_exit(dev, wl);
4695 }
4696 }
4697
4698 /* Perform a hardware reset. This can be called from any context. */
4699 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4700 {
4701 /* Must avoid requeueing, if we are in shutdown. */
4702 if (b43_status(dev) < B43_STAT_INITIALIZED)
4703 return;
4704 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4705 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4706 }
4707
4708 #ifdef CONFIG_PM
4709
4710 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4711 {
4712 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4713 struct b43_wl *wl = wldev->wl;
4714
4715 b43dbg(wl, "Suspending...\n");
4716
4717 mutex_lock(&wl->mutex);
4718 wldev->suspend_in_progress = true;
4719 wldev->suspend_init_status = b43_status(wldev);
4720 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4721 b43_wireless_core_stop(wldev);
4722 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4723 b43_wireless_core_exit(wldev);
4724 mutex_unlock(&wl->mutex);
4725
4726 b43dbg(wl, "Device suspended.\n");
4727
4728 return 0;
4729 }
4730
4731 static int b43_resume(struct ssb_device *dev)
4732 {
4733 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4734 struct b43_wl *wl = wldev->wl;
4735 int err = 0;
4736
4737 b43dbg(wl, "Resuming...\n");
4738
4739 mutex_lock(&wl->mutex);
4740 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4741 err = b43_wireless_core_init(wldev);
4742 if (err) {
4743 b43err(wl, "Resume failed at core init\n");
4744 goto out;
4745 }
4746 }
4747 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4748 err = b43_wireless_core_start(wldev);
4749 if (err) {
4750 b43_leds_exit(wldev);
4751 b43_rng_exit(wldev->wl);
4752 b43_wireless_core_exit(wldev);
4753 b43err(wl, "Resume failed at core start\n");
4754 goto out;
4755 }
4756 }
4757 b43dbg(wl, "Device resumed.\n");
4758 out:
4759 wldev->suspend_in_progress = false;
4760 mutex_unlock(&wl->mutex);
4761 return err;
4762 }
4763
4764 #else /* CONFIG_PM */
4765 # define b43_suspend NULL
4766 # define b43_resume NULL
4767 #endif /* CONFIG_PM */
4768
4769 static struct ssb_driver b43_ssb_driver = {
4770 .name = KBUILD_MODNAME,
4771 .id_table = b43_ssb_tbl,
4772 .probe = b43_probe,
4773 .remove = b43_remove,
4774 .suspend = b43_suspend,
4775 .resume = b43_resume,
4776 };
4777
4778 static void b43_print_driverinfo(void)
4779 {
4780 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4781 *feat_leds = "", *feat_rfkill = "";
4782
4783 #ifdef CONFIG_B43_PCI_AUTOSELECT
4784 feat_pci = "P";
4785 #endif
4786 #ifdef CONFIG_B43_PCMCIA
4787 feat_pcmcia = "M";
4788 #endif
4789 #ifdef CONFIG_B43_NPHY
4790 feat_nphy = "N";
4791 #endif
4792 #ifdef CONFIG_B43_LEDS
4793 feat_leds = "L";
4794 #endif
4795 #ifdef CONFIG_B43_RFKILL
4796 feat_rfkill = "R";
4797 #endif
4798 printk(KERN_INFO "Broadcom 43xx driver loaded "
4799 "[ Features: %s%s%s%s%s, Firmware-ID: "
4800 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4801 feat_pci, feat_pcmcia, feat_nphy,
4802 feat_leds, feat_rfkill);
4803 }
4804
4805 static int __init b43_init(void)
4806 {
4807 int err;
4808
4809 b43_debugfs_init();
4810 err = b43_pcmcia_init();
4811 if (err)
4812 goto err_dfs_exit;
4813 err = ssb_driver_register(&b43_ssb_driver);
4814 if (err)
4815 goto err_pcmcia_exit;
4816 b43_print_driverinfo();
4817
4818 return err;
4819
4820 err_pcmcia_exit:
4821 b43_pcmcia_exit();
4822 err_dfs_exit:
4823 b43_debugfs_exit();
4824 return err;
4825 }
4826
4827 static void __exit b43_exit(void)
4828 {
4829 ssb_driver_unregister(&b43_ssb_driver);
4830 b43_pcmcia_exit();
4831 b43_debugfs_exit();
4832 }
4833
4834 module_init(b43_init)
4835 module_exit(b43_exit)
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