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Merge branch 'master'
[linux-2.6/verdex.git] / arch / powerpc / kernel / cputable.c
blob1d85cedbbb7b740d4ed9d14db828e469f2942244
1 /*
2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
3 *
4 * Modifications for ppc64:
5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #include <linux/config.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/threads.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19
20 #include <asm/oprofile_impl.h>
21 #include <asm/cputable.h>
22
23 struct cpu_spec* cur_cpu_spec = NULL;
24 EXPORT_SYMBOL(cur_cpu_spec);
25
26 /* NOTE:
27 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
28 * the responsibility of the appropriate CPU save/restore functions to
29 * eventually copy these settings over. Those save/restore aren't yet
30 * part of the cputable though. That has to be fixed for both ppc32
31 * and ppc64
32 */
33 #ifdef CONFIG_PPC64
34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
36 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
37 #else
38 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
39 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
40 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
41 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
42 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
43 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
44 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
45 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
46 #endif /* CONFIG_PPC32 */
47 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
48
49 /* This table only contains "desktop" CPUs, it need to be filled with embedded
50 * ones as well...
51 */
52 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
53 PPC_FEATURE_HAS_MMU)
54 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
55 #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
56 #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5)
57 #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS)
58
59
60 /* We only set the spe features if the kernel was compiled with
61 * spe support
62 */
63 #ifdef CONFIG_SPE
64 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
65 #else
66 #define PPC_FEATURE_SPE_COMP 0
67 #endif
68
69 struct cpu_spec cpu_specs[] = {
70 #ifdef CONFIG_PPC64
71 { /* Power3 */
72 .pvr_mask = 0xffff0000,
73 .pvr_value = 0x00400000,
74 .cpu_name = "POWER3 (630)",
75 .cpu_features = CPU_FTRS_POWER3,
76 .cpu_user_features = COMMON_USER_PPC64,
77 .icache_bsize = 128,
78 .dcache_bsize = 128,
79 .num_pmcs = 8,
80 .cpu_setup = __setup_cpu_power3,
81 #ifdef CONFIG_OPROFILE
82 .oprofile_cpu_type = "ppc64/power3",
83 .oprofile_model = &op_model_rs64,
84 #endif
85 },
86 { /* Power3+ */
87 .pvr_mask = 0xffff0000,
88 .pvr_value = 0x00410000,
89 .cpu_name = "POWER3 (630+)",
90 .cpu_features = CPU_FTRS_POWER3,
91 .cpu_user_features = COMMON_USER_PPC64,
92 .icache_bsize = 128,
93 .dcache_bsize = 128,
94 .num_pmcs = 8,
95 .cpu_setup = __setup_cpu_power3,
96 #ifdef CONFIG_OPROFILE
97 .oprofile_cpu_type = "ppc64/power3",
98 .oprofile_model = &op_model_rs64,
99 #endif
100 },
101 { /* Northstar */
102 .pvr_mask = 0xffff0000,
103 .pvr_value = 0x00330000,
104 .cpu_name = "RS64-II (northstar)",
105 .cpu_features = CPU_FTRS_RS64,
106 .cpu_user_features = COMMON_USER_PPC64,
107 .icache_bsize = 128,
108 .dcache_bsize = 128,
109 .num_pmcs = 8,
110 .cpu_setup = __setup_cpu_power3,
111 #ifdef CONFIG_OPROFILE
112 .oprofile_cpu_type = "ppc64/rs64",
113 .oprofile_model = &op_model_rs64,
114 #endif
115 },
116 { /* Pulsar */
117 .pvr_mask = 0xffff0000,
118 .pvr_value = 0x00340000,
119 .cpu_name = "RS64-III (pulsar)",
120 .cpu_features = CPU_FTRS_RS64,
121 .cpu_user_features = COMMON_USER_PPC64,
122 .icache_bsize = 128,
123 .dcache_bsize = 128,
124 .num_pmcs = 8,
125 .cpu_setup = __setup_cpu_power3,
126 #ifdef CONFIG_OPROFILE
127 .oprofile_cpu_type = "ppc64/rs64",
128 .oprofile_model = &op_model_rs64,
129 #endif
130 },
131 { /* I-star */
132 .pvr_mask = 0xffff0000,
133 .pvr_value = 0x00360000,
134 .cpu_name = "RS64-III (icestar)",
135 .cpu_features = CPU_FTRS_RS64,
136 .cpu_user_features = COMMON_USER_PPC64,
137 .icache_bsize = 128,
138 .dcache_bsize = 128,
139 .num_pmcs = 8,
140 .cpu_setup = __setup_cpu_power3,
141 #ifdef CONFIG_OPROFILE
142 .oprofile_cpu_type = "ppc64/rs64",
143 .oprofile_model = &op_model_rs64,
144 #endif
145 },
146 { /* S-star */
147 .pvr_mask = 0xffff0000,
148 .pvr_value = 0x00370000,
149 .cpu_name = "RS64-IV (sstar)",
150 .cpu_features = CPU_FTRS_RS64,
151 .cpu_user_features = COMMON_USER_PPC64,
152 .icache_bsize = 128,
153 .dcache_bsize = 128,
154 .num_pmcs = 8,
155 .cpu_setup = __setup_cpu_power3,
156 #ifdef CONFIG_OPROFILE
157 .oprofile_cpu_type = "ppc64/rs64",
158 .oprofile_model = &op_model_rs64,
159 #endif
160 },
161 { /* Power4 */
162 .pvr_mask = 0xffff0000,
163 .pvr_value = 0x00350000,
164 .cpu_name = "POWER4 (gp)",
165 .cpu_features = CPU_FTRS_POWER4,
166 .cpu_user_features = COMMON_USER_POWER4,
167 .icache_bsize = 128,
168 .dcache_bsize = 128,
169 .num_pmcs = 8,
170 .cpu_setup = __setup_cpu_power4,
171 #ifdef CONFIG_OPROFILE
172 .oprofile_cpu_type = "ppc64/power4",
173 .oprofile_model = &op_model_rs64,
174 #endif
175 },
176 { /* Power4+ */
177 .pvr_mask = 0xffff0000,
178 .pvr_value = 0x00380000,
179 .cpu_name = "POWER4+ (gq)",
180 .cpu_features = CPU_FTRS_POWER4,
181 .cpu_user_features = COMMON_USER_POWER4,
182 .icache_bsize = 128,
183 .dcache_bsize = 128,
184 .num_pmcs = 8,
185 .cpu_setup = __setup_cpu_power4,
186 #ifdef CONFIG_OPROFILE
187 .oprofile_cpu_type = "ppc64/power4",
188 .oprofile_model = &op_model_power4,
189 #endif
190 },
191 { /* PPC970 */
192 .pvr_mask = 0xffff0000,
193 .pvr_value = 0x00390000,
194 .cpu_name = "PPC970",
195 .cpu_features = CPU_FTRS_PPC970,
196 .cpu_user_features = COMMON_USER_POWER4 |
197 PPC_FEATURE_HAS_ALTIVEC_COMP,
198 .icache_bsize = 128,
199 .dcache_bsize = 128,
200 .num_pmcs = 8,
201 .cpu_setup = __setup_cpu_ppc970,
202 #ifdef CONFIG_OPROFILE
203 .oprofile_cpu_type = "ppc64/970",
204 .oprofile_model = &op_model_power4,
205 #endif
206 },
207 #endif /* CONFIG_PPC64 */
208 #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
209 { /* PPC970FX */
210 .pvr_mask = 0xffff0000,
211 .pvr_value = 0x003c0000,
212 .cpu_name = "PPC970FX",
213 #ifdef CONFIG_PPC32
214 .cpu_features = CPU_FTRS_970_32,
215 #else
216 .cpu_features = CPU_FTRS_PPC970,
217 #endif
218 .cpu_user_features = COMMON_USER_POWER4 |
219 PPC_FEATURE_HAS_ALTIVEC_COMP,
220 .icache_bsize = 128,
221 .dcache_bsize = 128,
222 .num_pmcs = 8,
223 .cpu_setup = __setup_cpu_ppc970,
224 #ifdef CONFIG_OPROFILE
225 .oprofile_cpu_type = "ppc64/970",
226 .oprofile_model = &op_model_power4,
227 #endif
228 },
229 #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
230 #ifdef CONFIG_PPC64
231 { /* PPC970MP */
232 .pvr_mask = 0xffff0000,
233 .pvr_value = 0x00440000,
234 .cpu_name = "PPC970MP",
235 .cpu_features = CPU_FTRS_PPC970,
236 .cpu_user_features = COMMON_USER_POWER4 |
237 PPC_FEATURE_HAS_ALTIVEC_COMP,
238 .icache_bsize = 128,
239 .dcache_bsize = 128,
240 .cpu_setup = __setup_cpu_ppc970,
241 #ifdef CONFIG_OPROFILE
242 .oprofile_cpu_type = "ppc64/970",
243 .oprofile_model = &op_model_power4,
244 #endif
245 },
246 { /* Power5 GR */
247 .pvr_mask = 0xffff0000,
248 .pvr_value = 0x003a0000,
249 .cpu_name = "POWER5 (gr)",
250 .cpu_features = CPU_FTRS_POWER5,
251 .cpu_user_features = COMMON_USER_POWER5,
252 .icache_bsize = 128,
253 .dcache_bsize = 128,
254 .num_pmcs = 6,
255 .cpu_setup = __setup_cpu_power4,
256 #ifdef CONFIG_OPROFILE
257 .oprofile_cpu_type = "ppc64/power5",
258 .oprofile_model = &op_model_power4,
259 #endif
260 },
261 { /* Power5 GS */
262 .pvr_mask = 0xffff0000,
263 .pvr_value = 0x003b0000,
264 .cpu_name = "POWER5 (gs)",
265 .cpu_features = CPU_FTRS_POWER5,
266 .cpu_user_features = COMMON_USER_POWER5_PLUS,
267 .icache_bsize = 128,
268 .dcache_bsize = 128,
269 .num_pmcs = 6,
270 .cpu_setup = __setup_cpu_power4,
271 #ifdef CONFIG_OPROFILE
272 .oprofile_cpu_type = "ppc64/power5",
273 .oprofile_model = &op_model_power4,
274 #endif
275 },
276 { /* BE DD1.x */
277 .pvr_mask = 0xffff0000,
278 .pvr_value = 0x00700000,
279 .cpu_name = "Cell Broadband Engine",
280 .cpu_features = CPU_FTRS_CELL,
281 .cpu_user_features = COMMON_USER_PPC64 |
282 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP,
283 .icache_bsize = 128,
284 .dcache_bsize = 128,
285 .cpu_setup = __setup_cpu_be,
286 },
287 { /* default match */
288 .pvr_mask = 0x00000000,
289 .pvr_value = 0x00000000,
290 .cpu_name = "POWER4 (compatible)",
291 .cpu_features = CPU_FTRS_COMPATIBLE,
292 .cpu_user_features = COMMON_USER_PPC64,
293 .icache_bsize = 128,
294 .dcache_bsize = 128,
295 .num_pmcs = 6,
296 .cpu_setup = __setup_cpu_power4,
297 }
298 #endif /* CONFIG_PPC64 */
299 #ifdef CONFIG_PPC32
300 #if CLASSIC_PPC
301 { /* 601 */
302 .pvr_mask = 0xffff0000,
303 .pvr_value = 0x00010000,
304 .cpu_name = "601",
305 .cpu_features = CPU_FTRS_PPC601,
306 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
307 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
308 .icache_bsize = 32,
309 .dcache_bsize = 32,
310 },
311 { /* 603 */
312 .pvr_mask = 0xffff0000,
313 .pvr_value = 0x00030000,
314 .cpu_name = "603",
315 .cpu_features = CPU_FTRS_603,
316 .cpu_user_features = COMMON_USER,
317 .icache_bsize = 32,
318 .dcache_bsize = 32,
319 .cpu_setup = __setup_cpu_603
320 },
321 { /* 603e */
322 .pvr_mask = 0xffff0000,
323 .pvr_value = 0x00060000,
324 .cpu_name = "603e",
325 .cpu_features = CPU_FTRS_603,
326 .cpu_user_features = COMMON_USER,
327 .icache_bsize = 32,
328 .dcache_bsize = 32,
329 .cpu_setup = __setup_cpu_603
330 },
331 { /* 603ev */
332 .pvr_mask = 0xffff0000,
333 .pvr_value = 0x00070000,
334 .cpu_name = "603ev",
335 .cpu_features = CPU_FTRS_603,
336 .cpu_user_features = COMMON_USER,
337 .icache_bsize = 32,
338 .dcache_bsize = 32,
339 .cpu_setup = __setup_cpu_603
340 },
341 { /* 604 */
342 .pvr_mask = 0xffff0000,
343 .pvr_value = 0x00040000,
344 .cpu_name = "604",
345 .cpu_features = CPU_FTRS_604,
346 .cpu_user_features = COMMON_USER,
347 .icache_bsize = 32,
348 .dcache_bsize = 32,
349 .num_pmcs = 2,
350 .cpu_setup = __setup_cpu_604
351 },
352 { /* 604e */
353 .pvr_mask = 0xfffff000,
354 .pvr_value = 0x00090000,
355 .cpu_name = "604e",
356 .cpu_features = CPU_FTRS_604,
357 .cpu_user_features = COMMON_USER,
358 .icache_bsize = 32,
359 .dcache_bsize = 32,
360 .num_pmcs = 4,
361 .cpu_setup = __setup_cpu_604
362 },
363 { /* 604r */
364 .pvr_mask = 0xffff0000,
365 .pvr_value = 0x00090000,
366 .cpu_name = "604r",
367 .cpu_features = CPU_FTRS_604,
368 .cpu_user_features = COMMON_USER,
369 .icache_bsize = 32,
370 .dcache_bsize = 32,
371 .num_pmcs = 4,
372 .cpu_setup = __setup_cpu_604
373 },
374 { /* 604ev */
375 .pvr_mask = 0xffff0000,
376 .pvr_value = 0x000a0000,
377 .cpu_name = "604ev",
378 .cpu_features = CPU_FTRS_604,
379 .cpu_user_features = COMMON_USER,
380 .icache_bsize = 32,
381 .dcache_bsize = 32,
382 .num_pmcs = 4,
383 .cpu_setup = __setup_cpu_604
384 },
385 { /* 740/750 (0x4202, don't support TAU ?) */
386 .pvr_mask = 0xffffffff,
387 .pvr_value = 0x00084202,
388 .cpu_name = "740/750",
389 .cpu_features = CPU_FTRS_740_NOTAU,
390 .cpu_user_features = COMMON_USER,
391 .icache_bsize = 32,
392 .dcache_bsize = 32,
393 .num_pmcs = 4,
394 .cpu_setup = __setup_cpu_750
395 },
396 { /* 750CX (80100 and 8010x?) */
397 .pvr_mask = 0xfffffff0,
398 .pvr_value = 0x00080100,
399 .cpu_name = "750CX",
400 .cpu_features = CPU_FTRS_750,
401 .cpu_user_features = COMMON_USER,
402 .icache_bsize = 32,
403 .dcache_bsize = 32,
404 .num_pmcs = 4,
405 .cpu_setup = __setup_cpu_750cx
406 },
407 { /* 750CX (82201 and 82202) */
408 .pvr_mask = 0xfffffff0,
409 .pvr_value = 0x00082200,
410 .cpu_name = "750CX",
411 .cpu_features = CPU_FTRS_750,
412 .cpu_user_features = COMMON_USER,
413 .icache_bsize = 32,
414 .dcache_bsize = 32,
415 .num_pmcs = 4,
416 .cpu_setup = __setup_cpu_750cx
417 },
418 { /* 750CXe (82214) */
419 .pvr_mask = 0xfffffff0,
420 .pvr_value = 0x00082210,
421 .cpu_name = "750CXe",
422 .cpu_features = CPU_FTRS_750,
423 .cpu_user_features = COMMON_USER,
424 .icache_bsize = 32,
425 .dcache_bsize = 32,
426 .num_pmcs = 4,
427 .cpu_setup = __setup_cpu_750cx
428 },
429 { /* 750CXe "Gekko" (83214) */
430 .pvr_mask = 0xffffffff,
431 .pvr_value = 0x00083214,
432 .cpu_name = "750CXe",
433 .cpu_features = CPU_FTRS_750,
434 .cpu_user_features = COMMON_USER,
435 .icache_bsize = 32,
436 .dcache_bsize = 32,
437 .num_pmcs = 4,
438 .cpu_setup = __setup_cpu_750cx
439 },
440 { /* 745/755 */
441 .pvr_mask = 0xfffff000,
442 .pvr_value = 0x00083000,
443 .cpu_name = "745/755",
444 .cpu_features = CPU_FTRS_750,
445 .cpu_user_features = COMMON_USER,
446 .icache_bsize = 32,
447 .dcache_bsize = 32,
448 .num_pmcs = 4,
449 .cpu_setup = __setup_cpu_750
450 },
451 { /* 750FX rev 1.x */
452 .pvr_mask = 0xffffff00,
453 .pvr_value = 0x70000100,
454 .cpu_name = "750FX",
455 .cpu_features = CPU_FTRS_750FX1,
456 .cpu_user_features = COMMON_USER,
457 .icache_bsize = 32,
458 .dcache_bsize = 32,
459 .num_pmcs = 4,
460 .cpu_setup = __setup_cpu_750
461 },
462 { /* 750FX rev 2.0 must disable HID0[DPM] */
463 .pvr_mask = 0xffffffff,
464 .pvr_value = 0x70000200,
465 .cpu_name = "750FX",
466 .cpu_features = CPU_FTRS_750FX2,
467 .cpu_user_features = COMMON_USER,
468 .icache_bsize = 32,
469 .dcache_bsize = 32,
470 .num_pmcs = 4,
471 .cpu_setup = __setup_cpu_750
472 },
473 { /* 750FX (All revs except 2.0) */
474 .pvr_mask = 0xffff0000,
475 .pvr_value = 0x70000000,
476 .cpu_name = "750FX",
477 .cpu_features = CPU_FTRS_750FX,
478 .cpu_user_features = COMMON_USER,
479 .icache_bsize = 32,
480 .dcache_bsize = 32,
481 .num_pmcs = 4,
482 .cpu_setup = __setup_cpu_750fx
483 },
484 { /* 750GX */
485 .pvr_mask = 0xffff0000,
486 .pvr_value = 0x70020000,
487 .cpu_name = "750GX",
488 .cpu_features = CPU_FTRS_750GX,
489 .cpu_user_features = COMMON_USER,
490 .icache_bsize = 32,
491 .dcache_bsize = 32,
492 .num_pmcs = 4,
493 .cpu_setup = __setup_cpu_750fx
494 },
495 { /* 740/750 (L2CR bit need fixup for 740) */
496 .pvr_mask = 0xffff0000,
497 .pvr_value = 0x00080000,
498 .cpu_name = "740/750",
499 .cpu_features = CPU_FTRS_740,
500 .cpu_user_features = COMMON_USER,
501 .icache_bsize = 32,
502 .dcache_bsize = 32,
503 .num_pmcs = 4,
504 .cpu_setup = __setup_cpu_750
505 },
506 { /* 7400 rev 1.1 ? (no TAU) */
507 .pvr_mask = 0xffffffff,
508 .pvr_value = 0x000c1101,
509 .cpu_name = "7400 (1.1)",
510 .cpu_features = CPU_FTRS_7400_NOTAU,
511 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
512 .icache_bsize = 32,
513 .dcache_bsize = 32,
514 .num_pmcs = 4,
515 .cpu_setup = __setup_cpu_7400
516 },
517 { /* 7400 */
518 .pvr_mask = 0xffff0000,
519 .pvr_value = 0x000c0000,
520 .cpu_name = "7400",
521 .cpu_features = CPU_FTRS_7400,
522 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
523 .icache_bsize = 32,
524 .dcache_bsize = 32,
525 .num_pmcs = 4,
526 .cpu_setup = __setup_cpu_7400
527 },
528 { /* 7410 */
529 .pvr_mask = 0xffff0000,
530 .pvr_value = 0x800c0000,
531 .cpu_name = "7410",
532 .cpu_features = CPU_FTRS_7400,
533 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
534 .icache_bsize = 32,
535 .dcache_bsize = 32,
536 .num_pmcs = 4,
537 .cpu_setup = __setup_cpu_7410
538 },
539 { /* 7450 2.0 - no doze/nap */
540 .pvr_mask = 0xffffffff,
541 .pvr_value = 0x80000200,
542 .cpu_name = "7450",
543 .cpu_features = CPU_FTRS_7450_20,
544 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
545 .icache_bsize = 32,
546 .dcache_bsize = 32,
547 .num_pmcs = 6,
548 .cpu_setup = __setup_cpu_745x
549 },
550 { /* 7450 2.1 */
551 .pvr_mask = 0xffffffff,
552 .pvr_value = 0x80000201,
553 .cpu_name = "7450",
554 .cpu_features = CPU_FTRS_7450_21,
555 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
556 .icache_bsize = 32,
557 .dcache_bsize = 32,
558 .num_pmcs = 6,
559 .cpu_setup = __setup_cpu_745x
560 },
561 { /* 7450 2.3 and newer */
562 .pvr_mask = 0xffff0000,
563 .pvr_value = 0x80000000,
564 .cpu_name = "7450",
565 .cpu_features = CPU_FTRS_7450_23,
566 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
567 .icache_bsize = 32,
568 .dcache_bsize = 32,
569 .num_pmcs = 6,
570 .cpu_setup = __setup_cpu_745x
571 },
572 { /* 7455 rev 1.x */
573 .pvr_mask = 0xffffff00,
574 .pvr_value = 0x80010100,
575 .cpu_name = "7455",
576 .cpu_features = CPU_FTRS_7455_1,
577 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
578 .icache_bsize = 32,
579 .dcache_bsize = 32,
580 .num_pmcs = 6,
581 .cpu_setup = __setup_cpu_745x
582 },
583 { /* 7455 rev 2.0 */
584 .pvr_mask = 0xffffffff,
585 .pvr_value = 0x80010200,
586 .cpu_name = "7455",
587 .cpu_features = CPU_FTRS_7455_20,
588 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
589 .icache_bsize = 32,
590 .dcache_bsize = 32,
591 .num_pmcs = 6,
592 .cpu_setup = __setup_cpu_745x
593 },
594 { /* 7455 others */
595 .pvr_mask = 0xffff0000,
596 .pvr_value = 0x80010000,
597 .cpu_name = "7455",
598 .cpu_features = CPU_FTRS_7455,
599 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
600 .icache_bsize = 32,
601 .dcache_bsize = 32,
602 .num_pmcs = 6,
603 .cpu_setup = __setup_cpu_745x
604 },
605 { /* 7447/7457 Rev 1.0 */
606 .pvr_mask = 0xffffffff,
607 .pvr_value = 0x80020100,
608 .cpu_name = "7447/7457",
609 .cpu_features = CPU_FTRS_7447_10,
610 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
611 .icache_bsize = 32,
612 .dcache_bsize = 32,
613 .num_pmcs = 6,
614 .cpu_setup = __setup_cpu_745x
615 },
616 { /* 7447/7457 Rev 1.1 */
617 .pvr_mask = 0xffffffff,
618 .pvr_value = 0x80020101,
619 .cpu_name = "7447/7457",
620 .cpu_features = CPU_FTRS_7447_10,
621 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
622 .icache_bsize = 32,
623 .dcache_bsize = 32,
624 .num_pmcs = 6,
625 .cpu_setup = __setup_cpu_745x
626 },
627 { /* 7447/7457 Rev 1.2 and later */
628 .pvr_mask = 0xffff0000,
629 .pvr_value = 0x80020000,
630 .cpu_name = "7447/7457",
631 .cpu_features = CPU_FTRS_7447,
632 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
633 .icache_bsize = 32,
634 .dcache_bsize = 32,
635 .num_pmcs = 6,
636 .cpu_setup = __setup_cpu_745x
637 },
638 { /* 7447A */
639 .pvr_mask = 0xffff0000,
640 .pvr_value = 0x80030000,
641 .cpu_name = "7447A",
642 .cpu_features = CPU_FTRS_7447A,
643 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
644 .icache_bsize = 32,
645 .dcache_bsize = 32,
646 .num_pmcs = 6,
647 .cpu_setup = __setup_cpu_745x
648 },
649 { /* 7448 */
650 .pvr_mask = 0xffff0000,
651 .pvr_value = 0x80040000,
652 .cpu_name = "7448",
653 .cpu_features = CPU_FTRS_7447A,
654 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
655 .icache_bsize = 32,
656 .dcache_bsize = 32,
657 .num_pmcs = 6,
658 .cpu_setup = __setup_cpu_745x
659 },
660 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
661 .pvr_mask = 0x7fff0000,
662 .pvr_value = 0x00810000,
663 .cpu_name = "82xx",
664 .cpu_features = CPU_FTRS_82XX,
665 .cpu_user_features = COMMON_USER,
666 .icache_bsize = 32,
667 .dcache_bsize = 32,
668 .cpu_setup = __setup_cpu_603
669 },
670 { /* All G2_LE (603e core, plus some) have the same pvr */
671 .pvr_mask = 0x7fff0000,
672 .pvr_value = 0x00820000,
673 .cpu_name = "G2_LE",
674 .cpu_features = CPU_FTRS_G2_LE,
675 .cpu_user_features = COMMON_USER,
676 .icache_bsize = 32,
677 .dcache_bsize = 32,
678 .cpu_setup = __setup_cpu_603
679 },
680 { /* e300 (a 603e core, plus some) on 83xx */
681 .pvr_mask = 0x7fff0000,
682 .pvr_value = 0x00830000,
683 .cpu_name = "e300",
684 .cpu_features = CPU_FTRS_E300,
685 .cpu_user_features = COMMON_USER,
686 .icache_bsize = 32,
687 .dcache_bsize = 32,
688 .cpu_setup = __setup_cpu_603
689 },
690 { /* default match, we assume split I/D cache & TB (non-601)... */
691 .pvr_mask = 0x00000000,
692 .pvr_value = 0x00000000,
693 .cpu_name = "(generic PPC)",
694 .cpu_features = CPU_FTRS_CLASSIC32,
695 .cpu_user_features = COMMON_USER,
696 .icache_bsize = 32,
697 .dcache_bsize = 32,
698 },
699 #endif /* CLASSIC_PPC */
700 #ifdef CONFIG_8xx
701 { /* 8xx */
702 .pvr_mask = 0xffff0000,
703 .pvr_value = 0x00500000,
704 .cpu_name = "8xx",
705 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
706 * if the 8xx code is there.... */
707 .cpu_features = CPU_FTRS_8XX,
708 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
709 .icache_bsize = 16,
710 .dcache_bsize = 16,
711 },
712 #endif /* CONFIG_8xx */
713 #ifdef CONFIG_40x
714 { /* 403GC */
715 .pvr_mask = 0xffffff00,
716 .pvr_value = 0x00200200,
717 .cpu_name = "403GC",
718 .cpu_features = CPU_FTRS_40X,
719 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
720 .icache_bsize = 16,
721 .dcache_bsize = 16,
722 },
723 { /* 403GCX */
724 .pvr_mask = 0xffffff00,
725 .pvr_value = 0x00201400,
726 .cpu_name = "403GCX",
727 .cpu_features = CPU_FTRS_40X,
728 .cpu_user_features = PPC_FEATURE_32 |
729 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
730 .icache_bsize = 16,
731 .dcache_bsize = 16,
732 },
733 { /* 403G ?? */
734 .pvr_mask = 0xffff0000,
735 .pvr_value = 0x00200000,
736 .cpu_name = "403G ??",
737 .cpu_features = CPU_FTRS_40X,
738 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
739 .icache_bsize = 16,
740 .dcache_bsize = 16,
741 },
742 { /* 405GP */
743 .pvr_mask = 0xffff0000,
744 .pvr_value = 0x40110000,
745 .cpu_name = "405GP",
746 .cpu_features = CPU_FTRS_40X,
747 .cpu_user_features = PPC_FEATURE_32 |
748 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
749 .icache_bsize = 32,
750 .dcache_bsize = 32,
751 },
752 { /* STB 03xxx */
753 .pvr_mask = 0xffff0000,
754 .pvr_value = 0x40130000,
755 .cpu_name = "STB03xxx",
756 .cpu_features = CPU_FTRS_40X,
757 .cpu_user_features = PPC_FEATURE_32 |
758 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
759 .icache_bsize = 32,
760 .dcache_bsize = 32,
761 },
762 { /* STB 04xxx */
763 .pvr_mask = 0xffff0000,
764 .pvr_value = 0x41810000,
765 .cpu_name = "STB04xxx",
766 .cpu_features = CPU_FTRS_40X,
767 .cpu_user_features = PPC_FEATURE_32 |
768 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
769 .icache_bsize = 32,
770 .dcache_bsize = 32,
771 },
772 { /* NP405L */
773 .pvr_mask = 0xffff0000,
774 .pvr_value = 0x41610000,
775 .cpu_name = "NP405L",
776 .cpu_features = CPU_FTRS_40X,
777 .cpu_user_features = PPC_FEATURE_32 |
778 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
779 .icache_bsize = 32,
780 .dcache_bsize = 32,
781 },
782 { /* NP4GS3 */
783 .pvr_mask = 0xffff0000,
784 .pvr_value = 0x40B10000,
785 .cpu_name = "NP4GS3",
786 .cpu_features = CPU_FTRS_40X,
787 .cpu_user_features = PPC_FEATURE_32 |
788 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
789 .icache_bsize = 32,
790 .dcache_bsize = 32,
791 },
792 { /* NP405H */
793 .pvr_mask = 0xffff0000,
794 .pvr_value = 0x41410000,
795 .cpu_name = "NP405H",
796 .cpu_features = CPU_FTRS_40X,
797 .cpu_user_features = PPC_FEATURE_32 |
798 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
799 .icache_bsize = 32,
800 .dcache_bsize = 32,
801 },
802 { /* 405GPr */
803 .pvr_mask = 0xffff0000,
804 .pvr_value = 0x50910000,
805 .cpu_name = "405GPr",
806 .cpu_features = CPU_FTRS_40X,
807 .cpu_user_features = PPC_FEATURE_32 |
808 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
809 .icache_bsize = 32,
810 .dcache_bsize = 32,
811 },
812 { /* STBx25xx */
813 .pvr_mask = 0xffff0000,
814 .pvr_value = 0x51510000,
815 .cpu_name = "STBx25xx",
816 .cpu_features = CPU_FTRS_40X,
817 .cpu_user_features = PPC_FEATURE_32 |
818 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
819 .icache_bsize = 32,
820 .dcache_bsize = 32,
821 },
822 { /* 405LP */
823 .pvr_mask = 0xffff0000,
824 .pvr_value = 0x41F10000,
825 .cpu_name = "405LP",
826 .cpu_features = CPU_FTRS_40X,
827 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
828 .icache_bsize = 32,
829 .dcache_bsize = 32,
830 },
831 { /* Xilinx Virtex-II Pro */
832 .pvr_mask = 0xffff0000,
833 .pvr_value = 0x20010000,
834 .cpu_name = "Virtex-II Pro",
835 .cpu_features = CPU_FTRS_40X,
836 .cpu_user_features = PPC_FEATURE_32 |
837 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
838 .icache_bsize = 32,
839 .dcache_bsize = 32,
840 },
841 { /* 405EP */
842 .pvr_mask = 0xffff0000,
843 .pvr_value = 0x51210000,
844 .cpu_name = "405EP",
845 .cpu_features = CPU_FTRS_40X,
846 .cpu_user_features = PPC_FEATURE_32 |
847 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
848 .icache_bsize = 32,
849 .dcache_bsize = 32,
850 },
851
852 #endif /* CONFIG_40x */
853 #ifdef CONFIG_44x
854 {
855 .pvr_mask = 0xf0000fff,
856 .pvr_value = 0x40000850,
857 .cpu_name = "440EP Rev. A",
858 .cpu_features = CPU_FTRS_44X,
859 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
860 .icache_bsize = 32,
861 .dcache_bsize = 32,
862 },
863 {
864 .pvr_mask = 0xf0000fff,
865 .pvr_value = 0x400008d3,
866 .cpu_name = "440EP Rev. B",
867 .cpu_features = CPU_FTRS_44X,
868 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
869 .icache_bsize = 32,
870 .dcache_bsize = 32,
871 },
872 { /* 440GP Rev. B */
873 .pvr_mask = 0xf0000fff,
874 .pvr_value = 0x40000440,
875 .cpu_name = "440GP Rev. B",
876 .cpu_features = CPU_FTRS_44X,
877 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
878 .icache_bsize = 32,
879 .dcache_bsize = 32,
880 },
881 { /* 440GP Rev. C */
882 .pvr_mask = 0xf0000fff,
883 .pvr_value = 0x40000481,
884 .cpu_name = "440GP Rev. C",
885 .cpu_features = CPU_FTRS_44X,
886 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
887 .icache_bsize = 32,
888 .dcache_bsize = 32,
889 },
890 { /* 440GX Rev. A */
891 .pvr_mask = 0xf0000fff,
892 .pvr_value = 0x50000850,
893 .cpu_name = "440GX Rev. A",
894 .cpu_features = CPU_FTRS_44X,
895 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
896 .icache_bsize = 32,
897 .dcache_bsize = 32,
898 },
899 { /* 440GX Rev. B */
900 .pvr_mask = 0xf0000fff,
901 .pvr_value = 0x50000851,
902 .cpu_name = "440GX Rev. B",
903 .cpu_features = CPU_FTRS_44X,
904 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
905 .icache_bsize = 32,
906 .dcache_bsize = 32,
907 },
908 { /* 440GX Rev. C */
909 .pvr_mask = 0xf0000fff,
910 .pvr_value = 0x50000892,
911 .cpu_name = "440GX Rev. C",
912 .cpu_features = CPU_FTRS_44X,
913 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
914 .icache_bsize = 32,
915 .dcache_bsize = 32,
916 },
917 { /* 440GX Rev. F */
918 .pvr_mask = 0xf0000fff,
919 .pvr_value = 0x50000894,
920 .cpu_name = "440GX Rev. F",
921 .cpu_features = CPU_FTRS_44X,
922 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
923 .icache_bsize = 32,
924 .dcache_bsize = 32,
925 },
926 { /* 440SP Rev. A */
927 .pvr_mask = 0xff000fff,
928 .pvr_value = 0x53000891,
929 .cpu_name = "440SP Rev. A",
930 .cpu_features = CPU_FTRS_44X,
931 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
932 .icache_bsize = 32,
933 .dcache_bsize = 32,
934 },
935 { /* 440SPe Rev. A */
936 .pvr_mask = 0xff000fff,
937 .pvr_value = 0x53000890,
938 .cpu_name = "440SPe Rev. A",
939 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
940 CPU_FTR_USE_TB,
941 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
942 .icache_bsize = 32,
943 .dcache_bsize = 32,
944 },
945 #endif /* CONFIG_44x */
946 #ifdef CONFIG_FSL_BOOKE
947 { /* e200z5 */
948 .pvr_mask = 0xfff00000,
949 .pvr_value = 0x81000000,
950 .cpu_name = "e200z5",
951 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
952 .cpu_features = CPU_FTRS_E200,
953 .cpu_user_features = PPC_FEATURE_32 |
954 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
955 PPC_FEATURE_UNIFIED_CACHE,
956 .dcache_bsize = 32,
957 },
958 { /* e200z6 */
959 .pvr_mask = 0xfff00000,
960 .pvr_value = 0x81100000,
961 .cpu_name = "e200z6",
962 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
963 .cpu_features = CPU_FTRS_E200,
964 .cpu_user_features = PPC_FEATURE_32 |
965 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
966 PPC_FEATURE_HAS_EFP_SINGLE |
967 PPC_FEATURE_UNIFIED_CACHE,
968 .dcache_bsize = 32,
969 },
970 { /* e500 */
971 .pvr_mask = 0xffff0000,
972 .pvr_value = 0x80200000,
973 .cpu_name = "e500",
974 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
975 .cpu_features = CPU_FTRS_E500,
976 .cpu_user_features = PPC_FEATURE_32 |
977 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
978 PPC_FEATURE_HAS_EFP_SINGLE,
979 .icache_bsize = 32,
980 .dcache_bsize = 32,
981 .num_pmcs = 4,
982 },
983 { /* e500v2 */
984 .pvr_mask = 0xffff0000,
985 .pvr_value = 0x80210000,
986 .cpu_name = "e500v2",
987 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
988 .cpu_features = CPU_FTRS_E500_2,
989 .cpu_user_features = PPC_FEATURE_32 |
990 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
991 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
992 .icache_bsize = 32,
993 .dcache_bsize = 32,
994 .num_pmcs = 4,
995 },
996 #endif
997 #if !CLASSIC_PPC
998 { /* default match */
999 .pvr_mask = 0x00000000,
1000 .pvr_value = 0x00000000,
1001 .cpu_name = "(generic PPC)",
1002 .cpu_features = CPU_FTRS_GENERIC_32,
1003 .cpu_user_features = PPC_FEATURE_32,
1004 .icache_bsize = 32,
1005 .dcache_bsize = 32,
1006 }
1007 #endif /* !CLASSIC_PPC */
1008 #endif /* CONFIG_PPC32 */
1009 };
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