2 * oprofile/op_model_e500.c
4 * Freescale Book-E oprofile support, based on ppc64 oprofile support
5 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
7 * Copyright (c) 2004 Freescale Semiconductor, Inc
10 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/oprofile.h>
19 #include <linux/init.h>
20 #include <linux/smp.h>
21 #include <asm/ptrace.h>
22 #include <asm/system.h>
23 #include <asm/processor.h>
24 #include <asm/cputable.h>
25 #include <asm/reg_booke.h>
28 #include <asm/oprofile_impl.h>
30 static unsigned long reset_value
[OP_MAX_COUNTER
];
32 static int num_counters
;
33 static int oprofile_running
;
35 static inline unsigned int ctr_read(unsigned int i
)
39 return mfpmr(PMRN_PMC0
);
41 return mfpmr(PMRN_PMC1
);
43 return mfpmr(PMRN_PMC2
);
45 return mfpmr(PMRN_PMC3
);
51 static inline void ctr_write(unsigned int i
, unsigned int val
)
55 mtpmr(PMRN_PMC0
, val
);
58 mtpmr(PMRN_PMC1
, val
);
61 mtpmr(PMRN_PMC2
, val
);
64 mtpmr(PMRN_PMC3
, val
);
72 static void fsl_booke_reg_setup(struct op_counter_config
*ctr
,
73 struct op_system_config
*sys
,
78 num_counters
= num_ctrs
;
80 /* freeze all counters */
83 /* Our counters count up, and "count" refers to
84 * how much before the next interrupt, and we interrupt
85 * on overflow. So we calculate the starting value
86 * which will give us "count" until overflow.
87 * Then we set the events on the enabled counters */
88 for (i
= 0; i
< num_counters
; ++i
) {
89 reset_value
[i
] = 0x80000000UL
- ctr
[i
].count
;
93 set_pmc_event(i
, ctr
[i
].event
);
95 set_pmc_user_kernel(i
, ctr
[i
].user
, ctr
[i
].kernel
);
99 static void fsl_booke_start(struct op_counter_config
*ctr
)
103 mtmsr(mfmsr() | MSR_PMM
);
105 for (i
= 0; i
< num_counters
; ++i
) {
106 if (ctr
[i
].enabled
) {
107 ctr_write(i
, reset_value
[i
]);
108 /* Set Each enabled counterd to only
109 * count when the Mark bit is not set */
110 set_pmc_marked(i
, 1, 0);
115 /* Set the ctr to be stopped */
120 /* Clear the freeze bit, and enable the interrupt.
121 * The counters won't actually start until the rfi clears
125 oprofile_running
= 1;
127 pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
131 static void fsl_booke_stop(void)
133 /* freeze counters */
136 oprofile_running
= 0;
138 pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
145 static void fsl_booke_handle_interrupt(struct pt_regs
*regs
,
146 struct op_counter_config
*ctr
)
153 /* set the PMM bit (see comment below) */
154 mtmsr(mfmsr() | MSR_PMM
);
157 is_kernel
= (pc
>= KERNELBASE
);
159 for (i
= 0; i
< num_counters
; ++i
) {
162 if (oprofile_running
&& ctr
[i
].enabled
) {
163 oprofile_add_pc(pc
, is_kernel
, i
);
164 ctr_write(i
, reset_value
[i
]);
171 /* The freeze bit was set by the interrupt. */
172 /* Clear the freeze bit, and reenable the interrupt.
173 * The counters won't actually start until the rfi clears
178 struct op_powerpc_model op_model_fsl_booke
= {
179 .reg_setup
= fsl_booke_reg_setup
,
180 .start
= fsl_booke_start
,
181 .stop
= fsl_booke_stop
,
182 .handle_interrupt
= fsl_booke_handle_interrupt
,