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[PATCH] w1: new family structure.
[linux-2.6/verdex.git] / drivers / scsi / qla2xxx / qla_def.h
blob83a32e403e29424cef85ffffe5e15a478038206d
1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
6 * (www.qlogic.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 **
18 ******************************************************************************/
19
20 #ifndef __QLA_DEF_H
21 #define __QLA_DEF_H
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/dmapool.h>
33 #include <linux/mempool.h>
34 #include <linux/spinlock.h>
35 #include <linux/completion.h>
36 #include <asm/semaphore.h>
37
38 #include <scsi/scsi.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_device.h>
41 #include <scsi/scsi_cmnd.h>
42
43 /* XXX(hch): move to pci_ids.h */
44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
45 #define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
46 #endif
47
48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
49 #define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
50 #endif
51
52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
53 #define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
54 #endif
55
56 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
57 #define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
58 #endif
59
60 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
61 #define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
62 #endif
63
64 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
65 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
66 #else
67 #define IS_QLA2100(ha) 0
68 #endif
69
70 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
71 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
72 #else
73 #define IS_QLA2200(ha) 0
74 #endif
75
76 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
77 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
78 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
79 #else
80 #define IS_QLA2300(ha) 0
81 #define IS_QLA2312(ha) 0
82 #endif
83
84 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
85 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
86 #else
87 #define IS_QLA2322(ha) 0
88 #endif
89
90 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
91 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
92 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
93 #else
94 #define IS_QLA6312(ha) 0
95 #define IS_QLA6322(ha) 0
96 #endif
97
98 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
99 IS_QLA6312(ha) || IS_QLA6322(ha))
100
101 /*
102 * Only non-ISP2[12]00 have extended addressing support in the firmware.
103 */
104 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
105
106 /*
107 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
108 * but that's fine as we don't look at the last 24 ones for
109 * ISP2100 HBAs.
110 */
111 #define MAILBOX_REGISTER_COUNT_2100 8
112 #define MAILBOX_REGISTER_COUNT 32
113
114 #define QLA2200A_RISC_ROM_VER 4
115 #define FPM_2300 6
116 #define FPM_2310 7
117
118 #include "qla_settings.h"
119
120 /*
121 * Data bit definitions
122 */
123 #define BIT_0 0x1
124 #define BIT_1 0x2
125 #define BIT_2 0x4
126 #define BIT_3 0x8
127 #define BIT_4 0x10
128 #define BIT_5 0x20
129 #define BIT_6 0x40
130 #define BIT_7 0x80
131 #define BIT_8 0x100
132 #define BIT_9 0x200
133 #define BIT_10 0x400
134 #define BIT_11 0x800
135 #define BIT_12 0x1000
136 #define BIT_13 0x2000
137 #define BIT_14 0x4000
138 #define BIT_15 0x8000
139 #define BIT_16 0x10000
140 #define BIT_17 0x20000
141 #define BIT_18 0x40000
142 #define BIT_19 0x80000
143 #define BIT_20 0x100000
144 #define BIT_21 0x200000
145 #define BIT_22 0x400000
146 #define BIT_23 0x800000
147 #define BIT_24 0x1000000
148 #define BIT_25 0x2000000
149 #define BIT_26 0x4000000
150 #define BIT_27 0x8000000
151 #define BIT_28 0x10000000
152 #define BIT_29 0x20000000
153 #define BIT_30 0x40000000
154 #define BIT_31 0x80000000
155
156 #define LSB(x) ((uint8_t)(x))
157 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
158
159 #define LSW(x) ((uint16_t)(x))
160 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
161
162 #define LSD(x) ((uint32_t)((uint64_t)(x)))
163 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
164
165
166 /*
167 * I/O register
168 */
169
170 #define RD_REG_BYTE(addr) readb(addr)
171 #define RD_REG_WORD(addr) readw(addr)
172 #define RD_REG_DWORD(addr) readl(addr)
173 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
174 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
175 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
176 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
177 #define WRT_REG_WORD(addr, data) writew(data,addr)
178 #define WRT_REG_DWORD(addr, data) writel(data,addr)
179
180 /*
181 * Fibre Channel device definitions.
182 */
183 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
184 #define MAX_FIBRE_DEVICES 512
185 #define MAX_FIBRE_LUNS 256
186 #define MAX_RSCN_COUNT 32
187 #define MAX_HOST_COUNT 16
188
189 /*
190 * Host adapter default definitions.
191 */
192 #define MAX_BUSES 1 /* We only have one bus today */
193 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
194 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
195 #define MAX_TARGETS MAX_FIBRE_DEVICES
196 #define MIN_LUNS 8
197 #define MAX_LUNS MAX_FIBRE_LUNS
198 #define MAX_CMDS_PER_LUN 255
199
200 /*
201 * Fibre Channel device definitions.
202 */
203 #define SNS_LAST_LOOP_ID_2100 0xfe
204 #define SNS_LAST_LOOP_ID_2300 0x7ff
205
206 #define LAST_LOCAL_LOOP_ID 0x7d
207 #define SNS_FL_PORT 0x7e
208 #define FABRIC_CONTROLLER 0x7f
209 #define SIMPLE_NAME_SERVER 0x80
210 #define SNS_FIRST_LOOP_ID 0x81
211 #define MANAGEMENT_SERVER 0xfe
212 #define BROADCAST 0xff
213
214 #define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
215 x < SNS_FIRST_LOOP_ID) || \
216 x == MANAGEMENT_SERVER || \
217 x == BROADCAST)
218
219 /*
220 * Timeout timer counts in seconds
221 */
222 #define PORT_RETRY_TIME 1
223 #define LOOP_DOWN_TIMEOUT 60
224 #define LOOP_DOWN_TIME 255 /* 240 */
225 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
226
227 /* Maximum outstanding commands in ISP queues (1-65535) */
228 #define MAX_OUTSTANDING_COMMANDS 1024
229
230 /* ISP request and response entry counts (37-65535) */
231 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
232 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
233 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
234 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
235 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
236
237 /*
238 * SCSI Request Block
239 */
240 typedef struct srb {
241 struct list_head list;
242
243 struct scsi_qla_host *ha; /* HA the SP is queued on */
244 struct fc_port *fcport;
245
246 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
247
248 struct timer_list timer; /* Command timer */
249 atomic_t ref_count; /* Reference count for this structure */
250 uint16_t flags;
251
252 /* Request state */
253 uint16_t state;
254
255 /* Single transfer DMA context */
256 dma_addr_t dma_handle;
257
258 uint32_t request_sense_length;
259 uint8_t *request_sense_ptr;
260
261 /* SRB magic number */
262 uint16_t magic;
263 #define SRB_MAGIC 0x10CB
264 } srb_t;
265
266 /*
267 * SRB flag definitions
268 */
269 #define SRB_TIMEOUT BIT_0 /* Command timed out */
270 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
271 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
272 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
273
274 #define SRB_ABORTED BIT_4 /* Command aborted command already */
275 #define SRB_RETRY BIT_5 /* Command needs retrying */
276 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
277 #define SRB_FAILOVER BIT_7 /* Command in failover state */
278
279 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
280 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
281 #define SRB_IOCTL BIT_10 /* IOCTL command. */
282 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
283
284 /*
285 * SRB state definitions
286 */
287 #define SRB_FREE_STATE 0 /* returned back */
288 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
289 #define SRB_ACTIVE_STATE 2 /* in Active Array */
290 #define SRB_DONE_STATE 3 /* queued in Done Queue */
291 #define SRB_RETRY_STATE 4 /* in Retry Queue */
292 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
293 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
294 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
295 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
296 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
297
298
299 /*
300 * ISP I/O Register Set structure definitions.
301 */
302 typedef volatile struct {
303 volatile uint16_t flash_address; /* Flash BIOS address */
304 volatile uint16_t flash_data; /* Flash BIOS data */
305 uint16_t unused_1[1]; /* Gap */
306 volatile uint16_t ctrl_status; /* Control/Status */
307 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
308 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
309 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
310
311 volatile uint16_t ictrl; /* Interrupt control */
312 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
313 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
314
315 volatile uint16_t istatus; /* Interrupt status */
316 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
317
318 volatile uint16_t semaphore; /* Semaphore */
319 volatile uint16_t nvram; /* NVRAM register. */
320 #define NVR_DESELECT 0
321 #define NVR_BUSY BIT_15
322 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
323 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
324 #define NVR_DATA_IN BIT_3
325 #define NVR_DATA_OUT BIT_2
326 #define NVR_SELECT BIT_1
327 #define NVR_CLOCK BIT_0
328
329 union {
330 struct {
331 volatile uint16_t mailbox0;
332 volatile uint16_t mailbox1;
333 volatile uint16_t mailbox2;
334 volatile uint16_t mailbox3;
335 volatile uint16_t mailbox4;
336 volatile uint16_t mailbox5;
337 volatile uint16_t mailbox6;
338 volatile uint16_t mailbox7;
339 uint16_t unused_2[59]; /* Gap */
340 } __attribute__((packed)) isp2100;
341 struct {
342 /* Request Queue */
343 volatile uint16_t req_q_in; /* In-Pointer */
344 volatile uint16_t req_q_out; /* Out-Pointer */
345 /* Response Queue */
346 volatile uint16_t rsp_q_in; /* In-Pointer */
347 volatile uint16_t rsp_q_out; /* Out-Pointer */
348
349 /* RISC to Host Status */
350 volatile uint32_t host_status;
351 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
352 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
353
354 /* Host to Host Semaphore */
355 volatile uint16_t host_semaphore;
356 uint16_t unused_3[17]; /* Gap */
357 volatile uint16_t mailbox0;
358 volatile uint16_t mailbox1;
359 volatile uint16_t mailbox2;
360 volatile uint16_t mailbox3;
361 volatile uint16_t mailbox4;
362 volatile uint16_t mailbox5;
363 volatile uint16_t mailbox6;
364 volatile uint16_t mailbox7;
365 volatile uint16_t mailbox8;
366 volatile uint16_t mailbox9;
367 volatile uint16_t mailbox10;
368 volatile uint16_t mailbox11;
369 volatile uint16_t mailbox12;
370 volatile uint16_t mailbox13;
371 volatile uint16_t mailbox14;
372 volatile uint16_t mailbox15;
373 volatile uint16_t mailbox16;
374 volatile uint16_t mailbox17;
375 volatile uint16_t mailbox18;
376 volatile uint16_t mailbox19;
377 volatile uint16_t mailbox20;
378 volatile uint16_t mailbox21;
379 volatile uint16_t mailbox22;
380 volatile uint16_t mailbox23;
381 volatile uint16_t mailbox24;
382 volatile uint16_t mailbox25;
383 volatile uint16_t mailbox26;
384 volatile uint16_t mailbox27;
385 volatile uint16_t mailbox28;
386 volatile uint16_t mailbox29;
387 volatile uint16_t mailbox30;
388 volatile uint16_t mailbox31;
389 volatile uint16_t fb_cmd;
390 uint16_t unused_4[10]; /* Gap */
391 } __attribute__((packed)) isp2300;
392 } u;
393
394 volatile uint16_t fpm_diag_config;
395 uint16_t unused_5[0x6]; /* Gap */
396 volatile uint16_t pcr; /* Processor Control Register. */
397 uint16_t unused_6[0x5]; /* Gap */
398 volatile uint16_t mctr; /* Memory Configuration and Timing. */
399 uint16_t unused_7[0x3]; /* Gap */
400 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
401 uint16_t unused_8[0x3]; /* Gap */
402 volatile uint16_t hccr; /* Host command & control register. */
403 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
404 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
405 /* HCCR commands */
406 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
407 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
408 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
409 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
410 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
411 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
412 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
413 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
414
415 uint16_t unused_9[5]; /* Gap */
416 volatile uint16_t gpiod; /* GPIO Data register. */
417 volatile uint16_t gpioe; /* GPIO Enable register. */
418 #define GPIO_LED_MASK 0x00C0
419 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
420 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
421 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
422 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
423
424 union {
425 struct {
426 uint16_t unused_10[8]; /* Gap */
427 volatile uint16_t mailbox8;
428 volatile uint16_t mailbox9;
429 volatile uint16_t mailbox10;
430 volatile uint16_t mailbox11;
431 volatile uint16_t mailbox12;
432 volatile uint16_t mailbox13;
433 volatile uint16_t mailbox14;
434 volatile uint16_t mailbox15;
435 volatile uint16_t mailbox16;
436 volatile uint16_t mailbox17;
437 volatile uint16_t mailbox18;
438 volatile uint16_t mailbox19;
439 volatile uint16_t mailbox20;
440 volatile uint16_t mailbox21;
441 volatile uint16_t mailbox22;
442 volatile uint16_t mailbox23; /* Also probe reg. */
443 } __attribute__((packed)) isp2200;
444 } u_end;
445 } device_reg_t;
446
447 #define ISP_REQ_Q_IN(ha, reg) \
448 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
449 &(reg)->u.isp2100.mailbox4 : \
450 &(reg)->u.isp2300.req_q_in)
451 #define ISP_REQ_Q_OUT(ha, reg) \
452 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
453 &(reg)->u.isp2100.mailbox4 : \
454 &(reg)->u.isp2300.req_q_out)
455 #define ISP_RSP_Q_IN(ha, reg) \
456 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
457 &(reg)->u.isp2100.mailbox5 : \
458 &(reg)->u.isp2300.rsp_q_in)
459 #define ISP_RSP_Q_OUT(ha, reg) \
460 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
461 &(reg)->u.isp2100.mailbox5 : \
462 &(reg)->u.isp2300.rsp_q_out)
463
464 #define MAILBOX_REG(ha, reg, num) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 (num < 8 ? \
467 &(reg)->u.isp2100.mailbox0 + (num) : \
468 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
469 &(reg)->u.isp2300.mailbox0 + (num))
470 #define RD_MAILBOX_REG(ha, reg, num) \
471 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
472 #define WRT_MAILBOX_REG(ha, reg, num, data) \
473 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
474
475 #define FB_CMD_REG(ha, reg) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 &(reg)->fb_cmd_2100 : \
478 &(reg)->u.isp2300.fb_cmd)
479 #define RD_FB_CMD_REG(ha, reg) \
480 RD_REG_WORD(FB_CMD_REG(ha, reg))
481 #define WRT_FB_CMD_REG(ha, reg, data) \
482 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
483
484 typedef struct {
485 uint32_t out_mb; /* outbound from driver */
486 uint32_t in_mb; /* Incoming from RISC */
487 uint16_t mb[MAILBOX_REGISTER_COUNT];
488 long buf_size;
489 void *bufp;
490 uint32_t tov;
491 uint8_t flags;
492 #define MBX_DMA_IN BIT_0
493 #define MBX_DMA_OUT BIT_1
494 #define IOCTL_CMD BIT_2
495 } mbx_cmd_t;
496
497 #define MBX_TOV_SECONDS 30
498
499 /*
500 * ISP product identification definitions in mailboxes after reset.
501 */
502 #define PROD_ID_1 0x4953
503 #define PROD_ID_2 0x0000
504 #define PROD_ID_2a 0x5020
505 #define PROD_ID_3 0x2020
506
507 /*
508 * ISP mailbox Self-Test status codes
509 */
510 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
511 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
512 #define MBS_BUSY 4 /* Busy. */
513
514 /*
515 * ISP mailbox command complete status codes
516 */
517 #define MBS_COMMAND_COMPLETE 0x4000
518 #define MBS_INVALID_COMMAND 0x4001
519 #define MBS_HOST_INTERFACE_ERROR 0x4002
520 #define MBS_TEST_FAILED 0x4003
521 #define MBS_COMMAND_ERROR 0x4005
522 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
523 #define MBS_PORT_ID_USED 0x4007
524 #define MBS_LOOP_ID_USED 0x4008
525 #define MBS_ALL_IDS_IN_USE 0x4009
526 #define MBS_NOT_LOGGED_IN 0x400A
527
528 /*
529 * ISP mailbox asynchronous event status codes
530 */
531 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
532 #define MBA_RESET 0x8001 /* Reset Detected. */
533 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
534 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
535 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
536 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
537 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
538 /* occurred. */
539 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
540 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
541 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
542 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
543 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
544 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
545 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
546 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
547 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
548 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
549 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
550 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
551 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
552 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
553 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
554 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
555 /* used. */
556 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
557 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
558 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
559 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
560 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
561 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
562 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
563 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
564 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
565 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
566 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
567 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
568 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
569
570 /*
571 * Firmware options 1, 2, 3.
572 */
573 #define FO1_AE_ON_LIPF8 BIT_0
574 #define FO1_AE_ALL_LIP_RESET BIT_1
575 #define FO1_CTIO_RETRY BIT_3
576 #define FO1_DISABLE_LIP_F7_SW BIT_4
577 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
578 #define FO1_DISABLE_GPIO6_7 BIT_6
579 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
580 #define FO1_SET_EMPHASIS_SWING BIT_8
581 #define FO1_AE_AUTO_BYPASS BIT_9
582 #define FO1_ENABLE_PURE_IOCB BIT_10
583 #define FO1_AE_PLOGI_RJT BIT_11
584 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
585 #define FO1_AE_QUEUE_FULL BIT_13
586
587 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
588 #define FO2_REV_LOOPBACK BIT_1
589
590 #define FO3_ENABLE_EMERG_IOCB BIT_0
591 #define FO3_AE_RND_ERROR BIT_1
592
593 /*
594 * ISP mailbox commands
595 */
596 #define MBC_LOAD_RAM 1 /* Load RAM. */
597 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
598 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
599 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
600 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
601 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
602 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
603 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
604 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
605 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
606 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
607 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
608 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
609 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
610 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
611 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
612 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
613 #define MBC_RESET 0x18 /* Reset. */
614 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
615 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
616 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
617 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
618 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
619 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
620 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
621 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
622 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
623 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
624 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
625 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
626 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
627 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
628 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
629 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
630 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
631 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
632 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
633 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
634 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
635 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
636 /* Initialization Procedure */
637 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
638 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
639 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
640 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
641 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
642 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
643 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
644 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
645 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
646 #define MBC_LIP_RESET 0x6c /* LIP reset. */
647 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
648 /* commandd. */
649 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
650 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
651 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
652 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
653 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
654 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
655 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
656 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
657 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
658 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
659 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
660
661 /* Firmware return data sizes */
662 #define FCAL_MAP_SIZE 128
663
664 /* Mailbox bit definitions for out_mb and in_mb */
665 #define MBX_31 BIT_31
666 #define MBX_30 BIT_30
667 #define MBX_29 BIT_29
668 #define MBX_28 BIT_28
669 #define MBX_27 BIT_27
670 #define MBX_26 BIT_26
671 #define MBX_25 BIT_25
672 #define MBX_24 BIT_24
673 #define MBX_23 BIT_23
674 #define MBX_22 BIT_22
675 #define MBX_21 BIT_21
676 #define MBX_20 BIT_20
677 #define MBX_19 BIT_19
678 #define MBX_18 BIT_18
679 #define MBX_17 BIT_17
680 #define MBX_16 BIT_16
681 #define MBX_15 BIT_15
682 #define MBX_14 BIT_14
683 #define MBX_13 BIT_13
684 #define MBX_12 BIT_12
685 #define MBX_11 BIT_11
686 #define MBX_10 BIT_10
687 #define MBX_9 BIT_9
688 #define MBX_8 BIT_8
689 #define MBX_7 BIT_7
690 #define MBX_6 BIT_6
691 #define MBX_5 BIT_5
692 #define MBX_4 BIT_4
693 #define MBX_3 BIT_3
694 #define MBX_2 BIT_2
695 #define MBX_1 BIT_1
696 #define MBX_0 BIT_0
697
698 /*
699 * Firmware state codes from get firmware state mailbox command
700 */
701 #define FSTATE_CONFIG_WAIT 0
702 #define FSTATE_WAIT_AL_PA 1
703 #define FSTATE_WAIT_LOGIN 2
704 #define FSTATE_READY 3
705 #define FSTATE_LOSS_OF_SYNC 4
706 #define FSTATE_ERROR 5
707 #define FSTATE_REINIT 6
708 #define FSTATE_NON_PART 7
709
710 #define FSTATE_CONFIG_CORRECT 0
711 #define FSTATE_P2P_RCV_LIP 1
712 #define FSTATE_P2P_CHOOSE_LOOP 2
713 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
714 #define FSTATE_FATAL_ERROR 4
715 #define FSTATE_LOOP_BACK_CONN 5
716
717 /*
718 * Port Database structure definition
719 * Little endian except where noted.
720 */
721 #define PORT_DATABASE_SIZE 128 /* bytes */
722 typedef struct {
723 uint8_t options;
724 uint8_t control;
725 uint8_t master_state;
726 uint8_t slave_state;
727 uint8_t reserved[2];
728 uint8_t hard_address;
729 uint8_t reserved_1;
730 uint8_t port_id[4];
731 uint8_t node_name[WWN_SIZE];
732 uint8_t port_name[WWN_SIZE];
733 uint16_t execution_throttle;
734 uint16_t execution_count;
735 uint8_t reset_count;
736 uint8_t reserved_2;
737 uint16_t resource_allocation;
738 uint16_t current_allocation;
739 uint16_t queue_head;
740 uint16_t queue_tail;
741 uint16_t transmit_execution_list_next;
742 uint16_t transmit_execution_list_previous;
743 uint16_t common_features;
744 uint16_t total_concurrent_sequences;
745 uint16_t RO_by_information_category;
746 uint8_t recipient;
747 uint8_t initiator;
748 uint16_t receive_data_size;
749 uint16_t concurrent_sequences;
750 uint16_t open_sequences_per_exchange;
751 uint16_t lun_abort_flags;
752 uint16_t lun_stop_flags;
753 uint16_t stop_queue_head;
754 uint16_t stop_queue_tail;
755 uint16_t port_retry_timer;
756 uint16_t next_sequence_id;
757 uint16_t frame_count;
758 uint16_t PRLI_payload_length;
759 uint8_t prli_svc_param_word_0[2]; /* Big endian */
760 /* Bits 15-0 of word 0 */
761 uint8_t prli_svc_param_word_3[2]; /* Big endian */
762 /* Bits 15-0 of word 3 */
763 uint16_t loop_id;
764 uint16_t extended_lun_info_list_pointer;
765 uint16_t extended_lun_stop_list_pointer;
766 } port_database_t;
767
768 /*
769 * Port database slave/master states
770 */
771 #define PD_STATE_DISCOVERY 0
772 #define PD_STATE_WAIT_DISCOVERY_ACK 1
773 #define PD_STATE_PORT_LOGIN 2
774 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
775 #define PD_STATE_PROCESS_LOGIN 4
776 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
777 #define PD_STATE_PORT_LOGGED_IN 6
778 #define PD_STATE_PORT_UNAVAILABLE 7
779 #define PD_STATE_PROCESS_LOGOUT 8
780 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
781 #define PD_STATE_PORT_LOGOUT 10
782 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
783
784
785 /*
786 * ISP Initialization Control Block.
787 * Little endian except where noted.
788 */
789 #define ICB_VERSION 1
790 typedef struct {
791 uint8_t version;
792 uint8_t reserved_1;
793
794 /*
795 * LSB BIT 0 = Enable Hard Loop Id
796 * LSB BIT 1 = Enable Fairness
797 * LSB BIT 2 = Enable Full-Duplex
798 * LSB BIT 3 = Enable Fast Posting
799 * LSB BIT 4 = Enable Target Mode
800 * LSB BIT 5 = Disable Initiator Mode
801 * LSB BIT 6 = Enable ADISC
802 * LSB BIT 7 = Enable Target Inquiry Data
803 *
804 * MSB BIT 0 = Enable PDBC Notify
805 * MSB BIT 1 = Non Participating LIP
806 * MSB BIT 2 = Descending Loop ID Search
807 * MSB BIT 3 = Acquire Loop ID in LIPA
808 * MSB BIT 4 = Stop PortQ on Full Status
809 * MSB BIT 5 = Full Login after LIP
810 * MSB BIT 6 = Node Name Option
811 * MSB BIT 7 = Ext IFWCB enable bit
812 */
813 uint8_t firmware_options[2];
814
815 uint16_t frame_payload_size;
816 uint16_t max_iocb_allocation;
817 uint16_t execution_throttle;
818 uint8_t retry_count;
819 uint8_t retry_delay; /* unused */
820 uint8_t port_name[WWN_SIZE]; /* Big endian. */
821 uint16_t hard_address;
822 uint8_t inquiry_data;
823 uint8_t login_timeout;
824 uint8_t node_name[WWN_SIZE]; /* Big endian. */
825
826 uint16_t request_q_outpointer;
827 uint16_t response_q_inpointer;
828 uint16_t request_q_length;
829 uint16_t response_q_length;
830 uint32_t request_q_address[2];
831 uint32_t response_q_address[2];
832
833 uint16_t lun_enables;
834 uint8_t command_resource_count;
835 uint8_t immediate_notify_resource_count;
836 uint16_t timeout;
837 uint8_t reserved_2[2];
838
839 /*
840 * LSB BIT 0 = Timer Operation mode bit 0
841 * LSB BIT 1 = Timer Operation mode bit 1
842 * LSB BIT 2 = Timer Operation mode bit 2
843 * LSB BIT 3 = Timer Operation mode bit 3
844 * LSB BIT 4 = Init Config Mode bit 0
845 * LSB BIT 5 = Init Config Mode bit 1
846 * LSB BIT 6 = Init Config Mode bit 2
847 * LSB BIT 7 = Enable Non part on LIHA failure
848 *
849 * MSB BIT 0 = Enable class 2
850 * MSB BIT 1 = Enable ACK0
851 * MSB BIT 2 =
852 * MSB BIT 3 =
853 * MSB BIT 4 = FC Tape Enable
854 * MSB BIT 5 = Enable FC Confirm
855 * MSB BIT 6 = Enable command queuing in target mode
856 * MSB BIT 7 = No Logo On Link Down
857 */
858 uint8_t add_firmware_options[2];
859
860 uint8_t response_accumulation_timer;
861 uint8_t interrupt_delay_timer;
862
863 /*
864 * LSB BIT 0 = Enable Read xfr_rdy
865 * LSB BIT 1 = Soft ID only
866 * LSB BIT 2 =
867 * LSB BIT 3 =
868 * LSB BIT 4 = FCP RSP Payload [0]
869 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
870 * LSB BIT 6 = Enable Out-of-Order frame handling
871 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
872 *
873 * MSB BIT 0 = Sbus enable - 2300
874 * MSB BIT 1 =
875 * MSB BIT 2 =
876 * MSB BIT 3 =
877 * MSB BIT 4 =
878 * MSB BIT 5 = enable 50 ohm termination
879 * MSB BIT 6 = Data Rate (2300 only)
880 * MSB BIT 7 = Data Rate (2300 only)
881 */
882 uint8_t special_options[2];
883
884 uint8_t reserved_3[26];
885 } init_cb_t;
886
887 /*
888 * Get Link Status mailbox command return buffer.
889 */
890 typedef struct {
891 uint32_t link_fail_cnt;
892 uint32_t loss_sync_cnt;
893 uint32_t loss_sig_cnt;
894 uint32_t prim_seq_err_cnt;
895 uint32_t inval_xmit_word_cnt;
896 uint32_t inval_crc_cnt;
897 } link_stat_t;
898
899 /*
900 * NVRAM Command values.
901 */
902 #define NV_START_BIT BIT_2
903 #define NV_WRITE_OP (BIT_26+BIT_24)
904 #define NV_READ_OP (BIT_26+BIT_25)
905 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
906 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
907 #define NV_DELAY_COUNT 10
908
909 /*
910 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
911 */
912 typedef struct {
913 /*
914 * NVRAM header
915 */
916 uint8_t id[4];
917 uint8_t nvram_version;
918 uint8_t reserved_0;
919
920 /*
921 * NVRAM RISC parameter block
922 */
923 uint8_t parameter_block_version;
924 uint8_t reserved_1;
925
926 /*
927 * LSB BIT 0 = Enable Hard Loop Id
928 * LSB BIT 1 = Enable Fairness
929 * LSB BIT 2 = Enable Full-Duplex
930 * LSB BIT 3 = Enable Fast Posting
931 * LSB BIT 4 = Enable Target Mode
932 * LSB BIT 5 = Disable Initiator Mode
933 * LSB BIT 6 = Enable ADISC
934 * LSB BIT 7 = Enable Target Inquiry Data
935 *
936 * MSB BIT 0 = Enable PDBC Notify
937 * MSB BIT 1 = Non Participating LIP
938 * MSB BIT 2 = Descending Loop ID Search
939 * MSB BIT 3 = Acquire Loop ID in LIPA
940 * MSB BIT 4 = Stop PortQ on Full Status
941 * MSB BIT 5 = Full Login after LIP
942 * MSB BIT 6 = Node Name Option
943 * MSB BIT 7 = Ext IFWCB enable bit
944 */
945 uint8_t firmware_options[2];
946
947 uint16_t frame_payload_size;
948 uint16_t max_iocb_allocation;
949 uint16_t execution_throttle;
950 uint8_t retry_count;
951 uint8_t retry_delay; /* unused */
952 uint8_t port_name[WWN_SIZE]; /* Big endian. */
953 uint16_t hard_address;
954 uint8_t inquiry_data;
955 uint8_t login_timeout;
956 uint8_t node_name[WWN_SIZE]; /* Big endian. */
957
958 /*
959 * LSB BIT 0 = Timer Operation mode bit 0
960 * LSB BIT 1 = Timer Operation mode bit 1
961 * LSB BIT 2 = Timer Operation mode bit 2
962 * LSB BIT 3 = Timer Operation mode bit 3
963 * LSB BIT 4 = Init Config Mode bit 0
964 * LSB BIT 5 = Init Config Mode bit 1
965 * LSB BIT 6 = Init Config Mode bit 2
966 * LSB BIT 7 = Enable Non part on LIHA failure
967 *
968 * MSB BIT 0 = Enable class 2
969 * MSB BIT 1 = Enable ACK0
970 * MSB BIT 2 =
971 * MSB BIT 3 =
972 * MSB BIT 4 = FC Tape Enable
973 * MSB BIT 5 = Enable FC Confirm
974 * MSB BIT 6 = Enable command queuing in target mode
975 * MSB BIT 7 = No Logo On Link Down
976 */
977 uint8_t add_firmware_options[2];
978
979 uint8_t response_accumulation_timer;
980 uint8_t interrupt_delay_timer;
981
982 /*
983 * LSB BIT 0 = Enable Read xfr_rdy
984 * LSB BIT 1 = Soft ID only
985 * LSB BIT 2 =
986 * LSB BIT 3 =
987 * LSB BIT 4 = FCP RSP Payload [0]
988 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
989 * LSB BIT 6 = Enable Out-of-Order frame handling
990 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
991 *
992 * MSB BIT 0 = Sbus enable - 2300
993 * MSB BIT 1 =
994 * MSB BIT 2 =
995 * MSB BIT 3 =
996 * MSB BIT 4 =
997 * MSB BIT 5 = enable 50 ohm termination
998 * MSB BIT 6 = Data Rate (2300 only)
999 * MSB BIT 7 = Data Rate (2300 only)
1000 */
1001 uint8_t special_options[2];
1002
1003 /* Reserved for expanded RISC parameter block */
1004 uint8_t reserved_2[22];
1005
1006 /*
1007 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1008 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1009 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1010 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1011 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1012 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1013 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1014 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1015 *
1016 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1017 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1018 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1019 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1020 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1021 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1022 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1023 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1024 *
1025 * LSB BIT 0 = Output Swing 1G bit 0
1026 * LSB BIT 1 = Output Swing 1G bit 1
1027 * LSB BIT 2 = Output Swing 1G bit 2
1028 * LSB BIT 3 = Output Emphasis 1G bit 0
1029 * LSB BIT 4 = Output Emphasis 1G bit 1
1030 * LSB BIT 5 = Output Swing 2G bit 0
1031 * LSB BIT 6 = Output Swing 2G bit 1
1032 * LSB BIT 7 = Output Swing 2G bit 2
1033 *
1034 * MSB BIT 0 = Output Emphasis 2G bit 0
1035 * MSB BIT 1 = Output Emphasis 2G bit 1
1036 * MSB BIT 2 = Output Enable
1037 * MSB BIT 3 =
1038 * MSB BIT 4 =
1039 * MSB BIT 5 =
1040 * MSB BIT 6 =
1041 * MSB BIT 7 =
1042 */
1043 uint8_t seriallink_options[4];
1044
1045 /*
1046 * NVRAM host parameter block
1047 *
1048 * LSB BIT 0 = Enable spinup delay
1049 * LSB BIT 1 = Disable BIOS
1050 * LSB BIT 2 = Enable Memory Map BIOS
1051 * LSB BIT 3 = Enable Selectable Boot
1052 * LSB BIT 4 = Disable RISC code load
1053 * LSB BIT 5 = Set cache line size 1
1054 * LSB BIT 6 = PCI Parity Disable
1055 * LSB BIT 7 = Enable extended logging
1056 *
1057 * MSB BIT 0 = Enable 64bit addressing
1058 * MSB BIT 1 = Enable lip reset
1059 * MSB BIT 2 = Enable lip full login
1060 * MSB BIT 3 = Enable target reset
1061 * MSB BIT 4 = Enable database storage
1062 * MSB BIT 5 = Enable cache flush read
1063 * MSB BIT 6 = Enable database load
1064 * MSB BIT 7 = Enable alternate WWN
1065 */
1066 uint8_t host_p[2];
1067
1068 uint8_t boot_node_name[WWN_SIZE];
1069 uint8_t boot_lun_number;
1070 uint8_t reset_delay;
1071 uint8_t port_down_retry_count;
1072 uint8_t boot_id_number;
1073 uint16_t max_luns_per_target;
1074 uint8_t fcode_boot_port_name[WWN_SIZE];
1075 uint8_t alternate_port_name[WWN_SIZE];
1076 uint8_t alternate_node_name[WWN_SIZE];
1077
1078 /*
1079 * BIT 0 = Selective Login
1080 * BIT 1 = Alt-Boot Enable
1081 * BIT 2 =
1082 * BIT 3 = Boot Order List
1083 * BIT 4 =
1084 * BIT 5 = Selective LUN
1085 * BIT 6 =
1086 * BIT 7 = unused
1087 */
1088 uint8_t efi_parameters;
1089
1090 uint8_t link_down_timeout;
1091
1092 uint8_t adapter_id_0[4];
1093 uint8_t adapter_id_1[4];
1094 uint8_t adapter_id_2[4];
1095 uint8_t adapter_id_3[4];
1096
1097 uint8_t alt1_boot_node_name[WWN_SIZE];
1098 uint16_t alt1_boot_lun_number;
1099 uint8_t alt2_boot_node_name[WWN_SIZE];
1100 uint16_t alt2_boot_lun_number;
1101 uint8_t alt3_boot_node_name[WWN_SIZE];
1102 uint16_t alt3_boot_lun_number;
1103 uint8_t alt4_boot_node_name[WWN_SIZE];
1104 uint16_t alt4_boot_lun_number;
1105 uint8_t alt5_boot_node_name[WWN_SIZE];
1106 uint16_t alt5_boot_lun_number;
1107 uint8_t alt6_boot_node_name[WWN_SIZE];
1108 uint16_t alt6_boot_lun_number;
1109 uint8_t alt7_boot_node_name[WWN_SIZE];
1110 uint16_t alt7_boot_lun_number;
1111
1112 uint8_t reserved_3[2];
1113
1114 /* Offset 200-215 : Model Number */
1115 uint8_t model_number[16];
1116
1117 /* OEM related items */
1118 uint8_t oem_specific[16];
1119
1120 /*
1121 * NVRAM Adapter Features offset 232-239
1122 *
1123 * LSB BIT 0 = External GBIC
1124 * LSB BIT 1 = Risc RAM parity
1125 * LSB BIT 2 = Buffer Plus Module
1126 * LSB BIT 3 = Multi Chip Adapter
1127 * LSB BIT 4 = Internal connector
1128 * LSB BIT 5 =
1129 * LSB BIT 6 =
1130 * LSB BIT 7 =
1131 *
1132 * MSB BIT 0 =
1133 * MSB BIT 1 =
1134 * MSB BIT 2 =
1135 * MSB BIT 3 =
1136 * MSB BIT 4 =
1137 * MSB BIT 5 =
1138 * MSB BIT 6 =
1139 * MSB BIT 7 =
1140 */
1141 uint8_t adapter_features[2];
1142
1143 uint8_t reserved_4[16];
1144
1145 /* Subsystem vendor ID for ISP2200 */
1146 uint16_t subsystem_vendor_id_2200;
1147
1148 /* Subsystem device ID for ISP2200 */
1149 uint16_t subsystem_device_id_2200;
1150
1151 uint8_t reserved_5;
1152 uint8_t checksum;
1153 } nvram_t;
1154
1155 /*
1156 * ISP queue - response queue entry definition.
1157 */
1158 typedef struct {
1159 uint8_t data[60];
1160 uint32_t signature;
1161 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1162 } response_t;
1163
1164 typedef union {
1165 uint16_t extended;
1166 struct {
1167 uint8_t reserved;
1168 uint8_t standard;
1169 } id;
1170 } target_id_t;
1171
1172 #define SET_TARGET_ID(ha, to, from) \
1173 do { \
1174 if (HAS_EXTENDED_IDS(ha)) \
1175 to.extended = cpu_to_le16(from); \
1176 else \
1177 to.id.standard = (uint8_t)from; \
1178 } while (0)
1179
1180 /*
1181 * ISP queue - command entry structure definition.
1182 */
1183 #define COMMAND_TYPE 0x11 /* Command entry */
1184 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1185 typedef struct {
1186 uint8_t entry_type; /* Entry type. */
1187 uint8_t entry_count; /* Entry count. */
1188 uint8_t sys_define; /* System defined. */
1189 uint8_t entry_status; /* Entry Status. */
1190 uint32_t handle; /* System handle. */
1191 target_id_t target; /* SCSI ID */
1192 uint16_t lun; /* SCSI LUN */
1193 uint16_t control_flags; /* Control flags. */
1194 #define CF_WRITE BIT_6
1195 #define CF_READ BIT_5
1196 #define CF_SIMPLE_TAG BIT_3
1197 #define CF_ORDERED_TAG BIT_2
1198 #define CF_HEAD_TAG BIT_1
1199 uint16_t reserved_1;
1200 uint16_t timeout; /* Command timeout. */
1201 uint16_t dseg_count; /* Data segment count. */
1202 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1203 uint32_t byte_count; /* Total byte count. */
1204 uint32_t dseg_0_address; /* Data segment 0 address. */
1205 uint32_t dseg_0_length; /* Data segment 0 length. */
1206 uint32_t dseg_1_address; /* Data segment 1 address. */
1207 uint32_t dseg_1_length; /* Data segment 1 length. */
1208 uint32_t dseg_2_address; /* Data segment 2 address. */
1209 uint32_t dseg_2_length; /* Data segment 2 length. */
1210 } cmd_entry_t;
1211
1212 /*
1213 * ISP queue - 64-Bit addressing, command entry structure definition.
1214 */
1215 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1216 typedef struct {
1217 uint8_t entry_type; /* Entry type. */
1218 uint8_t entry_count; /* Entry count. */
1219 uint8_t sys_define; /* System defined. */
1220 uint8_t entry_status; /* Entry Status. */
1221 uint32_t handle; /* System handle. */
1222 target_id_t target; /* SCSI ID */
1223 uint16_t lun; /* SCSI LUN */
1224 uint16_t control_flags; /* Control flags. */
1225 uint16_t reserved_1;
1226 uint16_t timeout; /* Command timeout. */
1227 uint16_t dseg_count; /* Data segment count. */
1228 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1229 uint32_t byte_count; /* Total byte count. */
1230 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1231 uint32_t dseg_0_length; /* Data segment 0 length. */
1232 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1233 uint32_t dseg_1_length; /* Data segment 1 length. */
1234 } cmd_a64_entry_t, request_t;
1235
1236 /*
1237 * ISP queue - continuation entry structure definition.
1238 */
1239 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1240 typedef struct {
1241 uint8_t entry_type; /* Entry type. */
1242 uint8_t entry_count; /* Entry count. */
1243 uint8_t sys_define; /* System defined. */
1244 uint8_t entry_status; /* Entry Status. */
1245 uint32_t reserved;
1246 uint32_t dseg_0_address; /* Data segment 0 address. */
1247 uint32_t dseg_0_length; /* Data segment 0 length. */
1248 uint32_t dseg_1_address; /* Data segment 1 address. */
1249 uint32_t dseg_1_length; /* Data segment 1 length. */
1250 uint32_t dseg_2_address; /* Data segment 2 address. */
1251 uint32_t dseg_2_length; /* Data segment 2 length. */
1252 uint32_t dseg_3_address; /* Data segment 3 address. */
1253 uint32_t dseg_3_length; /* Data segment 3 length. */
1254 uint32_t dseg_4_address; /* Data segment 4 address. */
1255 uint32_t dseg_4_length; /* Data segment 4 length. */
1256 uint32_t dseg_5_address; /* Data segment 5 address. */
1257 uint32_t dseg_5_length; /* Data segment 5 length. */
1258 uint32_t dseg_6_address; /* Data segment 6 address. */
1259 uint32_t dseg_6_length; /* Data segment 6 length. */
1260 } cont_entry_t;
1261
1262 /*
1263 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1264 */
1265 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1266 typedef struct {
1267 uint8_t entry_type; /* Entry type. */
1268 uint8_t entry_count; /* Entry count. */
1269 uint8_t sys_define; /* System defined. */
1270 uint8_t entry_status; /* Entry Status. */
1271 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1272 uint32_t dseg_0_length; /* Data segment 0 length. */
1273 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1274 uint32_t dseg_1_length; /* Data segment 1 length. */
1275 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1276 uint32_t dseg_2_length; /* Data segment 2 length. */
1277 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1278 uint32_t dseg_3_length; /* Data segment 3 length. */
1279 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1280 uint32_t dseg_4_length; /* Data segment 4 length. */
1281 } cont_a64_entry_t;
1282
1283 /*
1284 * ISP queue - status entry structure definition.
1285 */
1286 #define STATUS_TYPE 0x03 /* Status entry. */
1287 typedef struct {
1288 uint8_t entry_type; /* Entry type. */
1289 uint8_t entry_count; /* Entry count. */
1290 uint8_t sys_define; /* System defined. */
1291 uint8_t entry_status; /* Entry Status. */
1292 uint32_t handle; /* System handle. */
1293 uint16_t scsi_status; /* SCSI status. */
1294 uint16_t comp_status; /* Completion status. */
1295 uint16_t state_flags; /* State flags. */
1296 uint16_t status_flags; /* Status flags. */
1297 uint16_t rsp_info_len; /* Response Info Length. */
1298 uint16_t req_sense_length; /* Request sense data length. */
1299 uint32_t residual_length; /* Residual transfer length. */
1300 uint8_t rsp_info[8]; /* FCP response information. */
1301 uint8_t req_sense_data[32]; /* Request sense data. */
1302 } sts_entry_t;
1303
1304 /*
1305 * Status entry entry status
1306 */
1307 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1308 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1309 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1310 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1311 #define RF_BUSY BIT_1 /* Busy */
1312
1313 /*
1314 * Status entry SCSI status bit definitions.
1315 */
1316 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1317 #define SS_RESIDUAL_UNDER BIT_11
1318 #define SS_RESIDUAL_OVER BIT_10
1319 #define SS_SENSE_LEN_VALID BIT_9
1320 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1321
1322 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1323 #define SS_BUSY_CONDITION BIT_3
1324 #define SS_CONDITION_MET BIT_2
1325 #define SS_CHECK_CONDITION BIT_1
1326
1327 /*
1328 * Status entry completion status
1329 */
1330 #define CS_COMPLETE 0x0 /* No errors */
1331 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1332 #define CS_DMA 0x2 /* A DMA direction error. */
1333 #define CS_TRANSPORT 0x3 /* Transport error. */
1334 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1335 #define CS_ABORTED 0x5 /* System aborted command. */
1336 #define CS_TIMEOUT 0x6 /* Timeout error. */
1337 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1338
1339 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1340 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1341 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1342 /* (selection timeout) */
1343 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1344 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1345 #define CS_PORT_BUSY 0x2B /* Port Busy */
1346 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1347 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1348 #define CS_UNKNOWN 0x81 /* Driver defined */
1349 #define CS_RETRY 0x82 /* Driver defined */
1350 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1351
1352 /*
1353 * Status entry status flags
1354 */
1355 #define SF_ABTS_TERMINATED BIT_10
1356 #define SF_LOGOUT_SENT BIT_13
1357
1358 /*
1359 * ISP queue - status continuation entry structure definition.
1360 */
1361 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1362 typedef struct {
1363 uint8_t entry_type; /* Entry type. */
1364 uint8_t entry_count; /* Entry count. */
1365 uint8_t sys_define; /* System defined. */
1366 uint8_t entry_status; /* Entry Status. */
1367 uint8_t data[60]; /* data */
1368 } sts_cont_entry_t;
1369
1370 /*
1371 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1372 * structure definition.
1373 */
1374 #define STATUS_TYPE_21 0x21 /* Status entry. */
1375 typedef struct {
1376 uint8_t entry_type; /* Entry type. */
1377 uint8_t entry_count; /* Entry count. */
1378 uint8_t handle_count; /* Handle count. */
1379 uint8_t entry_status; /* Entry Status. */
1380 uint32_t handle[15]; /* System handles. */
1381 } sts21_entry_t;
1382
1383 /*
1384 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1385 * structure definition.
1386 */
1387 #define STATUS_TYPE_22 0x22 /* Status entry. */
1388 typedef struct {
1389 uint8_t entry_type; /* Entry type. */
1390 uint8_t entry_count; /* Entry count. */
1391 uint8_t handle_count; /* Handle count. */
1392 uint8_t entry_status; /* Entry Status. */
1393 uint16_t handle[30]; /* System handles. */
1394 } sts22_entry_t;
1395
1396 /*
1397 * ISP queue - marker entry structure definition.
1398 */
1399 #define MARKER_TYPE 0x04 /* Marker entry. */
1400 typedef struct {
1401 uint8_t entry_type; /* Entry type. */
1402 uint8_t entry_count; /* Entry count. */
1403 uint8_t handle_count; /* Handle count. */
1404 uint8_t entry_status; /* Entry Status. */
1405 uint32_t sys_define_2; /* System defined. */
1406 target_id_t target; /* SCSI ID */
1407 uint8_t modifier; /* Modifier (7-0). */
1408 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1409 #define MK_SYNC_ID 1 /* Synchronize ID */
1410 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1411 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1412 /* clear port changed, */
1413 /* use sequence number. */
1414 uint8_t reserved_1;
1415 uint16_t sequence_number; /* Sequence number of event */
1416 uint16_t lun; /* SCSI LUN */
1417 uint8_t reserved_2[48];
1418 } mrk_entry_t;
1419
1420 /*
1421 * ISP queue - Management Server entry structure definition.
1422 */
1423 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1424 typedef struct {
1425 uint8_t entry_type; /* Entry type. */
1426 uint8_t entry_count; /* Entry count. */
1427 uint8_t handle_count; /* Handle count. */
1428 uint8_t entry_status; /* Entry Status. */
1429 uint32_t handle1; /* System handle. */
1430 target_id_t loop_id;
1431 uint16_t status;
1432 uint16_t control_flags; /* Control flags. */
1433 uint16_t reserved2;
1434 uint16_t timeout;
1435 uint16_t cmd_dsd_count;
1436 uint16_t total_dsd_count;
1437 uint8_t type;
1438 uint8_t r_ctl;
1439 uint16_t rx_id;
1440 uint16_t reserved3;
1441 uint32_t handle2;
1442 uint32_t rsp_bytecount;
1443 uint32_t req_bytecount;
1444 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1445 uint32_t dseg_req_length; /* Data segment 0 length. */
1446 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1447 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1448 } ms_iocb_entry_t;
1449
1450
1451 /*
1452 * ISP queue - Mailbox Command entry structure definition.
1453 */
1454 #define MBX_IOCB_TYPE 0x39
1455 struct mbx_entry {
1456 uint8_t entry_type;
1457 uint8_t entry_count;
1458 uint8_t sys_define1;
1459 /* Use sys_define1 for source type */
1460 #define SOURCE_SCSI 0x00
1461 #define SOURCE_IP 0x01
1462 #define SOURCE_VI 0x02
1463 #define SOURCE_SCTP 0x03
1464 #define SOURCE_MP 0x04
1465 #define SOURCE_MPIOCTL 0x05
1466 #define SOURCE_ASYNC_IOCB 0x07
1467
1468 uint8_t entry_status;
1469
1470 uint32_t handle;
1471 target_id_t loop_id;
1472
1473 uint16_t status;
1474 uint16_t state_flags;
1475 uint16_t status_flags;
1476
1477 uint32_t sys_define2[2];
1478
1479 uint16_t mb0;
1480 uint16_t mb1;
1481 uint16_t mb2;
1482 uint16_t mb3;
1483 uint16_t mb6;
1484 uint16_t mb7;
1485 uint16_t mb9;
1486 uint16_t mb10;
1487 uint32_t reserved_2[2];
1488 uint8_t node_name[WWN_SIZE];
1489 uint8_t port_name[WWN_SIZE];
1490 };
1491
1492 /*
1493 * ISP request and response queue entry sizes
1494 */
1495 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1496 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1497
1498
1499 /*
1500 * 24 bit port ID type definition.
1501 */
1502 typedef union {
1503 uint32_t b24 : 24;
1504
1505 struct {
1506 uint8_t d_id[3];
1507 uint8_t rsvd_1;
1508 } r;
1509
1510 struct {
1511 uint8_t al_pa;
1512 uint8_t area;
1513 uint8_t domain;
1514 uint8_t rsvd_1;
1515 } b;
1516 } port_id_t;
1517 #define INVALID_PORT_ID 0xFFFFFF
1518
1519 /*
1520 * Switch info gathering structure.
1521 */
1522 typedef struct {
1523 port_id_t d_id;
1524 uint8_t node_name[WWN_SIZE];
1525 uint8_t port_name[WWN_SIZE];
1526 uint32_t type;
1527 #define SW_TYPE_IP BIT_1
1528 #define SW_TYPE_SCSI BIT_0
1529 } sw_info_t;
1530
1531 /*
1532 * Inquiry command structure.
1533 */
1534 #define INQ_DATA_SIZE 36
1535
1536 /*
1537 * Inquiry mailbox IOCB packet definition.
1538 */
1539 typedef struct {
1540 union {
1541 cmd_a64_entry_t cmd;
1542 sts_entry_t rsp;
1543 } p;
1544 uint8_t inq[INQ_DATA_SIZE];
1545 } inq_cmd_rsp_t;
1546
1547 /*
1548 * Report LUN command structure.
1549 */
1550 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1551
1552 typedef struct {
1553 uint32_t len;
1554 uint32_t rsrv;
1555 } rpt_hdr_t;
1556
1557 typedef struct {
1558 struct {
1559 uint8_t b : 6;
1560 uint8_t address_method : 2;
1561 } msb;
1562 uint8_t lsb;
1563 uint8_t unused[6];
1564 } rpt_lun_t;
1565
1566 typedef struct {
1567 rpt_hdr_t hdr;
1568 rpt_lun_t lst[MAX_LUNS];
1569 } rpt_lun_lst_t;
1570
1571 /*
1572 * Report Lun mailbox IOCB packet definition.
1573 */
1574 typedef struct {
1575 union {
1576 cmd_a64_entry_t cmd;
1577 sts_entry_t rsp;
1578 } p;
1579 rpt_lun_lst_t list;
1580 } rpt_lun_cmd_rsp_t;
1581
1582 /*
1583 * Fibre channel port type.
1584 */
1585 typedef enum {
1586 FCT_UNKNOWN,
1587 FCT_RSCN,
1588 FCT_SWITCH,
1589 FCT_BROADCAST,
1590 FCT_INITIATOR,
1591 FCT_TARGET
1592 } fc_port_type_t;
1593
1594 /*
1595 * Fibre channel port structure.
1596 */
1597 typedef struct fc_port {
1598 struct list_head list;
1599 struct scsi_qla_host *ha;
1600 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1601
1602 uint8_t node_name[WWN_SIZE];
1603 uint8_t port_name[WWN_SIZE];
1604 port_id_t d_id;
1605 uint16_t loop_id;
1606 uint16_t old_loop_id;
1607
1608 fc_port_type_t port_type;
1609
1610 atomic_t state;
1611 uint32_t flags;
1612
1613 unsigned int os_target_id;
1614
1615 uint16_t iodesc_idx_sent;
1616
1617 int port_login_retry_count;
1618 int login_retry;
1619 atomic_t port_down_timer;
1620
1621 uint8_t device_type;
1622 uint8_t unused;
1623
1624 uint8_t mp_byte; /* multi-path byte (not used) */
1625 uint8_t cur_path; /* current path id */
1626
1627 struct fc_rport *rport;
1628 } fc_port_t;
1629
1630 /*
1631 * Fibre channel port/lun states.
1632 */
1633 #define FCS_UNCONFIGURED 1
1634 #define FCS_DEVICE_DEAD 2
1635 #define FCS_DEVICE_LOST 3
1636 #define FCS_ONLINE 4
1637 #define FCS_NOT_SUPPORTED 5
1638 #define FCS_FAILOVER 6
1639 #define FCS_FAILOVER_FAILED 7
1640
1641 /*
1642 * FC port flags.
1643 */
1644 #define FCF_FABRIC_DEVICE BIT_0
1645 #define FCF_LOGIN_NEEDED BIT_1
1646 #define FCF_FO_MASKED BIT_2
1647 #define FCF_FAILOVER_NEEDED BIT_3
1648 #define FCF_RESET_NEEDED BIT_4
1649 #define FCF_PERSISTENT_BOUND BIT_5
1650 #define FCF_TAPE_PRESENT BIT_6
1651 #define FCF_FARP_DONE BIT_7
1652 #define FCF_FARP_FAILED BIT_8
1653 #define FCF_FARP_REPLY_NEEDED BIT_9
1654 #define FCF_AUTH_REQ BIT_10
1655 #define FCF_SEND_AUTH_REQ BIT_11
1656 #define FCF_RECEIVE_AUTH_REQ BIT_12
1657 #define FCF_AUTH_SUCCESS BIT_13
1658 #define FCF_RLC_SUPPORT BIT_14
1659 #define FCF_CONFIG BIT_15 /* Needed? */
1660 #define FCF_RESCAN_NEEDED BIT_16
1661 #define FCF_XP_DEVICE BIT_17
1662 #define FCF_MSA_DEVICE BIT_18
1663 #define FCF_EVA_DEVICE BIT_19
1664 #define FCF_MSA_PORT_ACTIVE BIT_20
1665 #define FCF_FAILBACK_DISABLE BIT_21
1666 #define FCF_FAILOVER_DISABLE BIT_22
1667 #define FCF_DSXXX_DEVICE BIT_23
1668 #define FCF_AA_EVA_DEVICE BIT_24
1669
1670 /* No loop ID flag. */
1671 #define FC_NO_LOOP_ID 0x1000
1672
1673 /*
1674 * FC-CT interface
1675 *
1676 * NOTE: All structures are big-endian in form.
1677 */
1678
1679 #define CT_REJECT_RESPONSE 0x8001
1680 #define CT_ACCEPT_RESPONSE 0x8002
1681
1682 #define NS_N_PORT_TYPE 0x01
1683 #define NS_NL_PORT_TYPE 0x02
1684 #define NS_NX_PORT_TYPE 0x7F
1685
1686 #define GA_NXT_CMD 0x100
1687 #define GA_NXT_REQ_SIZE (16 + 4)
1688 #define GA_NXT_RSP_SIZE (16 + 620)
1689
1690 #define GID_PT_CMD 0x1A1
1691 #define GID_PT_REQ_SIZE (16 + 4)
1692 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1693
1694 #define GPN_ID_CMD 0x112
1695 #define GPN_ID_REQ_SIZE (16 + 4)
1696 #define GPN_ID_RSP_SIZE (16 + 8)
1697
1698 #define GNN_ID_CMD 0x113
1699 #define GNN_ID_REQ_SIZE (16 + 4)
1700 #define GNN_ID_RSP_SIZE (16 + 8)
1701
1702 #define GFT_ID_CMD 0x117
1703 #define GFT_ID_REQ_SIZE (16 + 4)
1704 #define GFT_ID_RSP_SIZE (16 + 32)
1705
1706 #define RFT_ID_CMD 0x217
1707 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1708 #define RFT_ID_RSP_SIZE 16
1709
1710 #define RFF_ID_CMD 0x21F
1711 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1712 #define RFF_ID_RSP_SIZE 16
1713
1714 #define RNN_ID_CMD 0x213
1715 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1716 #define RNN_ID_RSP_SIZE 16
1717
1718 #define RSNN_NN_CMD 0x239
1719 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1720 #define RSNN_NN_RSP_SIZE 16
1721
1722 /* CT command header -- request/response common fields */
1723 struct ct_cmd_hdr {
1724 uint8_t revision;
1725 uint8_t in_id[3];
1726 uint8_t gs_type;
1727 uint8_t gs_subtype;
1728 uint8_t options;
1729 uint8_t reserved;
1730 };
1731
1732 /* CT command request */
1733 struct ct_sns_req {
1734 struct ct_cmd_hdr header;
1735 uint16_t command;
1736 uint16_t max_rsp_size;
1737 uint8_t fragment_id;
1738 uint8_t reserved[3];
1739
1740 union {
1741 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1742 struct {
1743 uint8_t reserved;
1744 uint8_t port_id[3];
1745 } port_id;
1746
1747 struct {
1748 uint8_t port_type;
1749 uint8_t domain;
1750 uint8_t area;
1751 uint8_t reserved;
1752 } gid_pt;
1753
1754 struct {
1755 uint8_t reserved;
1756 uint8_t port_id[3];
1757 uint8_t fc4_types[32];
1758 } rft_id;
1759
1760 struct {
1761 uint8_t reserved;
1762 uint8_t port_id[3];
1763 uint16_t reserved2;
1764 uint8_t fc4_feature;
1765 uint8_t fc4_type;
1766 } rff_id;
1767
1768 struct {
1769 uint8_t reserved;
1770 uint8_t port_id[3];
1771 uint8_t node_name[8];
1772 } rnn_id;
1773
1774 struct {
1775 uint8_t node_name[8];
1776 uint8_t name_len;
1777 uint8_t sym_node_name[255];
1778 } rsnn_nn;
1779 } req;
1780 };
1781
1782 /* CT command response header */
1783 struct ct_rsp_hdr {
1784 struct ct_cmd_hdr header;
1785 uint16_t response;
1786 uint16_t residual;
1787 uint8_t fragment_id;
1788 uint8_t reason_code;
1789 uint8_t explanation_code;
1790 uint8_t vendor_unique;
1791 };
1792
1793 struct ct_sns_gid_pt_data {
1794 uint8_t control_byte;
1795 uint8_t port_id[3];
1796 };
1797
1798 struct ct_sns_rsp {
1799 struct ct_rsp_hdr header;
1800
1801 union {
1802 struct {
1803 uint8_t port_type;
1804 uint8_t port_id[3];
1805 uint8_t port_name[8];
1806 uint8_t sym_port_name_len;
1807 uint8_t sym_port_name[255];
1808 uint8_t node_name[8];
1809 uint8_t sym_node_name_len;
1810 uint8_t sym_node_name[255];
1811 uint8_t init_proc_assoc[8];
1812 uint8_t node_ip_addr[16];
1813 uint8_t class_of_service[4];
1814 uint8_t fc4_types[32];
1815 uint8_t ip_address[16];
1816 uint8_t fabric_port_name[8];
1817 uint8_t reserved;
1818 uint8_t hard_address[3];
1819 } ga_nxt;
1820
1821 struct {
1822 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1823 } gid_pt;
1824
1825 struct {
1826 uint8_t port_name[8];
1827 } gpn_id;
1828
1829 struct {
1830 uint8_t node_name[8];
1831 } gnn_id;
1832
1833 struct {
1834 uint8_t fc4_types[32];
1835 } gft_id;
1836 } rsp;
1837 };
1838
1839 struct ct_sns_pkt {
1840 union {
1841 struct ct_sns_req req;
1842 struct ct_sns_rsp rsp;
1843 } p;
1844 };
1845
1846 /*
1847 * SNS command structures -- for 2200 compatability.
1848 */
1849 #define RFT_ID_SNS_SCMD_LEN 22
1850 #define RFT_ID_SNS_CMD_SIZE 60
1851 #define RFT_ID_SNS_DATA_SIZE 16
1852
1853 #define RNN_ID_SNS_SCMD_LEN 10
1854 #define RNN_ID_SNS_CMD_SIZE 36
1855 #define RNN_ID_SNS_DATA_SIZE 16
1856
1857 #define GA_NXT_SNS_SCMD_LEN 6
1858 #define GA_NXT_SNS_CMD_SIZE 28
1859 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1860
1861 #define GID_PT_SNS_SCMD_LEN 6
1862 #define GID_PT_SNS_CMD_SIZE 28
1863 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1864
1865 #define GPN_ID_SNS_SCMD_LEN 6
1866 #define GPN_ID_SNS_CMD_SIZE 28
1867 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1868
1869 #define GNN_ID_SNS_SCMD_LEN 6
1870 #define GNN_ID_SNS_CMD_SIZE 28
1871 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1872
1873 struct sns_cmd_pkt {
1874 union {
1875 struct {
1876 uint16_t buffer_length;
1877 uint16_t reserved_1;
1878 uint32_t buffer_address[2];
1879 uint16_t subcommand_length;
1880 uint16_t reserved_2;
1881 uint16_t subcommand;
1882 uint16_t size;
1883 uint32_t reserved_3;
1884 uint8_t param[36];
1885 } cmd;
1886
1887 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1888 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1889 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1890 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1891 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1892 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1893 } p;
1894 };
1895
1896 /* IO descriptors */
1897 #define MAX_IO_DESCRIPTORS 32
1898
1899 #define ABORT_IOCB_CB 0
1900 #define ADISC_PORT_IOCB_CB 1
1901 #define LOGOUT_PORT_IOCB_CB 2
1902 #define LOGIN_PORT_IOCB_CB 3
1903 #define LAST_IOCB_CB 4
1904
1905 #define IODESC_INVALID_INDEX 0xFFFF
1906 #define IODESC_ADISC_NEEDED 0xFFFE
1907 #define IODESC_LOGIN_NEEDED 0xFFFD
1908
1909 struct io_descriptor {
1910 uint16_t used:1;
1911 uint16_t idx:11;
1912 uint16_t cb_idx:4;
1913
1914 struct timer_list timer;
1915
1916 struct scsi_qla_host *ha;
1917
1918 port_id_t d_id;
1919 fc_port_t *remote_fcport;
1920
1921 uint32_t signature;
1922 };
1923
1924 struct qla_fw_info {
1925 unsigned short addressing; /* addressing method used to load fw */
1926 #define FW_INFO_ADDR_NORMAL 0
1927 #define FW_INFO_ADDR_EXTENDED 1
1928 #define FW_INFO_ADDR_NOMORE 0xffff
1929 unsigned short *fwcode; /* pointer to FW array */
1930 unsigned short *fwlen; /* number of words in array */
1931 unsigned short *fwstart; /* start address for F/W */
1932 unsigned long *lfwstart; /* start address (long) for F/W */
1933 };
1934
1935 struct qla_board_info {
1936 char *drv_name;
1937
1938 char isp_name[8];
1939 struct qla_fw_info *fw_info;
1940 };
1941
1942 /* Return data from MBC_GET_ID_LIST call. */
1943 struct gid_list_info {
1944 uint8_t al_pa;
1945 uint8_t area;
1946 uint8_t domain;
1947 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1948 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
1949 };
1950 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1951
1952 /*
1953 * Linux Host Adapter structure
1954 */
1955 typedef struct scsi_qla_host {
1956 struct list_head list;
1957
1958 /* Commonly used flags and state information. */
1959 struct Scsi_Host *host;
1960 struct pci_dev *pdev;
1961
1962 unsigned long host_no;
1963 unsigned long instance;
1964
1965 volatile struct {
1966 uint32_t init_done :1;
1967 uint32_t online :1;
1968 uint32_t mbox_int :1;
1969 uint32_t mbox_busy :1;
1970 uint32_t rscn_queue_overflow :1;
1971 uint32_t reset_active :1;
1972
1973 uint32_t management_server_logged_in :1;
1974 uint32_t process_response_queue :1;
1975
1976 uint32_t disable_risc_code_load :1;
1977 uint32_t enable_64bit_addressing :1;
1978 uint32_t enable_lip_reset :1;
1979 uint32_t enable_lip_full_login :1;
1980 uint32_t enable_target_reset :1;
1981 uint32_t enable_led_scheme :1;
1982 } flags;
1983
1984 atomic_t loop_state;
1985 #define LOOP_TIMEOUT 1
1986 #define LOOP_DOWN 2
1987 #define LOOP_UP 3
1988 #define LOOP_UPDATE 4
1989 #define LOOP_READY 5
1990 #define LOOP_DEAD 6
1991
1992 unsigned long dpc_flags;
1993 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
1994 #define RESET_ACTIVE 1
1995 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
1996 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
1997 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
1998 #define LOOP_RESYNC_ACTIVE 5
1999 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2000 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2001 #define MAILBOX_RETRY 8
2002 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2003 #define FAILOVER_EVENT_NEEDED 10
2004 #define FAILOVER_EVENT 11
2005 #define FAILOVER_NEEDED 12
2006 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2007 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2008 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2009 #define ABORT_QUEUES_NEEDED 16
2010 #define RELOGIN_NEEDED 17
2011 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2012 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2013 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2014 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2015 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2016 #define IOCTL_ERROR_RECOVERY 23
2017 #define LOOP_RESET_NEEDED 24
2018
2019 uint32_t device_flags;
2020 #define DFLG_LOCAL_DEVICES BIT_0
2021 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2022 #define DFLG_FABRIC_DEVICES BIT_2
2023 #define SWITCH_FOUND BIT_3
2024 #define DFLG_NO_CABLE BIT_4
2025
2026 /* SRB cache. */
2027 #define SRB_MIN_REQ 128
2028 mempool_t *srb_mempool;
2029
2030 /* This spinlock is used to protect "io transactions", you must
2031 * aquire it before doing any IO to the card, eg with RD_REG*() and
2032 * WRT_REG*() for the duration of your entire commandtransaction.
2033 *
2034 * This spinlock is of lower priority than the io request lock.
2035 */
2036
2037 spinlock_t hardware_lock ____cacheline_aligned;
2038
2039 device_reg_t __iomem *iobase; /* Base I/O address */
2040 unsigned long pio_address;
2041 unsigned long pio_length;
2042 #define MIN_IOBASE_LEN 0x100
2043
2044 /* ISP ring lock, rings, and indexes */
2045 dma_addr_t request_dma; /* Physical address. */
2046 request_t *request_ring; /* Base virtual address */
2047 request_t *request_ring_ptr; /* Current address. */
2048 uint16_t req_ring_index; /* Current index. */
2049 uint16_t req_q_cnt; /* Number of available entries. */
2050 uint16_t request_q_length;
2051
2052 dma_addr_t response_dma; /* Physical address. */
2053 response_t *response_ring; /* Base virtual address */
2054 response_t *response_ring_ptr; /* Current address. */
2055 uint16_t rsp_ring_index; /* Current index. */
2056 uint16_t response_q_length;
2057
2058 uint16_t (*calc_request_entries)(uint16_t);
2059 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2060
2061 /* Outstandings ISP commands. */
2062 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2063 uint32_t current_outstanding_cmd;
2064 srb_t *status_srb; /* Status continuation entry. */
2065
2066 uint16_t revision;
2067 uint8_t ports;
2068
2069 /* ISP configuration data. */
2070 uint16_t loop_id; /* Host adapter loop id */
2071 uint16_t fb_rev;
2072
2073 port_id_t d_id; /* Host adapter port id */
2074 uint16_t max_public_loop_ids;
2075 uint16_t min_external_loopid; /* First external loop Id */
2076
2077 uint16_t link_data_rate; /* F/W operating speed */
2078
2079 uint8_t current_topology;
2080 uint8_t prev_topology;
2081 #define ISP_CFG_NL 1
2082 #define ISP_CFG_N 2
2083 #define ISP_CFG_FL 4
2084 #define ISP_CFG_F 8
2085
2086 uint8_t operating_mode; /* F/W operating mode */
2087 #define LOOP 0
2088 #define P2P 1
2089 #define LOOP_P2P 2
2090 #define P2P_LOOP 3
2091
2092 uint8_t marker_needed;
2093
2094 uint8_t interrupts_on;
2095
2096 /* HBA serial number */
2097 uint8_t serial0;
2098 uint8_t serial1;
2099 uint8_t serial2;
2100
2101 /* NVRAM configuration data */
2102 uint16_t nvram_base;
2103
2104 uint16_t loop_reset_delay;
2105 uint8_t retry_count;
2106 uint8_t login_timeout;
2107 uint16_t r_a_tov;
2108 int port_down_retry_count;
2109 uint8_t mbx_count;
2110 uint16_t last_loop_id;
2111
2112 uint32_t login_retry_count;
2113
2114 /* Fibre Channel Device List. */
2115 struct list_head fcports;
2116 struct list_head rscn_fcports;
2117
2118 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2119 uint16_t iodesc_signature;
2120
2121 /* RSCN queue. */
2122 uint32_t rscn_queue[MAX_RSCN_COUNT];
2123 uint8_t rscn_in_ptr;
2124 uint8_t rscn_out_ptr;
2125
2126 /* SNS command interfaces. */
2127 ms_iocb_entry_t *ms_iocb;
2128 dma_addr_t ms_iocb_dma;
2129 struct ct_sns_pkt *ct_sns;
2130 dma_addr_t ct_sns_dma;
2131 /* SNS command interfaces for 2200. */
2132 struct sns_cmd_pkt *sns_cmd;
2133 dma_addr_t sns_cmd_dma;
2134
2135 pid_t dpc_pid;
2136 int dpc_should_die;
2137 struct completion dpc_inited;
2138 struct completion dpc_exited;
2139 struct semaphore *dpc_wait;
2140 uint8_t dpc_active; /* DPC routine is active */
2141
2142 /* Timeout timers. */
2143 uint8_t loop_down_abort_time; /* port down timer */
2144 atomic_t loop_down_timer; /* loop down timer */
2145 uint8_t link_down_timeout; /* link down timeout */
2146
2147 uint32_t timer_active;
2148 struct timer_list timer;
2149
2150 dma_addr_t gid_list_dma;
2151 struct gid_list_info *gid_list;
2152
2153 dma_addr_t rlc_rsp_dma;
2154 rpt_lun_cmd_rsp_t *rlc_rsp;
2155
2156 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2157 #define DMA_POOL_SIZE 256
2158 struct dma_pool *s_dma_pool;
2159
2160 dma_addr_t init_cb_dma;
2161 init_cb_t *init_cb;
2162
2163 dma_addr_t iodesc_pd_dma;
2164 port_database_t *iodesc_pd;
2165
2166 /* These are used by mailbox operations. */
2167 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2168
2169 mbx_cmd_t *mcp;
2170 unsigned long mbx_cmd_flags;
2171 #define MBX_INTERRUPT 1
2172 #define MBX_INTR_WAIT 2
2173 #define MBX_UPDATE_FLASH_ACTIVE 3
2174
2175 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2176
2177 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2178 struct semaphore mbx_intr_sem; /* Used for completion notification */
2179
2180 uint32_t mbx_flags;
2181 #define MBX_IN_PROGRESS BIT_0
2182 #define MBX_BUSY BIT_1 /* Got the Access */
2183 #define MBX_SLEEPING_ON_SEM BIT_2
2184 #define MBX_POLLING_FOR_COMP BIT_3
2185 #define MBX_COMPLETED BIT_4
2186 #define MBX_TIMEDOUT BIT_5
2187 #define MBX_ACCESS_TIMEDOUT BIT_6
2188
2189 mbx_cmd_t mc;
2190
2191 /* Basic firmware related information. */
2192 struct qla_board_info *brd_info;
2193 uint16_t fw_major_version;
2194 uint16_t fw_minor_version;
2195 uint16_t fw_subminor_version;
2196 uint16_t fw_attributes;
2197 uint32_t fw_memory_size;
2198 uint32_t fw_transfer_size;
2199
2200 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2201 uint8_t fw_seriallink_options[4];
2202
2203 /* Firmware dump information. */
2204 void *fw_dump;
2205 int fw_dump_order;
2206 int fw_dump_reading;
2207 char *fw_dump_buffer;
2208 int fw_dump_buffer_len;
2209
2210 uint8_t host_str[16];
2211 uint16_t pci_attr;
2212
2213 uint16_t product_id[4];
2214
2215 uint8_t model_number[16+1];
2216 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2217 char *model_desc;
2218
2219 uint8_t node_name[WWN_SIZE];
2220 uint8_t nvram_version;
2221 uint32_t isp_abort_cnt;
2222
2223 /* Needed for BEACON */
2224 uint16_t beacon_blink_led;
2225 uint16_t beacon_green_on;
2226 } scsi_qla_host_t;
2227
2228
2229 /*
2230 * Macros to help code, maintain, etc.
2231 */
2232 #define LOOP_TRANSITION(ha) \
2233 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2234 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2235
2236 #define LOOP_NOT_READY(ha) \
2237 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2238 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2239 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2240 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2241 atomic_read(&ha->loop_state) == LOOP_DOWN)
2242
2243 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2244
2245 #define TGT_Q(ha, t) (ha->otgt[t])
2246
2247 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2248
2249 #define qla_printk(level, ha, format, arg...) \
2250 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2251
2252 /*
2253 * qla2x00 local function return status codes
2254 */
2255 #define MBS_MASK 0x3fff
2256
2257 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2258 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2259 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2260 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2261 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2262 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2263 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2264 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2265 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2266 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2267
2268 #define QLA_FUNCTION_TIMEOUT 0x100
2269 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2270 #define QLA_FUNCTION_FAILED 0x102
2271 #define QLA_MEMORY_ALLOC_FAILED 0x103
2272 #define QLA_LOCK_TIMEOUT 0x104
2273 #define QLA_ABORTED 0x105
2274 #define QLA_SUSPENDED 0x106
2275 #define QLA_BUSY 0x107
2276 #define QLA_RSCNS_HANDLED 0x108
2277
2278 /*
2279 * Stat info for all adpaters
2280 */
2281 struct _qla2x00stats {
2282 unsigned long mboxtout; /* mailbox timeouts */
2283 unsigned long mboxerr; /* mailbox errors */
2284 unsigned long ispAbort; /* ISP aborts */
2285 unsigned long debugNo;
2286 unsigned long loop_resync;
2287 unsigned long outarray_full;
2288 unsigned long retry_q_cnt;
2289 };
2290
2291 #define NVRAM_DELAY() udelay(10)
2292
2293 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2294
2295 /*
2296 * Flash support definitions
2297 */
2298 #define FLASH_IMAGE_SIZE 131072
2299
2300 #include "qla_gbl.h"
2301 #include "qla_dbg.h"
2302 #include "qla_inline.h"
2303
2304 /*
2305 * String arrays
2306 */
2307 #define LINESIZE 256
2308 #define MAXARGS 26
2309
2310 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2311 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2312 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2313 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2314 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2315 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2316
2317 #endif
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