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[PATCH] w1: new family structure.
[linux-2.6/verdex.git] / drivers / scsi / sata_vsc.c
blobc5e09dc6f3de67b3250250d7f064ff873d679bb6
1 /*
2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3 *
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 SGI
9 *
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/dma-mapping.h>
25 #include "scsi.h"
26 #include <scsi/scsi_host.h>
27 #include <linux/libata.h>
28
29 #define DRV_NAME "sata_vsc"
30 #define DRV_VERSION "1.0"
31
32 /* Interrupt register offsets (from chip base address) */
33 #define VSC_SATA_INT_STAT_OFFSET 0x00
34 #define VSC_SATA_INT_MASK_OFFSET 0x04
35
36 /* Taskfile registers offsets */
37 #define VSC_SATA_TF_CMD_OFFSET 0x00
38 #define VSC_SATA_TF_DATA_OFFSET 0x00
39 #define VSC_SATA_TF_ERROR_OFFSET 0x04
40 #define VSC_SATA_TF_FEATURE_OFFSET 0x06
41 #define VSC_SATA_TF_NSECT_OFFSET 0x08
42 #define VSC_SATA_TF_LBAL_OFFSET 0x0c
43 #define VSC_SATA_TF_LBAM_OFFSET 0x10
44 #define VSC_SATA_TF_LBAH_OFFSET 0x14
45 #define VSC_SATA_TF_DEVICE_OFFSET 0x18
46 #define VSC_SATA_TF_STATUS_OFFSET 0x1c
47 #define VSC_SATA_TF_COMMAND_OFFSET 0x1d
48 #define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
49 #define VSC_SATA_TF_CTL_OFFSET 0x29
50
51 /* DMA base */
52 #define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
53 #define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
54 #define VSC_SATA_DMA_CMD_OFFSET 0x70
55
56 /* SCRs base */
57 #define VSC_SATA_SCR_STATUS_OFFSET 0x100
58 #define VSC_SATA_SCR_ERROR_OFFSET 0x104
59 #define VSC_SATA_SCR_CONTROL_OFFSET 0x108
60
61 /* Port stride */
62 #define VSC_SATA_PORT_OFFSET 0x200
63
64
65 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
66 {
67 if (sc_reg > SCR_CONTROL)
68 return 0xffffffffU;
69 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
70 }
71
72
73 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
74 u32 val)
75 {
76 if (sc_reg > SCR_CONTROL)
77 return;
78 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
79 }
80
81
82 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
83 {
84 unsigned long mask_addr;
85 u8 mask;
86
87 mask_addr = (unsigned long) ap->host_set->mmio_base +
88 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
89 mask = readb(mask_addr);
90 if (ctl & ATA_NIEN)
91 mask |= 0x80;
92 else
93 mask &= 0x7F;
94 writeb(mask, mask_addr);
95 }
96
97
98 static void vsc_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
99 {
100 struct ata_ioports *ioaddr = &ap->ioaddr;
101 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
102
103 /*
104 * The only thing the ctl register is used for is SRST.
105 * That is not enabled or disabled via tf_load.
106 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
107 */
108 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
109 ap->last_ctl = tf->ctl;
110 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
111 }
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
114 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
115 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
116 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
117 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
118 } else if (is_addr) {
119 writew(tf->feature, ioaddr->feature_addr);
120 writew(tf->nsect, ioaddr->nsect_addr);
121 writew(tf->lbal, ioaddr->lbal_addr);
122 writew(tf->lbam, ioaddr->lbam_addr);
123 writew(tf->lbah, ioaddr->lbah_addr);
124 }
125
126 if (tf->flags & ATA_TFLAG_DEVICE)
127 writeb(tf->device, ioaddr->device_addr);
128
129 ata_wait_idle(ap);
130 }
131
132
133 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
134 {
135 struct ata_ioports *ioaddr = &ap->ioaddr;
136 u16 nsect, lbal, lbam, lbah;
137
138 nsect = tf->nsect = readw(ioaddr->nsect_addr);
139 lbal = tf->lbal = readw(ioaddr->lbal_addr);
140 lbam = tf->lbam = readw(ioaddr->lbam_addr);
141 lbah = tf->lbah = readw(ioaddr->lbah_addr);
142 tf->device = readw(ioaddr->device_addr);
143
144 if (tf->flags & ATA_TFLAG_LBA48) {
145 tf->hob_feature = readb(ioaddr->error_addr);
146 tf->hob_nsect = nsect >> 8;
147 tf->hob_lbal = lbal >> 8;
148 tf->hob_lbam = lbam >> 8;
149 tf->hob_lbah = lbah >> 8;
150 }
151 }
152
153
154 /*
155 * vsc_sata_interrupt
156 *
157 * Read the interrupt register and process for the devices that have them pending.
158 */
159 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
160 struct pt_regs *regs)
161 {
162 struct ata_host_set *host_set = dev_instance;
163 unsigned int i;
164 unsigned int handled = 0;
165 u32 int_status;
166
167 spin_lock(&host_set->lock);
168
169 int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
170
171 for (i = 0; i < host_set->n_ports; i++) {
172 if (int_status & ((u32) 0xFF << (8 * i))) {
173 struct ata_port *ap;
174
175 ap = host_set->ports[i];
176 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
177 struct ata_queued_cmd *qc;
178
179 qc = ata_qc_from_tag(ap, ap->active_tag);
180 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
181 handled += ata_host_intr(ap, qc);
182 }
183 }
184 }
185
186 spin_unlock(&host_set->lock);
187
188 return IRQ_RETVAL(handled);
189 }
190
191
192 static Scsi_Host_Template vsc_sata_sht = {
193 .module = THIS_MODULE,
194 .name = DRV_NAME,
195 .ioctl = ata_scsi_ioctl,
196 .queuecommand = ata_scsi_queuecmd,
197 .eh_strategy_handler = ata_scsi_error,
198 .can_queue = ATA_DEF_QUEUE,
199 .this_id = ATA_SHT_THIS_ID,
200 .sg_tablesize = LIBATA_MAX_PRD,
201 .max_sectors = ATA_MAX_SECTORS,
202 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
203 .emulated = ATA_SHT_EMULATED,
204 .use_clustering = ATA_SHT_USE_CLUSTERING,
205 .proc_name = DRV_NAME,
206 .dma_boundary = ATA_DMA_BOUNDARY,
207 .slave_configure = ata_scsi_slave_config,
208 .bios_param = ata_std_bios_param,
209 .ordered_flush = 1,
210 };
211
212
213 static struct ata_port_operations vsc_sata_ops = {
214 .port_disable = ata_port_disable,
215 .tf_load = vsc_sata_tf_load,
216 .tf_read = vsc_sata_tf_read,
217 .exec_command = ata_exec_command,
218 .check_status = ata_check_status,
219 .dev_select = ata_std_dev_select,
220 .phy_reset = sata_phy_reset,
221 .bmdma_setup = ata_bmdma_setup,
222 .bmdma_start = ata_bmdma_start,
223 .bmdma_stop = ata_bmdma_stop,
224 .bmdma_status = ata_bmdma_status,
225 .qc_prep = ata_qc_prep,
226 .qc_issue = ata_qc_issue_prot,
227 .eng_timeout = ata_eng_timeout,
228 .irq_handler = vsc_sata_interrupt,
229 .irq_clear = ata_bmdma_irq_clear,
230 .scr_read = vsc_sata_scr_read,
231 .scr_write = vsc_sata_scr_write,
232 .port_start = ata_port_start,
233 .port_stop = ata_port_stop,
234 .host_stop = ata_host_stop,
235 };
236
237 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
238 {
239 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
240 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
241 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
242 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
243 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
244 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
245 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
246 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
247 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
248 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
249 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
250 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
251 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
252 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
253 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
254 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
255 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
256 }
257
258
259 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
260 {
261 static int printed_version;
262 struct ata_probe_ent *probe_ent = NULL;
263 unsigned long base;
264 int pci_dev_busy = 0;
265 void *mmio_base;
266 int rc;
267
268 if (!printed_version++)
269 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
270
271 rc = pci_enable_device(pdev);
272 if (rc)
273 return rc;
274
275 /*
276 * Check if we have needed resource mapped.
277 */
278 if (pci_resource_len(pdev, 0) == 0) {
279 rc = -ENODEV;
280 goto err_out;
281 }
282
283 rc = pci_request_regions(pdev, DRV_NAME);
284 if (rc) {
285 pci_dev_busy = 1;
286 goto err_out;
287 }
288
289 /*
290 * Use 32 bit DMA mask, because 64 bit address support is poor.
291 */
292 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
293 if (rc)
294 goto err_out_regions;
295 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
296 if (rc)
297 goto err_out_regions;
298
299 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
300 if (probe_ent == NULL) {
301 rc = -ENOMEM;
302 goto err_out_regions;
303 }
304 memset(probe_ent, 0, sizeof(*probe_ent));
305 probe_ent->dev = pci_dev_to_dev(pdev);
306 INIT_LIST_HEAD(&probe_ent->node);
307
308 mmio_base = ioremap(pci_resource_start(pdev, 0),
309 pci_resource_len(pdev, 0));
310 if (mmio_base == NULL) {
311 rc = -ENOMEM;
312 goto err_out_free_ent;
313 }
314 base = (unsigned long) mmio_base;
315
316 /*
317 * Due to a bug in the chip, the default cache line size can't be used
318 */
319 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
320
321 probe_ent->sht = &vsc_sata_sht;
322 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
323 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
324 probe_ent->port_ops = &vsc_sata_ops;
325 probe_ent->n_ports = 4;
326 probe_ent->irq = pdev->irq;
327 probe_ent->irq_flags = SA_SHIRQ;
328 probe_ent->mmio_base = mmio_base;
329
330 /* We don't care much about the PIO/UDMA masks, but the core won't like us
331 * if we don't fill these
332 */
333 probe_ent->pio_mask = 0x1f;
334 probe_ent->mwdma_mask = 0x07;
335 probe_ent->udma_mask = 0x7f;
336
337 /* We have 4 ports per PCI function */
338 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
339 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
340 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
341 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
342
343 pci_set_master(pdev);
344
345 /*
346 * Config offset 0x98 is "Extended Control and Status Register 0"
347 * Default value is (1 << 28). All bits except bit 28 are reserved in
348 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
349 * If bit 28 is clear, each port has its own LED.
350 */
351 pci_write_config_dword(pdev, 0x98, 0);
352
353 /* FIXME: check ata_device_add return value */
354 ata_device_add(probe_ent);
355 kfree(probe_ent);
356
357 return 0;
358
359 err_out_free_ent:
360 kfree(probe_ent);
361 err_out_regions:
362 pci_release_regions(pdev);
363 err_out:
364 if (!pci_dev_busy)
365 pci_disable_device(pdev);
366 return rc;
367 }
368
369
370 /*
371 * 0x1725/0x7174 is the Vitesse VSC-7174
372 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
373 * compatibility is untested as of yet
374 */
375 static struct pci_device_id vsc_sata_pci_tbl[] = {
376 { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
377 { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
378 { }
379 };
380
381
382 static struct pci_driver vsc_sata_pci_driver = {
383 .name = DRV_NAME,
384 .id_table = vsc_sata_pci_tbl,
385 .probe = vsc_sata_init_one,
386 .remove = ata_pci_remove_one,
387 };
388
389
390 static int __init vsc_sata_init(void)
391 {
392 return pci_module_init(&vsc_sata_pci_driver);
393 }
394
395
396 static void __exit vsc_sata_exit(void)
397 {
398 pci_unregister_driver(&vsc_sata_pci_driver);
399 }
400
401
402 MODULE_AUTHOR("Jeremy Higdon");
403 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
404 MODULE_LICENSE("GPL");
405 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
406 MODULE_VERSION(DRV_VERSION);
407
408 module_init(vsc_sata_init);
409 module_exit(vsc_sata_exit);
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