2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <asm/sn/sn_sal.h>
13 #include <asm/sn/addrs.h>
14 #include <asm/sn/io.h>
15 #include <asm/sn/pcidev.h>
16 #include <asm/sn/pcibus_provider_defs.h>
17 #include <asm/sn/tioce_provider.h>
18 #include <asm/sn/sn2/sn_hwperf.h>
23 * WAR for SGI PV 944642. For revA TIOCE, need to use the following recipe
24 * (taken from the above PV) before and after accessing tioce internal MMR's
25 * to avoid tioce lockups.
27 * The recipe as taken from the PV:
29 * if(mmr address < 0x45000) {
30 * if(mmr address == 0 or 0x80)
31 * mmr wrt or read address 0xc0
32 * else if(mmr address == 0x148 or 0x200)
33 * mmr wrt or read address 0x28
35 * mmr wrt or read address 0x158
37 * do desired mmr access (rd or wrt)
39 * if(mmr address == 0x100)
40 * mmr wrt or read address 0x38
41 * mmr wrt or read address 0xb050
43 * do desired mmr access
45 * According to hw, we can use reads instead of writes to the above addres
47 * Note this WAR can only to be used for accessing internal MMR's in the
48 * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
49 * "Local CE Registers and Memories" and "PCI Compatible Config Space" address
50 * spaces from table 2-1 of the "CE Programmer's Reference Overview" document.
52 * All registers defined in struct tioce will meet that criteria.
56 tioce_mmr_war_pre(struct tioce_kernel
*kern
, void *mmr_addr
)
61 if (kern
->ce_common
->ce_rev
!= TIOCE_REV_A
)
64 mmr_base
= kern
->ce_common
->ce_pcibus
.bs_base
;
65 mmr_offset
= (u64
)mmr_addr
- mmr_base
;
67 if (mmr_offset
< 0x45000) {
70 if (mmr_offset
== 0 || mmr_offset
== 0x80)
71 mmr_war_offset
= 0xc0;
72 else if (mmr_offset
== 0x148 || mmr_offset
== 0x200)
73 mmr_war_offset
= 0x28;
75 mmr_war_offset
= 0x158;
77 readq_relaxed((void *)(mmr_base
+ mmr_war_offset
));
82 tioce_mmr_war_post(struct tioce_kernel
*kern
, void *mmr_addr
)
87 if (kern
->ce_common
->ce_rev
!= TIOCE_REV_A
)
90 mmr_base
= kern
->ce_common
->ce_pcibus
.bs_base
;
91 mmr_offset
= (u64
)mmr_addr
- mmr_base
;
93 if (mmr_offset
< 0x45000) {
94 if (mmr_offset
== 0x100)
95 readq_relaxed((void *)(mmr_base
+ 0x38));
96 readq_relaxed((void *)(mmr_base
+ 0xb050));
100 /* load mmr contents into a variable */
101 #define tioce_mmr_load(kern, mmrp, varp) do {\
102 tioce_mmr_war_pre(kern, mmrp); \
103 *(varp) = readq_relaxed(mmrp); \
104 tioce_mmr_war_post(kern, mmrp); \
107 /* store variable contents into mmr */
108 #define tioce_mmr_store(kern, mmrp, varp) do {\
109 tioce_mmr_war_pre(kern, mmrp); \
110 writeq(*varp, mmrp); \
111 tioce_mmr_war_post(kern, mmrp); \
114 /* store immediate value into mmr */
115 #define tioce_mmr_storei(kern, mmrp, val) do {\
116 tioce_mmr_war_pre(kern, mmrp); \
118 tioce_mmr_war_post(kern, mmrp); \
121 /* set bits (immediate value) into mmr */
122 #define tioce_mmr_seti(kern, mmrp, bits) do {\
124 tioce_mmr_load(kern, mmrp, &tmp); \
126 tioce_mmr_store(kern, mmrp, &tmp); \
129 /* clear bits (immediate value) into mmr */
130 #define tioce_mmr_clri(kern, mmrp, bits) do { \
132 tioce_mmr_load(kern, mmrp, &tmp); \
134 tioce_mmr_store(kern, mmrp, &tmp); \
138 * Bus address ranges for the 5 flavors of TIOCE DMA
141 #define TIOCE_D64_MIN 0x8000000000000000UL
142 #define TIOCE_D64_MAX 0xffffffffffffffffUL
143 #define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN)
145 #define TIOCE_D32_MIN 0x0000000080000000UL
146 #define TIOCE_D32_MAX 0x00000000ffffffffUL
147 #define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
149 #define TIOCE_M32_MIN 0x0000000000000000UL
150 #define TIOCE_M32_MAX 0x000000007fffffffUL
151 #define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
153 #define TIOCE_M40_MIN 0x0000004000000000UL
154 #define TIOCE_M40_MAX 0x0000007fffffffffUL
155 #define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
157 #define TIOCE_M40S_MIN 0x0000008000000000UL
158 #define TIOCE_M40S_MAX 0x000000ffffffffffUL
159 #define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
162 * ATE manipulation macros.
165 #define ATE_PAGESHIFT(ps) (__ffs(ps))
166 #define ATE_PAGEMASK(ps) ((ps)-1)
168 #define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
169 #define ATE_NPAGES(start, len, pagesize) \
170 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
172 #define ATE_VALID(ate) ((ate) & (1UL << 63))
173 #define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63))
176 * Flavors of ate-based mapping supported by tioce_alloc_map()
179 #define TIOCE_ATE_M32 1
180 #define TIOCE_ATE_M40 2
181 #define TIOCE_ATE_M40S 3
183 #define KB(x) ((u64)(x) << 10)
184 #define MB(x) ((u64)(x) << 20)
185 #define GB(x) ((u64)(x) << 30)
188 * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
189 * @ct_addr: system coretalk address
191 * Map @ct_addr into 64-bit CE bus space. No device context is necessary
192 * and no CE mapping are consumed.
194 * Bits 53:0 come from the coretalk address. The remaining bits are set as
197 * 63 - must be 1 to indicate d64 mode to CE hardware
198 * 62 - barrier bit ... controlled with tioce_dma_barrier()
199 * 61 - 0 since this is not an MSI transaction
200 * 60:54 - reserved, MBZ
203 tioce_dma_d64(unsigned long ct_addr
)
207 bus_addr
= ct_addr
| (1UL << 63);
213 * pcidev_to_tioce - return misc ce related pointers given a pci_dev
214 * @pci_dev: pci device context
215 * @base: ptr to store struct tioce_mmr * for the CE holding this device
216 * @kernel: ptr to store struct tioce_kernel * for the CE holding this device
217 * @port: ptr to store the CE port number that this device is on
219 * Return pointers to various CE-related structures for the CE upstream of
223 pcidev_to_tioce(struct pci_dev
*pdev
, struct tioce
**base
,
224 struct tioce_kernel
**kernel
, int *port
)
226 struct pcidev_info
*pcidev_info
;
227 struct tioce_common
*ce_common
;
228 struct tioce_kernel
*ce_kernel
;
230 pcidev_info
= SN_PCIDEV_INFO(pdev
);
231 ce_common
= (struct tioce_common
*)pcidev_info
->pdi_pcibus_info
;
232 ce_kernel
= (struct tioce_kernel
*)ce_common
->ce_kernel_private
;
235 *base
= (struct tioce
*)ce_common
->ce_pcibus
.bs_base
;
240 * we use port as a zero-based value internally, even though the
241 * documentation is 1-based.
245 (pdev
->bus
->number
< ce_kernel
->ce_port1_secondary
) ? 0 : 1;
249 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
250 * space using one of the various ATE-based address modes.
251 * @ce_kern: tioce context
252 * @type: map mode to use
253 * @port: 0-based port that the requesting device is downstream of
254 * @ct_addr: the coretalk address to map
255 * @len: number of bytes to map
257 * Given the addressing type, set up various paramaters that define the
258 * ATE pool to use. Search for a contiguous block of entries to cover the
259 * length, and if enough resources exist, fill in the ATE's and construct a
260 * tioce_dmamap struct to track the mapping.
263 tioce_alloc_map(struct tioce_kernel
*ce_kern
, int type
, int port
,
264 u64 ct_addr
, int len
)
276 struct tioce
*ce_mmr
;
278 struct tioce_dmamap
*map
;
280 ce_mmr
= (struct tioce
*)ce_kern
->ce_common
->ce_pcibus
.bs_base
;
285 * The first 64 entries of the ate3240 pool are dedicated to
286 * super-page (TIOCE_ATE_M40S) mode.
289 entries
= TIOCE_NUM_M3240_ATES
- 64;
290 ate_shadow
= ce_kern
->ce_ate3240_shadow
;
291 ate_reg
= ce_mmr
->ce_ure_ate3240
;
292 pagesize
= ce_kern
->ce_ate3240_pagesize
;
293 bus_base
= TIOCE_M32_MIN
;
297 entries
= TIOCE_NUM_M40_ATES
;
298 ate_shadow
= ce_kern
->ce_ate40_shadow
;
299 ate_reg
= ce_mmr
->ce_ure_ate40
;
301 bus_base
= TIOCE_M40_MIN
;
305 * ate3240 entries 0-31 are dedicated to port1 super-page
306 * mappings. ate3240 entries 32-63 are dedicated to port2.
310 ate_shadow
= ce_kern
->ce_ate3240_shadow
;
311 ate_reg
= ce_mmr
->ce_ure_ate3240
;
313 bus_base
= TIOCE_M40S_MIN
;
319 nates
= ATE_NPAGES(ct_addr
, len
, pagesize
);
323 last
= first
+ entries
- nates
;
324 for (i
= first
; i
<= last
; i
++) {
325 if (ATE_VALID(ate_shadow
[i
]))
328 for (j
= i
; j
< i
+ nates
; j
++)
329 if (ATE_VALID(ate_shadow
[j
]))
339 map
= kzalloc(sizeof(struct tioce_dmamap
), GFP_ATOMIC
);
344 for (j
= 0; j
< nates
; j
++) {
347 ate
= ATE_MAKE(addr
, pagesize
);
348 ate_shadow
[i
+ j
] = ate
;
349 tioce_mmr_storei(ce_kern
, &ate_reg
[i
+ j
], ate
);
354 map
->nbytes
= nates
* pagesize
;
355 map
->ct_start
= ct_addr
& ~ATE_PAGEMASK(pagesize
);
356 map
->pci_start
= bus_base
+ (i
* pagesize
);
357 map
->ate_hw
= &ate_reg
[i
];
358 map
->ate_shadow
= &ate_shadow
[i
];
359 map
->ate_count
= nates
;
361 list_add(&map
->ce_dmamap_list
, &ce_kern
->ce_dmamap_list
);
363 return (map
->pci_start
+ (ct_addr
- map
->ct_start
));
367 * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
368 * @pdev: linux pci_dev representing the function
369 * @paddr: system physical address
371 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
374 tioce_dma_d32(struct pci_dev
*pdev
, u64 ct_addr
)
378 struct tioce
*ce_mmr
;
379 struct tioce_kernel
*ce_kern
;
384 ct_upper
= ct_addr
& ~0x3fffffffUL
;
385 ct_lower
= ct_addr
& 0x3fffffffUL
;
387 pcidev_to_tioce(pdev
, &ce_mmr
, &ce_kern
, &port
);
389 if (ce_kern
->ce_port
[port
].dirmap_refcnt
== 0) {
392 ce_kern
->ce_port
[port
].dirmap_shadow
= ct_upper
;
393 tioce_mmr_storei(ce_kern
, &ce_mmr
->ce_ure_dir_map
[port
],
395 tmp
= ce_mmr
->ce_ure_dir_map
[port
];
398 dma_ok
= (ce_kern
->ce_port
[port
].dirmap_shadow
== ct_upper
);
401 ce_kern
->ce_port
[port
].dirmap_refcnt
++;
402 bus_addr
= TIOCE_D32_MIN
+ ct_lower
;
410 * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
412 * @bus_addr: bus address to swizzle
414 * Given a TIOCE bus address, set the appropriate bit to indicate barrier
418 tioce_dma_barrier(u64 bus_addr
, int on
)
422 /* barrier not supported in M40/M40S mode */
423 if (TIOCE_M40_ADDR(bus_addr
) || TIOCE_M40S_ADDR(bus_addr
))
426 if (TIOCE_D64_ADDR(bus_addr
))
427 barrier_bit
= (1UL << 62);
428 else /* must be m32 or d32 */
429 barrier_bit
= (1UL << 30);
431 return (on
) ? (bus_addr
| barrier_bit
) : (bus_addr
& ~barrier_bit
);
435 * tioce_dma_unmap - release CE mapping resources
436 * @pdev: linux pci_dev representing the function
437 * @bus_addr: bus address returned by an earlier tioce_dma_map
438 * @dir: mapping direction (unused)
440 * Locate mapping resources associated with @bus_addr and release them.
441 * For mappings created using the direct modes there are no resources
445 tioce_dma_unmap(struct pci_dev
*pdev
, dma_addr_t bus_addr
, int dir
)
449 struct tioce_kernel
*ce_kern
;
450 struct tioce
*ce_mmr
;
453 bus_addr
= tioce_dma_barrier(bus_addr
, 0);
454 pcidev_to_tioce(pdev
, &ce_mmr
, &ce_kern
, &port
);
456 /* nothing to do for D64 */
458 if (TIOCE_D64_ADDR(bus_addr
))
461 spin_lock_irqsave(&ce_kern
->ce_lock
, flags
);
463 if (TIOCE_D32_ADDR(bus_addr
)) {
464 if (--ce_kern
->ce_port
[port
].dirmap_refcnt
== 0) {
465 ce_kern
->ce_port
[port
].dirmap_shadow
= 0;
466 tioce_mmr_storei(ce_kern
, &ce_mmr
->ce_ure_dir_map
[port
],
470 struct tioce_dmamap
*map
;
472 list_for_each_entry(map
, &ce_kern
->ce_dmamap_list
,
476 last
= map
->pci_start
+ map
->nbytes
- 1;
477 if (bus_addr
>= map
->pci_start
&& bus_addr
<= last
)
481 if (&map
->ce_dmamap_list
== &ce_kern
->ce_dmamap_list
) {
483 "%s: %s - no map found for bus_addr 0x%lx\n",
484 __FUNCTION__
, pci_name(pdev
), bus_addr
);
485 } else if (--map
->refcnt
== 0) {
486 for (i
= 0; i
< map
->ate_count
; i
++) {
487 map
->ate_shadow
[i
] = 0;
488 tioce_mmr_storei(ce_kern
, &map
->ate_hw
[i
], 0);
491 list_del(&map
->ce_dmamap_list
);
496 spin_unlock_irqrestore(&ce_kern
->ce_lock
, flags
);
500 * tioce_do_dma_map - map pages for PCI DMA
501 * @pdev: linux pci_dev representing the function
502 * @paddr: host physical address to map
503 * @byte_count: bytes to map
505 * This is the main wrapper for mapping host physical pages to CE PCI space.
506 * The mapping mode used is based on the device's dma_mask.
509 tioce_do_dma_map(struct pci_dev
*pdev
, u64 paddr
, size_t byte_count
,
515 struct tioce_kernel
*ce_kern
;
516 struct tioce_dmamap
*map
;
520 dma_mask
= (barrier
) ? pdev
->dev
.coherent_dma_mask
: pdev
->dma_mask
;
522 /* cards must be able to address at least 31 bits */
523 if (dma_mask
< 0x7fffffffUL
)
526 ct_addr
= PHYS_TO_TIODMA(paddr
);
529 * If the device can generate 64 bit addresses, create a D64 map.
530 * Since this should never fail, bypass the rest of the checks.
532 if (dma_mask
== ~0UL) {
533 mapaddr
= tioce_dma_d64(ct_addr
);
537 pcidev_to_tioce(pdev
, NULL
, &ce_kern
, &port
);
539 spin_lock_irqsave(&ce_kern
->ce_lock
, flags
);
542 * D64 didn't work ... See if we have an existing map that covers
543 * this address range. Must account for devices dma_mask here since
544 * an existing map might have been done in a mode using more pci
545 * address bits than this device can support.
547 list_for_each_entry(map
, &ce_kern
->ce_dmamap_list
, ce_dmamap_list
) {
550 last
= map
->ct_start
+ map
->nbytes
- 1;
551 if (ct_addr
>= map
->ct_start
&&
552 ct_addr
+ byte_count
- 1 <= last
&&
553 map
->pci_start
<= dma_mask
) {
555 mapaddr
= map
->pci_start
+ (ct_addr
- map
->ct_start
);
561 * If we don't have a map yet, and the card can generate 40
562 * bit addresses, try the M40/M40S modes. Note these modes do not
563 * support a barrier bit, so if we need a consistent map these
566 if (!mapaddr
&& !barrier
&& dma_mask
>= 0xffffffffffUL
) {
568 * We have two options for 40-bit mappings: 16GB "super" ATE's
569 * and 64MB "regular" ATE's. We'll try both if needed for a
570 * given mapping but which one we try first depends on the
571 * size. For requests >64MB, prefer to use a super page with
572 * regular as the fallback. Otherwise, try in the reverse order.
575 if (byte_count
> MB(64)) {
576 mapaddr
= tioce_alloc_map(ce_kern
, TIOCE_ATE_M40S
,
577 port
, ct_addr
, byte_count
);
580 tioce_alloc_map(ce_kern
, TIOCE_ATE_M40
, -1,
581 ct_addr
, byte_count
);
583 mapaddr
= tioce_alloc_map(ce_kern
, TIOCE_ATE_M40
, -1,
584 ct_addr
, byte_count
);
587 tioce_alloc_map(ce_kern
, TIOCE_ATE_M40S
,
588 port
, ct_addr
, byte_count
);
593 * 32-bit direct is the next mode to try
595 if (!mapaddr
&& dma_mask
>= 0xffffffffUL
)
596 mapaddr
= tioce_dma_d32(pdev
, ct_addr
);
599 * Last resort, try 32-bit ATE-based map.
603 tioce_alloc_map(ce_kern
, TIOCE_ATE_M32
, -1, ct_addr
,
606 spin_unlock_irqrestore(&ce_kern
->ce_lock
, flags
);
609 if (mapaddr
&& barrier
)
610 mapaddr
= tioce_dma_barrier(mapaddr
, 1);
616 * tioce_dma - standard pci dma map interface
617 * @pdev: pci device requesting the map
618 * @paddr: system physical address to map into pci space
619 * @byte_count: # bytes to map
621 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
625 tioce_dma(struct pci_dev
*pdev
, u64 paddr
, size_t byte_count
)
627 return tioce_do_dma_map(pdev
, paddr
, byte_count
, 0);
631 * tioce_dma_consistent - consistent pci dma map interface
632 * @pdev: pci device requesting the map
633 * @paddr: system physical address to map into pci space
634 * @byte_count: # bytes to map
636 * Simply call tioce_do_dma_map() to create a map with the barrier bit set
639 tioce_dma_consistent(struct pci_dev
*pdev
, u64 paddr
, size_t byte_count
)
641 return tioce_do_dma_map(pdev
, paddr
, byte_count
, 1);
645 * tioce_error_intr_handler - SGI TIO CE error interrupt handler
647 * @arg: pointer to tioce_common struct for the given CE
650 * Handle a CE error interrupt. Simply a wrapper around a SAL call which
651 * defers processing to the SGI prom.
652 */ static irqreturn_t
653 tioce_error_intr_handler(int irq
, void *arg
, struct pt_regs
*pt
)
655 struct tioce_common
*soft
= arg
;
656 struct ia64_sal_retval ret_stuff
;
657 ret_stuff
.status
= 0;
660 SAL_CALL_NOLOCK(ret_stuff
, (u64
) SN_SAL_IOIF_ERROR_INTERRUPT
,
661 soft
->ce_pcibus
.bs_persist_segment
,
662 soft
->ce_pcibus
.bs_persist_busnum
, 0, 0, 0, 0, 0);
665 panic("tioce_error_intr_handler: Fatal TIOCE error");
671 * tioce_reserve_m32 - reserve M32 ate's for the indicated address range
672 * @tioce_kernel: TIOCE context to reserve ate's for
673 * @base: starting bus address to reserve
674 * @limit: last bus address to reserve
676 * If base/limit falls within the range of bus space mapped through the
677 * M32 space, reserve the resources corresponding to the range.
680 tioce_reserve_m32(struct tioce_kernel
*ce_kern
, u64 base
, u64 limit
)
682 int ate_index
, last_ate
, ps
;
683 struct tioce
*ce_mmr
;
685 ce_mmr
= (struct tioce
*)ce_kern
->ce_common
->ce_pcibus
.bs_base
;
686 ps
= ce_kern
->ce_ate3240_pagesize
;
687 ate_index
= ATE_PAGE(base
, ps
);
688 last_ate
= ate_index
+ ATE_NPAGES(base
, limit
-base
+1, ps
) - 1;
693 if (last_ate
>= TIOCE_NUM_M3240_ATES
)
694 last_ate
= TIOCE_NUM_M3240_ATES
- 1;
696 while (ate_index
<= last_ate
) {
699 ate
= ATE_MAKE(0xdeadbeef, ps
);
700 ce_kern
->ce_ate3240_shadow
[ate_index
] = ate
;
701 tioce_mmr_storei(ce_kern
, &ce_mmr
->ce_ure_ate3240
[ate_index
],
708 * tioce_kern_init - init kernel structures related to a given TIOCE
709 * @tioce_common: ptr to a cached tioce_common struct that originated in prom
711 static struct tioce_kernel
*
712 tioce_kern_init(struct tioce_common
*tioce_common
)
718 unsigned int seg
, bus
;
719 struct tioce
*tioce_mmr
;
720 struct tioce_kernel
*tioce_kern
;
722 tioce_kern
= kzalloc(sizeof(struct tioce_kernel
), GFP_KERNEL
);
727 tioce_kern
->ce_common
= tioce_common
;
728 spin_lock_init(&tioce_kern
->ce_lock
);
729 INIT_LIST_HEAD(&tioce_kern
->ce_dmamap_list
);
730 tioce_common
->ce_kernel_private
= (u64
) tioce_kern
;
733 * Determine the secondary bus number of the port2 logical PPB.
734 * This is used to decide whether a given pci device resides on
735 * port1 or port2. Note: We don't have enough plumbing set up
736 * here to use pci_read_config_xxx() so use the raw_pci_ops vector.
739 seg
= tioce_common
->ce_pcibus
.bs_persist_segment
;
740 bus
= tioce_common
->ce_pcibus
.bs_persist_busnum
;
742 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS
, 1,&tmp
);
743 tioce_kern
->ce_port1_secondary
= (u8
) tmp
;
746 * Set PMU pagesize to the largest size available, and zero out
750 tioce_mmr
= (struct tioce
*)tioce_common
->ce_pcibus
.bs_base
;
751 tioce_mmr_clri(tioce_kern
, &tioce_mmr
->ce_ure_page_map
,
752 CE_URE_PAGESIZE_MASK
);
753 tioce_mmr_seti(tioce_kern
, &tioce_mmr
->ce_ure_page_map
,
754 CE_URE_256K_PAGESIZE
);
755 ps
= tioce_kern
->ce_ate3240_pagesize
= KB(256);
757 for (i
= 0; i
< TIOCE_NUM_M40_ATES
; i
++) {
758 tioce_kern
->ce_ate40_shadow
[i
] = 0;
759 tioce_mmr_storei(tioce_kern
, &tioce_mmr
->ce_ure_ate40
[i
], 0);
762 for (i
= 0; i
< TIOCE_NUM_M3240_ATES
; i
++) {
763 tioce_kern
->ce_ate3240_shadow
[i
] = 0;
764 tioce_mmr_storei(tioce_kern
, &tioce_mmr
->ce_ure_ate3240
[i
], 0);
768 * Reserve ATE's corresponding to reserved address ranges. These
771 * Memory space covered by each PPB mem base/limit register
772 * Memory space covered by each PPB prefetch base/limit register
774 * These bus ranges are for pio (downstream) traffic only, and so
775 * cannot be used for DMA.
778 for (dev
= 1; dev
<= 2; dev
++) {
783 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
784 PCI_MEMORY_BASE
, 2, &tmp
);
785 base
= (u64
)tmp
<< 16;
787 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
788 PCI_MEMORY_LIMIT
, 2, &tmp
);
789 limit
= (u64
)tmp
<< 16;
793 tioce_reserve_m32(tioce_kern
, base
, limit
);
796 * prefetch mem base/limit. The tioce ppb's have 64-bit
797 * decoders, so read the upper portions w/o checking the
801 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
802 PCI_PREF_MEMORY_BASE
, 2, &tmp
);
803 base
= ((u64
)tmp
& PCI_PREF_RANGE_MASK
) << 16;
805 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
806 PCI_PREF_BASE_UPPER32
, 4, &tmp
);
807 base
|= (u64
)tmp
<< 32;
809 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
810 PCI_PREF_MEMORY_LIMIT
, 2, &tmp
);
812 limit
= ((u64
)tmp
& PCI_PREF_RANGE_MASK
) << 16;
815 raw_pci_ops
->read(seg
, bus
, PCI_DEVFN(dev
, 0),
816 PCI_PREF_LIMIT_UPPER32
, 4, &tmp
);
817 limit
|= (u64
)tmp
<< 32;
819 if ((base
< limit
) && TIOCE_M32_ADDR(base
))
820 tioce_reserve_m32(tioce_kern
, base
, limit
);
827 * tioce_force_interrupt - implement altix force_interrupt() backend for CE
828 * @sn_irq_info: sn asic irq that we need an interrupt generated for
830 * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to
831 * force a secondary interrupt to be generated. This is to work around an
832 * asic issue where there is a small window of opportunity for a legacy device
833 * interrupt to be lost.
836 tioce_force_interrupt(struct sn_irq_info
*sn_irq_info
)
838 struct pcidev_info
*pcidev_info
;
839 struct tioce_common
*ce_common
;
840 struct tioce_kernel
*ce_kern
;
841 struct tioce
*ce_mmr
;
844 if (!sn_irq_info
->irq_bridge
)
847 if (sn_irq_info
->irq_bridge_type
!= PCIIO_ASIC_TYPE_TIOCE
)
850 pcidev_info
= (struct pcidev_info
*)sn_irq_info
->irq_pciioinfo
;
854 ce_common
= (struct tioce_common
*)pcidev_info
->pdi_pcibus_info
;
855 ce_mmr
= (struct tioce
*)ce_common
->ce_pcibus
.bs_base
;
856 ce_kern
= (struct tioce_kernel
*)ce_common
->ce_kernel_private
;
859 * TIOCE Rev A workaround (PV 945826), force an interrupt by writing
860 * the TIO_INTx register directly (1/26/2006)
862 if (ce_common
->ce_rev
== TIOCE_REV_A
) {
863 u64 int_bit_mask
= (1ULL << sn_irq_info
->irq_int_bit
);
866 tioce_mmr_load(ce_kern
, &ce_mmr
->ce_adm_int_status
, &status
);
867 if (status
& int_bit_mask
) {
868 u64 force_irq
= (1 << 8) | sn_irq_info
->irq_irq
;
869 u64 ctalk
= sn_irq_info
->irq_xtalkaddr
;
872 nasid
= (ctalk
& CTALK_NASID_MASK
) >> CTALK_NASID_SHFT
;
873 offset
= (ctalk
& CTALK_NODE_OFFSET
);
874 HUB_S(TIO_IOSPACE_ADDR(nasid
, offset
), force_irq
);
881 * irq_int_bit is originally set up by prom, and holds the interrupt
882 * bit shift (not mask) as defined by the bit definitions in the
883 * ce_adm_int mmr. These shifts are not the same for the
884 * ce_adm_force_int register, so do an explicit mapping here to make
888 switch (sn_irq_info
->irq_int_bit
) {
889 case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT
:
890 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT
;
892 case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT
:
893 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT
;
895 case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT
:
896 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT
;
898 case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT
:
899 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT
;
901 case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT
:
902 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT
;
904 case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT
:
905 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT
;
907 case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT
:
908 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT
;
910 case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT
:
911 force_int_val
= 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT
;
916 tioce_mmr_storei(ce_kern
, &ce_mmr
->ce_adm_force_int
, force_int_val
);
920 * tioce_target_interrupt - implement set_irq_affinity for tioce resident
921 * functions. Note: only applies to line interrupts, not MSI's.
923 * @sn_irq_info: SN IRQ context
925 * Given an sn_irq_info, set the associated CE device's interrupt destination
926 * register. Since the interrupt destination registers are on a per-ce-slot
927 * basis, this will retarget line interrupts for all functions downstream of
931 tioce_target_interrupt(struct sn_irq_info
*sn_irq_info
)
933 struct pcidev_info
*pcidev_info
;
934 struct tioce_common
*ce_common
;
935 struct tioce_kernel
*ce_kern
;
936 struct tioce
*ce_mmr
;
940 pcidev_info
= (struct pcidev_info
*)sn_irq_info
->irq_pciioinfo
;
944 ce_common
= (struct tioce_common
*)pcidev_info
->pdi_pcibus_info
;
945 ce_mmr
= (struct tioce
*)ce_common
->ce_pcibus
.bs_base
;
946 ce_kern
= (struct tioce_kernel
*)ce_common
->ce_kernel_private
;
948 bit
= sn_irq_info
->irq_int_bit
;
950 tioce_mmr_seti(ce_kern
, &ce_mmr
->ce_adm_int_mask
, (1UL << bit
));
951 vector
= (u64
)sn_irq_info
->irq_irq
<< INTR_VECTOR_SHFT
;
952 vector
|= sn_irq_info
->irq_xtalkaddr
;
953 tioce_mmr_storei(ce_kern
, &ce_mmr
->ce_adm_int_dest
[bit
], vector
);
954 tioce_mmr_clri(ce_kern
, &ce_mmr
->ce_adm_int_mask
, (1UL << bit
));
956 tioce_force_interrupt(sn_irq_info
);
960 * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
961 * @prom_bussoft: Common prom/kernel struct representing the bus
963 * Replicates the tioce_common pointed to by @prom_bussoft in kernel
964 * space. Allocates and initializes a kernel-only area for a given CE,
965 * and sets up an irq for handling CE error interrupts.
967 * On successful setup, returns the kernel version of tioce_common back to
971 tioce_bus_fixup(struct pcibus_bussoft
*prom_bussoft
, struct pci_controller
*controller
)
974 cnodeid_t my_cnode
, mem_cnode
;
975 struct tioce_common
*tioce_common
;
976 struct tioce_kernel
*tioce_kern
;
977 struct tioce
*tioce_mmr
;
980 * Allocate kernel bus soft and copy from prom.
983 tioce_common
= kzalloc(sizeof(struct tioce_common
), GFP_KERNEL
);
987 memcpy(tioce_common
, prom_bussoft
, sizeof(struct tioce_common
));
988 tioce_common
->ce_pcibus
.bs_base
|= __IA64_UNCACHED_OFFSET
;
990 tioce_kern
= tioce_kern_init(tioce_common
);
991 if (tioce_kern
== NULL
) {
997 * Clear out any transient errors before registering the error
1001 tioce_mmr
= (struct tioce
*)tioce_common
->ce_pcibus
.bs_base
;
1002 tioce_mmr_seti(tioce_kern
, &tioce_mmr
->ce_adm_int_status_alias
, ~0ULL);
1003 tioce_mmr_seti(tioce_kern
, &tioce_mmr
->ce_adm_error_summary_alias
,
1005 tioce_mmr_seti(tioce_kern
, &tioce_mmr
->ce_dre_comp_err_addr
, ~0ULL);
1007 if (request_irq(SGI_PCIASIC_ERROR
,
1008 tioce_error_intr_handler
,
1009 SA_SHIRQ
, "TIOCE error", (void *)tioce_common
))
1011 "%s: Unable to get irq %d. "
1012 "Error interrupts won't be routed for "
1013 "TIOCE bus %04x:%02x\n",
1014 __FUNCTION__
, SGI_PCIASIC_ERROR
,
1015 tioce_common
->ce_pcibus
.bs_persist_segment
,
1016 tioce_common
->ce_pcibus
.bs_persist_busnum
);
1019 * identify closest nasid for memory allocations
1022 my_nasid
= NASID_GET(tioce_common
->ce_pcibus
.bs_base
);
1023 my_cnode
= nasid_to_cnodeid(my_nasid
);
1025 if (sn_hwperf_get_nearest_node(my_cnode
, &mem_cnode
, NULL
) < 0) {
1026 printk(KERN_WARNING
"tioce_bus_fixup: failed to find "
1027 "closest node with MEM to TIO node %d\n", my_cnode
);
1028 mem_cnode
= (cnodeid_t
)-1; /* use any node */
1031 controller
->node
= mem_cnode
;
1033 return tioce_common
;
1036 static struct sn_pcibus_provider tioce_pci_interfaces
= {
1037 .dma_map
= tioce_dma
,
1038 .dma_map_consistent
= tioce_dma_consistent
,
1039 .dma_unmap
= tioce_dma_unmap
,
1040 .bus_fixup
= tioce_bus_fixup
,
1041 .force_interrupt
= tioce_force_interrupt
,
1042 .target_interrupt
= tioce_target_interrupt
1046 * tioce_init_provider - init SN PCI provider ops for TIO CE
1049 tioce_init_provider(void)
1051 sn_pci_provider
[PCIIO_ASIC_TYPE_TIOCE
] = &tioce_pci_interfaces
;