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[PATCH] libata: flush COMRESET set and clear
[linux-2.6/verdex.git] / arch / x86_64 / kernel / mpparse.c
blob7ec031c6ca10fe566e444fcafcb3b1b4995887b9
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/acpi.h>
26
27 #include <asm/smp.h>
28 #include <asm/mtrr.h>
29 #include <asm/mpspec.h>
30 #include <asm/pgalloc.h>
31 #include <asm/io_apic.h>
32 #include <asm/proto.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 int acpi_found_madt;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47 cpumask_t pci_bus_to_cpumask [256] = { [0 ... 255] = CPU_MASK_ALL };
48
49 static int mp_current_pci_id = 0;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55
56 /* MP IRQ source entries */
57 int mp_irq_entries;
58
59 int nr_ioapics;
60 int pic_mode;
61 unsigned long mp_lapic_addr = 0;
62
63
64
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_id = -1U;
67 /* Internal processor count */
68 static unsigned int num_processors = 0;
69
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
72
73 /* ACPI MADT entry parsing functions */
74 #ifdef CONFIG_ACPI_BOOT
75 extern struct acpi_boot_flags acpi_boot;
76 #ifdef CONFIG_X86_LOCAL_APIC
77 extern int acpi_parse_lapic (acpi_table_entry_header *header);
78 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
80 #endif /*CONFIG_X86_LOCAL_APIC*/
81 #ifdef CONFIG_X86_IO_APIC
82 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
83 #endif /*CONFIG_X86_IO_APIC*/
84 #endif /*CONFIG_ACPI_BOOT*/
85
86 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
87
88
89 /*
90 * Intel MP BIOS table parsing routines:
91 */
92
93 /*
94 * Checksum an MP configuration block.
95 */
96
97 static int __init mpf_checksum(unsigned char *mp, int len)
98 {
99 int sum = 0;
100
101 while (len--)
102 sum += *mp++;
103
104 return sum & 0xFF;
105 }
106
107 static void __init MP_processor_info (struct mpc_config_processor *m)
108 {
109 int ver;
110
111 if (!(m->mpc_cpuflag & CPU_ENABLED))
112 return;
113
114 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
115 m->mpc_apicid,
116 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
117 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
118 m->mpc_apicver);
119
120 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
121 Dprintk(" Bootup CPU\n");
122 boot_cpu_id = m->mpc_apicid;
123 }
124 if (num_processors >= NR_CPUS) {
125 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
126 " Processor ignored.\n", NR_CPUS);
127 return;
128 }
129 if (num_processors >= maxcpus) {
130 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
131 " Processor ignored.\n", maxcpus);
132 return;
133 }
134
135 num_processors++;
136
137 if (m->mpc_apicid > MAX_APICS) {
138 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
139 m->mpc_apicid, MAX_APICS);
140 return;
141 }
142 ver = m->mpc_apicver;
143
144 physid_set(m->mpc_apicid, phys_cpu_present_map);
145 /*
146 * Validate version
147 */
148 if (ver == 0x0) {
149 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
150 ver = 0x10;
151 }
152 apic_version[m->mpc_apicid] = ver;
153 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
154 }
155
156 static void __init MP_bus_info (struct mpc_config_bus *m)
157 {
158 char str[7];
159
160 memcpy(str, m->mpc_bustype, 6);
161 str[6] = 0;
162 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
163
164 if (strncmp(str, "ISA", 3) == 0) {
165 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
166 } else if (strncmp(str, "EISA", 4) == 0) {
167 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
168 } else if (strncmp(str, "PCI", 3) == 0) {
169 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
170 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
171 mp_current_pci_id++;
172 } else if (strncmp(str, "MCA", 3) == 0) {
173 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
174 } else {
175 printk(KERN_ERR "Unknown bustype %s\n", str);
176 }
177 }
178
179 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
180 {
181 if (!(m->mpc_flags & MPC_APIC_USABLE))
182 return;
183
184 printk("I/O APIC #%d Version %d at 0x%X.\n",
185 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
186 if (nr_ioapics >= MAX_IO_APICS) {
187 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
188 MAX_IO_APICS, nr_ioapics);
189 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
190 }
191 if (!m->mpc_apicaddr) {
192 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
193 " found in MP table, skipping!\n");
194 return;
195 }
196 mp_ioapics[nr_ioapics] = *m;
197 nr_ioapics++;
198 }
199
200 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
201 {
202 mp_irqs [mp_irq_entries] = *m;
203 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
204 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->mpc_irqtype, m->mpc_irqflag & 3,
206 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
207 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
208 if (++mp_irq_entries == MAX_IRQ_SOURCES)
209 panic("Max # of irq sources exceeded!!\n");
210 }
211
212 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
213 {
214 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
215 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
216 m->mpc_irqtype, m->mpc_irqflag & 3,
217 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
218 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
219 /*
220 * Well it seems all SMP boards in existence
221 * use ExtINT/LVT1 == LINT0 and
222 * NMI/LVT2 == LINT1 - the following check
223 * will show us if this assumptions is false.
224 * Until then we do not have to add baggage.
225 */
226 if ((m->mpc_irqtype == mp_ExtINT) &&
227 (m->mpc_destapiclint != 0))
228 BUG();
229 if ((m->mpc_irqtype == mp_NMI) &&
230 (m->mpc_destapiclint != 1))
231 BUG();
232 }
233
234 /*
235 * Read/parse the MPC
236 */
237
238 static int __init smp_read_mpc(struct mp_config_table *mpc)
239 {
240 char str[16];
241 int count=sizeof(*mpc);
242 unsigned char *mpt=((unsigned char *)mpc)+count;
243
244 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
245 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
246 mpc->mpc_signature[0],
247 mpc->mpc_signature[1],
248 mpc->mpc_signature[2],
249 mpc->mpc_signature[3]);
250 return 0;
251 }
252 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
253 printk("SMP mptable: checksum error!\n");
254 return 0;
255 }
256 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
257 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
258 mpc->mpc_spec);
259 return 0;
260 }
261 if (!mpc->mpc_lapic) {
262 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
263 return 0;
264 }
265 memcpy(str,mpc->mpc_oem,8);
266 str[8]=0;
267 printk(KERN_INFO "OEM ID: %s ",str);
268
269 memcpy(str,mpc->mpc_productid,12);
270 str[12]=0;
271 printk(KERN_INFO "Product ID: %s ",str);
272
273 printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
274
275 /* save the local APIC address, it might be non-default */
276 if (!acpi_lapic)
277 mp_lapic_addr = mpc->mpc_lapic;
278
279 /*
280 * Now process the configuration blocks.
281 */
282 while (count < mpc->mpc_length) {
283 switch(*mpt) {
284 case MP_PROCESSOR:
285 {
286 struct mpc_config_processor *m=
287 (struct mpc_config_processor *)mpt;
288 if (!acpi_lapic)
289 MP_processor_info(m);
290 mpt += sizeof(*m);
291 count += sizeof(*m);
292 break;
293 }
294 case MP_BUS:
295 {
296 struct mpc_config_bus *m=
297 (struct mpc_config_bus *)mpt;
298 MP_bus_info(m);
299 mpt += sizeof(*m);
300 count += sizeof(*m);
301 break;
302 }
303 case MP_IOAPIC:
304 {
305 struct mpc_config_ioapic *m=
306 (struct mpc_config_ioapic *)mpt;
307 MP_ioapic_info(m);
308 mpt+=sizeof(*m);
309 count+=sizeof(*m);
310 break;
311 }
312 case MP_INTSRC:
313 {
314 struct mpc_config_intsrc *m=
315 (struct mpc_config_intsrc *)mpt;
316
317 MP_intsrc_info(m);
318 mpt+=sizeof(*m);
319 count+=sizeof(*m);
320 break;
321 }
322 case MP_LINTSRC:
323 {
324 struct mpc_config_lintsrc *m=
325 (struct mpc_config_lintsrc *)mpt;
326 MP_lintsrc_info(m);
327 mpt+=sizeof(*m);
328 count+=sizeof(*m);
329 break;
330 }
331 }
332 }
333 clustered_apic_check();
334 if (!num_processors)
335 printk(KERN_ERR "SMP mptable: no processors registered!\n");
336 return num_processors;
337 }
338
339 static int __init ELCR_trigger(unsigned int irq)
340 {
341 unsigned int port;
342
343 port = 0x4d0 + (irq >> 3);
344 return (inb(port) >> (irq & 7)) & 1;
345 }
346
347 static void __init construct_default_ioirq_mptable(int mpc_default_type)
348 {
349 struct mpc_config_intsrc intsrc;
350 int i;
351 int ELCR_fallback = 0;
352
353 intsrc.mpc_type = MP_INTSRC;
354 intsrc.mpc_irqflag = 0; /* conforming */
355 intsrc.mpc_srcbus = 0;
356 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
357
358 intsrc.mpc_irqtype = mp_INT;
359
360 /*
361 * If true, we have an ISA/PCI system with no IRQ entries
362 * in the MP table. To prevent the PCI interrupts from being set up
363 * incorrectly, we try to use the ELCR. The sanity check to see if
364 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
365 * never be level sensitive, so we simply see if the ELCR agrees.
366 * If it does, we assume it's valid.
367 */
368 if (mpc_default_type == 5) {
369 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
370
371 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
372 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
373 else {
374 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
375 ELCR_fallback = 1;
376 }
377 }
378
379 for (i = 0; i < 16; i++) {
380 switch (mpc_default_type) {
381 case 2:
382 if (i == 0 || i == 13)
383 continue; /* IRQ0 & IRQ13 not connected */
384 /* fall through */
385 default:
386 if (i == 2)
387 continue; /* IRQ2 is never connected */
388 }
389
390 if (ELCR_fallback) {
391 /*
392 * If the ELCR indicates a level-sensitive interrupt, we
393 * copy that information over to the MP table in the
394 * irqflag field (level sensitive, active high polarity).
395 */
396 if (ELCR_trigger(i))
397 intsrc.mpc_irqflag = 13;
398 else
399 intsrc.mpc_irqflag = 0;
400 }
401
402 intsrc.mpc_srcbusirq = i;
403 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
404 MP_intsrc_info(&intsrc);
405 }
406
407 intsrc.mpc_irqtype = mp_ExtINT;
408 intsrc.mpc_srcbusirq = 0;
409 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
410 MP_intsrc_info(&intsrc);
411 }
412
413 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
414 {
415 struct mpc_config_processor processor;
416 struct mpc_config_bus bus;
417 struct mpc_config_ioapic ioapic;
418 struct mpc_config_lintsrc lintsrc;
419 int linttypes[2] = { mp_ExtINT, mp_NMI };
420 int i;
421
422 /*
423 * local APIC has default address
424 */
425 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
426
427 /*
428 * 2 CPUs, numbered 0 & 1.
429 */
430 processor.mpc_type = MP_PROCESSOR;
431 /* Either an integrated APIC or a discrete 82489DX. */
432 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
433 processor.mpc_cpuflag = CPU_ENABLED;
434 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
435 (boot_cpu_data.x86_model << 4) |
436 boot_cpu_data.x86_mask;
437 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
438 processor.mpc_reserved[0] = 0;
439 processor.mpc_reserved[1] = 0;
440 for (i = 0; i < 2; i++) {
441 processor.mpc_apicid = i;
442 MP_processor_info(&processor);
443 }
444
445 bus.mpc_type = MP_BUS;
446 bus.mpc_busid = 0;
447 switch (mpc_default_type) {
448 default:
449 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
450 mpc_default_type);
451 /* fall through */
452 case 1:
453 case 5:
454 memcpy(bus.mpc_bustype, "ISA ", 6);
455 break;
456 case 2:
457 case 6:
458 case 3:
459 memcpy(bus.mpc_bustype, "EISA ", 6);
460 break;
461 case 4:
462 case 7:
463 memcpy(bus.mpc_bustype, "MCA ", 6);
464 }
465 MP_bus_info(&bus);
466 if (mpc_default_type > 4) {
467 bus.mpc_busid = 1;
468 memcpy(bus.mpc_bustype, "PCI ", 6);
469 MP_bus_info(&bus);
470 }
471
472 ioapic.mpc_type = MP_IOAPIC;
473 ioapic.mpc_apicid = 2;
474 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
475 ioapic.mpc_flags = MPC_APIC_USABLE;
476 ioapic.mpc_apicaddr = 0xFEC00000;
477 MP_ioapic_info(&ioapic);
478
479 /*
480 * We set up most of the low 16 IO-APIC pins according to MPS rules.
481 */
482 construct_default_ioirq_mptable(mpc_default_type);
483
484 lintsrc.mpc_type = MP_LINTSRC;
485 lintsrc.mpc_irqflag = 0; /* conforming */
486 lintsrc.mpc_srcbusid = 0;
487 lintsrc.mpc_srcbusirq = 0;
488 lintsrc.mpc_destapic = MP_APIC_ALL;
489 for (i = 0; i < 2; i++) {
490 lintsrc.mpc_irqtype = linttypes[i];
491 lintsrc.mpc_destapiclint = i;
492 MP_lintsrc_info(&lintsrc);
493 }
494 }
495
496 static struct intel_mp_floating *mpf_found;
497
498 /*
499 * Scan the memory blocks for an SMP configuration block.
500 */
501 void __init get_smp_config (void)
502 {
503 struct intel_mp_floating *mpf = mpf_found;
504
505 /*
506 * ACPI may be used to obtain the entire SMP configuration or just to
507 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
508 * ACPI supports both logical (e.g. Hyper-Threading) and physical
509 * processors, where MPS only supports physical.
510 */
511 if (acpi_lapic && acpi_ioapic) {
512 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
513 return;
514 }
515 else if (acpi_lapic)
516 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
517
518 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
519 if (mpf->mpf_feature2 & (1<<7)) {
520 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
521 pic_mode = 1;
522 } else {
523 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
524 pic_mode = 0;
525 }
526
527 /*
528 * Now see if we need to read further.
529 */
530 if (mpf->mpf_feature1 != 0) {
531
532 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
533 construct_default_ISA_mptable(mpf->mpf_feature1);
534
535 } else if (mpf->mpf_physptr) {
536
537 /*
538 * Read the physical hardware table. Anything here will
539 * override the defaults.
540 */
541 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
542 smp_found_config = 0;
543 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
544 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
545 return;
546 }
547 /*
548 * If there are no explicit MP IRQ entries, then we are
549 * broken. We set up most of the low 16 IO-APIC pins to
550 * ISA defaults and hope it will work.
551 */
552 if (!mp_irq_entries) {
553 struct mpc_config_bus bus;
554
555 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
556
557 bus.mpc_type = MP_BUS;
558 bus.mpc_busid = 0;
559 memcpy(bus.mpc_bustype, "ISA ", 6);
560 MP_bus_info(&bus);
561
562 construct_default_ioirq_mptable(0);
563 }
564
565 } else
566 BUG();
567
568 printk(KERN_INFO "Processors: %d\n", num_processors);
569 /*
570 * Only use the first configuration found.
571 */
572 }
573
574 static int __init smp_scan_config (unsigned long base, unsigned long length)
575 {
576 extern void __bad_mpf_size(void);
577 unsigned int *bp = phys_to_virt(base);
578 struct intel_mp_floating *mpf;
579
580 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
581 if (sizeof(*mpf) != 16)
582 __bad_mpf_size();
583
584 while (length > 0) {
585 mpf = (struct intel_mp_floating *)bp;
586 if ((*bp == SMP_MAGIC_IDENT) &&
587 (mpf->mpf_length == 1) &&
588 !mpf_checksum((unsigned char *)bp, 16) &&
589 ((mpf->mpf_specification == 1)
590 || (mpf->mpf_specification == 4)) ) {
591
592 smp_found_config = 1;
593 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
594 if (mpf->mpf_physptr)
595 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
596 mpf_found = mpf;
597 return 1;
598 }
599 bp += 4;
600 length -= 16;
601 }
602 return 0;
603 }
604
605 void __init find_intel_smp (void)
606 {
607 unsigned int address;
608
609 /*
610 * FIXME: Linux assumes you have 640K of base ram..
611 * this continues the error...
612 *
613 * 1) Scan the bottom 1K for a signature
614 * 2) Scan the top 1K of base RAM
615 * 3) Scan the 64K of bios
616 */
617 if (smp_scan_config(0x0,0x400) ||
618 smp_scan_config(639*0x400,0x400) ||
619 smp_scan_config(0xF0000,0x10000))
620 return;
621 /*
622 * If it is an SMP machine we should know now, unless the
623 * configuration is in an EISA/MCA bus machine with an
624 * extended bios data area.
625 *
626 * there is a real-mode segmented pointer pointing to the
627 * 4K EBDA area at 0x40E, calculate and scan it here.
628 *
629 * NOTE! There are Linux loaders that will corrupt the EBDA
630 * area, and as such this kind of SMP config may be less
631 * trustworthy, simply because the SMP table may have been
632 * stomped on during early boot. These loaders are buggy and
633 * should be fixed.
634 */
635
636 address = *(unsigned short *)phys_to_virt(0x40E);
637 address <<= 4;
638 if (smp_scan_config(address, 0x1000))
639 return;
640
641 /* If we have come this far, we did not find an MP table */
642 printk(KERN_INFO "No mptable found.\n");
643 }
644
645 /*
646 * - Intel MP Configuration Table
647 */
648 void __init find_smp_config (void)
649 {
650 #ifdef CONFIG_X86_LOCAL_APIC
651 find_intel_smp();
652 #endif
653 }
654
655
656 /* --------------------------------------------------------------------------
657 ACPI-based MP Configuration
658 -------------------------------------------------------------------------- */
659
660 #ifdef CONFIG_ACPI_BOOT
661
662 void __init mp_register_lapic_address (
663 u64 address)
664 {
665 mp_lapic_addr = (unsigned long) address;
666
667 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
668
669 if (boot_cpu_id == -1U)
670 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
671
672 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
673 }
674
675
676 void __init mp_register_lapic (
677 u8 id,
678 u8 enabled)
679 {
680 struct mpc_config_processor processor;
681 int boot_cpu = 0;
682
683 if (id >= MAX_APICS) {
684 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
685 id, MAX_APICS);
686 return;
687 }
688
689 if (id == boot_cpu_physical_apicid)
690 boot_cpu = 1;
691
692 processor.mpc_type = MP_PROCESSOR;
693 processor.mpc_apicid = id;
694 processor.mpc_apicver = 0x10; /* TBD: lapic version */
695 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
696 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
697 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
698 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
699 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
700 processor.mpc_reserved[0] = 0;
701 processor.mpc_reserved[1] = 0;
702
703 MP_processor_info(&processor);
704 }
705
706 #ifdef CONFIG_X86_IO_APIC
707
708 #define MP_ISA_BUS 0
709 #define MP_MAX_IOAPIC_PIN 127
710
711 static struct mp_ioapic_routing {
712 int apic_id;
713 int gsi_start;
714 int gsi_end;
715 u32 pin_programmed[4];
716 } mp_ioapic_routing[MAX_IO_APICS];
717
718
719 static int mp_find_ioapic (
720 int gsi)
721 {
722 int i = 0;
723
724 /* Find the IOAPIC that manages this GSI. */
725 for (i = 0; i < nr_ioapics; i++) {
726 if ((gsi >= mp_ioapic_routing[i].gsi_start)
727 && (gsi <= mp_ioapic_routing[i].gsi_end))
728 return i;
729 }
730
731 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
732
733 return -1;
734 }
735
736
737 void __init mp_register_ioapic (
738 u8 id,
739 u32 address,
740 u32 gsi_base)
741 {
742 int idx = 0;
743
744 if (nr_ioapics >= MAX_IO_APICS) {
745 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
746 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
747 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
748 }
749 if (!address) {
750 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
751 " found in MADT table, skipping!\n");
752 return;
753 }
754
755 idx = nr_ioapics++;
756
757 mp_ioapics[idx].mpc_type = MP_IOAPIC;
758 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
759 mp_ioapics[idx].mpc_apicaddr = address;
760
761 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
762 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
763 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
764
765 /*
766 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
767 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
768 */
769 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
770 mp_ioapic_routing[idx].gsi_start = gsi_base;
771 mp_ioapic_routing[idx].gsi_end = gsi_base +
772 io_apic_get_redir_entries(idx);
773
774 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
775 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
776 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
777 mp_ioapic_routing[idx].gsi_start,
778 mp_ioapic_routing[idx].gsi_end);
779
780 return;
781 }
782
783
784 void __init mp_override_legacy_irq (
785 u8 bus_irq,
786 u8 polarity,
787 u8 trigger,
788 u32 gsi)
789 {
790 struct mpc_config_intsrc intsrc;
791 int ioapic = -1;
792 int pin = -1;
793
794 /*
795 * Convert 'gsi' to 'ioapic.pin'.
796 */
797 ioapic = mp_find_ioapic(gsi);
798 if (ioapic < 0)
799 return;
800 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
801
802 /*
803 * TBD: This check is for faulty timer entries, where the override
804 * erroneously sets the trigger to level, resulting in a HUGE
805 * increase of timer interrupts!
806 */
807 if ((bus_irq == 0) && (trigger == 3))
808 trigger = 1;
809
810 intsrc.mpc_type = MP_INTSRC;
811 intsrc.mpc_irqtype = mp_INT;
812 intsrc.mpc_irqflag = (trigger << 2) | polarity;
813 intsrc.mpc_srcbus = MP_ISA_BUS;
814 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
815 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
816 intsrc.mpc_dstirq = pin; /* INTIN# */
817
818 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
819 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
820 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
821 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
822
823 mp_irqs[mp_irq_entries] = intsrc;
824 if (++mp_irq_entries == MAX_IRQ_SOURCES)
825 panic("Max # of irq sources exceeded!\n");
826
827 return;
828 }
829
830
831 void __init mp_config_acpi_legacy_irqs (void)
832 {
833 struct mpc_config_intsrc intsrc;
834 int i = 0;
835 int ioapic = -1;
836
837 /*
838 * Fabricate the legacy ISA bus (bus #31).
839 */
840 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
841 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
842
843 /*
844 * Locate the IOAPIC that manages the ISA IRQs (0-15).
845 */
846 ioapic = mp_find_ioapic(0);
847 if (ioapic < 0)
848 return;
849
850 intsrc.mpc_type = MP_INTSRC;
851 intsrc.mpc_irqflag = 0; /* Conforming */
852 intsrc.mpc_srcbus = MP_ISA_BUS;
853 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
854
855 /*
856 * Use the default configuration for the IRQs 0-15. Unless
857 * overridden by (MADT) interrupt source override entries.
858 */
859 for (i = 0; i < 16; i++) {
860 int idx;
861
862 for (idx = 0; idx < mp_irq_entries; idx++) {
863 struct mpc_config_intsrc *irq = mp_irqs + idx;
864
865 /* Do we already have a mapping for this ISA IRQ? */
866 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
867 break;
868
869 /* Do we already have a mapping for this IOAPIC pin */
870 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
871 (irq->mpc_dstirq == i))
872 break;
873 }
874
875 if (idx != mp_irq_entries) {
876 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
877 continue; /* IRQ already used */
878 }
879
880 intsrc.mpc_irqtype = mp_INT;
881 intsrc.mpc_srcbusirq = i; /* Identity mapped */
882 intsrc.mpc_dstirq = i;
883
884 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
885 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
886 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
887 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
888 intsrc.mpc_dstirq);
889
890 mp_irqs[mp_irq_entries] = intsrc;
891 if (++mp_irq_entries == MAX_IRQ_SOURCES)
892 panic("Max # of irq sources exceeded!\n");
893 }
894
895 return;
896 }
897
898 int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
899 {
900 int ioapic = -1;
901 int ioapic_pin = 0;
902 int idx, bit = 0;
903
904 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
905 return gsi;
906
907 #ifdef CONFIG_ACPI_BUS
908 /* Don't set up the ACPI SCI because it's already set up */
909 if (acpi_fadt.sci_int == gsi)
910 return gsi;
911 #endif
912
913 ioapic = mp_find_ioapic(gsi);
914 if (ioapic < 0) {
915 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
916 return gsi;
917 }
918
919 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
920
921 /*
922 * Avoid pin reprogramming. PRTs typically include entries
923 * with redundant pin->gsi mappings (but unique PCI devices);
924 * we only program the IOAPIC on the first.
925 */
926 bit = ioapic_pin % 32;
927 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
928 if (idx > 3) {
929 printk(KERN_ERR "Invalid reference to IOAPIC pin "
930 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
931 ioapic_pin);
932 return gsi;
933 }
934 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
935 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
936 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
937 return gsi;
938 }
939
940 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
941
942 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
943 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
944 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
945 return gsi;
946 }
947
948 #endif /*CONFIG_X86_IO_APIC*/
949 #endif /*CONFIG_ACPI_BOOT*/
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