include/asm-i386/mach-summit/mach_apic.h

   1 #ifndef __ASM_MACH_APIC_H
   2 #define __ASM_MACH_APIC_H
   3
   4 #include <linux/config.h>
   5 #include <asm/smp.h>
   6
   7 #define esr_disable (1)
   8 #define NO_BALANCE_IRQ (0)
   9
  10 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  11  * The low nibble is a 4-bit bitmap. */
  12 #define XAPIC_DEST_CPUS_SHIFT   4
  13 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  14 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  15
  16 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  17
  18 static inline cpumask_t target_cpus(void)
  19 {
  20         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  21          * dest_LowestPrio mode logical clustered apic interrupt routing
  22          * Just start on cpu 0.  IRQ balancing will spread load
  23          */
  24         return cpumask_of_cpu(0);
  25 }
  26 #define TARGET_CPUS     (target_cpus())
  27
  28 #define INT_DELIVERY_MODE (dest_LowestPrio)
  29 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
  30
  31 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  32 {
  33         return 0;
  34 }
  35
  36 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  37 static inline unsigned long check_apicid_present(int bit)
  38 {
  39         return 1;
  40 }
  41
  42 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  43
  44 extern u8 bios_cpu_apicid[];
  45 extern u8 cpu_2_logical_apicid[];
  46
  47 static inline void init_apic_ldr(void)
  48 {
  49         unsigned long val, id;
  50         int i, count;
  51         u8 lid;
  52         u8 my_id = (u8)hard_smp_processor_id();
  53         u8 my_cluster = (u8)apicid_cluster(my_id);
  54
  55         /* Create logical APIC IDs by counting CPUs already in cluster. */
  56         for (count = 0, i = NR_CPUS; --i >= 0; ) {
  57                 lid = cpu_2_logical_apicid[i];
  58                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  59                         ++count;
  60         }
  61         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  62          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  63         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  64         id = my_cluster | (1UL << count);
  65         apic_write_around(APIC_DFR, APIC_DFR_VALUE);
  66         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  67         val |= SET_APIC_LOGICAL_ID(id);
  68         apic_write_around(APIC_LDR, val);
  69 }
  70
  71 static inline int multi_timer_check(int apic, int irq)
  72 {
  73         return 0;
  74 }
  75
  76 static inline int apic_id_registered(void)
  77 {
  78         return 1;
  79 }
  80
  81 static inline void clustered_apic_check(void)
  82 {
  83         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  84                                                 nr_ioapics);
  85 }
  86
  87 static inline int apicid_to_node(int logical_apicid)
  88 {
  89         return logical_apicid >> 5;          /* 2 clusterids per CEC */
  90 }
  91
  92 /* Mapping from cpu number to logical apicid */
  93 static inline int cpu_to_logical_apicid(int cpu)
  94 {
  95        if (cpu >= NR_CPUS)
  96                return BAD_APICID;
  97         return (int)cpu_2_logical_apicid[cpu];
  98 }
  99
 100 static inline int cpu_present_to_apicid(int mps_cpu)
 101 {
 102         if (mps_cpu < NR_CPUS)
 103                 return (int)bios_cpu_apicid[mps_cpu];
 104         else
 105                 return BAD_APICID;
 106 }
 107
 108 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 109 {
 110         /* For clustered we don't have a good way to do this yet - hack */
 111         return physids_promote(0x0F);
 112 }
 113
 114 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 115 {
 116         return physid_mask_of_physid(0);
 117 }
 118
 119 static inline int mpc_apic_id(struct mpc_config_processor *m,
 120                         struct mpc_config_translation *translation_record)
 121 {
 122         printk("Processor #%d %ld:%ld APIC version %d\n",
 123                         m->mpc_apicid,
 124                         (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
 125                         (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
 126                         m->mpc_apicver);
 127         return (m->mpc_apicid);
 128 }
 129
 130 static inline void setup_portio_remap(void)
 131 {
 132 }
 133
 134 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 135 {
 136         return 1;
 137 }
 138
 139 static inline void enable_apic_mode(void)
 140 {
 141 }
 142
 143 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 144 {
 145         int num_bits_set;
 146         int cpus_found = 0;
 147         int cpu;
 148         int apicid;
 149
 150         num_bits_set = cpus_weight(cpumask);
 151         /* Return id to all */
 152         if (num_bits_set == NR_CPUS)
 153                 return (int) 0xFF;
 154         /*
 155          * The cpus in the mask must all be on the apic cluster.  If are not
 156          * on the same apicid cluster return default value of TARGET_CPUS.
 157          */
 158         cpu = first_cpu(cpumask);
 159         apicid = cpu_to_logical_apicid(cpu);
 160         while (cpus_found < num_bits_set) {
 161                 if (cpu_isset(cpu, cpumask)) {
 162                         int new_apicid = cpu_to_logical_apicid(cpu);
 163                         if (apicid_cluster(apicid) !=
 164                                         apicid_cluster(new_apicid)){
 165                                 printk ("%s: Not a valid mask!\n",__FUNCTION__);
 166                                 return 0xFF;
 167                         }
 168                         apicid = apicid | new_apicid;
 169                         cpus_found++;
 170                 }
 171                 cpu++;
 172         }
 173         return apicid;
 174 }
 175
 176 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 177  * register's value.  For any box whose BIOS changes APIC IDs, like
 178  * clustered APIC systems, we must use hard_smp_processor_id.
 179  *
 180  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 181  */
 182 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 183 {
 184         return hard_smp_processor_id() >> index_msb;
 185 }
 186
 187 #endif /* __ASM_MACH_APIC_H */