arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c

   1 /*
   2  * (C) 2004  Sebastian Witt <se.witt@gmx.net>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *  Based upon reverse engineered information
   6  *
   7  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17
  18 #define NFORCE2_XTAL 25
  19 #define NFORCE2_BOOTFSB 0x48
  20 #define NFORCE2_PLLENABLE 0xa8
  21 #define NFORCE2_PLLREG 0xa4
  22 #define NFORCE2_PLLADR 0xa0
  23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
  24
  25 #define NFORCE2_MIN_FSB 50
  26 #define NFORCE2_SAFE_DISTANCE 50
  27
  28 /* Delay in ms between FSB changes */
  29 //#define NFORCE2_DELAY 10
  30
  31 /* nforce2_chipset:
  32  * FSB is changed using the chipset
  33  */
  34 static struct pci_dev *nforce2_chipset_dev;
  35
  36 /* fid:
  37  * multiplier * 10
  38  */
  39 static int fid = 0;
  40
  41 /* min_fsb, max_fsb:
  42  * minimum and maximum FSB (= FSB at boot time)
  43  */
  44 static int min_fsb = 0;
  45 static int max_fsb = 0;
  46
  47 MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
  48 MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
  49 MODULE_LICENSE("GPL");
  50
  51 module_param(fid, int, 0444);
  52 module_param(min_fsb, int, 0444);
  53
  54 MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
  55 MODULE_PARM_DESC(min_fsb,
  56                  "Minimum FSB to use, if not defined: current FSB - 50");
  57
  58 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
  59
  60 /*
  61  * nforce2_calc_fsb - calculate FSB
  62  * @pll: PLL value
  63  *
  64  *   Calculates FSB from PLL value
  65  */
  66 static int nforce2_calc_fsb(int pll)
  67 {
  68         unsigned char mul, div;
  69
  70         mul = (pll >> 8) & 0xff;
  71         div = pll & 0xff;
  72
  73         if (div > 0)
  74                 return NFORCE2_XTAL * mul / div;
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * nforce2_calc_pll - calculate PLL value
  81  * @fsb: FSB
  82  *
  83  *   Calculate PLL value for given FSB
  84  */
  85 static int nforce2_calc_pll(unsigned int fsb)
  86 {
  87         unsigned char xmul, xdiv;
  88         unsigned char mul = 0, div = 0;
  89         int tried = 0;
  90
  91         /* Try to calculate multiplier and divider up to 4 times */
  92         while (((mul == 0) || (div == 0)) && (tried <= 3)) {
  93                 for (xdiv = 1; xdiv <= 0x80; xdiv++)
  94                         for (xmul = 1; xmul <= 0xfe; xmul++)
  95                                 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
  96                                     fsb + tried) {
  97                                         mul = xmul;
  98                                         div = xdiv;
  99                                 }
 100                 tried++;
 101         }
 102
 103         if ((mul == 0) || (div == 0))
 104                 return -1;
 105
 106         return NFORCE2_PLL(mul, div);
 107 }
 108
 109 /*
 110  * nforce2_write_pll - write PLL value to chipset
 111  * @pll: PLL value
 112  *
 113  *   Writes new FSB PLL value to chipset
 114  */
 115 static void nforce2_write_pll(int pll)
 116 {
 117         int temp;
 118
 119         /* Set the pll addr. to 0x00 */
 120         temp = 0x00;
 121         pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
 122
 123         /* Now write the value in all 64 registers */
 124         for (temp = 0; temp <= 0x3f; temp++) {
 125                 pci_write_config_dword(nforce2_chipset_dev,
 126                                        NFORCE2_PLLREG, pll);
 127         }
 128
 129         return;
 130 }
 131
 132 /*
 133  * nforce2_fsb_read - Read FSB
 134  *
 135  *   Read FSB from chipset
 136  *   If bootfsb != 0, return FSB at boot-time
 137  */
 138 static unsigned int nforce2_fsb_read(int bootfsb)
 139 {
 140         struct pci_dev *nforce2_sub5;
 141         u32 fsb, temp = 0;
 142
 143
 144         /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
 145         nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 146                                       0x01EF,
 147                                       PCI_ANY_ID,
 148                                       PCI_ANY_ID,
 149                                       NULL);
 150
 151         if (!nforce2_sub5)
 152                 return 0;
 153
 154         pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
 155         fsb /= 1000000;
 156
 157         /* Check if PLL register is already set */
 158         pci_read_config_byte(nforce2_chipset_dev,
 159                              NFORCE2_PLLENABLE, (u8 *)&temp);
 160
 161         if(bootfsb || !temp)
 162                 return fsb;
 163
 164         /* Use PLL register FSB value */
 165         pci_read_config_dword(nforce2_chipset_dev,
 166                               NFORCE2_PLLREG, &temp);
 167         fsb = nforce2_calc_fsb(temp);
 168
 169         return fsb;
 170 }
 171
 172 /*
 173  * nforce2_set_fsb - set new FSB
 174  * @fsb: New FSB
 175  *
 176  *   Sets new FSB
 177  */
 178 static int nforce2_set_fsb(unsigned int fsb)
 179 {
 180         u32 pll, temp = 0;
 181         unsigned int tfsb;
 182         int diff;
 183
 184         if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
 185                 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
 186                 return -EINVAL;
 187         }
 188
 189         tfsb = nforce2_fsb_read(0);
 190         if (!tfsb) {
 191                 printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
 192                 return -EINVAL;
 193         }
 194
 195         /* First write? Then set actual value */
 196         pci_read_config_byte(nforce2_chipset_dev,
 197                              NFORCE2_PLLENABLE, (u8 *)&temp);
 198         if (!temp) {
 199                 pll = nforce2_calc_pll(tfsb);
 200
 201                 if (pll < 0)
 202                         return -EINVAL;
 203
 204                 nforce2_write_pll(pll);
 205         }
 206
 207         /* Enable write access */
 208         temp = 0x01;
 209         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8)temp);
 210
 211         diff = tfsb - fsb;
 212
 213         if (!diff)
 214                 return 0;
 215
 216         while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
 217                 if (diff < 0)
 218                         tfsb++;
 219                 else
 220                         tfsb--;
 221
 222                 /* Calculate the PLL reg. value */
 223                 if ((pll = nforce2_calc_pll(tfsb)) == -1)
 224                         return -EINVAL;
 225
 226                 nforce2_write_pll(pll);
 227 #ifdef NFORCE2_DELAY
 228                 mdelay(NFORCE2_DELAY);
 229 #endif
 230         }
 231
 232         temp = 0x40;
 233         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLADR, (u8)temp);
 234
 235         return 0;
 236 }
 237
 238 /**
 239  * nforce2_get - get the CPU frequency
 240  * @cpu: CPU number
 241  *
 242  * Returns the CPU frequency
 243  */
 244 static unsigned int nforce2_get(unsigned int cpu)
 245 {
 246         if (cpu)
 247                 return 0;
 248         return nforce2_fsb_read(0) * fid * 100;
 249 }
 250
 251 /**
 252  * nforce2_target - set a new CPUFreq policy
 253  * @policy: new policy
 254  * @target_freq: the target frequency
 255  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 256  *
 257  * Sets a new CPUFreq policy.
 258  */
 259 static int nforce2_target(struct cpufreq_policy *policy,
 260                           unsigned int target_freq, unsigned int relation)
 261 {
 262 //        unsigned long         flags;
 263         struct cpufreq_freqs freqs;
 264         unsigned int target_fsb;
 265
 266         if ((target_freq > policy->max) || (target_freq < policy->min))
 267                 return -EINVAL;
 268
 269         target_fsb = target_freq / (fid * 100);
 270
 271         freqs.old = nforce2_get(policy->cpu);
 272         freqs.new = target_fsb * fid * 100;
 273         freqs.cpu = 0;          /* Only one CPU on nForce2 plattforms */
 274
 275         if (freqs.old == freqs.new)
 276                 return 0;
 277
 278         dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n",
 279                freqs.old, freqs.new);
 280
 281         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 282
 283         /* Disable IRQs */
 284         //local_irq_save(flags);
 285
 286         if (nforce2_set_fsb(target_fsb) < 0)
 287                 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
 288                        target_fsb);
 289         else
 290                 dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n",
 291                        target_fsb);
 292
 293         /* Enable IRQs */
 294         //local_irq_restore(flags);
 295
 296         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 297
 298         return 0;
 299 }
 300
 301 /**
 302  * nforce2_verify - verifies a new CPUFreq policy
 303  * @policy: new policy
 304  */
 305 static int nforce2_verify(struct cpufreq_policy *policy)
 306 {
 307         unsigned int fsb_pol_max;
 308
 309         fsb_pol_max = policy->max / (fid * 100);
 310
 311         if (policy->min < (fsb_pol_max * fid * 100))
 312                 policy->max = (fsb_pol_max + 1) * fid * 100;
 313
 314         cpufreq_verify_within_limits(policy,
 315                                      policy->cpuinfo.min_freq,
 316                                      policy->cpuinfo.max_freq);
 317         return 0;
 318 }
 319
 320 static int nforce2_cpu_init(struct cpufreq_policy *policy)
 321 {
 322         unsigned int fsb;
 323         unsigned int rfid;
 324
 325         /* capability check */
 326         if (policy->cpu != 0)
 327                 return -ENODEV;
 328
 329         /* Get current FSB */
 330         fsb = nforce2_fsb_read(0);
 331
 332         if (!fsb)
 333                 return -EIO;
 334
 335         /* FIX: Get FID from CPU */
 336         if (!fid) {
 337                 if (!cpu_khz) {
 338                         printk(KERN_WARNING
 339                                "cpufreq: cpu_khz not set, can't calculate multiplier!\n");
 340                         return -ENODEV;
 341                 }
 342
 343                 fid = cpu_khz / (fsb * 100);
 344                 rfid = fid % 5;
 345
 346                 if (rfid) {
 347                         if (rfid > 2)
 348                                 fid += 5 - rfid;
 349                         else
 350                                 fid -= rfid;
 351                 }
 352         }
 353
 354         printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
 355                fid / 10, fid % 10);
 356
 357         /* Set maximum FSB to FSB at boot time */
 358         max_fsb = nforce2_fsb_read(1);
 359
 360         if(!max_fsb)
 361                 return -EIO;
 362
 363         if (!min_fsb)
 364                 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
 365
 366         if (min_fsb < NFORCE2_MIN_FSB)
 367                 min_fsb = NFORCE2_MIN_FSB;
 368
 369         /* cpuinfo and default policy values */
 370         policy->cpuinfo.min_freq = min_fsb * fid * 100;
 371         policy->cpuinfo.max_freq = max_fsb * fid * 100;
 372         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 373         policy->cur = nforce2_get(policy->cpu);
 374         policy->min = policy->cpuinfo.min_freq;
 375         policy->max = policy->cpuinfo.max_freq;
 376         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 377
 378         return 0;
 379 }
 380
 381 static int nforce2_cpu_exit(struct cpufreq_policy *policy)
 382 {
 383         return 0;
 384 }
 385
 386 static struct cpufreq_driver nforce2_driver = {
 387         .name = "nforce2",
 388         .verify = nforce2_verify,
 389         .target = nforce2_target,
 390         .get = nforce2_get,
 391         .init = nforce2_cpu_init,
 392         .exit = nforce2_cpu_exit,
 393         .owner = THIS_MODULE,
 394 };
 395
 396 /**
 397  * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 398  *
 399  * Detects nForce2 A2 and C1 stepping
 400  *
 401  */
 402 static unsigned int nforce2_detect_chipset(void)
 403 {
 404         u8 revision;
 405
 406         nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 407                                              PCI_DEVICE_ID_NVIDIA_NFORCE2,
 408                                              PCI_ANY_ID,
 409                                              PCI_ANY_ID,
 410                                              NULL);
 411
 412         if (nforce2_chipset_dev == NULL)
 413                 return -ENODEV;
 414
 415         pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);
 416
 417         printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
 418                revision);
 419         printk(KERN_INFO
 420                "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
 421
 422         return 0;
 423 }
 424
 425 /**
 426  * nforce2_init - initializes the nForce2 CPUFreq driver
 427  *
 428  * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 429  * devices, -EINVAL on problems during initiatization, and zero on
 430  * success.
 431  */
 432 static int __init nforce2_init(void)
 433 {
 434         /* TODO: do we need to detect the processor? */
 435
 436         /* detect chipset */
 437         if (nforce2_detect_chipset()) {
 438                 printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
 439                 return -ENODEV;
 440         }
 441
 442         return cpufreq_register_driver(&nforce2_driver);
 443 }
 444
 445 /**
 446  * nforce2_exit - unregisters cpufreq module
 447  *
 448  *   Unregisters nForce2 FSB change support.
 449  */
 450 static void __exit nforce2_exit(void)
 451 {
 452         cpufreq_unregister_driver(&nforce2_driver);
 453 }
 454
 455 module_init(nforce2_init);
 456 module_exit(nforce2_exit);
 457