arch/ia64/sn/pci/pci_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
   7  *
   8  * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
   9  * a description of how these routines should be used.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <asm/dma.h>
  14 #include <asm/sn/pcibr_provider.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17 #include <asm/sn/sn_sal.h>
  18
  19 #define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
  20 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
  21
  22 /**
  23  * sn_dma_supported - test a DMA mask
  24  * @dev: device to test
  25  * @mask: DMA mask to test
  26  *
  27  * Return whether the given PCI device DMA address mask can be supported
  28  * properly.  For example, if your device can only drive the low 24-bits
  29  * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
  30  * this function.  Of course, SN only supports devices that have 32 or more
  31  * address bits when using the PMU.
  32  */
  33 int sn_dma_supported(struct device *dev, u64 mask)
  34 {
  35         BUG_ON(dev->bus != &pci_bus_type);
  36
  37         if (mask < 0x7fffffff)
  38                 return 0;
  39         return 1;
  40 }
  41 EXPORT_SYMBOL(sn_dma_supported);
  42
  43 /**
  44  * sn_dma_set_mask - set the DMA mask
  45  * @dev: device to set
  46  * @dma_mask: new mask
  47  *
  48  * Set @dev's DMA mask if the hw supports it.
  49  */
  50 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
  51 {
  52         BUG_ON(dev->bus != &pci_bus_type);
  53
  54         if (!sn_dma_supported(dev, dma_mask))
  55                 return 0;
  56
  57         *dev->dma_mask = dma_mask;
  58         return 1;
  59 }
  60 EXPORT_SYMBOL(sn_dma_set_mask);
  61
  62 /**
  63  * sn_dma_alloc_coherent - allocate memory for coherent DMA
  64  * @dev: device to allocate for
  65  * @size: size of the region
  66  * @dma_handle: DMA (bus) address
  67  * @flags: memory allocation flags
  68  *
  69  * dma_alloc_coherent() returns a pointer to a memory region suitable for
  70  * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
  71  * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
  72  *
  73  * This interface is usually used for "command" streams (e.g. the command
  74  * queue for a SCSI controller).  See Documentation/DMA-API.txt for
  75  * more information.
  76  */
  77 void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  78                             dma_addr_t * dma_handle, gfp_t flags)
  79 {
  80         void *cpuaddr;
  81         unsigned long phys_addr;
  82         int node;
  83         struct pci_dev *pdev = to_pci_dev(dev);
  84         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
  85
  86         BUG_ON(dev->bus != &pci_bus_type);
  87
  88         /*
  89          * Allocate the memory.
  90          */
  91         node = pcibus_to_node(pdev->bus);
  92         if (likely(node >=0)) {
  93                 struct page *p = alloc_pages_node(node, GFP_ATOMIC, get_order(size));
  94
  95                 if (likely(p))
  96                         cpuaddr = page_address(p);
  97                 else
  98                         return NULL;
  99         } else
 100                 cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size));
 101
 102         if (unlikely(!cpuaddr))
 103                 return NULL;
 104
 105         memset(cpuaddr, 0x0, size);
 106
 107         /* physical addr. of the memory we just got */
 108         phys_addr = __pa(cpuaddr);
 109
 110         /*
 111          * 64 bit address translations should never fail.
 112          * 32 bit translations can fail if there are insufficient mapping
 113          * resources.
 114          */
 115
 116         *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size);
 117         if (!*dma_handle) {
 118                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 119                 free_pages((unsigned long)cpuaddr, get_order(size));
 120                 return NULL;
 121         }
 122
 123         return cpuaddr;
 124 }
 125 EXPORT_SYMBOL(sn_dma_alloc_coherent);
 126
 127 /**
 128  * sn_pci_free_coherent - free memory associated with coherent DMAable region
 129  * @dev: device to free for
 130  * @size: size to free
 131  * @cpu_addr: kernel virtual address to free
 132  * @dma_handle: DMA address associated with this region
 133  *
 134  * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 135  * any associated IOMMU mappings.
 136  */
 137 void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
 138                           dma_addr_t dma_handle)
 139 {
 140         struct pci_dev *pdev = to_pci_dev(dev);
 141         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 142
 143         BUG_ON(dev->bus != &pci_bus_type);
 144
 145         provider->dma_unmap(pdev, dma_handle, 0);
 146         free_pages((unsigned long)cpu_addr, get_order(size));
 147 }
 148 EXPORT_SYMBOL(sn_dma_free_coherent);
 149
 150 /**
 151  * sn_dma_map_single - map a single page for DMA
 152  * @dev: device to map for
 153  * @cpu_addr: kernel virtual address of the region to map
 154  * @size: size of the region
 155  * @direction: DMA direction
 156  *
 157  * Map the region pointed to by @cpu_addr for DMA and return the
 158  * DMA address.
 159  *
 160  * We map this to the one step pcibr_dmamap_trans interface rather than
 161  * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 162  * no way of saving the dmamap handle from the alloc to later free
 163  * (which is pretty much unacceptable).
 164  *
 165  * TODO: simplify our interface;
 166  *       figure out how to save dmamap handle so can use two step.
 167  */
 168 dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
 169                              int direction)
 170 {
 171         dma_addr_t dma_addr;
 172         unsigned long phys_addr;
 173         struct pci_dev *pdev = to_pci_dev(dev);
 174         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 175
 176         BUG_ON(dev->bus != &pci_bus_type);
 177
 178         phys_addr = __pa(cpu_addr);
 179         dma_addr = provider->dma_map(pdev, phys_addr, size);
 180         if (!dma_addr) {
 181                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 182                 return 0;
 183         }
 184         return dma_addr;
 185 }
 186 EXPORT_SYMBOL(sn_dma_map_single);
 187
 188 /**
 189  * sn_dma_unmap_single - unamp a DMA mapped page
 190  * @dev: device to sync
 191  * @dma_addr: DMA address to sync
 192  * @size: size of region
 193  * @direction: DMA direction
 194  *
 195  * This routine is supposed to sync the DMA region specified
 196  * by @dma_handle into the coherence domain.  On SN, we're always cache
 197  * coherent, so we just need to free any ATEs associated with this mapping.
 198  */
 199 void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 200                          int direction)
 201 {
 202         struct pci_dev *pdev = to_pci_dev(dev);
 203         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 204
 205         BUG_ON(dev->bus != &pci_bus_type);
 206
 207         provider->dma_unmap(pdev, dma_addr, direction);
 208 }
 209 EXPORT_SYMBOL(sn_dma_unmap_single);
 210
 211 /**
 212  * sn_dma_unmap_sg - unmap a DMA scatterlist
 213  * @dev: device to unmap
 214  * @sg: scatterlist to unmap
 215  * @nhwentries: number of scatterlist entries
 216  * @direction: DMA direction
 217  *
 218  * Unmap a set of streaming mode DMA translations.
 219  */
 220 void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 221                      int nhwentries, int direction)
 222 {
 223         int i;
 224         struct pci_dev *pdev = to_pci_dev(dev);
 225         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 226
 227         BUG_ON(dev->bus != &pci_bus_type);
 228
 229         for (i = 0; i < nhwentries; i++, sg++) {
 230                 provider->dma_unmap(pdev, sg->dma_address, direction);
 231                 sg->dma_address = (dma_addr_t) NULL;
 232                 sg->dma_length = 0;
 233         }
 234 }
 235 EXPORT_SYMBOL(sn_dma_unmap_sg);
 236
 237 /**
 238  * sn_dma_map_sg - map a scatterlist for DMA
 239  * @dev: device to map for
 240  * @sg: scatterlist to map
 241  * @nhwentries: number of entries
 242  * @direction: direction of the DMA transaction
 243  *
 244  * Maps each entry of @sg for DMA.
 245  */
 246 int sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
 247                   int direction)
 248 {
 249         unsigned long phys_addr;
 250         struct scatterlist *saved_sg = sg;
 251         struct pci_dev *pdev = to_pci_dev(dev);
 252         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 253         int i;
 254
 255         BUG_ON(dev->bus != &pci_bus_type);
 256
 257         /*
 258          * Setup a DMA address for each entry in the scatterlist.
 259          */
 260         for (i = 0; i < nhwentries; i++, sg++) {
 261                 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
 262                 sg->dma_address = provider->dma_map(pdev,
 263                                                     phys_addr, sg->length);
 264
 265                 if (!sg->dma_address) {
 266                         printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 267
 268                         /*
 269                          * Free any successfully allocated entries.
 270                          */
 271                         if (i > 0)
 272                                 sn_dma_unmap_sg(dev, saved_sg, i, direction);
 273                         return 0;
 274                 }
 275
 276                 sg->dma_length = sg->length;
 277         }
 278
 279         return nhwentries;
 280 }
 281 EXPORT_SYMBOL(sn_dma_map_sg);
 282
 283 void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 284                                 size_t size, int direction)
 285 {
 286         BUG_ON(dev->bus != &pci_bus_type);
 287 }
 288 EXPORT_SYMBOL(sn_dma_sync_single_for_cpu);
 289
 290 void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 291                                    size_t size, int direction)
 292 {
 293         BUG_ON(dev->bus != &pci_bus_type);
 294 }
 295 EXPORT_SYMBOL(sn_dma_sync_single_for_device);
 296
 297 void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 298                             int nelems, int direction)
 299 {
 300         BUG_ON(dev->bus != &pci_bus_type);
 301 }
 302 EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu);
 303
 304 void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 305                                int nelems, int direction)
 306 {
 307         BUG_ON(dev->bus != &pci_bus_type);
 308 }
 309 EXPORT_SYMBOL(sn_dma_sync_sg_for_device);
 310
 311 int sn_dma_mapping_error(dma_addr_t dma_addr)
 312 {
 313         return 0;
 314 }
 315 EXPORT_SYMBOL(sn_dma_mapping_error);
 316
 317 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
 318 {
 319         if (!SN_PCIBUS_BUSSOFT(bus))
 320                 return ERR_PTR(-ENODEV);
 321
 322         return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
 323 }
 324
 325 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 326 {
 327         unsigned long addr;
 328         int ret;
 329         struct ia64_sal_retval isrv;
 330
 331         /*
 332          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 333          * around hw issues at the pci bus level.  SGI proms older than
 334          * 4.10 don't implment this.
 335          */
 336
 337         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 338                 pci_domain_nr(bus), bus->number,
 339                 0, /* io */
 340                 0, /* read */
 341                 port, size, __pa(val));
 342
 343         if (isrv.status == 0)
 344                 return size;
 345
 346         /*
 347          * If the above failed, retry using the SAL_PROBE call which should
 348          * be present in all proms (but which cannot work round PCI chipset
 349          * bugs).  This code is retained for compatability with old
 350          * pre-4.10 proms, and should be removed at some point in the future.
 351          */
 352
 353         if (!SN_PCIBUS_BUSSOFT(bus))
 354                 return -ENODEV;
 355
 356         addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 357         addr += port;
 358
 359         ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
 360
 361         if (ret == 2)
 362                 return -EINVAL;
 363
 364         if (ret == 1)
 365                 *val = -1;
 366
 367         return size;
 368 }
 369
 370 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 371 {
 372         int ret = size;
 373         unsigned long paddr;
 374         unsigned long *addr;
 375         struct ia64_sal_retval isrv;
 376
 377         /*
 378          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 379          * around hw issues at the pci bus level.  SGI proms older than
 380          * 4.10 don't implment this.
 381          */
 382
 383         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 384                 pci_domain_nr(bus), bus->number,
 385                 0, /* io */
 386                 1, /* write */
 387                 port, size, __pa(&val));
 388
 389         if (isrv.status == 0)
 390                 return size;
 391
 392         /*
 393          * If the above failed, retry using the SAL_PROBE call which should
 394          * be present in all proms (but which cannot work round PCI chipset
 395          * bugs).  This code is retained for compatability with old
 396          * pre-4.10 proms, and should be removed at some point in the future.
 397          */
 398
 399         if (!SN_PCIBUS_BUSSOFT(bus)) {
 400                 ret = -ENODEV;
 401                 goto out;
 402         }
 403
 404         /* Put the phys addr in uncached space */
 405         paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 406         paddr += port;
 407         addr = (unsigned long *)paddr;
 408
 409         switch (size) {
 410         case 1:
 411                 *(volatile u8 *)(addr) = (u8)(val);
 412                 break;
 413         case 2:
 414                 *(volatile u16 *)(addr) = (u16)(val);
 415                 break;
 416         case 4:
 417                 *(volatile u32 *)(addr) = (u32)(val);
 418                 break;
 419         default:
 420                 ret = -EINVAL;
 421                 break;
 422         }
 423  out:
 424         return ret;
 425 }