arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   6  * traditional SpeedStep.
   7  *
   8  * Modelled on speedstep.c
   9  *
  10  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  11  *
  12  * WARNING WARNING WARNING
  13  *
  14  * This driver manipulates the PERF_CTL MSR, which is only somewhat
  15  * documented.  While it seems to work on my laptop, it has not been
  16  * tested anywhere else, and it may not work for you, do strange
  17  * things or simply crash.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/config.h>
  25 #include <linux/sched.h>        /* current */
  26 #include <linux/delay.h>
  27 #include <linux/compiler.h>
  28
  29 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
  30 #include <linux/acpi.h>
  31 #include <acpi/processor.h>
  32 #endif
  33
  34 #include <asm/msr.h>
  35 #include <asm/processor.h>
  36 #include <asm/cpufeature.h>
  37
  38 #define PFX             "speedstep-centrino: "
  39 #define MAINTAINER      "Jeremy Fitzhardinge <jeremy@goop.org>"
  40
  41 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  42
  43
  44 struct cpu_id
  45 {
  46         __u8    x86;            /* CPU family */
  47         __u8    x86_model;      /* model */
  48         __u8    x86_mask;       /* stepping */
  49 };
  50
  51 enum {
  52         CPU_BANIAS,
  53         CPU_DOTHAN_A1,
  54         CPU_DOTHAN_A2,
  55         CPU_DOTHAN_B0,
  56         CPU_MP4HT_D0,
  57         CPU_MP4HT_E0,
  58 };
  59
  60 static const struct cpu_id cpu_ids[] = {
  61         [CPU_BANIAS]    = { 6,  9, 5 },
  62         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  63         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  64         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  65         [CPU_MP4HT_D0]  = {15,  3, 4 },
  66         [CPU_MP4HT_E0]  = {15,  4, 1 },
  67 };
  68 #define N_IDS   ARRAY_SIZE(cpu_ids)
  69
  70 struct cpu_model
  71 {
  72         const struct cpu_id *cpu_id;
  73         const char      *model_name;
  74         unsigned        max_freq; /* max clock in kHz */
  75
  76         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  77 };
  78 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
  79
  80 /* Operating points for current CPU */
  81 static struct cpu_model *centrino_model[NR_CPUS];
  82 static const struct cpu_id *centrino_cpu[NR_CPUS];
  83
  84 static struct cpufreq_driver centrino_driver;
  85
  86 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  87
  88 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  89    frequency/voltage operating point; frequency in MHz, volts in mV.
  90    This is stored as "index" in the structure. */
  91 #define OP(mhz, mv)                                                     \
  92         {                                                               \
  93                 .frequency = (mhz) * 1000,                              \
  94                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  95         }
  96
  97 /*
  98  * These voltage tables were derived from the Intel Pentium M
  99  * datasheet, document 25261202.pdf, Table 5.  I have verified they
 100  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
 101  * M.
 102  */
 103
 104 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
 105 static struct cpufreq_frequency_table banias_900[] =
 106 {
 107         OP(600,  844),
 108         OP(800,  988),
 109         OP(900, 1004),
 110         { .frequency = CPUFREQ_TABLE_END }
 111 };
 112
 113 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 114 static struct cpufreq_frequency_table banias_1000[] =
 115 {
 116         OP(600,   844),
 117         OP(800,   972),
 118         OP(900,   988),
 119         OP(1000, 1004),
 120         { .frequency = CPUFREQ_TABLE_END }
 121 };
 122
 123 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 124 static struct cpufreq_frequency_table banias_1100[] =
 125 {
 126         OP( 600,  956),
 127         OP( 800, 1020),
 128         OP( 900, 1100),
 129         OP(1000, 1164),
 130         OP(1100, 1180),
 131         { .frequency = CPUFREQ_TABLE_END }
 132 };
 133
 134
 135 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 136 static struct cpufreq_frequency_table banias_1200[] =
 137 {
 138         OP( 600,  956),
 139         OP( 800, 1004),
 140         OP( 900, 1020),
 141         OP(1000, 1100),
 142         OP(1100, 1164),
 143         OP(1200, 1180),
 144         { .frequency = CPUFREQ_TABLE_END }
 145 };
 146
 147 /* Intel Pentium M processor 1.30GHz (Banias) */
 148 static struct cpufreq_frequency_table banias_1300[] =
 149 {
 150         OP( 600,  956),
 151         OP( 800, 1260),
 152         OP(1000, 1292),
 153         OP(1200, 1356),
 154         OP(1300, 1388),
 155         { .frequency = CPUFREQ_TABLE_END }
 156 };
 157
 158 /* Intel Pentium M processor 1.40GHz (Banias) */
 159 static struct cpufreq_frequency_table banias_1400[] =
 160 {
 161         OP( 600,  956),
 162         OP( 800, 1180),
 163         OP(1000, 1308),
 164         OP(1200, 1436),
 165         OP(1400, 1484),
 166         { .frequency = CPUFREQ_TABLE_END }
 167 };
 168
 169 /* Intel Pentium M processor 1.50GHz (Banias) */
 170 static struct cpufreq_frequency_table banias_1500[] =
 171 {
 172         OP( 600,  956),
 173         OP( 800, 1116),
 174         OP(1000, 1228),
 175         OP(1200, 1356),
 176         OP(1400, 1452),
 177         OP(1500, 1484),
 178         { .frequency = CPUFREQ_TABLE_END }
 179 };
 180
 181 /* Intel Pentium M processor 1.60GHz (Banias) */
 182 static struct cpufreq_frequency_table banias_1600[] =
 183 {
 184         OP( 600,  956),
 185         OP( 800, 1036),
 186         OP(1000, 1164),
 187         OP(1200, 1276),
 188         OP(1400, 1420),
 189         OP(1600, 1484),
 190         { .frequency = CPUFREQ_TABLE_END }
 191 };
 192
 193 /* Intel Pentium M processor 1.70GHz (Banias) */
 194 static struct cpufreq_frequency_table banias_1700[] =
 195 {
 196         OP( 600,  956),
 197         OP( 800, 1004),
 198         OP(1000, 1116),
 199         OP(1200, 1228),
 200         OP(1400, 1308),
 201         OP(1700, 1484),
 202         { .frequency = CPUFREQ_TABLE_END }
 203 };
 204 #undef OP
 205
 206 #define _BANIAS(cpuid, max, name)       \
 207 {       .cpu_id         = cpuid,        \
 208         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 209         .max_freq       = (max)*1000,   \
 210         .op_points      = banias_##max, \
 211 }
 212 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 213
 214 /* CPU models, their operating frequency range, and freq/voltage
 215    operating points */
 216 static struct cpu_model models[] =
 217 {
 218         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 219         BANIAS(1000),
 220         BANIAS(1100),
 221         BANIAS(1200),
 222         BANIAS(1300),
 223         BANIAS(1400),
 224         BANIAS(1500),
 225         BANIAS(1600),
 226         BANIAS(1700),
 227
 228         /* NULL model_name is a wildcard */
 229         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 230         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 231         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 232         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 233         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 234
 235         { NULL, }
 236 };
 237 #undef _BANIAS
 238 #undef BANIAS
 239
 240 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 241 {
 242         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 243         struct cpu_model *model;
 244
 245         for(model = models; model->cpu_id != NULL; model++)
 246                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 247                     (model->model_name == NULL ||
 248                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 249                         break;
 250
 251         if (model->cpu_id == NULL) {
 252                 /* No match at all */
 253                 dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
 254                        "send /proc/cpuinfo to " MAINTAINER "\n",
 255                        cpu->x86_model_id);
 256                 return -ENOENT;
 257         }
 258
 259         if (model->op_points == NULL) {
 260                 /* Matched a non-match */
 261                 dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n",
 262                        cpu->x86_model_id);
 263 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 264                 dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
 265 #endif
 266                 return -ENOENT;
 267         }
 268
 269         centrino_model[policy->cpu] = model;
 270
 271         dprintk("found \"%s\": max frequency: %dkHz\n",
 272                model->model_name, model->max_freq);
 273
 274         return 0;
 275 }
 276
 277 #else
 278 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
 279 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 280
 281 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
 282 {
 283         if ((c->x86 == x->x86) &&
 284             (c->x86_model == x->x86_model) &&
 285             (c->x86_mask == x->x86_mask))
 286                 return 1;
 287         return 0;
 288 }
 289
 290 /* To be called only after centrino_model is initialized */
 291 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 292 {
 293         int i;
 294
 295         /*
 296          * Extract clock in kHz from PERF_CTL value
 297          * for centrino, as some DSDTs are buggy.
 298          * Ideally, this can be done using the acpi_data structure.
 299          */
 300         if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
 301             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
 302             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
 303                 msr = (msr >> 8) & 0xff;
 304                 return msr * 100000;
 305         }
 306
 307         if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
 308                 return 0;
 309
 310         msr &= 0xffff;
 311         for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
 312                 if (msr == centrino_model[cpu]->op_points[i].index)
 313                         return centrino_model[cpu]->op_points[i].frequency;
 314         }
 315         if (failsafe)
 316                 return centrino_model[cpu]->op_points[i-1].frequency;
 317         else
 318                 return 0;
 319 }
 320
 321 /* Return the current CPU frequency in kHz */
 322 static unsigned int get_cur_freq(unsigned int cpu)
 323 {
 324         unsigned l, h;
 325         unsigned clock_freq;
 326         cpumask_t saved_mask;
 327
 328         saved_mask = current->cpus_allowed;
 329         set_cpus_allowed(current, cpumask_of_cpu(cpu));
 330         if (smp_processor_id() != cpu)
 331                 return 0;
 332
 333         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 334         clock_freq = extract_clock(l, cpu, 0);
 335
 336         if (unlikely(clock_freq == 0)) {
 337                 /*
 338                  * On some CPUs, we can see transient MSR values (which are
 339                  * not present in _PSS), while CPU is doing some automatic
 340                  * P-state transition (like TM2). Get the last freq set
 341                  * in PERF_CTL.
 342                  */
 343                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 344                 clock_freq = extract_clock(l, cpu, 1);
 345         }
 346
 347         set_cpus_allowed(current, saved_mask);
 348         return clock_freq;
 349 }
 350
 351
 352 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 353
 354 static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
 355
 356 /*
 357  * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
 358  * library
 359  *
 360  * Before doing the actual init, we need to do _PSD related setup whenever
 361  * supported by the BIOS. These are handled by this early_init routine.
 362  */
 363 static int centrino_cpu_early_init_acpi(void)
 364 {
 365         unsigned int    i, j;
 366         struct acpi_processor_performance       *data;
 367
 368         for_each_cpu(i) {
 369                 data = kzalloc(sizeof(struct acpi_processor_performance),
 370                                 GFP_KERNEL);
 371                 if (!data) {
 372                         for_each_cpu(j) {
 373                                 kfree(acpi_perf_data[j]);
 374                                 acpi_perf_data[j] = NULL;
 375                         }
 376                         return (-ENOMEM);
 377                 }
 378                 acpi_perf_data[i] = data;
 379         }
 380
 381         acpi_processor_preregister_performance(acpi_perf_data);
 382         return 0;
 383 }
 384
 385 /*
 386  * centrino_cpu_init_acpi - register with ACPI P-States library
 387  *
 388  * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
 389  * in order to determine correct frequency and voltage pairings by reading
 390  * the _PSS of the ACPI DSDT or SSDT tables.
 391  */
 392 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
 393 {
 394         unsigned long                   cur_freq;
 395         int                             result = 0, i;
 396         unsigned int                    cpu = policy->cpu;
 397         struct acpi_processor_performance       *p;
 398
 399         p = acpi_perf_data[cpu];
 400
 401         /* register with ACPI core */
 402         if (acpi_processor_register_performance(p, cpu)) {
 403                 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
 404                 return -EIO;
 405         }
 406         policy->cpus = p->shared_cpu_map;
 407         policy->shared_type = p->shared_type;
 408
 409         /* verify the acpi_data */
 410         if (p->state_count <= 1) {
 411                 dprintk("No P-States\n");
 412                 result = -ENODEV;
 413                 goto err_unreg;
 414         }
 415
 416         if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
 417             (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 418                 dprintk("Invalid control/status registers (%x - %x)\n",
 419                         p->control_register.space_id, p->status_register.space_id);
 420                 result = -EIO;
 421                 goto err_unreg;
 422         }
 423
 424         for (i=0; i<p->state_count; i++) {
 425                 if (p->states[i].control != p->states[i].status) {
 426                         dprintk("Different control (%llu) and status values (%llu)\n",
 427                                 p->states[i].control, p->states[i].status);
 428                         result = -EINVAL;
 429                         goto err_unreg;
 430                 }
 431
 432                 if (!p->states[i].core_frequency) {
 433                         dprintk("Zero core frequency for state %u\n", i);
 434                         result = -EINVAL;
 435                         goto err_unreg;
 436                 }
 437
 438                 if (p->states[i].core_frequency > p->states[0].core_frequency) {
 439                         dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
 440                                 p->states[i].core_frequency, p->states[0].core_frequency);
 441                         p->states[i].core_frequency = 0;
 442                         continue;
 443                 }
 444         }
 445
 446         centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
 447         if (!centrino_model[cpu]) {
 448                 result = -ENOMEM;
 449                 goto err_unreg;
 450         }
 451
 452         centrino_model[cpu]->model_name=NULL;
 453         centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
 454         centrino_model[cpu]->op_points =  kmalloc(sizeof(struct cpufreq_frequency_table) *
 455                                              (p->state_count + 1), GFP_KERNEL);
 456         if (!centrino_model[cpu]->op_points) {
 457                 result = -ENOMEM;
 458                 goto err_kfree;
 459         }
 460
 461         for (i=0; i<p->state_count; i++) {
 462                 centrino_model[cpu]->op_points[i].index = p->states[i].control;
 463                 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
 464                 dprintk("adding state %i with frequency %u and control value %04x\n",
 465                         i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
 466         }
 467         centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
 468
 469         cur_freq = get_cur_freq(cpu);
 470
 471         for (i=0; i<p->state_count; i++) {
 472                 if (!p->states[i].core_frequency) {
 473                         dprintk("skipping state %u\n", i);
 474                         centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
 475                         continue;
 476                 }
 477
 478                 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
 479                     (centrino_model[cpu]->op_points[i].frequency)) {
 480                         dprintk("Invalid encoded frequency (%u vs. %u)\n",
 481                                 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
 482                                 centrino_model[cpu]->op_points[i].frequency);
 483                         result = -EINVAL;
 484                         goto err_kfree_all;
 485                 }
 486
 487                 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
 488                         p->state = i;
 489         }
 490
 491         /* notify BIOS that we exist */
 492         acpi_processor_notify_smm(THIS_MODULE);
 493
 494         return 0;
 495
 496  err_kfree_all:
 497         kfree(centrino_model[cpu]->op_points);
 498  err_kfree:
 499         kfree(centrino_model[cpu]);
 500  err_unreg:
 501         acpi_processor_unregister_performance(p, cpu);
 502         dprintk(KERN_INFO PFX "invalid ACPI data\n");
 503         return (result);
 504 }
 505 #else
 506 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
 507 static inline int centrino_cpu_early_init_acpi(void) { return 0; }
 508 #endif
 509
 510 static int centrino_cpu_init(struct cpufreq_policy *policy)
 511 {
 512         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 513         unsigned freq;
 514         unsigned l, h;
 515         int ret;
 516         int i;
 517
 518         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 519         if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
 520                 return -ENODEV;
 521
 522         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
 523                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 524
 525         if (centrino_cpu_init_acpi(policy)) {
 526                 if (policy->cpu != 0)
 527                         return -ENODEV;
 528
 529                 for (i = 0; i < N_IDS; i++)
 530                         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 531                                 break;
 532
 533                 if (i != N_IDS)
 534                         centrino_cpu[policy->cpu] = &cpu_ids[i];
 535
 536                 if (!centrino_cpu[policy->cpu]) {
 537                         dprintk(KERN_INFO PFX "found unsupported CPU with "
 538                         "Enhanced SpeedStep: send /proc/cpuinfo to "
 539                         MAINTAINER "\n");
 540                         return -ENODEV;
 541                 }
 542
 543                 if (centrino_cpu_init_table(policy)) {
 544                         return -ENODEV;
 545                 }
 546         }
 547
 548         /* Check to see if Enhanced SpeedStep is enabled, and try to
 549            enable it if not. */
 550         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 551
 552         if (!(l & (1<<16))) {
 553                 l |= (1<<16);
 554                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 555                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 556
 557                 /* check to see if it stuck */
 558                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 559                 if (!(l & (1<<16))) {
 560                         printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
 561                         return -ENODEV;
 562                 }
 563         }
 564
 565         freq = get_cur_freq(policy->cpu);
 566
 567         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 568         policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
 569         policy->cur = freq;
 570
 571         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 572
 573         ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
 574         if (ret)
 575                 return (ret);
 576
 577         cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
 578
 579         return 0;
 580 }
 581
 582 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 583 {
 584         unsigned int cpu = policy->cpu;
 585
 586         if (!centrino_model[cpu])
 587                 return -ENODEV;
 588
 589         cpufreq_frequency_table_put_attr(cpu);
 590
 591 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 592         if (!centrino_model[cpu]->model_name) {
 593                 static struct acpi_processor_performance *p;
 594
 595                 if (acpi_perf_data[cpu]) {
 596                         p = acpi_perf_data[cpu];
 597                         dprintk("unregistering and freeing ACPI data\n");
 598                         acpi_processor_unregister_performance(p, cpu);
 599                         kfree(centrino_model[cpu]->op_points);
 600                         kfree(centrino_model[cpu]);
 601                 }
 602         }
 603 #endif
 604
 605         centrino_model[cpu] = NULL;
 606
 607         return 0;
 608 }
 609
 610 /**
 611  * centrino_verify - verifies a new CPUFreq policy
 612  * @policy: new policy
 613  *
 614  * Limit must be within this model's frequency range at least one
 615  * border included.
 616  */
 617 static int centrino_verify (struct cpufreq_policy *policy)
 618 {
 619         return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
 620 }
 621
 622 /**
 623  * centrino_setpolicy - set a new CPUFreq policy
 624  * @policy: new policy
 625  * @target_freq: the target frequency
 626  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 627  *
 628  * Sets a new CPUFreq policy.
 629  */
 630 static int centrino_target (struct cpufreq_policy *policy,
 631                             unsigned int target_freq,
 632                             unsigned int relation)
 633 {
 634         unsigned int    newstate = 0;
 635         unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
 636         struct cpufreq_freqs    freqs;
 637         cpumask_t               online_policy_cpus;
 638         cpumask_t               saved_mask;
 639         cpumask_t               set_mask;
 640         cpumask_t               covered_cpus;
 641         int                     retval = 0;
 642         unsigned int            j, k, first_cpu, tmp;
 643
 644         if (unlikely(centrino_model[cpu] == NULL))
 645                 return -ENODEV;
 646
 647         if (unlikely(cpufreq_frequency_table_target(policy,
 648                         centrino_model[cpu]->op_points,
 649                         target_freq,
 650                         relation,
 651                         &newstate))) {
 652                 return -EINVAL;
 653         }
 654
 655 #ifdef CONFIG_HOTPLUG_CPU
 656         /* cpufreq holds the hotplug lock, so we are safe from here on */
 657         cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
 658 #else
 659         online_policy_cpus = policy->cpus;
 660 #endif
 661
 662         saved_mask = current->cpus_allowed;
 663         first_cpu = 1;
 664         cpus_clear(covered_cpus);
 665         for_each_cpu_mask(j, online_policy_cpus) {
 666                 /*
 667                  * Support for SMP systems.
 668                  * Make sure we are running on CPU that wants to change freq
 669                  */
 670                 cpus_clear(set_mask);
 671                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 672                         cpus_or(set_mask, set_mask, online_policy_cpus);
 673                 else
 674                         cpu_set(j, set_mask);
 675
 676                 set_cpus_allowed(current, set_mask);
 677                 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
 678                         dprintk("couldn't limit to CPUs in this domain\n");
 679                         retval = -EAGAIN;
 680                         if (first_cpu) {
 681                                 /* We haven't started the transition yet. */
 682                                 goto migrate_end;
 683                         }
 684                         break;
 685                 }
 686
 687                 msr = centrino_model[cpu]->op_points[newstate].index;
 688
 689                 if (first_cpu) {
 690                         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 691                         if (msr == (oldmsr & 0xffff)) {
 692                                 dprintk("no change needed - msr was and needs "
 693                                         "to be %x\n", oldmsr);
 694                                 retval = 0;
 695                                 goto migrate_end;
 696                         }
 697
 698                         freqs.old = extract_clock(oldmsr, cpu, 0);
 699                         freqs.new = extract_clock(msr, cpu, 0);
 700
 701                         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 702                                 target_freq, freqs.old, freqs.new, msr);
 703
 704                         for_each_cpu_mask(k, online_policy_cpus) {
 705                                 freqs.cpu = k;
 706                                 cpufreq_notify_transition(&freqs,
 707                                         CPUFREQ_PRECHANGE);
 708                         }
 709
 710                         first_cpu = 0;
 711                         /* all but 16 LSB are reserved, treat them with care */
 712                         oldmsr &= ~0xffff;
 713                         msr &= 0xffff;
 714                         oldmsr |= msr;
 715                 }
 716
 717                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 718                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 719                         break;
 720
 721                 cpu_set(j, covered_cpus);
 722         }
 723
 724         for_each_cpu_mask(k, online_policy_cpus) {
 725                 freqs.cpu = k;
 726                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 727         }
 728
 729         if (unlikely(retval)) {
 730                 /*
 731                  * We have failed halfway through the frequency change.
 732                  * We have sent callbacks to policy->cpus and
 733                  * MSRs have already been written on coverd_cpus.
 734                  * Best effort undo..
 735                  */
 736
 737                 if (!cpus_empty(covered_cpus)) {
 738                         for_each_cpu_mask(j, covered_cpus) {
 739                                 set_cpus_allowed(current, cpumask_of_cpu(j));
 740                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 741                         }
 742                 }
 743
 744                 tmp = freqs.new;
 745                 freqs.new = freqs.old;
 746                 freqs.old = tmp;
 747                 for_each_cpu_mask(j, online_policy_cpus) {
 748                         freqs.cpu = j;
 749                         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 750                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 751                 }
 752         }
 753
 754 migrate_end:
 755         set_cpus_allowed(current, saved_mask);
 756         return 0;
 757 }
 758
 759 static struct freq_attr* centrino_attr[] = {
 760         &cpufreq_freq_attr_scaling_available_freqs,
 761         NULL,
 762 };
 763
 764 static struct cpufreq_driver centrino_driver = {
 765         .name           = "centrino", /* should be speedstep-centrino,
 766                                          but there's a 16 char limit */
 767         .init           = centrino_cpu_init,
 768         .exit           = centrino_cpu_exit,
 769         .verify         = centrino_verify,
 770         .target         = centrino_target,
 771         .get            = get_cur_freq,
 772         .attr           = centrino_attr,
 773         .owner          = THIS_MODULE,
 774 };
 775
 776
 777 /**
 778  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 779  *
 780  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 781  * unsupported devices, -ENOENT if there's no voltage table for this
 782  * particular CPU model, -EINVAL on problems during initiatization,
 783  * and zero on success.
 784  *
 785  * This is quite picky.  Not only does the CPU have to advertise the
 786  * "est" flag in the cpuid capability flags, we look for a specific
 787  * CPU model and stepping, and we need to have the exact model name in
 788  * our voltage tables.  That is, be paranoid about not releasing
 789  * someone's valuable magic smoke.
 790  */
 791 static int __init centrino_init(void)
 792 {
 793         struct cpuinfo_x86 *cpu = cpu_data;
 794
 795         if (!cpu_has(cpu, X86_FEATURE_EST))
 796                 return -ENODEV;
 797
 798         centrino_cpu_early_init_acpi();
 799
 800         return cpufreq_register_driver(&centrino_driver);
 801 }
 802
 803 static void __exit centrino_exit(void)
 804 {
 805 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 806         unsigned int j;
 807 #endif
 808
 809         cpufreq_unregister_driver(&centrino_driver);
 810
 811 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 812         for_each_cpu(j) {
 813                 kfree(acpi_perf_data[j]);
 814                 acpi_perf_data[j] = NULL;
 815         }
 816 #endif
 817 }
 818
 819 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 820 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 821 MODULE_LICENSE ("GPL");
 822
 823 late_initcall(centrino_init);
 824 module_exit(centrino_exit);