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[XFRM]: skb_cow_data() does not set proper owner for new skbs.
[linux-2.6/verdex.git] / drivers / net / ns83820.c
blob2fcc181a8624c817504b32bd68d523620ccc1128
1 #define _VERSION "0.20"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 *
67 * 20040828 0.21 - add hardware vlan accleration
68 * by Neil Horman <nhorman@redhat.com>
69 * Driver Overview
70 * ===============
71 *
72 * This driver was originally written for the National Semiconductor
73 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
74 * this code will turn out to be a) clean, b) correct, and c) fast.
75 * With that in mind, I'm aiming to split the code up as much as
76 * reasonably possible. At present there are X major sections that
77 * break down into a) packet receive, b) packet transmit, c) link
78 * management, d) initialization and configuration. Where possible,
79 * these code paths are designed to run in parallel.
80 *
81 * This driver has been tested and found to work with the following
82 * cards (in no particular order):
83 *
84 * Cameo SOHO-GA2000T SOHO-GA2500T
85 * D-Link DGE-500T
86 * PureData PDP8023Z-TG
87 * SMC SMC9452TX SMC9462TX
88 * Netgear GA621
89 *
90 * Special thanks to SMC for providing hardware to test this driver on.
91 *
92 * Reports of success or failure would be greatly appreciated.
93 */
94 //#define dprintk printk
95 #define dprintk(x...) do { } while (0)
96
97 #include <linux/config.h>
98 #include <linux/module.h>
99 #include <linux/moduleparam.h>
100 #include <linux/types.h>
101 #include <linux/pci.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/delay.h>
105 #include <linux/smp_lock.h>
106 #include <linux/workqueue.h>
107 #include <linux/init.h>
108 #include <linux/ip.h> /* for iph */
109 #include <linux/in.h> /* for IPPROTO_... */
110 #include <linux/eeprom.h>
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116
117 #include <asm/io.h>
118 #include <asm/uaccess.h>
119 #include <asm/system.h>
120
121 #define DRV_NAME "ns83820"
122
123 /* Global parameters. See module_param near the bottom. */
124 static int ihr = 2;
125 static int reset_phy = 0;
126 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
127
128 /* Dprintk is used for more interesting debug events */
129 #undef Dprintk
130 #define Dprintk dprintk
131
132 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
133 #define USE_64BIT_ADDR "+"
134 #endif
135
136 #if defined(USE_64BIT_ADDR)
137 #define VERSION _VERSION USE_64BIT_ADDR
138 #define TRY_DAC 1
139 #else
140 #define VERSION _VERSION
141 #define TRY_DAC 0
142 #endif
143
144 /* tunables */
145 #define RX_BUF_SIZE 1500 /* 8192 */
146 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
147 #define NS83820_VLAN_ACCEL_SUPPORT
148 #endif
149
150 /* Must not exceed ~65000. */
151 #define NR_RX_DESC 64
152 #define NR_TX_DESC 128
153
154 /* not tunable */
155 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
156
157 #define MIN_TX_DESC_FREE 8
158
159 /* register defines */
160 #define CFGCS 0x04
161
162 #define CR_TXE 0x00000001
163 #define CR_TXD 0x00000002
164 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
165 * The Receive engine skips one descriptor and moves
166 * onto the next one!! */
167 #define CR_RXE 0x00000004
168 #define CR_RXD 0x00000008
169 #define CR_TXR 0x00000010
170 #define CR_RXR 0x00000020
171 #define CR_SWI 0x00000080
172 #define CR_RST 0x00000100
173
174 #define PTSCR_EEBIST_FAIL 0x00000001
175 #define PTSCR_EEBIST_EN 0x00000002
176 #define PTSCR_EELOAD_EN 0x00000004
177 #define PTSCR_RBIST_FAIL 0x000001b8
178 #define PTSCR_RBIST_DONE 0x00000200
179 #define PTSCR_RBIST_EN 0x00000400
180 #define PTSCR_RBIST_RST 0x00002000
181
182 #define MEAR_EEDI 0x00000001
183 #define MEAR_EEDO 0x00000002
184 #define MEAR_EECLK 0x00000004
185 #define MEAR_EESEL 0x00000008
186 #define MEAR_MDIO 0x00000010
187 #define MEAR_MDDIR 0x00000020
188 #define MEAR_MDC 0x00000040
189
190 #define ISR_TXDESC3 0x40000000
191 #define ISR_TXDESC2 0x20000000
192 #define ISR_TXDESC1 0x10000000
193 #define ISR_TXDESC0 0x08000000
194 #define ISR_RXDESC3 0x04000000
195 #define ISR_RXDESC2 0x02000000
196 #define ISR_RXDESC1 0x01000000
197 #define ISR_RXDESC0 0x00800000
198 #define ISR_TXRCMP 0x00400000
199 #define ISR_RXRCMP 0x00200000
200 #define ISR_DPERR 0x00100000
201 #define ISR_SSERR 0x00080000
202 #define ISR_RMABT 0x00040000
203 #define ISR_RTABT 0x00020000
204 #define ISR_RXSOVR 0x00010000
205 #define ISR_HIBINT 0x00008000
206 #define ISR_PHY 0x00004000
207 #define ISR_PME 0x00002000
208 #define ISR_SWI 0x00001000
209 #define ISR_MIB 0x00000800
210 #define ISR_TXURN 0x00000400
211 #define ISR_TXIDLE 0x00000200
212 #define ISR_TXERR 0x00000100
213 #define ISR_TXDESC 0x00000080
214 #define ISR_TXOK 0x00000040
215 #define ISR_RXORN 0x00000020
216 #define ISR_RXIDLE 0x00000010
217 #define ISR_RXEARLY 0x00000008
218 #define ISR_RXERR 0x00000004
219 #define ISR_RXDESC 0x00000002
220 #define ISR_RXOK 0x00000001
221
222 #define TXCFG_CSI 0x80000000
223 #define TXCFG_HBI 0x40000000
224 #define TXCFG_MLB 0x20000000
225 #define TXCFG_ATP 0x10000000
226 #define TXCFG_ECRETRY 0x00800000
227 #define TXCFG_BRST_DIS 0x00080000
228 #define TXCFG_MXDMA1024 0x00000000
229 #define TXCFG_MXDMA512 0x00700000
230 #define TXCFG_MXDMA256 0x00600000
231 #define TXCFG_MXDMA128 0x00500000
232 #define TXCFG_MXDMA64 0x00400000
233 #define TXCFG_MXDMA32 0x00300000
234 #define TXCFG_MXDMA16 0x00200000
235 #define TXCFG_MXDMA8 0x00100000
236
237 #define CFG_LNKSTS 0x80000000
238 #define CFG_SPDSTS 0x60000000
239 #define CFG_SPDSTS1 0x40000000
240 #define CFG_SPDSTS0 0x20000000
241 #define CFG_DUPSTS 0x10000000
242 #define CFG_TBI_EN 0x01000000
243 #define CFG_MODE_1000 0x00400000
244 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
245 * Read the Phy response and then configure the MAC accordingly */
246 #define CFG_AUTO_1000 0x00200000
247 #define CFG_PINT_CTL 0x001c0000
248 #define CFG_PINT_DUPSTS 0x00100000
249 #define CFG_PINT_LNKSTS 0x00080000
250 #define CFG_PINT_SPDSTS 0x00040000
251 #define CFG_TMRTEST 0x00020000
252 #define CFG_MRM_DIS 0x00010000
253 #define CFG_MWI_DIS 0x00008000
254 #define CFG_T64ADDR 0x00004000
255 #define CFG_PCI64_DET 0x00002000
256 #define CFG_DATA64_EN 0x00001000
257 #define CFG_M64ADDR 0x00000800
258 #define CFG_PHY_RST 0x00000400
259 #define CFG_PHY_DIS 0x00000200
260 #define CFG_EXTSTS_EN 0x00000100
261 #define CFG_REQALG 0x00000080
262 #define CFG_SB 0x00000040
263 #define CFG_POW 0x00000020
264 #define CFG_EXD 0x00000010
265 #define CFG_PESEL 0x00000008
266 #define CFG_BROM_DIS 0x00000004
267 #define CFG_EXT_125 0x00000002
268 #define CFG_BEM 0x00000001
269
270 #define EXTSTS_UDPPKT 0x00200000
271 #define EXTSTS_TCPPKT 0x00080000
272 #define EXTSTS_IPPKT 0x00020000
273 #define EXTSTS_VPKT 0x00010000
274 #define EXTSTS_VTG_MASK 0x0000ffff
275
276 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
277
278 #define MIBC_MIBS 0x00000008
279 #define MIBC_ACLR 0x00000004
280 #define MIBC_FRZ 0x00000002
281 #define MIBC_WRN 0x00000001
282
283 #define PCR_PSEN (1 << 31)
284 #define PCR_PS_MCAST (1 << 30)
285 #define PCR_PS_DA (1 << 29)
286 #define PCR_STHI_8 (3 << 23)
287 #define PCR_STLO_4 (1 << 23)
288 #define PCR_FFHI_8K (3 << 21)
289 #define PCR_FFLO_4K (1 << 21)
290 #define PCR_PAUSE_CNT 0xFFFE
291
292 #define RXCFG_AEP 0x80000000
293 #define RXCFG_ARP 0x40000000
294 #define RXCFG_STRIPCRC 0x20000000
295 #define RXCFG_RX_FD 0x10000000
296 #define RXCFG_ALP 0x08000000
297 #define RXCFG_AIRL 0x04000000
298 #define RXCFG_MXDMA512 0x00700000
299 #define RXCFG_DRTH 0x0000003e
300 #define RXCFG_DRTH0 0x00000002
301
302 #define RFCR_RFEN 0x80000000
303 #define RFCR_AAB 0x40000000
304 #define RFCR_AAM 0x20000000
305 #define RFCR_AAU 0x10000000
306 #define RFCR_APM 0x08000000
307 #define RFCR_APAT 0x07800000
308 #define RFCR_APAT3 0x04000000
309 #define RFCR_APAT2 0x02000000
310 #define RFCR_APAT1 0x01000000
311 #define RFCR_APAT0 0x00800000
312 #define RFCR_AARP 0x00400000
313 #define RFCR_MHEN 0x00200000
314 #define RFCR_UHEN 0x00100000
315 #define RFCR_ULM 0x00080000
316
317 #define VRCR_RUDPE 0x00000080
318 #define VRCR_RTCPE 0x00000040
319 #define VRCR_RIPE 0x00000020
320 #define VRCR_IPEN 0x00000010
321 #define VRCR_DUTF 0x00000008
322 #define VRCR_DVTF 0x00000004
323 #define VRCR_VTREN 0x00000002
324 #define VRCR_VTDEN 0x00000001
325
326 #define VTCR_PPCHK 0x00000008
327 #define VTCR_GCHK 0x00000004
328 #define VTCR_VPPTI 0x00000002
329 #define VTCR_VGTI 0x00000001
330
331 #define CR 0x00
332 #define CFG 0x04
333 #define MEAR 0x08
334 #define PTSCR 0x0c
335 #define ISR 0x10
336 #define IMR 0x14
337 #define IER 0x18
338 #define IHR 0x1c
339 #define TXDP 0x20
340 #define TXDP_HI 0x24
341 #define TXCFG 0x28
342 #define GPIOR 0x2c
343 #define RXDP 0x30
344 #define RXDP_HI 0x34
345 #define RXCFG 0x38
346 #define PQCR 0x3c
347 #define WCSR 0x40
348 #define PCR 0x44
349 #define RFCR 0x48
350 #define RFDR 0x4c
351
352 #define SRR 0x58
353
354 #define VRCR 0xbc
355 #define VTCR 0xc0
356 #define VDR 0xc4
357 #define CCSR 0xcc
358
359 #define TBICR 0xe0
360 #define TBISR 0xe4
361 #define TANAR 0xe8
362 #define TANLPAR 0xec
363 #define TANER 0xf0
364 #define TESR 0xf4
365
366 #define TBICR_MR_AN_ENABLE 0x00001000
367 #define TBICR_MR_RESTART_AN 0x00000200
368
369 #define TBISR_MR_LINK_STATUS 0x00000020
370 #define TBISR_MR_AN_COMPLETE 0x00000004
371
372 #define TANAR_PS2 0x00000100
373 #define TANAR_PS1 0x00000080
374 #define TANAR_HALF_DUP 0x00000040
375 #define TANAR_FULL_DUP 0x00000020
376
377 #define GPIOR_GP5_OE 0x00000200
378 #define GPIOR_GP4_OE 0x00000100
379 #define GPIOR_GP3_OE 0x00000080
380 #define GPIOR_GP2_OE 0x00000040
381 #define GPIOR_GP1_OE 0x00000020
382 #define GPIOR_GP3_OUT 0x00000004
383 #define GPIOR_GP1_OUT 0x00000001
384
385 #define LINK_AUTONEGOTIATE 0x01
386 #define LINK_DOWN 0x02
387 #define LINK_UP 0x04
388
389 #ifdef USE_64BIT_ADDR
390 #define HW_ADDR_LEN 8
391 #define desc_addr_set(desc, addr) \
392 do { \
393 u64 __addr = (addr); \
394 (desc)[0] = cpu_to_le32(__addr); \
395 (desc)[1] = cpu_to_le32(__addr >> 32); \
396 } while(0)
397 #define desc_addr_get(desc) \
398 (((u64)le32_to_cpu((desc)[1]) << 32) \
399 | le32_to_cpu((desc)[0]))
400 #else
401 #define HW_ADDR_LEN 4
402 #define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr))
403 #define desc_addr_get(desc) (le32_to_cpu((desc)[0]))
404 #endif
405
406 #define DESC_LINK 0
407 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
408 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
409 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
410
411 #define CMDSTS_OWN 0x80000000
412 #define CMDSTS_MORE 0x40000000
413 #define CMDSTS_INTR 0x20000000
414 #define CMDSTS_ERR 0x10000000
415 #define CMDSTS_OK 0x08000000
416 #define CMDSTS_RUNT 0x00200000
417 #define CMDSTS_LEN_MASK 0x0000ffff
418
419 #define CMDSTS_DEST_MASK 0x01800000
420 #define CMDSTS_DEST_SELF 0x00800000
421 #define CMDSTS_DEST_MULTI 0x01000000
422
423 #define DESC_SIZE 8 /* Should be cache line sized */
424
425 struct rx_info {
426 spinlock_t lock;
427 int up;
428 long idle;
429
430 struct sk_buff *skbs[NR_RX_DESC];
431
432 u32 *next_rx_desc;
433 u16 next_rx, next_empty;
434
435 u32 *descs;
436 dma_addr_t phy_descs;
437 };
438
439
440 struct ns83820 {
441 struct net_device_stats stats;
442 u8 __iomem *base;
443
444 struct pci_dev *pci_dev;
445
446 #ifdef NS83820_VLAN_ACCEL_SUPPORT
447 struct vlan_group *vlgrp;
448 #endif
449
450 struct rx_info rx_info;
451 struct tasklet_struct rx_tasklet;
452
453 unsigned ihr;
454 struct work_struct tq_refill;
455
456 /* protects everything below. irqsave when using. */
457 spinlock_t misc_lock;
458
459 u32 CFG_cache;
460
461 u32 MEAR_cache;
462 u32 IMR_cache;
463 struct eeprom ee;
464
465 unsigned linkstate;
466
467 spinlock_t tx_lock;
468
469 u16 tx_done_idx;
470 u16 tx_idx;
471 volatile u16 tx_free_idx; /* idx of free desc chain */
472 u16 tx_intr_idx;
473
474 atomic_t nr_tx_skbs;
475 struct sk_buff *tx_skbs[NR_TX_DESC];
476
477 char pad[16] __attribute__((aligned(16)));
478 u32 *tx_descs;
479 dma_addr_t tx_phy_descs;
480
481 struct timer_list tx_watchdog;
482 };
483
484 static inline struct ns83820 *PRIV(struct net_device *dev)
485 {
486 return netdev_priv(dev);
487 }
488
489 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
490
491 static inline void kick_rx(struct net_device *ndev)
492 {
493 struct ns83820 *dev = PRIV(ndev);
494 dprintk("kick_rx: maybe kicking\n");
495 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
496 dprintk("actually kicking\n");
497 writel(dev->rx_info.phy_descs +
498 (4 * DESC_SIZE * dev->rx_info.next_rx),
499 dev->base + RXDP);
500 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
501 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
502 ndev->name);
503 __kick_rx(dev);
504 }
505 }
506
507 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
508 #define start_tx_okay(dev) \
509 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
510
511
512 #ifdef NS83820_VLAN_ACCEL_SUPPORT
513 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
514 {
515 struct ns83820 *dev = PRIV(ndev);
516
517 spin_lock_irq(&dev->misc_lock);
518 spin_lock(&dev->tx_lock);
519
520 dev->vlgrp = grp;
521
522 spin_unlock(&dev->tx_lock);
523 spin_unlock_irq(&dev->misc_lock);
524 }
525
526 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
527 {
528 struct ns83820 *dev = PRIV(ndev);
529
530 spin_lock_irq(&dev->misc_lock);
531 spin_lock(&dev->tx_lock);
532 if (dev->vlgrp)
533 dev->vlgrp->vlan_devices[vid] = NULL;
534 spin_unlock(&dev->tx_lock);
535 spin_unlock_irq(&dev->misc_lock);
536 }
537 #endif
538
539 /* Packet Receiver
540 *
541 * The hardware supports linked lists of receive descriptors for
542 * which ownership is transfered back and forth by means of an
543 * ownership bit. While the hardware does support the use of a
544 * ring for receive descriptors, we only make use of a chain in
545 * an attempt to reduce bus traffic under heavy load scenarios.
546 * This will also make bugs a bit more obvious. The current code
547 * only makes use of a single rx chain; I hope to implement
548 * priority based rx for version 1.0. Goal: even under overload
549 * conditions, still route realtime traffic with as low jitter as
550 * possible.
551 */
552 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
553 {
554 desc_addr_set(desc + DESC_LINK, link);
555 desc_addr_set(desc + DESC_BUFPTR, buf);
556 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
557 mb();
558 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
559 }
560
561 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
562 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
563 {
564 unsigned next_empty;
565 u32 cmdsts;
566 u32 *sg;
567 dma_addr_t buf;
568
569 next_empty = dev->rx_info.next_empty;
570
571 /* don't overrun last rx marker */
572 if (unlikely(nr_rx_empty(dev) <= 2)) {
573 kfree_skb(skb);
574 return 1;
575 }
576
577 #if 0
578 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
579 dev->rx_info.next_empty,
580 dev->rx_info.nr_used,
581 dev->rx_info.next_rx
582 );
583 #endif
584
585 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
586 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
587 BUG();
588 dev->rx_info.skbs[next_empty] = skb;
589
590 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
591 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
592 buf = pci_map_single(dev->pci_dev, skb->tail,
593 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
594 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
595 /* update link of previous rx */
596 if (likely(next_empty != dev->rx_info.next_rx))
597 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
598
599 return 0;
600 }
601
602 static inline int rx_refill(struct net_device *ndev, int gfp)
603 {
604 struct ns83820 *dev = PRIV(ndev);
605 unsigned i;
606 unsigned long flags = 0;
607
608 if (unlikely(nr_rx_empty(dev) <= 2))
609 return 0;
610
611 dprintk("rx_refill(%p)\n", ndev);
612 if (gfp == GFP_ATOMIC)
613 spin_lock_irqsave(&dev->rx_info.lock, flags);
614 for (i=0; i<NR_RX_DESC; i++) {
615 struct sk_buff *skb;
616 long res;
617 /* extra 16 bytes for alignment */
618 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
619 if (unlikely(!skb))
620 break;
621
622 res = (long)skb->tail & 0xf;
623 res = 0x10 - res;
624 res &= 0xf;
625 skb_reserve(skb, res);
626
627 skb->dev = ndev;
628 if (gfp != GFP_ATOMIC)
629 spin_lock_irqsave(&dev->rx_info.lock, flags);
630 res = ns83820_add_rx_skb(dev, skb);
631 if (gfp != GFP_ATOMIC)
632 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
633 if (res) {
634 i = 1;
635 break;
636 }
637 }
638 if (gfp == GFP_ATOMIC)
639 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
640
641 return i ? 0 : -ENOMEM;
642 }
643
644 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
645 static void fastcall rx_refill_atomic(struct net_device *ndev)
646 {
647 rx_refill(ndev, GFP_ATOMIC);
648 }
649
650 /* REFILL */
651 static inline void queue_refill(void *_dev)
652 {
653 struct net_device *ndev = _dev;
654 struct ns83820 *dev = PRIV(ndev);
655
656 rx_refill(ndev, GFP_KERNEL);
657 if (dev->rx_info.up)
658 kick_rx(ndev);
659 }
660
661 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
662 {
663 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
664 }
665
666 static void FASTCALL(phy_intr(struct net_device *ndev));
667 static void fastcall phy_intr(struct net_device *ndev)
668 {
669 struct ns83820 *dev = PRIV(ndev);
670 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
671 u32 cfg, new_cfg;
672 u32 tbisr, tanar, tanlpar;
673 int speed, fullduplex, newlinkstate;
674
675 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
676
677 if (dev->CFG_cache & CFG_TBI_EN) {
678 /* we have an optical transceiver */
679 tbisr = readl(dev->base + TBISR);
680 tanar = readl(dev->base + TANAR);
681 tanlpar = readl(dev->base + TANLPAR);
682 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
683 tbisr, tanar, tanlpar);
684
685 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
686 && (tanar & TANAR_FULL_DUP)) ) {
687
688 /* both of us are full duplex */
689 writel(readl(dev->base + TXCFG)
690 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
691 dev->base + TXCFG);
692 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
693 dev->base + RXCFG);
694 /* Light up full duplex LED */
695 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
696 dev->base + GPIOR);
697
698 } else if(((tanlpar & TANAR_HALF_DUP)
699 && (tanar & TANAR_HALF_DUP))
700 || ((tanlpar & TANAR_FULL_DUP)
701 && (tanar & TANAR_HALF_DUP))
702 || ((tanlpar & TANAR_HALF_DUP)
703 && (tanar & TANAR_FULL_DUP))) {
704
705 /* one or both of us are half duplex */
706 writel((readl(dev->base + TXCFG)
707 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
708 dev->base + TXCFG);
709 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
710 dev->base + RXCFG);
711 /* Turn off full duplex LED */
712 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
713 dev->base + GPIOR);
714 }
715
716 speed = 4; /* 1000F */
717
718 } else {
719 /* we have a copper transceiver */
720 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
721
722 if (cfg & CFG_SPDSTS1)
723 new_cfg |= CFG_MODE_1000;
724 else
725 new_cfg &= ~CFG_MODE_1000;
726
727 speed = ((cfg / CFG_SPDSTS0) & 3);
728 fullduplex = (cfg & CFG_DUPSTS);
729
730 if (fullduplex)
731 new_cfg |= CFG_SB;
732
733 if ((cfg & CFG_LNKSTS) &&
734 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
735 writel(new_cfg, dev->base + CFG);
736 dev->CFG_cache = new_cfg;
737 }
738
739 dev->CFG_cache &= ~CFG_SPDSTS;
740 dev->CFG_cache |= cfg & CFG_SPDSTS;
741 }
742
743 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
744
745 if (newlinkstate & LINK_UP
746 && dev->linkstate != newlinkstate) {
747 netif_start_queue(ndev);
748 netif_wake_queue(ndev);
749 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
750 ndev->name,
751 speeds[speed],
752 fullduplex ? "full" : "half");
753 } else if (newlinkstate & LINK_DOWN
754 && dev->linkstate != newlinkstate) {
755 netif_stop_queue(ndev);
756 printk(KERN_INFO "%s: link now down.\n", ndev->name);
757 }
758
759 dev->linkstate = newlinkstate;
760 }
761
762 static int ns83820_setup_rx(struct net_device *ndev)
763 {
764 struct ns83820 *dev = PRIV(ndev);
765 unsigned i;
766 int ret;
767
768 dprintk("ns83820_setup_rx(%p)\n", ndev);
769
770 dev->rx_info.idle = 1;
771 dev->rx_info.next_rx = 0;
772 dev->rx_info.next_rx_desc = dev->rx_info.descs;
773 dev->rx_info.next_empty = 0;
774
775 for (i=0; i<NR_RX_DESC; i++)
776 clear_rx_desc(dev, i);
777
778 writel(0, dev->base + RXDP_HI);
779 writel(dev->rx_info.phy_descs, dev->base + RXDP);
780
781 ret = rx_refill(ndev, GFP_KERNEL);
782 if (!ret) {
783 dprintk("starting receiver\n");
784 /* prevent the interrupt handler from stomping on us */
785 spin_lock_irq(&dev->rx_info.lock);
786
787 writel(0x0001, dev->base + CCSR);
788 writel(0, dev->base + RFCR);
789 writel(0x7fc00000, dev->base + RFCR);
790 writel(0xffc00000, dev->base + RFCR);
791
792 dev->rx_info.up = 1;
793
794 phy_intr(ndev);
795
796 /* Okay, let it rip */
797 spin_lock_irq(&dev->misc_lock);
798 dev->IMR_cache |= ISR_PHY;
799 dev->IMR_cache |= ISR_RXRCMP;
800 //dev->IMR_cache |= ISR_RXERR;
801 //dev->IMR_cache |= ISR_RXOK;
802 dev->IMR_cache |= ISR_RXORN;
803 dev->IMR_cache |= ISR_RXSOVR;
804 dev->IMR_cache |= ISR_RXDESC;
805 dev->IMR_cache |= ISR_RXIDLE;
806 dev->IMR_cache |= ISR_TXDESC;
807 dev->IMR_cache |= ISR_TXIDLE;
808
809 writel(dev->IMR_cache, dev->base + IMR);
810 writel(1, dev->base + IER);
811 spin_unlock_irq(&dev->misc_lock);
812
813 kick_rx(ndev);
814
815 spin_unlock_irq(&dev->rx_info.lock);
816 }
817 return ret;
818 }
819
820 static void ns83820_cleanup_rx(struct ns83820 *dev)
821 {
822 unsigned i;
823 unsigned long flags;
824
825 dprintk("ns83820_cleanup_rx(%p)\n", dev);
826
827 /* disable receive interrupts */
828 spin_lock_irqsave(&dev->misc_lock, flags);
829 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
830 writel(dev->IMR_cache, dev->base + IMR);
831 spin_unlock_irqrestore(&dev->misc_lock, flags);
832
833 /* synchronize with the interrupt handler and kill it */
834 dev->rx_info.up = 0;
835 synchronize_irq(dev->pci_dev->irq);
836
837 /* touch the pci bus... */
838 readl(dev->base + IMR);
839
840 /* assumes the transmitter is already disabled and reset */
841 writel(0, dev->base + RXDP_HI);
842 writel(0, dev->base + RXDP);
843
844 for (i=0; i<NR_RX_DESC; i++) {
845 struct sk_buff *skb = dev->rx_info.skbs[i];
846 dev->rx_info.skbs[i] = NULL;
847 clear_rx_desc(dev, i);
848 if (skb)
849 kfree_skb(skb);
850 }
851 }
852
853 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
854 static void fastcall ns83820_rx_kick(struct net_device *ndev)
855 {
856 struct ns83820 *dev = PRIV(ndev);
857 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
858 if (dev->rx_info.up) {
859 rx_refill_atomic(ndev);
860 kick_rx(ndev);
861 }
862 }
863
864 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
865 schedule_work(&dev->tq_refill);
866 else
867 kick_rx(ndev);
868 if (dev->rx_info.idle)
869 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
870 }
871
872 /* rx_irq
873 *
874 */
875 static void FASTCALL(rx_irq(struct net_device *ndev));
876 static void fastcall rx_irq(struct net_device *ndev)
877 {
878 struct ns83820 *dev = PRIV(ndev);
879 struct rx_info *info = &dev->rx_info;
880 unsigned next_rx;
881 int rx_rc, len;
882 u32 cmdsts, *desc;
883 unsigned long flags;
884 int nr = 0;
885
886 dprintk("rx_irq(%p)\n", ndev);
887 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
888 readl(dev->base + RXDP),
889 (long)(dev->rx_info.phy_descs),
890 (int)dev->rx_info.next_rx,
891 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
892 (int)dev->rx_info.next_empty,
893 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
894 );
895
896 spin_lock_irqsave(&info->lock, flags);
897 if (!info->up)
898 goto out;
899
900 dprintk("walking descs\n");
901 next_rx = info->next_rx;
902 desc = info->next_rx_desc;
903 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
904 (cmdsts != CMDSTS_OWN)) {
905 struct sk_buff *skb;
906 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
907 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
908
909 dprintk("cmdsts: %08x\n", cmdsts);
910 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
911 dprintk("extsts: %08x\n", extsts);
912
913 skb = info->skbs[next_rx];
914 info->skbs[next_rx] = NULL;
915 info->next_rx = (next_rx + 1) % NR_RX_DESC;
916
917 mb();
918 clear_rx_desc(dev, next_rx);
919
920 pci_unmap_single(dev->pci_dev, bufptr,
921 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
922 len = cmdsts & CMDSTS_LEN_MASK;
923 #ifdef NS83820_VLAN_ACCEL_SUPPORT
924 /* NH: As was mentioned below, this chip is kinda
925 * brain dead about vlan tag stripping. Frames
926 * that are 64 bytes with a vlan header appended
927 * like arp frames, or pings, are flagged as Runts
928 * when the tag is stripped and hardware. This
929 * also means that the OK bit in the descriptor
930 * is cleared when the frame comes in so we have
931 * to do a specific length check here to make sure
932 * the frame would have been ok, had we not stripped
933 * the tag.
934 */
935 if (likely((CMDSTS_OK & cmdsts) ||
936 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
937 #else
938 if (likely(CMDSTS_OK & cmdsts)) {
939 #endif
940 skb_put(skb, len);
941 if (unlikely(!skb))
942 goto netdev_mangle_me_harder_failed;
943 if (cmdsts & CMDSTS_DEST_MULTI)
944 dev->stats.multicast ++;
945 dev->stats.rx_packets ++;
946 dev->stats.rx_bytes += len;
947 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
948 skb->ip_summed = CHECKSUM_UNNECESSARY;
949 } else {
950 skb->ip_summed = CHECKSUM_NONE;
951 }
952 skb->protocol = eth_type_trans(skb, ndev);
953 #ifdef NS83820_VLAN_ACCEL_SUPPORT
954 if(extsts & EXTSTS_VPKT) {
955 unsigned short tag;
956 tag = ntohs(extsts & EXTSTS_VTG_MASK);
957 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
958 } else {
959 rx_rc = netif_rx(skb);
960 }
961 #else
962 rx_rc = netif_rx(skb);
963 #endif
964 if (NET_RX_DROP == rx_rc) {
965 netdev_mangle_me_harder_failed:
966 dev->stats.rx_dropped ++;
967 }
968 } else {
969 kfree_skb(skb);
970 }
971
972 nr++;
973 next_rx = info->next_rx;
974 desc = info->descs + (DESC_SIZE * next_rx);
975 }
976 info->next_rx = next_rx;
977 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
978
979 out:
980 if (0 && !nr) {
981 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
982 }
983
984 spin_unlock_irqrestore(&info->lock, flags);
985 }
986
987 static void rx_action(unsigned long _dev)
988 {
989 struct net_device *ndev = (void *)_dev;
990 struct ns83820 *dev = PRIV(ndev);
991 rx_irq(ndev);
992 writel(ihr, dev->base + IHR);
993
994 spin_lock_irq(&dev->misc_lock);
995 dev->IMR_cache |= ISR_RXDESC;
996 writel(dev->IMR_cache, dev->base + IMR);
997 spin_unlock_irq(&dev->misc_lock);
998
999 rx_irq(ndev);
1000 ns83820_rx_kick(ndev);
1001 }
1002
1003 /* Packet Transmit code
1004 */
1005 static inline void kick_tx(struct ns83820 *dev)
1006 {
1007 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1008 dev, dev->tx_idx, dev->tx_free_idx);
1009 writel(CR_TXE, dev->base + CR);
1010 }
1011
1012 /* No spinlock needed on the transmit irq path as the interrupt handler is
1013 * serialized.
1014 */
1015 static void do_tx_done(struct net_device *ndev)
1016 {
1017 struct ns83820 *dev = PRIV(ndev);
1018 u32 cmdsts, tx_done_idx, *desc;
1019
1020 spin_lock_irq(&dev->tx_lock);
1021
1022 dprintk("do_tx_done(%p)\n", ndev);
1023 tx_done_idx = dev->tx_done_idx;
1024 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1025
1026 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1027 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1028 while ((tx_done_idx != dev->tx_free_idx) &&
1029 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1030 struct sk_buff *skb;
1031 unsigned len;
1032 dma_addr_t addr;
1033
1034 if (cmdsts & CMDSTS_ERR)
1035 dev->stats.tx_errors ++;
1036 if (cmdsts & CMDSTS_OK)
1037 dev->stats.tx_packets ++;
1038 if (cmdsts & CMDSTS_OK)
1039 dev->stats.tx_bytes += cmdsts & 0xffff;
1040
1041 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1042 tx_done_idx, dev->tx_free_idx, cmdsts);
1043 skb = dev->tx_skbs[tx_done_idx];
1044 dev->tx_skbs[tx_done_idx] = NULL;
1045 dprintk("done(%p)\n", skb);
1046
1047 len = cmdsts & CMDSTS_LEN_MASK;
1048 addr = desc_addr_get(desc + DESC_BUFPTR);
1049 if (skb) {
1050 pci_unmap_single(dev->pci_dev,
1051 addr,
1052 len,
1053 PCI_DMA_TODEVICE);
1054 dev_kfree_skb_irq(skb);
1055 atomic_dec(&dev->nr_tx_skbs);
1056 } else
1057 pci_unmap_page(dev->pci_dev,
1058 addr,
1059 len,
1060 PCI_DMA_TODEVICE);
1061
1062 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1063 dev->tx_done_idx = tx_done_idx;
1064 desc[DESC_CMDSTS] = cpu_to_le32(0);
1065 mb();
1066 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1067 }
1068
1069 /* Allow network stack to resume queueing packets after we've
1070 * finished transmitting at least 1/4 of the packets in the queue.
1071 */
1072 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1073 dprintk("start_queue(%p)\n", ndev);
1074 netif_start_queue(ndev);
1075 netif_wake_queue(ndev);
1076 }
1077 spin_unlock_irq(&dev->tx_lock);
1078 }
1079
1080 static void ns83820_cleanup_tx(struct ns83820 *dev)
1081 {
1082 unsigned i;
1083
1084 for (i=0; i<NR_TX_DESC; i++) {
1085 struct sk_buff *skb = dev->tx_skbs[i];
1086 dev->tx_skbs[i] = NULL;
1087 if (skb) {
1088 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1089 pci_unmap_single(dev->pci_dev,
1090 desc_addr_get(desc + DESC_BUFPTR),
1091 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1092 PCI_DMA_TODEVICE);
1093 dev_kfree_skb_irq(skb);
1094 atomic_dec(&dev->nr_tx_skbs);
1095 }
1096 }
1097
1098 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1099 }
1100
1101 /* transmit routine. This code relies on the network layer serializing
1102 * its calls in, but will run happily in parallel with the interrupt
1103 * handler. This code currently has provisions for fragmenting tx buffers
1104 * while trying to track down a bug in either the zero copy code or
1105 * the tx fifo (hence the MAX_FRAG_LEN).
1106 */
1107 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1108 {
1109 struct ns83820 *dev = PRIV(ndev);
1110 u32 free_idx, cmdsts, extsts;
1111 int nr_free, nr_frags;
1112 unsigned tx_done_idx, last_idx;
1113 dma_addr_t buf;
1114 unsigned len;
1115 skb_frag_t *frag;
1116 int stopped = 0;
1117 int do_intr = 0;
1118 volatile u32 *first_desc;
1119
1120 dprintk("ns83820_hard_start_xmit\n");
1121
1122 nr_frags = skb_shinfo(skb)->nr_frags;
1123 again:
1124 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1125 netif_stop_queue(ndev);
1126 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1127 return 1;
1128 netif_start_queue(ndev);
1129 }
1130
1131 last_idx = free_idx = dev->tx_free_idx;
1132 tx_done_idx = dev->tx_done_idx;
1133 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1134 nr_free -= 1;
1135 if (nr_free <= nr_frags) {
1136 dprintk("stop_queue - not enough(%p)\n", ndev);
1137 netif_stop_queue(ndev);
1138
1139 /* Check again: we may have raced with a tx done irq */
1140 if (dev->tx_done_idx != tx_done_idx) {
1141 dprintk("restart queue(%p)\n", ndev);
1142 netif_start_queue(ndev);
1143 goto again;
1144 }
1145 return 1;
1146 }
1147
1148 if (free_idx == dev->tx_intr_idx) {
1149 do_intr = 1;
1150 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1151 }
1152
1153 nr_free -= nr_frags;
1154 if (nr_free < MIN_TX_DESC_FREE) {
1155 dprintk("stop_queue - last entry(%p)\n", ndev);
1156 netif_stop_queue(ndev);
1157 stopped = 1;
1158 }
1159
1160 frag = skb_shinfo(skb)->frags;
1161 if (!nr_frags)
1162 frag = NULL;
1163 extsts = 0;
1164 if (skb->ip_summed == CHECKSUM_HW) {
1165 extsts |= EXTSTS_IPPKT;
1166 if (IPPROTO_TCP == skb->nh.iph->protocol)
1167 extsts |= EXTSTS_TCPPKT;
1168 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1169 extsts |= EXTSTS_UDPPKT;
1170 }
1171
1172 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1173 if(vlan_tx_tag_present(skb)) {
1174 /* fetch the vlan tag info out of the
1175 * ancilliary data if the vlan code
1176 * is using hw vlan acceleration
1177 */
1178 short tag = vlan_tx_tag_get(skb);
1179 extsts |= (EXTSTS_VPKT | htons(tag));
1180 }
1181 #endif
1182
1183 len = skb->len;
1184 if (nr_frags)
1185 len -= skb->data_len;
1186 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1187
1188 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1189
1190 for (;;) {
1191 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1192 u32 residue = 0;
1193
1194 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1195 (unsigned long long)buf);
1196 last_idx = free_idx;
1197 free_idx = (free_idx + 1) % NR_TX_DESC;
1198 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1199 desc_addr_set(desc + DESC_BUFPTR, buf);
1200 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1201
1202 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1203 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1204 cmdsts |= len;
1205 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1206
1207 if (residue) {
1208 buf += len;
1209 len = residue;
1210 continue;
1211 }
1212
1213 if (!nr_frags)
1214 break;
1215
1216 buf = pci_map_page(dev->pci_dev, frag->page,
1217 frag->page_offset,
1218 frag->size, PCI_DMA_TODEVICE);
1219 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1220 (long long)buf, (long) page_to_pfn(frag->page),
1221 frag->page_offset);
1222 len = frag->size;
1223 frag++;
1224 nr_frags--;
1225 }
1226 dprintk("done pkt\n");
1227
1228 spin_lock_irq(&dev->tx_lock);
1229 dev->tx_skbs[last_idx] = skb;
1230 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1231 dev->tx_free_idx = free_idx;
1232 atomic_inc(&dev->nr_tx_skbs);
1233 spin_unlock_irq(&dev->tx_lock);
1234
1235 kick_tx(dev);
1236
1237 /* Check again: we may have raced with a tx done irq */
1238 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1239 netif_start_queue(ndev);
1240
1241 /* set the transmit start time to catch transmit timeouts */
1242 ndev->trans_start = jiffies;
1243 return 0;
1244 }
1245
1246 static void ns83820_update_stats(struct ns83820 *dev)
1247 {
1248 u8 __iomem *base = dev->base;
1249
1250 /* the DP83820 will freeze counters, so we need to read all of them */
1251 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1252 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1253 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1254 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1255 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1256 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1257 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1258 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1259 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1260 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1261 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1262 }
1263
1264 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1265 {
1266 struct ns83820 *dev = PRIV(ndev);
1267
1268 /* somewhat overkill */
1269 spin_lock_irq(&dev->misc_lock);
1270 ns83820_update_stats(dev);
1271 spin_unlock_irq(&dev->misc_lock);
1272
1273 return &dev->stats;
1274 }
1275
1276 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1277 {
1278 struct ns83820 *dev = PRIV(ndev);
1279 strcpy(info->driver, "ns83820");
1280 strcpy(info->version, VERSION);
1281 strcpy(info->bus_info, pci_name(dev->pci_dev));
1282 }
1283
1284 static u32 ns83820_get_link(struct net_device *ndev)
1285 {
1286 struct ns83820 *dev = PRIV(ndev);
1287 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1288 return cfg & CFG_LNKSTS ? 1 : 0;
1289 }
1290
1291 static struct ethtool_ops ops = {
1292 .get_drvinfo = ns83820_get_drvinfo,
1293 .get_link = ns83820_get_link
1294 };
1295
1296 static void ns83820_mib_isr(struct ns83820 *dev)
1297 {
1298 spin_lock(&dev->misc_lock);
1299 ns83820_update_stats(dev);
1300 spin_unlock(&dev->misc_lock);
1301 }
1302
1303 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1304 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1305 {
1306 struct net_device *ndev = data;
1307 struct ns83820 *dev = PRIV(ndev);
1308 u32 isr;
1309 dprintk("ns83820_irq(%p)\n", ndev);
1310
1311 dev->ihr = 0;
1312
1313 isr = readl(dev->base + ISR);
1314 dprintk("irq: %08x\n", isr);
1315 ns83820_do_isr(ndev, isr);
1316 return IRQ_HANDLED;
1317 }
1318
1319 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1320 {
1321 struct ns83820 *dev = PRIV(ndev);
1322 #ifdef DEBUG
1323 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1324 Dprintk("odd isr? 0x%08x\n", isr);
1325 #endif
1326
1327 if (ISR_RXIDLE & isr) {
1328 dev->rx_info.idle = 1;
1329 Dprintk("oh dear, we are idle\n");
1330 ns83820_rx_kick(ndev);
1331 }
1332
1333 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1334 prefetch(dev->rx_info.next_rx_desc);
1335
1336 spin_lock_irq(&dev->misc_lock);
1337 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1338 writel(dev->IMR_cache, dev->base + IMR);
1339 spin_unlock_irq(&dev->misc_lock);
1340
1341 tasklet_schedule(&dev->rx_tasklet);
1342 //rx_irq(ndev);
1343 //writel(4, dev->base + IHR);
1344 }
1345
1346 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1347 ns83820_rx_kick(ndev);
1348
1349 if (unlikely(ISR_RXSOVR & isr)) {
1350 //printk("overrun: rxsovr\n");
1351 dev->stats.rx_fifo_errors ++;
1352 }
1353
1354 if (unlikely(ISR_RXORN & isr)) {
1355 //printk("overrun: rxorn\n");
1356 dev->stats.rx_fifo_errors ++;
1357 }
1358
1359 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1360 writel(CR_RXE, dev->base + CR);
1361
1362 if (ISR_TXIDLE & isr) {
1363 u32 txdp;
1364 txdp = readl(dev->base + TXDP);
1365 dprintk("txdp: %08x\n", txdp);
1366 txdp -= dev->tx_phy_descs;
1367 dev->tx_idx = txdp / (DESC_SIZE * 4);
1368 if (dev->tx_idx >= NR_TX_DESC) {
1369 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1370 dev->tx_idx = 0;
1371 }
1372 /* The may have been a race between a pci originated read
1373 * and the descriptor update from the cpu. Just in case,
1374 * kick the transmitter if the hardware thinks it is on a
1375 * different descriptor than we are.
1376 */
1377 if (dev->tx_idx != dev->tx_free_idx)
1378 kick_tx(dev);
1379 }
1380
1381 /* Defer tx ring processing until more than a minimum amount of
1382 * work has accumulated
1383 */
1384 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1385 do_tx_done(ndev);
1386
1387 /* Disable TxOk if there are no outstanding tx packets.
1388 */
1389 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1390 (dev->IMR_cache & ISR_TXOK)) {
1391 spin_lock_irq(&dev->misc_lock);
1392 dev->IMR_cache &= ~ISR_TXOK;
1393 writel(dev->IMR_cache, dev->base + IMR);
1394 spin_unlock_irq(&dev->misc_lock);
1395 }
1396 }
1397
1398 /* The TxIdle interrupt can come in before the transmit has
1399 * completed. Normally we reap packets off of the combination
1400 * of TxDesc and TxIdle and leave TxOk disabled (since it
1401 * occurs on every packet), but when no further irqs of this
1402 * nature are expected, we must enable TxOk.
1403 */
1404 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1405 spin_lock_irq(&dev->misc_lock);
1406 dev->IMR_cache |= ISR_TXOK;
1407 writel(dev->IMR_cache, dev->base + IMR);
1408 spin_unlock_irq(&dev->misc_lock);
1409 }
1410
1411 /* MIB interrupt: one of the statistics counters is about to overflow */
1412 if (unlikely(ISR_MIB & isr))
1413 ns83820_mib_isr(dev);
1414
1415 /* PHY: Link up/down/negotiation state change */
1416 if (unlikely(ISR_PHY & isr))
1417 phy_intr(ndev);
1418
1419 #if 0 /* Still working on the interrupt mitigation strategy */
1420 if (dev->ihr)
1421 writel(dev->ihr, dev->base + IHR);
1422 #endif
1423 }
1424
1425 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1426 {
1427 Dprintk("resetting chip...\n");
1428 writel(which, dev->base + CR);
1429 do {
1430 schedule();
1431 } while (readl(dev->base + CR) & which);
1432 Dprintk("okay!\n");
1433 }
1434
1435 static int ns83820_stop(struct net_device *ndev)
1436 {
1437 struct ns83820 *dev = PRIV(ndev);
1438
1439 /* FIXME: protect against interrupt handler? */
1440 del_timer_sync(&dev->tx_watchdog);
1441
1442 /* disable interrupts */
1443 writel(0, dev->base + IMR);
1444 writel(0, dev->base + IER);
1445 readl(dev->base + IER);
1446
1447 dev->rx_info.up = 0;
1448 synchronize_irq(dev->pci_dev->irq);
1449
1450 ns83820_do_reset(dev, CR_RST);
1451
1452 synchronize_irq(dev->pci_dev->irq);
1453
1454 spin_lock_irq(&dev->misc_lock);
1455 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1456 spin_unlock_irq(&dev->misc_lock);
1457
1458 ns83820_cleanup_rx(dev);
1459 ns83820_cleanup_tx(dev);
1460
1461 return 0;
1462 }
1463
1464 static void ns83820_tx_timeout(struct net_device *ndev)
1465 {
1466 struct ns83820 *dev = PRIV(ndev);
1467 u32 tx_done_idx, *desc;
1468 unsigned long flags;
1469
1470 local_irq_save(flags);
1471
1472 tx_done_idx = dev->tx_done_idx;
1473 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1474
1475 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1476 ndev->name,
1477 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1478
1479 #if defined(DEBUG)
1480 {
1481 u32 isr;
1482 isr = readl(dev->base + ISR);
1483 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1484 ns83820_do_isr(ndev, isr);
1485 }
1486 #endif
1487
1488 do_tx_done(ndev);
1489
1490 tx_done_idx = dev->tx_done_idx;
1491 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1492
1493 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1494 ndev->name,
1495 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1496
1497 local_irq_restore(flags);
1498 }
1499
1500 static void ns83820_tx_watch(unsigned long data)
1501 {
1502 struct net_device *ndev = (void *)data;
1503 struct ns83820 *dev = PRIV(ndev);
1504
1505 #if defined(DEBUG)
1506 printk("ns83820_tx_watch: %u %u %d\n",
1507 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1508 );
1509 #endif
1510
1511 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1512 dev->tx_done_idx != dev->tx_free_idx) {
1513 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1514 ndev->name,
1515 dev->tx_done_idx, dev->tx_free_idx,
1516 atomic_read(&dev->nr_tx_skbs));
1517 ns83820_tx_timeout(ndev);
1518 }
1519
1520 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1521 }
1522
1523 static int ns83820_open(struct net_device *ndev)
1524 {
1525 struct ns83820 *dev = PRIV(ndev);
1526 unsigned i;
1527 u32 desc;
1528 int ret;
1529
1530 dprintk("ns83820_open\n");
1531
1532 writel(0, dev->base + PQCR);
1533
1534 ret = ns83820_setup_rx(ndev);
1535 if (ret)
1536 goto failed;
1537
1538 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1539 for (i=0; i<NR_TX_DESC; i++) {
1540 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1541 = cpu_to_le32(
1542 dev->tx_phy_descs
1543 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1544 }
1545
1546 dev->tx_idx = 0;
1547 dev->tx_done_idx = 0;
1548 desc = dev->tx_phy_descs;
1549 writel(0, dev->base + TXDP_HI);
1550 writel(desc, dev->base + TXDP);
1551
1552 init_timer(&dev->tx_watchdog);
1553 dev->tx_watchdog.data = (unsigned long)ndev;
1554 dev->tx_watchdog.function = ns83820_tx_watch;
1555 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1556
1557 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1558
1559 return 0;
1560
1561 failed:
1562 ns83820_stop(ndev);
1563 return ret;
1564 }
1565
1566 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1567 {
1568 unsigned i;
1569 for (i=0; i<3; i++) {
1570 u32 data;
1571 #if 0 /* I've left this in as an example of how to use eeprom.h */
1572 data = eeprom_readw(&dev->ee, 0xa + 2 - i);
1573 #else
1574 /* Read from the perfect match memory: this is loaded by
1575 * the chip from the EEPROM via the EELOAD self test.
1576 */
1577 writel(i*2, dev->base + RFCR);
1578 data = readl(dev->base + RFDR);
1579 #endif
1580 *mac++ = data;
1581 *mac++ = data >> 8;
1582 }
1583 }
1584
1585 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1586 {
1587 if (new_mtu > RX_BUF_SIZE)
1588 return -EINVAL;
1589 ndev->mtu = new_mtu;
1590 return 0;
1591 }
1592
1593 static void ns83820_set_multicast(struct net_device *ndev)
1594 {
1595 struct ns83820 *dev = PRIV(ndev);
1596 u8 __iomem *rfcr = dev->base + RFCR;
1597 u32 and_mask = 0xffffffff;
1598 u32 or_mask = 0;
1599 u32 val;
1600
1601 if (ndev->flags & IFF_PROMISC)
1602 or_mask |= RFCR_AAU | RFCR_AAM;
1603 else
1604 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1605
1606 if (ndev->flags & IFF_ALLMULTI)
1607 or_mask |= RFCR_AAM;
1608 else
1609 and_mask &= ~RFCR_AAM;
1610
1611 spin_lock_irq(&dev->misc_lock);
1612 val = (readl(rfcr) & and_mask) | or_mask;
1613 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1614 writel(val & ~RFCR_RFEN, rfcr);
1615 writel(val, rfcr);
1616 spin_unlock_irq(&dev->misc_lock);
1617 }
1618
1619 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1620 {
1621 struct ns83820 *dev = PRIV(ndev);
1622 int timed_out = 0;
1623 long start;
1624 u32 status;
1625 int loops = 0;
1626
1627 dprintk("%s: start %s\n", ndev->name, name);
1628
1629 start = jiffies;
1630
1631 writel(enable, dev->base + PTSCR);
1632 for (;;) {
1633 loops++;
1634 status = readl(dev->base + PTSCR);
1635 if (!(status & enable))
1636 break;
1637 if (status & done)
1638 break;
1639 if (status & fail)
1640 break;
1641 if ((jiffies - start) >= HZ) {
1642 timed_out = 1;
1643 break;
1644 }
1645 set_current_state(TASK_UNINTERRUPTIBLE);
1646 schedule_timeout(1);
1647 }
1648
1649 if (status & fail)
1650 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1651 ndev->name, name, status, fail);
1652 else if (timed_out)
1653 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1654 ndev->name, name, status);
1655
1656 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1657 }
1658
1659 #ifdef PHY_CODE_IS_FINISHED
1660 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1661 {
1662 /* drive MDC low */
1663 dev->MEAR_cache &= ~MEAR_MDC;
1664 writel(dev->MEAR_cache, dev->base + MEAR);
1665 readl(dev->base + MEAR);
1666
1667 /* enable output, set bit */
1668 dev->MEAR_cache |= MEAR_MDDIR;
1669 if (bit)
1670 dev->MEAR_cache |= MEAR_MDIO;
1671 else
1672 dev->MEAR_cache &= ~MEAR_MDIO;
1673
1674 /* set the output bit */
1675 writel(dev->MEAR_cache, dev->base + MEAR);
1676 readl(dev->base + MEAR);
1677
1678 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1679 udelay(1);
1680
1681 /* drive MDC high causing the data bit to be latched */
1682 dev->MEAR_cache |= MEAR_MDC;
1683 writel(dev->MEAR_cache, dev->base + MEAR);
1684 readl(dev->base + MEAR);
1685
1686 /* Wait again... */
1687 udelay(1);
1688 }
1689
1690 static int ns83820_mii_read_bit(struct ns83820 *dev)
1691 {
1692 int bit;
1693
1694 /* drive MDC low, disable output */
1695 dev->MEAR_cache &= ~MEAR_MDC;
1696 dev->MEAR_cache &= ~MEAR_MDDIR;
1697 writel(dev->MEAR_cache, dev->base + MEAR);
1698 readl(dev->base + MEAR);
1699
1700 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1701 udelay(1);
1702
1703 /* drive MDC high causing the data bit to be latched */
1704 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1705 dev->MEAR_cache |= MEAR_MDC;
1706 writel(dev->MEAR_cache, dev->base + MEAR);
1707
1708 /* Wait again... */
1709 udelay(1);
1710
1711 return bit;
1712 }
1713
1714 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1715 {
1716 unsigned data = 0;
1717 int i;
1718
1719 /* read some garbage so that we eventually sync up */
1720 for (i=0; i<64; i++)
1721 ns83820_mii_read_bit(dev);
1722
1723 ns83820_mii_write_bit(dev, 0); /* start */
1724 ns83820_mii_write_bit(dev, 1);
1725 ns83820_mii_write_bit(dev, 1); /* opcode read */
1726 ns83820_mii_write_bit(dev, 0);
1727
1728 /* write out the phy address: 5 bits, msb first */
1729 for (i=0; i<5; i++)
1730 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1731
1732 /* write out the register address, 5 bits, msb first */
1733 for (i=0; i<5; i++)
1734 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1735
1736 ns83820_mii_read_bit(dev); /* turn around cycles */
1737 ns83820_mii_read_bit(dev);
1738
1739 /* read in the register data, 16 bits msb first */
1740 for (i=0; i<16; i++) {
1741 data <<= 1;
1742 data |= ns83820_mii_read_bit(dev);
1743 }
1744
1745 return data;
1746 }
1747
1748 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1749 {
1750 int i;
1751
1752 /* read some garbage so that we eventually sync up */
1753 for (i=0; i<64; i++)
1754 ns83820_mii_read_bit(dev);
1755
1756 ns83820_mii_write_bit(dev, 0); /* start */
1757 ns83820_mii_write_bit(dev, 1);
1758 ns83820_mii_write_bit(dev, 0); /* opcode read */
1759 ns83820_mii_write_bit(dev, 1);
1760
1761 /* write out the phy address: 5 bits, msb first */
1762 for (i=0; i<5; i++)
1763 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1764
1765 /* write out the register address, 5 bits, msb first */
1766 for (i=0; i<5; i++)
1767 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1768
1769 ns83820_mii_read_bit(dev); /* turn around cycles */
1770 ns83820_mii_read_bit(dev);
1771
1772 /* read in the register data, 16 bits msb first */
1773 for (i=0; i<16; i++)
1774 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1775
1776 return data;
1777 }
1778
1779 static void ns83820_probe_phy(struct net_device *ndev)
1780 {
1781 struct ns83820 *dev = PRIV(ndev);
1782 static int first;
1783 int i;
1784 #define MII_PHYIDR1 0x02
1785 #define MII_PHYIDR2 0x03
1786
1787 #if 0
1788 if (!first) {
1789 unsigned tmp;
1790 ns83820_mii_read_reg(dev, 1, 0x09);
1791 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1792
1793 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1794 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1795 udelay(1300);
1796 ns83820_mii_read_reg(dev, 1, 0x09);
1797 }
1798 #endif
1799 first = 1;
1800
1801 for (i=1; i<2; i++) {
1802 int j;
1803 unsigned a, b;
1804 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1805 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1806
1807 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1808 // ndev->name, i, a, b);
1809
1810 for (j=0; j<0x16; j+=4) {
1811 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1812 ndev->name, j,
1813 ns83820_mii_read_reg(dev, i, 0 + j),
1814 ns83820_mii_read_reg(dev, i, 1 + j),
1815 ns83820_mii_read_reg(dev, i, 2 + j),
1816 ns83820_mii_read_reg(dev, i, 3 + j)
1817 );
1818 }
1819 }
1820 {
1821 unsigned a, b;
1822 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1823 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1824 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1825 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1826
1827 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1828 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1829 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1830 dprintk("version: 0x%04x 0x%04x\n", a, b);
1831 }
1832 }
1833 #endif
1834
1835 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1836 {
1837 struct net_device *ndev;
1838 struct ns83820 *dev;
1839 long addr;
1840 int err;
1841 int using_dac = 0;
1842
1843 /* See if we can set the dma mask early on; failure is fatal. */
1844 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1845 using_dac = 1;
1846 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1847 using_dac = 0;
1848 } else {
1849 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1850 return -ENODEV;
1851 }
1852
1853 ndev = alloc_etherdev(sizeof(struct ns83820));
1854 dev = PRIV(ndev);
1855 err = -ENOMEM;
1856 if (!dev)
1857 goto out;
1858
1859 spin_lock_init(&dev->rx_info.lock);
1860 spin_lock_init(&dev->tx_lock);
1861 spin_lock_init(&dev->misc_lock);
1862 dev->pci_dev = pci_dev;
1863
1864 dev->ee.cache = &dev->MEAR_cache;
1865 dev->ee.lock = &dev->misc_lock;
1866 SET_MODULE_OWNER(ndev);
1867 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1868
1869 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1870 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1871
1872 err = pci_enable_device(pci_dev);
1873 if (err) {
1874 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1875 goto out_free;
1876 }
1877
1878 pci_set_master(pci_dev);
1879 addr = pci_resource_start(pci_dev, 1);
1880 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1881 dev->tx_descs = pci_alloc_consistent(pci_dev,
1882 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1883 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1884 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1885 err = -ENOMEM;
1886 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1887 goto out_disable;
1888
1889 dprintk("%p: %08lx %p: %08lx\n",
1890 dev->tx_descs, (long)dev->tx_phy_descs,
1891 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1892
1893 /* disable interrupts */
1894 writel(0, dev->base + IMR);
1895 writel(0, dev->base + IER);
1896 readl(dev->base + IER);
1897
1898 dev->IMR_cache = 0;
1899
1900 setup_ee_mem_bitbanger(&dev->ee, dev->base + MEAR, 3, 2, 1, 0,
1901 0);
1902
1903 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1904 DRV_NAME, ndev);
1905 if (err) {
1906 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1907 pci_dev->irq);
1908 goto out_disable;
1909 }
1910
1911 /*
1912 * FIXME: we are holding rtnl_lock() over obscenely long area only
1913 * because some of the setup code uses dev->name. It's Wrong(tm) -
1914 * we should be using driver-specific names for all that stuff.
1915 * For now that will do, but we really need to come back and kill
1916 * most of the dev_alloc_name() users later.
1917 */
1918 rtnl_lock();
1919 err = dev_alloc_name(ndev, ndev->name);
1920 if (err < 0) {
1921 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1922 goto out_free_irq;
1923 }
1924
1925 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1926 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1927 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1928
1929 ndev->open = ns83820_open;
1930 ndev->stop = ns83820_stop;
1931 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1932 ndev->get_stats = ns83820_get_stats;
1933 ndev->change_mtu = ns83820_change_mtu;
1934 ndev->set_multicast_list = ns83820_set_multicast;
1935 SET_ETHTOOL_OPS(ndev, &ops);
1936 ndev->tx_timeout = ns83820_tx_timeout;
1937 ndev->watchdog_timeo = 5 * HZ;
1938 pci_set_drvdata(pci_dev, ndev);
1939
1940 ns83820_do_reset(dev, CR_RST);
1941
1942 /* Must reset the ram bist before running it */
1943 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1944 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1945 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1946 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1947 PTSCR_EEBIST_FAIL);
1948 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1949
1950 /* I love config registers */
1951 dev->CFG_cache = readl(dev->base + CFG);
1952
1953 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1954 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1955 ndev->name);
1956 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1957 if (!(dev->CFG_cache & CFG_DATA64_EN))
1958 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1959 ndev->name);
1960 } else
1961 dev->CFG_cache &= ~(CFG_DATA64_EN);
1962
1963 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1964 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1965 CFG_M64ADDR);
1966 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1967 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1968 dev->CFG_cache |= CFG_REQALG;
1969 dev->CFG_cache |= CFG_POW;
1970 dev->CFG_cache |= CFG_TMRTEST;
1971
1972 /* When compiled with 64 bit addressing, we must always enable
1973 * the 64 bit descriptor format.
1974 */
1975 #ifdef USE_64BIT_ADDR
1976 dev->CFG_cache |= CFG_M64ADDR;
1977 #endif
1978 if (using_dac)
1979 dev->CFG_cache |= CFG_T64ADDR;
1980
1981 /* Big endian mode does not seem to do what the docs suggest */
1982 dev->CFG_cache &= ~CFG_BEM;
1983
1984 /* setup optical transceiver if we have one */
1985 if (dev->CFG_cache & CFG_TBI_EN) {
1986 printk(KERN_INFO "%s: enabling optical transceiver\n",
1987 ndev->name);
1988 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1989
1990 /* setup auto negotiation feature advertisement */
1991 writel(readl(dev->base + TANAR)
1992 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1993 dev->base + TANAR);
1994
1995 /* start auto negotiation */
1996 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1997 dev->base + TBICR);
1998 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1999 dev->linkstate = LINK_AUTONEGOTIATE;
2000
2001 dev->CFG_cache |= CFG_MODE_1000;
2002 }
2003
2004 writel(dev->CFG_cache, dev->base + CFG);
2005 dprintk("CFG: %08x\n", dev->CFG_cache);
2006
2007 if (reset_phy) {
2008 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2009 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2010 msleep(10);
2011 writel(dev->CFG_cache, dev->base + CFG);
2012 }
2013
2014 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2015 * the PCI layer. FIXME.
2016 */
2017 if (readl(dev->base + SRR))
2018 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2019 #endif
2020
2021 /* Note! The DMA burst size interacts with packet
2022 * transmission, such that the largest packet that
2023 * can be transmitted is 8192 - FLTH - burst size.
2024 * If only the transmit fifo was larger...
2025 */
2026 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2027 * some DELL and COMPAQ SMP systems */
2028 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2029 | ((1600 / 32) * 0x100),
2030 dev->base + TXCFG);
2031
2032 /* Flush the interrupt holdoff timer */
2033 writel(0x000, dev->base + IHR);
2034 writel(0x100, dev->base + IHR);
2035 writel(0x000, dev->base + IHR);
2036
2037 /* Set Rx to full duplex, don't accept runt, errored, long or length
2038 * range errored packets. Use 512 byte DMA.
2039 */
2040 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2041 * some DELL and COMPAQ SMP systems
2042 * Turn on ALP, only we are accpeting Jumbo Packets */
2043 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2044 | RXCFG_STRIPCRC
2045 //| RXCFG_ALP
2046 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2047
2048 /* Disable priority queueing */
2049 writel(0, dev->base + PQCR);
2050
2051 /* Enable IP checksum validation and detetion of VLAN headers.
2052 * Note: do not set the reject options as at least the 0x102
2053 * revision of the chip does not properly accept IP fragments
2054 * at least for UDP.
2055 */
2056 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2057 * the MAC it calculates the packetsize AFTER stripping the VLAN
2058 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2059 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2060 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2061 * it discrards it!. These guys......
2062 * also turn on tag stripping if hardware acceleration is enabled
2063 */
2064 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2065 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2066 #else
2067 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2068 #endif
2069 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2070
2071 /* Enable per-packet TCP/UDP/IP checksumming
2072 * and per packet vlan tag insertion if
2073 * vlan hardware acceleration is enabled
2074 */
2075 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2076 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2077 #else
2078 #define VTCR_INIT_VALUE VTCR_PPCHK
2079 #endif
2080 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2081
2082 /* Ramit : Enable async and sync pause frames */
2083 /* writel(0, dev->base + PCR); */
2084 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2085 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2086 dev->base + PCR);
2087
2088 /* Disable Wake On Lan */
2089 writel(0, dev->base + WCSR);
2090
2091 ns83820_getmac(dev, ndev->dev_addr);
2092
2093 /* Yes, we support dumb IP checksum on transmit */
2094 ndev->features |= NETIF_F_SG;
2095 ndev->features |= NETIF_F_IP_CSUM;
2096
2097 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2098 /* We also support hardware vlan acceleration */
2099 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2100 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2101 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2102 #endif
2103
2104 if (using_dac) {
2105 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2106 ndev->name);
2107 ndev->features |= NETIF_F_HIGHDMA;
2108 }
2109
2110 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2111 ndev->name,
2112 (unsigned)readl(dev->base + SRR) >> 8,
2113 (unsigned)readl(dev->base + SRR) & 0xff,
2114 ndev->dev_addr[0], ndev->dev_addr[1],
2115 ndev->dev_addr[2], ndev->dev_addr[3],
2116 ndev->dev_addr[4], ndev->dev_addr[5],
2117 addr, pci_dev->irq,
2118 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2119 );
2120
2121 #ifdef PHY_CODE_IS_FINISHED
2122 ns83820_probe_phy(ndev);
2123 #endif
2124
2125 err = register_netdevice(ndev);
2126 if (err) {
2127 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2128 goto out_cleanup;
2129 }
2130 rtnl_unlock();
2131
2132 return 0;
2133
2134 out_cleanup:
2135 writel(0, dev->base + IMR); /* paranoia */
2136 writel(0, dev->base + IER);
2137 readl(dev->base + IER);
2138 out_free_irq:
2139 rtnl_unlock();
2140 free_irq(pci_dev->irq, ndev);
2141 out_disable:
2142 if (dev->base)
2143 iounmap(dev->base);
2144 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2145 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2146 pci_disable_device(pci_dev);
2147 out_free:
2148 free_netdev(ndev);
2149 pci_set_drvdata(pci_dev, NULL);
2150 out:
2151 return err;
2152 }
2153
2154 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2155 {
2156 struct net_device *ndev = pci_get_drvdata(pci_dev);
2157 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2158
2159 if (!ndev) /* paranoia */
2160 return;
2161
2162 writel(0, dev->base + IMR); /* paranoia */
2163 writel(0, dev->base + IER);
2164 readl(dev->base + IER);
2165
2166 unregister_netdev(ndev);
2167 free_irq(dev->pci_dev->irq, ndev);
2168 iounmap(dev->base);
2169 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2170 dev->tx_descs, dev->tx_phy_descs);
2171 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2172 dev->rx_info.descs, dev->rx_info.phy_descs);
2173 pci_disable_device(dev->pci_dev);
2174 free_netdev(ndev);
2175 pci_set_drvdata(pci_dev, NULL);
2176 }
2177
2178 static struct pci_device_id ns83820_pci_tbl[] = {
2179 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2180 { 0, },
2181 };
2182
2183 static struct pci_driver driver = {
2184 .name = "ns83820",
2185 .id_table = ns83820_pci_tbl,
2186 .probe = ns83820_init_one,
2187 .remove = __devexit_p(ns83820_remove_one),
2188 #if 0 /* FIXME: implement */
2189 .suspend = ,
2190 .resume = ,
2191 #endif
2192 };
2193
2194
2195 static int __init ns83820_init(void)
2196 {
2197 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2198 return pci_module_init(&driver);
2199 }
2200
2201 static void __exit ns83820_exit(void)
2202 {
2203 pci_unregister_driver(&driver);
2204 }
2205
2206 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2207 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2208 MODULE_LICENSE("GPL");
2209
2210 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2211
2212 module_param(lnksts, int, 0);
2213 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2214
2215 module_param(ihr, int, 0);
2216 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2217
2218 module_param(reset_phy, int, 0);
2219 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2220
2221 module_init(ns83820_init);
2222 module_exit(ns83820_exit);
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