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[XFRM]: skb_cow_data() does not set proper owner for new skbs.
[linux-2.6/verdex.git] / drivers / net / tg3.c
blob4d2bdbdd34e83f990e77d97675e5a9cb03e0c95e
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Copyright (C) 2000-2003 Broadcom Corporation.
11 */
12
13 #include <linux/config.h>
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/ethtool.h>
29 #include <linux/mii.h>
30 #include <linux/if_vlan.h>
31 #include <linux/ip.h>
32 #include <linux/tcp.h>
33 #include <linux/workqueue.h>
34
35 #include <net/checksum.h>
36
37 #include <asm/system.h>
38 #include <asm/io.h>
39 #include <asm/byteorder.h>
40 #include <asm/uaccess.h>
41
42 #ifdef CONFIG_SPARC64
43 #include <asm/idprom.h>
44 #include <asm/oplib.h>
45 #include <asm/pbm.h>
46 #endif
47
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define TG3_VLAN_TAG_USED 1
50 #else
51 #define TG3_VLAN_TAG_USED 0
52 #endif
53
54 #ifdef NETIF_F_TSO
55 #define TG3_TSO_SUPPORT 1
56 #else
57 #define TG3_TSO_SUPPORT 0
58 #endif
59
60 #include "tg3.h"
61
62 #define DRV_MODULE_NAME "tg3"
63 #define PFX DRV_MODULE_NAME ": "
64 #define DRV_MODULE_VERSION "3.27"
65 #define DRV_MODULE_RELDATE "May 5, 2005"
66
67 #define TG3_DEF_MAC_MODE 0
68 #define TG3_DEF_RX_MODE 0
69 #define TG3_DEF_TX_MODE 0
70 #define TG3_DEF_MSG_ENABLE \
71 (NETIF_MSG_DRV | \
72 NETIF_MSG_PROBE | \
73 NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | \
75 NETIF_MSG_IFDOWN | \
76 NETIF_MSG_IFUP | \
77 NETIF_MSG_RX_ERR | \
78 NETIF_MSG_TX_ERR)
79
80 /* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
82 */
83 #define TG3_TX_TIMEOUT (5 * HZ)
84
85 /* hardware minimum and maximum for a single frame's data payload */
86 #define TG3_MIN_MTU 60
87 #define TG3_MAX_MTU(tp) \
88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
89
90 /* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
93 */
94 #define TG3_RX_RING_SIZE 512
95 #define TG3_DEF_RX_RING_PENDING 200
96 #define TG3_RX_JUMBO_RING_SIZE 256
97 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
98
99 /* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
104 */
105 #define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
107
108 #define TG3_TX_RING_SIZE 512
109 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
110
111 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
112 TG3_RX_RING_SIZE)
113 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
118 TG3_TX_RING_SIZE)
119 #define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121 #define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
126
127 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
129
130 /* minimum number of free TX descriptors required to wake up TX process */
131 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
132
133 /* number of ETHTOOL_GSTATS u64's */
134 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
135
136 static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_MODULE_VERSION);
143
144 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145 module_param(tg3_debug, int, 0);
146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148 static struct pci_device_id tg3_pci_tbl[] = {
149 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
151 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
231 { 0, }
232 };
233
234 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
235
236 static struct {
237 const char string[ETH_GSTRING_LEN];
238 } ethtool_stats_keys[TG3_NUM_STATS] = {
239 { "rx_octets" },
240 { "rx_fragments" },
241 { "rx_ucast_packets" },
242 { "rx_mcast_packets" },
243 { "rx_bcast_packets" },
244 { "rx_fcs_errors" },
245 { "rx_align_errors" },
246 { "rx_xon_pause_rcvd" },
247 { "rx_xoff_pause_rcvd" },
248 { "rx_mac_ctrl_rcvd" },
249 { "rx_xoff_entered" },
250 { "rx_frame_too_long_errors" },
251 { "rx_jabbers" },
252 { "rx_undersize_packets" },
253 { "rx_in_length_errors" },
254 { "rx_out_length_errors" },
255 { "rx_64_or_less_octet_packets" },
256 { "rx_65_to_127_octet_packets" },
257 { "rx_128_to_255_octet_packets" },
258 { "rx_256_to_511_octet_packets" },
259 { "rx_512_to_1023_octet_packets" },
260 { "rx_1024_to_1522_octet_packets" },
261 { "rx_1523_to_2047_octet_packets" },
262 { "rx_2048_to_4095_octet_packets" },
263 { "rx_4096_to_8191_octet_packets" },
264 { "rx_8192_to_9022_octet_packets" },
265
266 { "tx_octets" },
267 { "tx_collisions" },
268
269 { "tx_xon_sent" },
270 { "tx_xoff_sent" },
271 { "tx_flow_control" },
272 { "tx_mac_errors" },
273 { "tx_single_collisions" },
274 { "tx_mult_collisions" },
275 { "tx_deferred" },
276 { "tx_excessive_collisions" },
277 { "tx_late_collisions" },
278 { "tx_collide_2times" },
279 { "tx_collide_3times" },
280 { "tx_collide_4times" },
281 { "tx_collide_5times" },
282 { "tx_collide_6times" },
283 { "tx_collide_7times" },
284 { "tx_collide_8times" },
285 { "tx_collide_9times" },
286 { "tx_collide_10times" },
287 { "tx_collide_11times" },
288 { "tx_collide_12times" },
289 { "tx_collide_13times" },
290 { "tx_collide_14times" },
291 { "tx_collide_15times" },
292 { "tx_ucast_packets" },
293 { "tx_mcast_packets" },
294 { "tx_bcast_packets" },
295 { "tx_carrier_sense_errors" },
296 { "tx_discards" },
297 { "tx_errors" },
298
299 { "dma_writeq_full" },
300 { "dma_write_prioq_full" },
301 { "rxbds_empty" },
302 { "rx_discards" },
303 { "rx_errors" },
304 { "rx_threshold_hit" },
305
306 { "dma_readq_full" },
307 { "dma_read_prioq_full" },
308 { "tx_comp_queue_full" },
309
310 { "ring_set_send_prod_index" },
311 { "ring_status_update" },
312 { "nic_irqs" },
313 { "nic_avoided_irqs" },
314 { "nic_tx_threshold_hit" }
315 };
316
317 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
318 {
319 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
320 unsigned long flags;
321
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags);
326 } else {
327 writel(val, tp->regs + off);
328 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
329 readl(tp->regs + off);
330 }
331 }
332
333 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
334 {
335 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
336 unsigned long flags;
337
338 spin_lock_irqsave(&tp->indirect_lock, flags);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
341 spin_unlock_irqrestore(&tp->indirect_lock, flags);
342 } else {
343 void __iomem *dest = tp->regs + off;
344 writel(val, dest);
345 readl(dest); /* always flush PCI write */
346 }
347 }
348
349 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
350 {
351 void __iomem *mbox = tp->regs + off;
352 writel(val, mbox);
353 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
354 readl(mbox);
355 }
356
357 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
358 {
359 void __iomem *mbox = tp->regs + off;
360 writel(val, mbox);
361 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
362 writel(val, mbox);
363 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
364 readl(mbox);
365 }
366
367 #define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
368 #define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
369 #define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
370
371 #define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
372 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
373 #define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
374 #define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
375 #define tr32(reg) readl(tp->regs + (reg))
376 #define tr16(reg) readw(tp->regs + (reg))
377 #define tr8(reg) readb(tp->regs + (reg))
378
379 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
380 {
381 unsigned long flags;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
385 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
386
387 /* Always leave this as zero. */
388 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
389 spin_unlock_irqrestore(&tp->indirect_lock, flags);
390 }
391
392 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
393 {
394 unsigned long flags;
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
398 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
399
400 /* Always leave this as zero. */
401 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
403 }
404
405 static void tg3_disable_ints(struct tg3 *tp)
406 {
407 tw32(TG3PCI_MISC_HOST_CTRL,
408 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
409 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
410 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
411 }
412
413 static inline void tg3_cond_int(struct tg3 *tp)
414 {
415 if (tp->hw_status->status & SD_STATUS_UPDATED)
416 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
417 }
418
419 static void tg3_enable_ints(struct tg3 *tp)
420 {
421 tw32(TG3PCI_MISC_HOST_CTRL,
422 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
423 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
424 (tp->last_tag << 24));
425 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
426
427 tg3_cond_int(tp);
428 }
429
430 static inline unsigned int tg3_has_work(struct tg3 *tp)
431 {
432 struct tg3_hw_status *sblk = tp->hw_status;
433 unsigned int work_exists = 0;
434
435 /* check for phy events */
436 if (!(tp->tg3_flags &
437 (TG3_FLAG_USE_LINKCHG_REG |
438 TG3_FLAG_POLL_SERDES))) {
439 if (sblk->status & SD_STATUS_LINK_CHG)
440 work_exists = 1;
441 }
442 /* check for RX/TX work to do */
443 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
444 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
445 work_exists = 1;
446
447 return work_exists;
448 }
449
450 /* tg3_restart_ints
451 * similar to tg3_enable_ints, but it accurately determines whether there
452 * is new work pending and can return without flushing the PIO write
453 * which reenables interrupts
454 */
455 static void tg3_restart_ints(struct tg3 *tp)
456 {
457 tw32(TG3PCI_MISC_HOST_CTRL,
458 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
459 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
460 tp->last_tag << 24);
461 mmiowb();
462
463 /* When doing tagged status, this work check is unnecessary.
464 * The last_tag we write above tells the chip which piece of
465 * work we've completed.
466 */
467 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
468 tg3_has_work(tp))
469 tw32(HOSTCC_MODE, tp->coalesce_mode |
470 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
471 }
472
473 static inline void tg3_netif_stop(struct tg3 *tp)
474 {
475 netif_poll_disable(tp->dev);
476 netif_tx_disable(tp->dev);
477 }
478
479 static inline void tg3_netif_start(struct tg3 *tp)
480 {
481 netif_wake_queue(tp->dev);
482 /* NOTE: unconditional netif_wake_queue is only appropriate
483 * so long as all callers are assured to have free tx slots
484 * (such as after tg3_init_hw)
485 */
486 netif_poll_enable(tp->dev);
487 tg3_cond_int(tp);
488 }
489
490 static void tg3_switch_clocks(struct tg3 *tp)
491 {
492 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
493 u32 orig_clock_ctrl;
494
495 orig_clock_ctrl = clock_ctrl;
496 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
497 CLOCK_CTRL_CLKRUN_OENABLE |
498 0x1f);
499 tp->pci_clock_ctrl = clock_ctrl;
500
501 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
502 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
503 tw32_f(TG3PCI_CLOCK_CTRL,
504 clock_ctrl | CLOCK_CTRL_625_CORE);
505 udelay(40);
506 }
507 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
508 tw32_f(TG3PCI_CLOCK_CTRL,
509 clock_ctrl |
510 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
511 udelay(40);
512 tw32_f(TG3PCI_CLOCK_CTRL,
513 clock_ctrl | (CLOCK_CTRL_ALTCLK));
514 udelay(40);
515 }
516 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
517 udelay(40);
518 }
519
520 #define PHY_BUSY_LOOPS 5000
521
522 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
523 {
524 u32 frame_val;
525 unsigned int loops;
526 int ret;
527
528 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
529 tw32_f(MAC_MI_MODE,
530 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
531 udelay(80);
532 }
533
534 *val = 0x0;
535
536 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
537 MI_COM_PHY_ADDR_MASK);
538 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
539 MI_COM_REG_ADDR_MASK);
540 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
541
542 tw32_f(MAC_MI_COM, frame_val);
543
544 loops = PHY_BUSY_LOOPS;
545 while (loops != 0) {
546 udelay(10);
547 frame_val = tr32(MAC_MI_COM);
548
549 if ((frame_val & MI_COM_BUSY) == 0) {
550 udelay(5);
551 frame_val = tr32(MAC_MI_COM);
552 break;
553 }
554 loops -= 1;
555 }
556
557 ret = -EBUSY;
558 if (loops != 0) {
559 *val = frame_val & MI_COM_DATA_MASK;
560 ret = 0;
561 }
562
563 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
564 tw32_f(MAC_MI_MODE, tp->mi_mode);
565 udelay(80);
566 }
567
568 return ret;
569 }
570
571 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
572 {
573 u32 frame_val;
574 unsigned int loops;
575 int ret;
576
577 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
578 tw32_f(MAC_MI_MODE,
579 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
580 udelay(80);
581 }
582
583 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
584 MI_COM_PHY_ADDR_MASK);
585 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
586 MI_COM_REG_ADDR_MASK);
587 frame_val |= (val & MI_COM_DATA_MASK);
588 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
589
590 tw32_f(MAC_MI_COM, frame_val);
591
592 loops = PHY_BUSY_LOOPS;
593 while (loops != 0) {
594 udelay(10);
595 frame_val = tr32(MAC_MI_COM);
596 if ((frame_val & MI_COM_BUSY) == 0) {
597 udelay(5);
598 frame_val = tr32(MAC_MI_COM);
599 break;
600 }
601 loops -= 1;
602 }
603
604 ret = -EBUSY;
605 if (loops != 0)
606 ret = 0;
607
608 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
609 tw32_f(MAC_MI_MODE, tp->mi_mode);
610 udelay(80);
611 }
612
613 return ret;
614 }
615
616 static void tg3_phy_set_wirespeed(struct tg3 *tp)
617 {
618 u32 val;
619
620 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
621 return;
622
623 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
624 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
625 tg3_writephy(tp, MII_TG3_AUX_CTRL,
626 (val | (1 << 15) | (1 << 4)));
627 }
628
629 static int tg3_bmcr_reset(struct tg3 *tp)
630 {
631 u32 phy_control;
632 int limit, err;
633
634 /* OK, reset it, and poll the BMCR_RESET bit until it
635 * clears or we time out.
636 */
637 phy_control = BMCR_RESET;
638 err = tg3_writephy(tp, MII_BMCR, phy_control);
639 if (err != 0)
640 return -EBUSY;
641
642 limit = 5000;
643 while (limit--) {
644 err = tg3_readphy(tp, MII_BMCR, &phy_control);
645 if (err != 0)
646 return -EBUSY;
647
648 if ((phy_control & BMCR_RESET) == 0) {
649 udelay(40);
650 break;
651 }
652 udelay(10);
653 }
654 if (limit <= 0)
655 return -EBUSY;
656
657 return 0;
658 }
659
660 static int tg3_wait_macro_done(struct tg3 *tp)
661 {
662 int limit = 100;
663
664 while (limit--) {
665 u32 tmp32;
666
667 if (!tg3_readphy(tp, 0x16, &tmp32)) {
668 if ((tmp32 & 0x1000) == 0)
669 break;
670 }
671 }
672 if (limit <= 0)
673 return -EBUSY;
674
675 return 0;
676 }
677
678 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
679 {
680 static const u32 test_pat[4][6] = {
681 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
682 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
683 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
684 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
685 };
686 int chan;
687
688 for (chan = 0; chan < 4; chan++) {
689 int i;
690
691 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
692 (chan * 0x2000) | 0x0200);
693 tg3_writephy(tp, 0x16, 0x0002);
694
695 for (i = 0; i < 6; i++)
696 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
697 test_pat[chan][i]);
698
699 tg3_writephy(tp, 0x16, 0x0202);
700 if (tg3_wait_macro_done(tp)) {
701 *resetp = 1;
702 return -EBUSY;
703 }
704
705 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
706 (chan * 0x2000) | 0x0200);
707 tg3_writephy(tp, 0x16, 0x0082);
708 if (tg3_wait_macro_done(tp)) {
709 *resetp = 1;
710 return -EBUSY;
711 }
712
713 tg3_writephy(tp, 0x16, 0x0802);
714 if (tg3_wait_macro_done(tp)) {
715 *resetp = 1;
716 return -EBUSY;
717 }
718
719 for (i = 0; i < 6; i += 2) {
720 u32 low, high;
721
722 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
723 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
724 tg3_wait_macro_done(tp)) {
725 *resetp = 1;
726 return -EBUSY;
727 }
728 low &= 0x7fff;
729 high &= 0x000f;
730 if (low != test_pat[chan][i] ||
731 high != test_pat[chan][i+1]) {
732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
734 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
735
736 return -EBUSY;
737 }
738 }
739 }
740
741 return 0;
742 }
743
744 static int tg3_phy_reset_chanpat(struct tg3 *tp)
745 {
746 int chan;
747
748 for (chan = 0; chan < 4; chan++) {
749 int i;
750
751 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
752 (chan * 0x2000) | 0x0200);
753 tg3_writephy(tp, 0x16, 0x0002);
754 for (i = 0; i < 6; i++)
755 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
756 tg3_writephy(tp, 0x16, 0x0202);
757 if (tg3_wait_macro_done(tp))
758 return -EBUSY;
759 }
760
761 return 0;
762 }
763
764 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
765 {
766 u32 reg32, phy9_orig;
767 int retries, do_phy_reset, err;
768
769 retries = 10;
770 do_phy_reset = 1;
771 do {
772 if (do_phy_reset) {
773 err = tg3_bmcr_reset(tp);
774 if (err)
775 return err;
776 do_phy_reset = 0;
777 }
778
779 /* Disable transmitter and interrupt. */
780 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
781 continue;
782
783 reg32 |= 0x3000;
784 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
785
786 /* Set full-duplex, 1000 mbps. */
787 tg3_writephy(tp, MII_BMCR,
788 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
789
790 /* Set to master mode. */
791 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
792 continue;
793
794 tg3_writephy(tp, MII_TG3_CTRL,
795 (MII_TG3_CTRL_AS_MASTER |
796 MII_TG3_CTRL_ENABLE_AS_MASTER));
797
798 /* Enable SM_DSP_CLOCK and 6dB. */
799 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
800
801 /* Block the PHY control access. */
802 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
803 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
804
805 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
806 if (!err)
807 break;
808 } while (--retries);
809
810 err = tg3_phy_reset_chanpat(tp);
811 if (err)
812 return err;
813
814 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
815 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
816
817 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
818 tg3_writephy(tp, 0x16, 0x0000);
819
820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
822 /* Set Extended packet length bit for jumbo frames */
823 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
824 }
825 else {
826 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
827 }
828
829 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
830
831 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
832 reg32 &= ~0x3000;
833 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
834 } else if (!err)
835 err = -EBUSY;
836
837 return err;
838 }
839
840 /* This will reset the tigon3 PHY if there is no valid
841 * link unless the FORCE argument is non-zero.
842 */
843 static int tg3_phy_reset(struct tg3 *tp)
844 {
845 u32 phy_status;
846 int err;
847
848 err = tg3_readphy(tp, MII_BMSR, &phy_status);
849 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
850 if (err != 0)
851 return -EBUSY;
852
853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
856 err = tg3_phy_reset_5703_4_5(tp);
857 if (err)
858 return err;
859 goto out;
860 }
861
862 err = tg3_bmcr_reset(tp);
863 if (err)
864 return err;
865
866 out:
867 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
868 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
874 }
875 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
876 tg3_writephy(tp, 0x1c, 0x8d68);
877 tg3_writephy(tp, 0x1c, 0x8d68);
878 }
879 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
880 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
881 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
882 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
883 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
884 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
885 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
886 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
887 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
888 }
889 /* Set Extended packet length bit (bit 14) on all chips that */
890 /* support jumbo frames */
891 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
892 /* Cannot do read-modify-write on 5401 */
893 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
894 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
895 u32 phy_reg;
896
897 /* Set bit 14 with read-modify-write to preserve other bits */
898 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
899 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
900 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
901 }
902
903 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
904 * jumbo frames transmission.
905 */
906 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
907 u32 phy_reg;
908
909 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
910 tg3_writephy(tp, MII_TG3_EXT_CTRL,
911 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
912 }
913
914 tg3_phy_set_wirespeed(tp);
915 return 0;
916 }
917
918 static void tg3_frob_aux_power(struct tg3 *tp)
919 {
920 struct tg3 *tp_peer = tp;
921
922 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
923 return;
924
925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
926 tp_peer = pci_get_drvdata(tp->pdev_peer);
927 if (!tp_peer)
928 BUG();
929 }
930
931
932 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
933 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
936 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
937 (GRC_LCLCTRL_GPIO_OE0 |
938 GRC_LCLCTRL_GPIO_OE1 |
939 GRC_LCLCTRL_GPIO_OE2 |
940 GRC_LCLCTRL_GPIO_OUTPUT0 |
941 GRC_LCLCTRL_GPIO_OUTPUT1));
942 udelay(100);
943 } else {
944 u32 no_gpio2;
945 u32 grc_local_ctrl;
946
947 if (tp_peer != tp &&
948 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
949 return;
950
951 /* On 5753 and variants, GPIO2 cannot be used. */
952 no_gpio2 = tp->nic_sram_data_cfg &
953 NIC_SRAM_DATA_CFG_NO_GPIO2;
954
955 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
956 GRC_LCLCTRL_GPIO_OE1 |
957 GRC_LCLCTRL_GPIO_OE2 |
958 GRC_LCLCTRL_GPIO_OUTPUT1 |
959 GRC_LCLCTRL_GPIO_OUTPUT2;
960 if (no_gpio2) {
961 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
962 GRC_LCLCTRL_GPIO_OUTPUT2);
963 }
964 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
965 grc_local_ctrl);
966 udelay(100);
967
968 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
969
970 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
971 grc_local_ctrl);
972 udelay(100);
973
974 if (!no_gpio2) {
975 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
976 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
977 grc_local_ctrl);
978 udelay(100);
979 }
980 }
981 } else {
982 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
983 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
984 if (tp_peer != tp &&
985 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
986 return;
987
988 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
989 (GRC_LCLCTRL_GPIO_OE1 |
990 GRC_LCLCTRL_GPIO_OUTPUT1));
991 udelay(100);
992
993 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
994 (GRC_LCLCTRL_GPIO_OE1));
995 udelay(100);
996
997 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
998 (GRC_LCLCTRL_GPIO_OE1 |
999 GRC_LCLCTRL_GPIO_OUTPUT1));
1000 udelay(100);
1001 }
1002 }
1003 }
1004
1005 static int tg3_setup_phy(struct tg3 *, int);
1006
1007 #define RESET_KIND_SHUTDOWN 0
1008 #define RESET_KIND_INIT 1
1009 #define RESET_KIND_SUSPEND 2
1010
1011 static void tg3_write_sig_post_reset(struct tg3 *, int);
1012 static int tg3_halt_cpu(struct tg3 *, u32);
1013
1014 static int tg3_set_power_state(struct tg3 *tp, int state)
1015 {
1016 u32 misc_host_ctrl;
1017 u16 power_control, power_caps;
1018 int pm = tp->pm_cap;
1019
1020 /* Make sure register accesses (indirect or otherwise)
1021 * will function correctly.
1022 */
1023 pci_write_config_dword(tp->pdev,
1024 TG3PCI_MISC_HOST_CTRL,
1025 tp->misc_host_ctrl);
1026
1027 pci_read_config_word(tp->pdev,
1028 pm + PCI_PM_CTRL,
1029 &power_control);
1030 power_control |= PCI_PM_CTRL_PME_STATUS;
1031 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1032 switch (state) {
1033 case 0:
1034 power_control |= 0;
1035 pci_write_config_word(tp->pdev,
1036 pm + PCI_PM_CTRL,
1037 power_control);
1038 udelay(100); /* Delay after power state change */
1039
1040 /* Switch out of Vaux if it is not a LOM */
1041 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1042 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1043 udelay(100);
1044 }
1045
1046 return 0;
1047
1048 case 1:
1049 power_control |= 1;
1050 break;
1051
1052 case 2:
1053 power_control |= 2;
1054 break;
1055
1056 case 3:
1057 power_control |= 3;
1058 break;
1059
1060 default:
1061 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1062 "requested.\n",
1063 tp->dev->name, state);
1064 return -EINVAL;
1065 };
1066
1067 power_control |= PCI_PM_CTRL_PME_ENABLE;
1068
1069 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1070 tw32(TG3PCI_MISC_HOST_CTRL,
1071 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1072
1073 if (tp->link_config.phy_is_low_power == 0) {
1074 tp->link_config.phy_is_low_power = 1;
1075 tp->link_config.orig_speed = tp->link_config.speed;
1076 tp->link_config.orig_duplex = tp->link_config.duplex;
1077 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1078 }
1079
1080 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1081 tp->link_config.speed = SPEED_10;
1082 tp->link_config.duplex = DUPLEX_HALF;
1083 tp->link_config.autoneg = AUTONEG_ENABLE;
1084 tg3_setup_phy(tp, 0);
1085 }
1086
1087 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1088
1089 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1090 u32 mac_mode;
1091
1092 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1093 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1094 udelay(40);
1095
1096 mac_mode = MAC_MODE_PORT_MODE_MII;
1097
1098 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1099 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1100 mac_mode |= MAC_MODE_LINK_POLARITY;
1101 } else {
1102 mac_mode = MAC_MODE_PORT_MODE_TBI;
1103 }
1104
1105 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1106 tw32(MAC_LED_CTRL, tp->led_ctrl);
1107
1108 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1109 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1110 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1111
1112 tw32_f(MAC_MODE, mac_mode);
1113 udelay(100);
1114
1115 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1116 udelay(10);
1117 }
1118
1119 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1120 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1122 u32 base_val;
1123
1124 base_val = tp->pci_clock_ctrl;
1125 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1126 CLOCK_CTRL_TXCLK_DISABLE);
1127
1128 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1129 CLOCK_CTRL_ALTCLK |
1130 CLOCK_CTRL_PWRDOWN_PLL133);
1131 udelay(40);
1132 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1133 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1134 u32 newbits1, newbits2;
1135
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1138 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1139 CLOCK_CTRL_TXCLK_DISABLE |
1140 CLOCK_CTRL_ALTCLK);
1141 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1142 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1143 newbits1 = CLOCK_CTRL_625_CORE;
1144 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1145 } else {
1146 newbits1 = CLOCK_CTRL_ALTCLK;
1147 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1148 }
1149
1150 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1151 udelay(40);
1152
1153 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1154 udelay(40);
1155
1156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1157 u32 newbits3;
1158
1159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1161 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1162 CLOCK_CTRL_TXCLK_DISABLE |
1163 CLOCK_CTRL_44MHZ_CORE);
1164 } else {
1165 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1166 }
1167
1168 tw32_f(TG3PCI_CLOCK_CTRL,
1169 tp->pci_clock_ctrl | newbits3);
1170 udelay(40);
1171 }
1172 }
1173
1174 tg3_frob_aux_power(tp);
1175
1176 /* Workaround for unstable PLL clock */
1177 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1178 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1179 u32 val = tr32(0x7d00);
1180
1181 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1182 tw32(0x7d00, val);
1183 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1184 tg3_halt_cpu(tp, RX_CPU_BASE);
1185 }
1186
1187 /* Finally, set the new power state. */
1188 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1189 udelay(100); /* Delay after power state change */
1190
1191 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1192
1193 return 0;
1194 }
1195
1196 static void tg3_link_report(struct tg3 *tp)
1197 {
1198 if (!netif_carrier_ok(tp->dev)) {
1199 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1200 } else {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1202 tp->dev->name,
1203 (tp->link_config.active_speed == SPEED_1000 ?
1204 1000 :
1205 (tp->link_config.active_speed == SPEED_100 ?
1206 100 : 10)),
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1208 "full" : "half"));
1209
1210 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1211 "%s for RX.\n",
1212 tp->dev->name,
1213 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1214 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1215 }
1216 }
1217
1218 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1219 {
1220 u32 new_tg3_flags = 0;
1221 u32 old_rx_mode = tp->rx_mode;
1222 u32 old_tx_mode = tp->tx_mode;
1223
1224 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1225 if (local_adv & ADVERTISE_PAUSE_CAP) {
1226 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1227 if (remote_adv & LPA_PAUSE_CAP)
1228 new_tg3_flags |=
1229 (TG3_FLAG_RX_PAUSE |
1230 TG3_FLAG_TX_PAUSE);
1231 else if (remote_adv & LPA_PAUSE_ASYM)
1232 new_tg3_flags |=
1233 (TG3_FLAG_RX_PAUSE);
1234 } else {
1235 if (remote_adv & LPA_PAUSE_CAP)
1236 new_tg3_flags |=
1237 (TG3_FLAG_RX_PAUSE |
1238 TG3_FLAG_TX_PAUSE);
1239 }
1240 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1241 if ((remote_adv & LPA_PAUSE_CAP) &&
1242 (remote_adv & LPA_PAUSE_ASYM))
1243 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1244 }
1245
1246 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1247 tp->tg3_flags |= new_tg3_flags;
1248 } else {
1249 new_tg3_flags = tp->tg3_flags;
1250 }
1251
1252 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1253 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1254 else
1255 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1256
1257 if (old_rx_mode != tp->rx_mode) {
1258 tw32_f(MAC_RX_MODE, tp->rx_mode);
1259 }
1260
1261 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1262 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1263 else
1264 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1265
1266 if (old_tx_mode != tp->tx_mode) {
1267 tw32_f(MAC_TX_MODE, tp->tx_mode);
1268 }
1269 }
1270
1271 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1272 {
1273 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1274 case MII_TG3_AUX_STAT_10HALF:
1275 *speed = SPEED_10;
1276 *duplex = DUPLEX_HALF;
1277 break;
1278
1279 case MII_TG3_AUX_STAT_10FULL:
1280 *speed = SPEED_10;
1281 *duplex = DUPLEX_FULL;
1282 break;
1283
1284 case MII_TG3_AUX_STAT_100HALF:
1285 *speed = SPEED_100;
1286 *duplex = DUPLEX_HALF;
1287 break;
1288
1289 case MII_TG3_AUX_STAT_100FULL:
1290 *speed = SPEED_100;
1291 *duplex = DUPLEX_FULL;
1292 break;
1293
1294 case MII_TG3_AUX_STAT_1000HALF:
1295 *speed = SPEED_1000;
1296 *duplex = DUPLEX_HALF;
1297 break;
1298
1299 case MII_TG3_AUX_STAT_1000FULL:
1300 *speed = SPEED_1000;
1301 *duplex = DUPLEX_FULL;
1302 break;
1303
1304 default:
1305 *speed = SPEED_INVALID;
1306 *duplex = DUPLEX_INVALID;
1307 break;
1308 };
1309 }
1310
1311 static void tg3_phy_copper_begin(struct tg3 *tp)
1312 {
1313 u32 new_adv;
1314 int i;
1315
1316 if (tp->link_config.phy_is_low_power) {
1317 /* Entering low power mode. Disable gigabit and
1318 * 100baseT advertisements.
1319 */
1320 tg3_writephy(tp, MII_TG3_CTRL, 0);
1321
1322 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1323 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1324 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1325 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1326
1327 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1328 } else if (tp->link_config.speed == SPEED_INVALID) {
1329 tp->link_config.advertising =
1330 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1331 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1332 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1333 ADVERTISED_Autoneg | ADVERTISED_MII);
1334
1335 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1336 tp->link_config.advertising &=
1337 ~(ADVERTISED_1000baseT_Half |
1338 ADVERTISED_1000baseT_Full);
1339
1340 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1341 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1342 new_adv |= ADVERTISE_10HALF;
1343 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1344 new_adv |= ADVERTISE_10FULL;
1345 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1346 new_adv |= ADVERTISE_100HALF;
1347 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1348 new_adv |= ADVERTISE_100FULL;
1349 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1350
1351 if (tp->link_config.advertising &
1352 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1353 new_adv = 0;
1354 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1355 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1356 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1357 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1358 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1359 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1360 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1361 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1362 MII_TG3_CTRL_ENABLE_AS_MASTER);
1363 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1364 } else {
1365 tg3_writephy(tp, MII_TG3_CTRL, 0);
1366 }
1367 } else {
1368 /* Asking for a specific link mode. */
1369 if (tp->link_config.speed == SPEED_1000) {
1370 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1371 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1372
1373 if (tp->link_config.duplex == DUPLEX_FULL)
1374 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1375 else
1376 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1377 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1378 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1379 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1380 MII_TG3_CTRL_ENABLE_AS_MASTER);
1381 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1382 } else {
1383 tg3_writephy(tp, MII_TG3_CTRL, 0);
1384
1385 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1386 if (tp->link_config.speed == SPEED_100) {
1387 if (tp->link_config.duplex == DUPLEX_FULL)
1388 new_adv |= ADVERTISE_100FULL;
1389 else
1390 new_adv |= ADVERTISE_100HALF;
1391 } else {
1392 if (tp->link_config.duplex == DUPLEX_FULL)
1393 new_adv |= ADVERTISE_10FULL;
1394 else
1395 new_adv |= ADVERTISE_10HALF;
1396 }
1397 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1398 }
1399 }
1400
1401 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1402 tp->link_config.speed != SPEED_INVALID) {
1403 u32 bmcr, orig_bmcr;
1404
1405 tp->link_config.active_speed = tp->link_config.speed;
1406 tp->link_config.active_duplex = tp->link_config.duplex;
1407
1408 bmcr = 0;
1409 switch (tp->link_config.speed) {
1410 default:
1411 case SPEED_10:
1412 break;
1413
1414 case SPEED_100:
1415 bmcr |= BMCR_SPEED100;
1416 break;
1417
1418 case SPEED_1000:
1419 bmcr |= TG3_BMCR_SPEED1000;
1420 break;
1421 };
1422
1423 if (tp->link_config.duplex == DUPLEX_FULL)
1424 bmcr |= BMCR_FULLDPLX;
1425
1426 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1427 (bmcr != orig_bmcr)) {
1428 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1429 for (i = 0; i < 1500; i++) {
1430 u32 tmp;
1431
1432 udelay(10);
1433 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1434 tg3_readphy(tp, MII_BMSR, &tmp))
1435 continue;
1436 if (!(tmp & BMSR_LSTATUS)) {
1437 udelay(40);
1438 break;
1439 }
1440 }
1441 tg3_writephy(tp, MII_BMCR, bmcr);
1442 udelay(40);
1443 }
1444 } else {
1445 tg3_writephy(tp, MII_BMCR,
1446 BMCR_ANENABLE | BMCR_ANRESTART);
1447 }
1448 }
1449
1450 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1451 {
1452 int err;
1453
1454 /* Turn off tap power management. */
1455 /* Set Extended packet length bit */
1456 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1457
1458 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1459 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1460
1461 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1462 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1463
1464 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1465 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1466
1467 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1468 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1469
1470 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1471 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1472
1473 udelay(40);
1474
1475 return err;
1476 }
1477
1478 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1479 {
1480 u32 adv_reg, all_mask;
1481
1482 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1483 return 0;
1484
1485 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1486 ADVERTISE_100HALF | ADVERTISE_100FULL);
1487 if ((adv_reg & all_mask) != all_mask)
1488 return 0;
1489 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1490 u32 tg3_ctrl;
1491
1492 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1493 return 0;
1494
1495 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1496 MII_TG3_CTRL_ADV_1000_FULL);
1497 if ((tg3_ctrl & all_mask) != all_mask)
1498 return 0;
1499 }
1500 return 1;
1501 }
1502
1503 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1504 {
1505 int current_link_up;
1506 u32 bmsr, dummy;
1507 u16 current_speed;
1508 u8 current_duplex;
1509 int i, err;
1510
1511 tw32(MAC_EVENT, 0);
1512
1513 tw32_f(MAC_STATUS,
1514 (MAC_STATUS_SYNC_CHANGED |
1515 MAC_STATUS_CFG_CHANGED |
1516 MAC_STATUS_MI_COMPLETION |
1517 MAC_STATUS_LNKSTATE_CHANGED));
1518 udelay(40);
1519
1520 tp->mi_mode = MAC_MI_MODE_BASE;
1521 tw32_f(MAC_MI_MODE, tp->mi_mode);
1522 udelay(80);
1523
1524 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1525
1526 /* Some third-party PHYs need to be reset on link going
1527 * down.
1528 */
1529 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1532 netif_carrier_ok(tp->dev)) {
1533 tg3_readphy(tp, MII_BMSR, &bmsr);
1534 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1535 !(bmsr & BMSR_LSTATUS))
1536 force_reset = 1;
1537 }
1538 if (force_reset)
1539 tg3_phy_reset(tp);
1540
1541 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1542 tg3_readphy(tp, MII_BMSR, &bmsr);
1543 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1544 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1545 bmsr = 0;
1546
1547 if (!(bmsr & BMSR_LSTATUS)) {
1548 err = tg3_init_5401phy_dsp(tp);
1549 if (err)
1550 return err;
1551
1552 tg3_readphy(tp, MII_BMSR, &bmsr);
1553 for (i = 0; i < 1000; i++) {
1554 udelay(10);
1555 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1556 (bmsr & BMSR_LSTATUS)) {
1557 udelay(40);
1558 break;
1559 }
1560 }
1561
1562 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1563 !(bmsr & BMSR_LSTATUS) &&
1564 tp->link_config.active_speed == SPEED_1000) {
1565 err = tg3_phy_reset(tp);
1566 if (!err)
1567 err = tg3_init_5401phy_dsp(tp);
1568 if (err)
1569 return err;
1570 }
1571 }
1572 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1573 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1574 /* 5701 {A0,B0} CRC bug workaround */
1575 tg3_writephy(tp, 0x15, 0x0a75);
1576 tg3_writephy(tp, 0x1c, 0x8c68);
1577 tg3_writephy(tp, 0x1c, 0x8d68);
1578 tg3_writephy(tp, 0x1c, 0x8c68);
1579 }
1580
1581 /* Clear pending interrupts... */
1582 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1583 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1584
1585 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1586 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1587 else
1588 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1589
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1591 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1592 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1593 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1594 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1595 else
1596 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1597 }
1598
1599 current_link_up = 0;
1600 current_speed = SPEED_INVALID;
1601 current_duplex = DUPLEX_INVALID;
1602
1603 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1604 u32 val;
1605
1606 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1607 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1608 if (!(val & (1 << 10))) {
1609 val |= (1 << 10);
1610 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1611 goto relink;
1612 }
1613 }
1614
1615 bmsr = 0;
1616 for (i = 0; i < 100; i++) {
1617 tg3_readphy(tp, MII_BMSR, &bmsr);
1618 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1619 (bmsr & BMSR_LSTATUS))
1620 break;
1621 udelay(40);
1622 }
1623
1624 if (bmsr & BMSR_LSTATUS) {
1625 u32 aux_stat, bmcr;
1626
1627 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1628 for (i = 0; i < 2000; i++) {
1629 udelay(10);
1630 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1631 aux_stat)
1632 break;
1633 }
1634
1635 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1636 &current_speed,
1637 &current_duplex);
1638
1639 bmcr = 0;
1640 for (i = 0; i < 200; i++) {
1641 tg3_readphy(tp, MII_BMCR, &bmcr);
1642 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1643 continue;
1644 if (bmcr && bmcr != 0x7fff)
1645 break;
1646 udelay(10);
1647 }
1648
1649 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1650 if (bmcr & BMCR_ANENABLE) {
1651 current_link_up = 1;
1652
1653 /* Force autoneg restart if we are exiting
1654 * low power mode.
1655 */
1656 if (!tg3_copper_is_advertising_all(tp))
1657 current_link_up = 0;
1658 } else {
1659 current_link_up = 0;
1660 }
1661 } else {
1662 if (!(bmcr & BMCR_ANENABLE) &&
1663 tp->link_config.speed == current_speed &&
1664 tp->link_config.duplex == current_duplex) {
1665 current_link_up = 1;
1666 } else {
1667 current_link_up = 0;
1668 }
1669 }
1670
1671 tp->link_config.active_speed = current_speed;
1672 tp->link_config.active_duplex = current_duplex;
1673 }
1674
1675 if (current_link_up == 1 &&
1676 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1677 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1678 u32 local_adv, remote_adv;
1679
1680 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1681 local_adv = 0;
1682 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1683
1684 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1685 remote_adv = 0;
1686
1687 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1688
1689 /* If we are not advertising full pause capability,
1690 * something is wrong. Bring the link down and reconfigure.
1691 */
1692 if (local_adv != ADVERTISE_PAUSE_CAP) {
1693 current_link_up = 0;
1694 } else {
1695 tg3_setup_flow_control(tp, local_adv, remote_adv);
1696 }
1697 }
1698 relink:
1699 if (current_link_up == 0) {
1700 u32 tmp;
1701
1702 tg3_phy_copper_begin(tp);
1703
1704 tg3_readphy(tp, MII_BMSR, &tmp);
1705 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1706 (tmp & BMSR_LSTATUS))
1707 current_link_up = 1;
1708 }
1709
1710 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1711 if (current_link_up == 1) {
1712 if (tp->link_config.active_speed == SPEED_100 ||
1713 tp->link_config.active_speed == SPEED_10)
1714 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1715 else
1716 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1717 } else
1718 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1719
1720 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1721 if (tp->link_config.active_duplex == DUPLEX_HALF)
1722 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1723
1724 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1726 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1727 (current_link_up == 1 &&
1728 tp->link_config.active_speed == SPEED_10))
1729 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1730 } else {
1731 if (current_link_up == 1)
1732 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1733 }
1734
1735 /* ??? Without this setting Netgear GA302T PHY does not
1736 * ??? send/receive packets...
1737 */
1738 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1739 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1740 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1741 tw32_f(MAC_MI_MODE, tp->mi_mode);
1742 udelay(80);
1743 }
1744
1745 tw32_f(MAC_MODE, tp->mac_mode);
1746 udelay(40);
1747
1748 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1749 /* Polled via timer. */
1750 tw32_f(MAC_EVENT, 0);
1751 } else {
1752 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1753 }
1754 udelay(40);
1755
1756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1757 current_link_up == 1 &&
1758 tp->link_config.active_speed == SPEED_1000 &&
1759 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1760 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1761 udelay(120);
1762 tw32_f(MAC_STATUS,
1763 (MAC_STATUS_SYNC_CHANGED |
1764 MAC_STATUS_CFG_CHANGED));
1765 udelay(40);
1766 tg3_write_mem(tp,
1767 NIC_SRAM_FIRMWARE_MBOX,
1768 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1769 }
1770
1771 if (current_link_up != netif_carrier_ok(tp->dev)) {
1772 if (current_link_up)
1773 netif_carrier_on(tp->dev);
1774 else
1775 netif_carrier_off(tp->dev);
1776 tg3_link_report(tp);
1777 }
1778
1779 return 0;
1780 }
1781
1782 struct tg3_fiber_aneginfo {
1783 int state;
1784 #define ANEG_STATE_UNKNOWN 0
1785 #define ANEG_STATE_AN_ENABLE 1
1786 #define ANEG_STATE_RESTART_INIT 2
1787 #define ANEG_STATE_RESTART 3
1788 #define ANEG_STATE_DISABLE_LINK_OK 4
1789 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1790 #define ANEG_STATE_ABILITY_DETECT 6
1791 #define ANEG_STATE_ACK_DETECT_INIT 7
1792 #define ANEG_STATE_ACK_DETECT 8
1793 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1794 #define ANEG_STATE_COMPLETE_ACK 10
1795 #define ANEG_STATE_IDLE_DETECT_INIT 11
1796 #define ANEG_STATE_IDLE_DETECT 12
1797 #define ANEG_STATE_LINK_OK 13
1798 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1799 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1800
1801 u32 flags;
1802 #define MR_AN_ENABLE 0x00000001
1803 #define MR_RESTART_AN 0x00000002
1804 #define MR_AN_COMPLETE 0x00000004
1805 #define MR_PAGE_RX 0x00000008
1806 #define MR_NP_LOADED 0x00000010
1807 #define MR_TOGGLE_TX 0x00000020
1808 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1809 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1810 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1811 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1812 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1813 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1814 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1815 #define MR_TOGGLE_RX 0x00002000
1816 #define MR_NP_RX 0x00004000
1817
1818 #define MR_LINK_OK 0x80000000
1819
1820 unsigned long link_time, cur_time;
1821
1822 u32 ability_match_cfg;
1823 int ability_match_count;
1824
1825 char ability_match, idle_match, ack_match;
1826
1827 u32 txconfig, rxconfig;
1828 #define ANEG_CFG_NP 0x00000080
1829 #define ANEG_CFG_ACK 0x00000040
1830 #define ANEG_CFG_RF2 0x00000020
1831 #define ANEG_CFG_RF1 0x00000010
1832 #define ANEG_CFG_PS2 0x00000001
1833 #define ANEG_CFG_PS1 0x00008000
1834 #define ANEG_CFG_HD 0x00004000
1835 #define ANEG_CFG_FD 0x00002000
1836 #define ANEG_CFG_INVAL 0x00001f06
1837
1838 };
1839 #define ANEG_OK 0
1840 #define ANEG_DONE 1
1841 #define ANEG_TIMER_ENAB 2
1842 #define ANEG_FAILED -1
1843
1844 #define ANEG_STATE_SETTLE_TIME 10000
1845
1846 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1847 struct tg3_fiber_aneginfo *ap)
1848 {
1849 unsigned long delta;
1850 u32 rx_cfg_reg;
1851 int ret;
1852
1853 if (ap->state == ANEG_STATE_UNKNOWN) {
1854 ap->rxconfig = 0;
1855 ap->link_time = 0;
1856 ap->cur_time = 0;
1857 ap->ability_match_cfg = 0;
1858 ap->ability_match_count = 0;
1859 ap->ability_match = 0;
1860 ap->idle_match = 0;
1861 ap->ack_match = 0;
1862 }
1863 ap->cur_time++;
1864
1865 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1866 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1867
1868 if (rx_cfg_reg != ap->ability_match_cfg) {
1869 ap->ability_match_cfg = rx_cfg_reg;
1870 ap->ability_match = 0;
1871 ap->ability_match_count = 0;
1872 } else {
1873 if (++ap->ability_match_count > 1) {
1874 ap->ability_match = 1;
1875 ap->ability_match_cfg = rx_cfg_reg;
1876 }
1877 }
1878 if (rx_cfg_reg & ANEG_CFG_ACK)
1879 ap->ack_match = 1;
1880 else
1881 ap->ack_match = 0;
1882
1883 ap->idle_match = 0;
1884 } else {
1885 ap->idle_match = 1;
1886 ap->ability_match_cfg = 0;
1887 ap->ability_match_count = 0;
1888 ap->ability_match = 0;
1889 ap->ack_match = 0;
1890
1891 rx_cfg_reg = 0;
1892 }
1893
1894 ap->rxconfig = rx_cfg_reg;
1895 ret = ANEG_OK;
1896
1897 switch(ap->state) {
1898 case ANEG_STATE_UNKNOWN:
1899 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1900 ap->state = ANEG_STATE_AN_ENABLE;
1901
1902 /* fallthru */
1903 case ANEG_STATE_AN_ENABLE:
1904 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1905 if (ap->flags & MR_AN_ENABLE) {
1906 ap->link_time = 0;
1907 ap->cur_time = 0;
1908 ap->ability_match_cfg = 0;
1909 ap->ability_match_count = 0;
1910 ap->ability_match = 0;
1911 ap->idle_match = 0;
1912 ap->ack_match = 0;
1913
1914 ap->state = ANEG_STATE_RESTART_INIT;
1915 } else {
1916 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1917 }
1918 break;
1919
1920 case ANEG_STATE_RESTART_INIT:
1921 ap->link_time = ap->cur_time;
1922 ap->flags &= ~(MR_NP_LOADED);
1923 ap->txconfig = 0;
1924 tw32(MAC_TX_AUTO_NEG, 0);
1925 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1926 tw32_f(MAC_MODE, tp->mac_mode);
1927 udelay(40);
1928
1929 ret = ANEG_TIMER_ENAB;
1930 ap->state = ANEG_STATE_RESTART;
1931
1932 /* fallthru */
1933 case ANEG_STATE_RESTART:
1934 delta = ap->cur_time - ap->link_time;
1935 if (delta > ANEG_STATE_SETTLE_TIME) {
1936 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1937 } else {
1938 ret = ANEG_TIMER_ENAB;
1939 }
1940 break;
1941
1942 case ANEG_STATE_DISABLE_LINK_OK:
1943 ret = ANEG_DONE;
1944 break;
1945
1946 case ANEG_STATE_ABILITY_DETECT_INIT:
1947 ap->flags &= ~(MR_TOGGLE_TX);
1948 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1949 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1950 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1951 tw32_f(MAC_MODE, tp->mac_mode);
1952 udelay(40);
1953
1954 ap->state = ANEG_STATE_ABILITY_DETECT;
1955 break;
1956
1957 case ANEG_STATE_ABILITY_DETECT:
1958 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1959 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1960 }
1961 break;
1962
1963 case ANEG_STATE_ACK_DETECT_INIT:
1964 ap->txconfig |= ANEG_CFG_ACK;
1965 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1966 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1967 tw32_f(MAC_MODE, tp->mac_mode);
1968 udelay(40);
1969
1970 ap->state = ANEG_STATE_ACK_DETECT;
1971
1972 /* fallthru */
1973 case ANEG_STATE_ACK_DETECT:
1974 if (ap->ack_match != 0) {
1975 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1976 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1977 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1978 } else {
1979 ap->state = ANEG_STATE_AN_ENABLE;
1980 }
1981 } else if (ap->ability_match != 0 &&
1982 ap->rxconfig == 0) {
1983 ap->state = ANEG_STATE_AN_ENABLE;
1984 }
1985 break;
1986
1987 case ANEG_STATE_COMPLETE_ACK_INIT:
1988 if (ap->rxconfig & ANEG_CFG_INVAL) {
1989 ret = ANEG_FAILED;
1990 break;
1991 }
1992 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1993 MR_LP_ADV_HALF_DUPLEX |
1994 MR_LP_ADV_SYM_PAUSE |
1995 MR_LP_ADV_ASYM_PAUSE |
1996 MR_LP_ADV_REMOTE_FAULT1 |
1997 MR_LP_ADV_REMOTE_FAULT2 |
1998 MR_LP_ADV_NEXT_PAGE |
1999 MR_TOGGLE_RX |
2000 MR_NP_RX);
2001 if (ap->rxconfig & ANEG_CFG_FD)
2002 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2003 if (ap->rxconfig & ANEG_CFG_HD)
2004 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2005 if (ap->rxconfig & ANEG_CFG_PS1)
2006 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2007 if (ap->rxconfig & ANEG_CFG_PS2)
2008 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2009 if (ap->rxconfig & ANEG_CFG_RF1)
2010 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2011 if (ap->rxconfig & ANEG_CFG_RF2)
2012 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2013 if (ap->rxconfig & ANEG_CFG_NP)
2014 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2015
2016 ap->link_time = ap->cur_time;
2017
2018 ap->flags ^= (MR_TOGGLE_TX);
2019 if (ap->rxconfig & 0x0008)
2020 ap->flags |= MR_TOGGLE_RX;
2021 if (ap->rxconfig & ANEG_CFG_NP)
2022 ap->flags |= MR_NP_RX;
2023 ap->flags |= MR_PAGE_RX;
2024
2025 ap->state = ANEG_STATE_COMPLETE_ACK;
2026 ret = ANEG_TIMER_ENAB;
2027 break;
2028
2029 case ANEG_STATE_COMPLETE_ACK:
2030 if (ap->ability_match != 0 &&
2031 ap->rxconfig == 0) {
2032 ap->state = ANEG_STATE_AN_ENABLE;
2033 break;
2034 }
2035 delta = ap->cur_time - ap->link_time;
2036 if (delta > ANEG_STATE_SETTLE_TIME) {
2037 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2038 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2039 } else {
2040 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2041 !(ap->flags & MR_NP_RX)) {
2042 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2043 } else {
2044 ret = ANEG_FAILED;
2045 }
2046 }
2047 }
2048 break;
2049
2050 case ANEG_STATE_IDLE_DETECT_INIT:
2051 ap->link_time = ap->cur_time;
2052 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2053 tw32_f(MAC_MODE, tp->mac_mode);
2054 udelay(40);
2055
2056 ap->state = ANEG_STATE_IDLE_DETECT;
2057 ret = ANEG_TIMER_ENAB;
2058 break;
2059
2060 case ANEG_STATE_IDLE_DETECT:
2061 if (ap->ability_match != 0 &&
2062 ap->rxconfig == 0) {
2063 ap->state = ANEG_STATE_AN_ENABLE;
2064 break;
2065 }
2066 delta = ap->cur_time - ap->link_time;
2067 if (delta > ANEG_STATE_SETTLE_TIME) {
2068 /* XXX another gem from the Broadcom driver :( */
2069 ap->state = ANEG_STATE_LINK_OK;
2070 }
2071 break;
2072
2073 case ANEG_STATE_LINK_OK:
2074 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2075 ret = ANEG_DONE;
2076 break;
2077
2078 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2079 /* ??? unimplemented */
2080 break;
2081
2082 case ANEG_STATE_NEXT_PAGE_WAIT:
2083 /* ??? unimplemented */
2084 break;
2085
2086 default:
2087 ret = ANEG_FAILED;
2088 break;
2089 };
2090
2091 return ret;
2092 }
2093
2094 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2095 {
2096 int res = 0;
2097 struct tg3_fiber_aneginfo aninfo;
2098 int status = ANEG_FAILED;
2099 unsigned int tick;
2100 u32 tmp;
2101
2102 tw32_f(MAC_TX_AUTO_NEG, 0);
2103
2104 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2105 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2106 udelay(40);
2107
2108 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2109 udelay(40);
2110
2111 memset(&aninfo, 0, sizeof(aninfo));
2112 aninfo.flags |= MR_AN_ENABLE;
2113 aninfo.state = ANEG_STATE_UNKNOWN;
2114 aninfo.cur_time = 0;
2115 tick = 0;
2116 while (++tick < 195000) {
2117 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2118 if (status == ANEG_DONE || status == ANEG_FAILED)
2119 break;
2120
2121 udelay(1);
2122 }
2123
2124 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2125 tw32_f(MAC_MODE, tp->mac_mode);
2126 udelay(40);
2127
2128 *flags = aninfo.flags;
2129
2130 if (status == ANEG_DONE &&
2131 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2132 MR_LP_ADV_FULL_DUPLEX)))
2133 res = 1;
2134
2135 return res;
2136 }
2137
2138 static void tg3_init_bcm8002(struct tg3 *tp)
2139 {
2140 u32 mac_status = tr32(MAC_STATUS);
2141 int i;
2142
2143 /* Reset when initting first time or we have a link. */
2144 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2145 !(mac_status & MAC_STATUS_PCS_SYNCED))
2146 return;
2147
2148 /* Set PLL lock range. */
2149 tg3_writephy(tp, 0x16, 0x8007);
2150
2151 /* SW reset */
2152 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2153
2154 /* Wait for reset to complete. */
2155 /* XXX schedule_timeout() ... */
2156 for (i = 0; i < 500; i++)
2157 udelay(10);
2158
2159 /* Config mode; select PMA/Ch 1 regs. */
2160 tg3_writephy(tp, 0x10, 0x8411);
2161
2162 /* Enable auto-lock and comdet, select txclk for tx. */
2163 tg3_writephy(tp, 0x11, 0x0a10);
2164
2165 tg3_writephy(tp, 0x18, 0x00a0);
2166 tg3_writephy(tp, 0x16, 0x41ff);
2167
2168 /* Assert and deassert POR. */
2169 tg3_writephy(tp, 0x13, 0x0400);
2170 udelay(40);
2171 tg3_writephy(tp, 0x13, 0x0000);
2172
2173 tg3_writephy(tp, 0x11, 0x0a50);
2174 udelay(40);
2175 tg3_writephy(tp, 0x11, 0x0a10);
2176
2177 /* Wait for signal to stabilize */
2178 /* XXX schedule_timeout() ... */
2179 for (i = 0; i < 15000; i++)
2180 udelay(10);
2181
2182 /* Deselect the channel register so we can read the PHYID
2183 * later.
2184 */
2185 tg3_writephy(tp, 0x10, 0x8011);
2186 }
2187
2188 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2189 {
2190 u32 sg_dig_ctrl, sg_dig_status;
2191 u32 serdes_cfg, expected_sg_dig_ctrl;
2192 int workaround, port_a;
2193 int current_link_up;
2194
2195 serdes_cfg = 0;
2196 expected_sg_dig_ctrl = 0;
2197 workaround = 0;
2198 port_a = 1;
2199 current_link_up = 0;
2200
2201 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2202 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2203 workaround = 1;
2204 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2205 port_a = 0;
2206
2207 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2208 /* preserve bits 20-23 for voltage regulator */
2209 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2210 }
2211
2212 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2213
2214 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2215 if (sg_dig_ctrl & (1 << 31)) {
2216 if (workaround) {
2217 u32 val = serdes_cfg;
2218
2219 if (port_a)
2220 val |= 0xc010000;
2221 else
2222 val |= 0x4010000;
2223 tw32_f(MAC_SERDES_CFG, val);
2224 }
2225 tw32_f(SG_DIG_CTRL, 0x01388400);
2226 }
2227 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2228 tg3_setup_flow_control(tp, 0, 0);
2229 current_link_up = 1;
2230 }
2231 goto out;
2232 }
2233
2234 /* Want auto-negotiation. */
2235 expected_sg_dig_ctrl = 0x81388400;
2236
2237 /* Pause capability */
2238 expected_sg_dig_ctrl |= (1 << 11);
2239
2240 /* Asymettric pause */
2241 expected_sg_dig_ctrl |= (1 << 12);
2242
2243 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2244 if (workaround)
2245 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2246 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2247 udelay(5);
2248 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2249
2250 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2251 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2252 MAC_STATUS_SIGNAL_DET)) {
2253 int i;
2254
2255 /* Giver time to negotiate (~200ms) */
2256 for (i = 0; i < 40000; i++) {
2257 sg_dig_status = tr32(SG_DIG_STATUS);
2258 if (sg_dig_status & (0x3))
2259 break;
2260 udelay(5);
2261 }
2262 mac_status = tr32(MAC_STATUS);
2263
2264 if ((sg_dig_status & (1 << 1)) &&
2265 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2266 u32 local_adv, remote_adv;
2267
2268 local_adv = ADVERTISE_PAUSE_CAP;
2269 remote_adv = 0;
2270 if (sg_dig_status & (1 << 19))
2271 remote_adv |= LPA_PAUSE_CAP;
2272 if (sg_dig_status & (1 << 20))
2273 remote_adv |= LPA_PAUSE_ASYM;
2274
2275 tg3_setup_flow_control(tp, local_adv, remote_adv);
2276 current_link_up = 1;
2277 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2278 } else if (!(sg_dig_status & (1 << 1))) {
2279 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2280 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2281 else {
2282 if (workaround) {
2283 u32 val = serdes_cfg;
2284
2285 if (port_a)
2286 val |= 0xc010000;
2287 else
2288 val |= 0x4010000;
2289
2290 tw32_f(MAC_SERDES_CFG, val);
2291 }
2292
2293 tw32_f(SG_DIG_CTRL, 0x01388400);
2294 udelay(40);
2295
2296 /* Link parallel detection - link is up */
2297 /* only if we have PCS_SYNC and not */
2298 /* receiving config code words */
2299 mac_status = tr32(MAC_STATUS);
2300 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2301 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2302 tg3_setup_flow_control(tp, 0, 0);
2303 current_link_up = 1;
2304 }
2305 }
2306 }
2307 }
2308
2309 out:
2310 return current_link_up;
2311 }
2312
2313 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2314 {
2315 int current_link_up = 0;
2316
2317 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2318 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2319 goto out;
2320 }
2321
2322 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2323 u32 flags;
2324 int i;
2325
2326 if (fiber_autoneg(tp, &flags)) {
2327 u32 local_adv, remote_adv;
2328
2329 local_adv = ADVERTISE_PAUSE_CAP;
2330 remote_adv = 0;
2331 if (flags & MR_LP_ADV_SYM_PAUSE)
2332 remote_adv |= LPA_PAUSE_CAP;
2333 if (flags & MR_LP_ADV_ASYM_PAUSE)
2334 remote_adv |= LPA_PAUSE_ASYM;
2335
2336 tg3_setup_flow_control(tp, local_adv, remote_adv);
2337
2338 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2339 current_link_up = 1;
2340 }
2341 for (i = 0; i < 30; i++) {
2342 udelay(20);
2343 tw32_f(MAC_STATUS,
2344 (MAC_STATUS_SYNC_CHANGED |
2345 MAC_STATUS_CFG_CHANGED));
2346 udelay(40);
2347 if ((tr32(MAC_STATUS) &
2348 (MAC_STATUS_SYNC_CHANGED |
2349 MAC_STATUS_CFG_CHANGED)) == 0)
2350 break;
2351 }
2352
2353 mac_status = tr32(MAC_STATUS);
2354 if (current_link_up == 0 &&
2355 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2356 !(mac_status & MAC_STATUS_RCVD_CFG))
2357 current_link_up = 1;
2358 } else {
2359 /* Forcing 1000FD link up. */
2360 current_link_up = 1;
2361 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2362
2363 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2364 udelay(40);
2365 }
2366
2367 out:
2368 return current_link_up;
2369 }
2370
2371 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2372 {
2373 u32 orig_pause_cfg;
2374 u16 orig_active_speed;
2375 u8 orig_active_duplex;
2376 u32 mac_status;
2377 int current_link_up;
2378 int i;
2379
2380 orig_pause_cfg =
2381 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2382 TG3_FLAG_TX_PAUSE));
2383 orig_active_speed = tp->link_config.active_speed;
2384 orig_active_duplex = tp->link_config.active_duplex;
2385
2386 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2387 netif_carrier_ok(tp->dev) &&
2388 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2389 mac_status = tr32(MAC_STATUS);
2390 mac_status &= (MAC_STATUS_PCS_SYNCED |
2391 MAC_STATUS_SIGNAL_DET |
2392 MAC_STATUS_CFG_CHANGED |
2393 MAC_STATUS_RCVD_CFG);
2394 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2395 MAC_STATUS_SIGNAL_DET)) {
2396 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2397 MAC_STATUS_CFG_CHANGED));
2398 return 0;
2399 }
2400 }
2401
2402 tw32_f(MAC_TX_AUTO_NEG, 0);
2403
2404 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2405 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2406 tw32_f(MAC_MODE, tp->mac_mode);
2407 udelay(40);
2408
2409 if (tp->phy_id == PHY_ID_BCM8002)
2410 tg3_init_bcm8002(tp);
2411
2412 /* Enable link change event even when serdes polling. */
2413 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2414 udelay(40);
2415
2416 current_link_up = 0;
2417 mac_status = tr32(MAC_STATUS);
2418
2419 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2420 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2421 else
2422 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2423
2424 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2425 tw32_f(MAC_MODE, tp->mac_mode);
2426 udelay(40);
2427
2428 tp->hw_status->status =
2429 (SD_STATUS_UPDATED |
2430 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2431
2432 for (i = 0; i < 100; i++) {
2433 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2434 MAC_STATUS_CFG_CHANGED));
2435 udelay(5);
2436 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2437 MAC_STATUS_CFG_CHANGED)) == 0)
2438 break;
2439 }
2440
2441 mac_status = tr32(MAC_STATUS);
2442 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2443 current_link_up = 0;
2444 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2445 tw32_f(MAC_MODE, (tp->mac_mode |
2446 MAC_MODE_SEND_CONFIGS));
2447 udelay(1);
2448 tw32_f(MAC_MODE, tp->mac_mode);
2449 }
2450 }
2451
2452 if (current_link_up == 1) {
2453 tp->link_config.active_speed = SPEED_1000;
2454 tp->link_config.active_duplex = DUPLEX_FULL;
2455 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2456 LED_CTRL_LNKLED_OVERRIDE |
2457 LED_CTRL_1000MBPS_ON));
2458 } else {
2459 tp->link_config.active_speed = SPEED_INVALID;
2460 tp->link_config.active_duplex = DUPLEX_INVALID;
2461 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2462 LED_CTRL_LNKLED_OVERRIDE |
2463 LED_CTRL_TRAFFIC_OVERRIDE));
2464 }
2465
2466 if (current_link_up != netif_carrier_ok(tp->dev)) {
2467 if (current_link_up)
2468 netif_carrier_on(tp->dev);
2469 else
2470 netif_carrier_off(tp->dev);
2471 tg3_link_report(tp);
2472 } else {
2473 u32 now_pause_cfg =
2474 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2475 TG3_FLAG_TX_PAUSE);
2476 if (orig_pause_cfg != now_pause_cfg ||
2477 orig_active_speed != tp->link_config.active_speed ||
2478 orig_active_duplex != tp->link_config.active_duplex)
2479 tg3_link_report(tp);
2480 }
2481
2482 return 0;
2483 }
2484
2485 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2486 {
2487 int err;
2488
2489 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2490 err = tg3_setup_fiber_phy(tp, force_reset);
2491 } else {
2492 err = tg3_setup_copper_phy(tp, force_reset);
2493 }
2494
2495 if (tp->link_config.active_speed == SPEED_1000 &&
2496 tp->link_config.active_duplex == DUPLEX_HALF)
2497 tw32(MAC_TX_LENGTHS,
2498 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2499 (6 << TX_LENGTHS_IPG_SHIFT) |
2500 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2501 else
2502 tw32(MAC_TX_LENGTHS,
2503 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2504 (6 << TX_LENGTHS_IPG_SHIFT) |
2505 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2506
2507 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2508 if (netif_carrier_ok(tp->dev)) {
2509 tw32(HOSTCC_STAT_COAL_TICKS,
2510 tp->coal.stats_block_coalesce_usecs);
2511 } else {
2512 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2513 }
2514 }
2515
2516 return err;
2517 }
2518
2519 /* Tigon3 never reports partial packet sends. So we do not
2520 * need special logic to handle SKBs that have not had all
2521 * of their frags sent yet, like SunGEM does.
2522 */
2523 static void tg3_tx(struct tg3 *tp)
2524 {
2525 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2526 u32 sw_idx = tp->tx_cons;
2527
2528 while (sw_idx != hw_idx) {
2529 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2530 struct sk_buff *skb = ri->skb;
2531 int i;
2532
2533 if (unlikely(skb == NULL))
2534 BUG();
2535
2536 pci_unmap_single(tp->pdev,
2537 pci_unmap_addr(ri, mapping),
2538 skb_headlen(skb),
2539 PCI_DMA_TODEVICE);
2540
2541 ri->skb = NULL;
2542
2543 sw_idx = NEXT_TX(sw_idx);
2544
2545 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2546 if (unlikely(sw_idx == hw_idx))
2547 BUG();
2548
2549 ri = &tp->tx_buffers[sw_idx];
2550 if (unlikely(ri->skb != NULL))
2551 BUG();
2552
2553 pci_unmap_page(tp->pdev,
2554 pci_unmap_addr(ri, mapping),
2555 skb_shinfo(skb)->frags[i].size,
2556 PCI_DMA_TODEVICE);
2557
2558 sw_idx = NEXT_TX(sw_idx);
2559 }
2560
2561 dev_kfree_skb_irq(skb);
2562 }
2563
2564 tp->tx_cons = sw_idx;
2565
2566 if (netif_queue_stopped(tp->dev) &&
2567 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2568 netif_wake_queue(tp->dev);
2569 }
2570
2571 /* Returns size of skb allocated or < 0 on error.
2572 *
2573 * We only need to fill in the address because the other members
2574 * of the RX descriptor are invariant, see tg3_init_rings.
2575 *
2576 * Note the purposeful assymetry of cpu vs. chip accesses. For
2577 * posting buffers we only dirty the first cache line of the RX
2578 * descriptor (containing the address). Whereas for the RX status
2579 * buffers the cpu only reads the last cacheline of the RX descriptor
2580 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2581 */
2582 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2583 int src_idx, u32 dest_idx_unmasked)
2584 {
2585 struct tg3_rx_buffer_desc *desc;
2586 struct ring_info *map, *src_map;
2587 struct sk_buff *skb;
2588 dma_addr_t mapping;
2589 int skb_size, dest_idx;
2590
2591 src_map = NULL;
2592 switch (opaque_key) {
2593 case RXD_OPAQUE_RING_STD:
2594 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2595 desc = &tp->rx_std[dest_idx];
2596 map = &tp->rx_std_buffers[dest_idx];
2597 if (src_idx >= 0)
2598 src_map = &tp->rx_std_buffers[src_idx];
2599 skb_size = RX_PKT_BUF_SZ;
2600 break;
2601
2602 case RXD_OPAQUE_RING_JUMBO:
2603 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2604 desc = &tp->rx_jumbo[dest_idx];
2605 map = &tp->rx_jumbo_buffers[dest_idx];
2606 if (src_idx >= 0)
2607 src_map = &tp->rx_jumbo_buffers[src_idx];
2608 skb_size = RX_JUMBO_PKT_BUF_SZ;
2609 break;
2610
2611 default:
2612 return -EINVAL;
2613 };
2614
2615 /* Do not overwrite any of the map or rp information
2616 * until we are sure we can commit to a new buffer.
2617 *
2618 * Callers depend upon this behavior and assume that
2619 * we leave everything unchanged if we fail.
2620 */
2621 skb = dev_alloc_skb(skb_size);
2622 if (skb == NULL)
2623 return -ENOMEM;
2624
2625 skb->dev = tp->dev;
2626 skb_reserve(skb, tp->rx_offset);
2627
2628 mapping = pci_map_single(tp->pdev, skb->data,
2629 skb_size - tp->rx_offset,
2630 PCI_DMA_FROMDEVICE);
2631
2632 map->skb = skb;
2633 pci_unmap_addr_set(map, mapping, mapping);
2634
2635 if (src_map != NULL)
2636 src_map->skb = NULL;
2637
2638 desc->addr_hi = ((u64)mapping >> 32);
2639 desc->addr_lo = ((u64)mapping & 0xffffffff);
2640
2641 return skb_size;
2642 }
2643
2644 /* We only need to move over in the address because the other
2645 * members of the RX descriptor are invariant. See notes above
2646 * tg3_alloc_rx_skb for full details.
2647 */
2648 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2649 int src_idx, u32 dest_idx_unmasked)
2650 {
2651 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2652 struct ring_info *src_map, *dest_map;
2653 int dest_idx;
2654
2655 switch (opaque_key) {
2656 case RXD_OPAQUE_RING_STD:
2657 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2658 dest_desc = &tp->rx_std[dest_idx];
2659 dest_map = &tp->rx_std_buffers[dest_idx];
2660 src_desc = &tp->rx_std[src_idx];
2661 src_map = &tp->rx_std_buffers[src_idx];
2662 break;
2663
2664 case RXD_OPAQUE_RING_JUMBO:
2665 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2666 dest_desc = &tp->rx_jumbo[dest_idx];
2667 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2668 src_desc = &tp->rx_jumbo[src_idx];
2669 src_map = &tp->rx_jumbo_buffers[src_idx];
2670 break;
2671
2672 default:
2673 return;
2674 };
2675
2676 dest_map->skb = src_map->skb;
2677 pci_unmap_addr_set(dest_map, mapping,
2678 pci_unmap_addr(src_map, mapping));
2679 dest_desc->addr_hi = src_desc->addr_hi;
2680 dest_desc->addr_lo = src_desc->addr_lo;
2681
2682 src_map->skb = NULL;
2683 }
2684
2685 #if TG3_VLAN_TAG_USED
2686 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2687 {
2688 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2689 }
2690 #endif
2691
2692 /* The RX ring scheme is composed of multiple rings which post fresh
2693 * buffers to the chip, and one special ring the chip uses to report
2694 * status back to the host.
2695 *
2696 * The special ring reports the status of received packets to the
2697 * host. The chip does not write into the original descriptor the
2698 * RX buffer was obtained from. The chip simply takes the original
2699 * descriptor as provided by the host, updates the status and length
2700 * field, then writes this into the next status ring entry.
2701 *
2702 * Each ring the host uses to post buffers to the chip is described
2703 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2704 * it is first placed into the on-chip ram. When the packet's length
2705 * is known, it walks down the TG3_BDINFO entries to select the ring.
2706 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2707 * which is within the range of the new packet's length is chosen.
2708 *
2709 * The "separate ring for rx status" scheme may sound queer, but it makes
2710 * sense from a cache coherency perspective. If only the host writes
2711 * to the buffer post rings, and only the chip writes to the rx status
2712 * rings, then cache lines never move beyond shared-modified state.
2713 * If both the host and chip were to write into the same ring, cache line
2714 * eviction could occur since both entities want it in an exclusive state.
2715 */
2716 static int tg3_rx(struct tg3 *tp, int budget)
2717 {
2718 u32 work_mask;
2719 u32 sw_idx = tp->rx_rcb_ptr;
2720 u16 hw_idx;
2721 int received;
2722
2723 hw_idx = tp->hw_status->idx[0].rx_producer;
2724 /*
2725 * We need to order the read of hw_idx and the read of
2726 * the opaque cookie.
2727 */
2728 rmb();
2729 work_mask = 0;
2730 received = 0;
2731 while (sw_idx != hw_idx && budget > 0) {
2732 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2733 unsigned int len;
2734 struct sk_buff *skb;
2735 dma_addr_t dma_addr;
2736 u32 opaque_key, desc_idx, *post_ptr;
2737
2738 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2739 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2740 if (opaque_key == RXD_OPAQUE_RING_STD) {
2741 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2742 mapping);
2743 skb = tp->rx_std_buffers[desc_idx].skb;
2744 post_ptr = &tp->rx_std_ptr;
2745 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2746 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2747 mapping);
2748 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2749 post_ptr = &tp->rx_jumbo_ptr;
2750 }
2751 else {
2752 goto next_pkt_nopost;
2753 }
2754
2755 work_mask |= opaque_key;
2756
2757 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2758 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2759 drop_it:
2760 tg3_recycle_rx(tp, opaque_key,
2761 desc_idx, *post_ptr);
2762 drop_it_no_recycle:
2763 /* Other statistics kept track of by card. */
2764 tp->net_stats.rx_dropped++;
2765 goto next_pkt;
2766 }
2767
2768 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2769
2770 if (len > RX_COPY_THRESHOLD
2771 && tp->rx_offset == 2
2772 /* rx_offset != 2 iff this is a 5701 card running
2773 * in PCI-X mode [see tg3_get_invariants()] */
2774 ) {
2775 int skb_size;
2776
2777 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2778 desc_idx, *post_ptr);
2779 if (skb_size < 0)
2780 goto drop_it;
2781
2782 pci_unmap_single(tp->pdev, dma_addr,
2783 skb_size - tp->rx_offset,
2784 PCI_DMA_FROMDEVICE);
2785
2786 skb_put(skb, len);
2787 } else {
2788 struct sk_buff *copy_skb;
2789
2790 tg3_recycle_rx(tp, opaque_key,
2791 desc_idx, *post_ptr);
2792
2793 copy_skb = dev_alloc_skb(len + 2);
2794 if (copy_skb == NULL)
2795 goto drop_it_no_recycle;
2796
2797 copy_skb->dev = tp->dev;
2798 skb_reserve(copy_skb, 2);
2799 skb_put(copy_skb, len);
2800 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2801 memcpy(copy_skb->data, skb->data, len);
2802 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2803
2804 /* We'll reuse the original ring buffer. */
2805 skb = copy_skb;
2806 }
2807
2808 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2809 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2810 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2811 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2812 skb->ip_summed = CHECKSUM_UNNECESSARY;
2813 else
2814 skb->ip_summed = CHECKSUM_NONE;
2815
2816 skb->protocol = eth_type_trans(skb, tp->dev);
2817 #if TG3_VLAN_TAG_USED
2818 if (tp->vlgrp != NULL &&
2819 desc->type_flags & RXD_FLAG_VLAN) {
2820 tg3_vlan_rx(tp, skb,
2821 desc->err_vlan & RXD_VLAN_MASK);
2822 } else
2823 #endif
2824 netif_receive_skb(skb);
2825
2826 tp->dev->last_rx = jiffies;
2827 received++;
2828 budget--;
2829
2830 next_pkt:
2831 (*post_ptr)++;
2832 next_pkt_nopost:
2833 sw_idx++;
2834 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2835
2836 /* Refresh hw_idx to see if there is new work */
2837 if (sw_idx == hw_idx) {
2838 hw_idx = tp->hw_status->idx[0].rx_producer;
2839 rmb();
2840 }
2841 }
2842
2843 /* ACK the status ring. */
2844 tp->rx_rcb_ptr = sw_idx;
2845 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2846
2847 /* Refill RX ring(s). */
2848 if (work_mask & RXD_OPAQUE_RING_STD) {
2849 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2850 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2851 sw_idx);
2852 }
2853 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2854 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2855 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2856 sw_idx);
2857 }
2858 mmiowb();
2859
2860 return received;
2861 }
2862
2863 static int tg3_poll(struct net_device *netdev, int *budget)
2864 {
2865 struct tg3 *tp = netdev_priv(netdev);
2866 struct tg3_hw_status *sblk = tp->hw_status;
2867 unsigned long flags;
2868 int done;
2869
2870 spin_lock_irqsave(&tp->lock, flags);
2871
2872 /* handle link change and other phy events */
2873 if (!(tp->tg3_flags &
2874 (TG3_FLAG_USE_LINKCHG_REG |
2875 TG3_FLAG_POLL_SERDES))) {
2876 if (sblk->status & SD_STATUS_LINK_CHG) {
2877 sblk->status = SD_STATUS_UPDATED |
2878 (sblk->status & ~SD_STATUS_LINK_CHG);
2879 tg3_setup_phy(tp, 0);
2880 }
2881 }
2882
2883 /* run TX completion thread */
2884 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2885 spin_lock(&tp->tx_lock);
2886 tg3_tx(tp);
2887 spin_unlock(&tp->tx_lock);
2888 }
2889
2890 spin_unlock_irqrestore(&tp->lock, flags);
2891
2892 /* run RX thread, within the bounds set by NAPI.
2893 * All RX "locking" is done by ensuring outside
2894 * code synchronizes with dev->poll()
2895 */
2896 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2897 int orig_budget = *budget;
2898 int work_done;
2899
2900 if (orig_budget > netdev->quota)
2901 orig_budget = netdev->quota;
2902
2903 work_done = tg3_rx(tp, orig_budget);
2904
2905 *budget -= work_done;
2906 netdev->quota -= work_done;
2907 }
2908
2909 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2910 tp->last_tag = sblk->status_tag;
2911 rmb();
2912
2913 /* if no more work, tell net stack and NIC we're done */
2914 done = !tg3_has_work(tp);
2915 if (done) {
2916 spin_lock_irqsave(&tp->lock, flags);
2917 __netif_rx_complete(netdev);
2918 tg3_restart_ints(tp);
2919 spin_unlock_irqrestore(&tp->lock, flags);
2920 }
2921
2922 return (done ? 0 : 1);
2923 }
2924
2925 /* MSI ISR - No need to check for interrupt sharing and no need to
2926 * flush status block and interrupt mailbox. PCI ordering rules
2927 * guarantee that MSI will arrive after the status block.
2928 */
2929 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2930 {
2931 struct net_device *dev = dev_id;
2932 struct tg3 *tp = netdev_priv(dev);
2933 struct tg3_hw_status *sblk = tp->hw_status;
2934 unsigned long flags;
2935
2936 spin_lock_irqsave(&tp->lock, flags);
2937
2938 /*
2939 * Writing any value to intr-mbox-0 clears PCI INTA# and
2940 * chip-internal interrupt pending events.
2941 * Writing non-zero to intr-mbox-0 additional tells the
2942 * NIC to stop sending us irqs, engaging "in-intr-handler"
2943 * event coalescing.
2944 */
2945 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2946 tp->last_tag = sblk->status_tag;
2947 sblk->status &= ~SD_STATUS_UPDATED;
2948 if (likely(tg3_has_work(tp)))
2949 netif_rx_schedule(dev); /* schedule NAPI poll */
2950 else {
2951 /* No work, re-enable interrupts. */
2952 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2953 tp->last_tag << 24);
2954 }
2955
2956 spin_unlock_irqrestore(&tp->lock, flags);
2957
2958 return IRQ_RETVAL(1);
2959 }
2960
2961 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2962 {
2963 struct net_device *dev = dev_id;
2964 struct tg3 *tp = netdev_priv(dev);
2965 struct tg3_hw_status *sblk = tp->hw_status;
2966 unsigned long flags;
2967 unsigned int handled = 1;
2968
2969 spin_lock_irqsave(&tp->lock, flags);
2970
2971 /* In INTx mode, it is possible for the interrupt to arrive at
2972 * the CPU before the status block posted prior to the interrupt.
2973 * Reading the PCI State register will confirm whether the
2974 * interrupt is ours and will flush the status block.
2975 */
2976 if ((sblk->status & SD_STATUS_UPDATED) ||
2977 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2978 /*
2979 * Writing any value to intr-mbox-0 clears PCI INTA# and
2980 * chip-internal interrupt pending events.
2981 * Writing non-zero to intr-mbox-0 additional tells the
2982 * NIC to stop sending us irqs, engaging "in-intr-handler"
2983 * event coalescing.
2984 */
2985 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2986 0x00000001);
2987 sblk->status &= ~SD_STATUS_UPDATED;
2988 if (likely(tg3_has_work(tp)))
2989 netif_rx_schedule(dev); /* schedule NAPI poll */
2990 else {
2991 /* No work, shared interrupt perhaps? re-enable
2992 * interrupts, and flush that PCI write
2993 */
2994 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2995 0x00000000);
2996 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2997 }
2998 } else { /* shared interrupt */
2999 handled = 0;
3000 }
3001
3002 spin_unlock_irqrestore(&tp->lock, flags);
3003
3004 return IRQ_RETVAL(handled);
3005 }
3006
3007 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3008 {
3009 struct net_device *dev = dev_id;
3010 struct tg3 *tp = netdev_priv(dev);
3011 struct tg3_hw_status *sblk = tp->hw_status;
3012 unsigned long flags;
3013 unsigned int handled = 1;
3014
3015 spin_lock_irqsave(&tp->lock, flags);
3016
3017 /* In INTx mode, it is possible for the interrupt to arrive at
3018 * the CPU before the status block posted prior to the interrupt.
3019 * Reading the PCI State register will confirm whether the
3020 * interrupt is ours and will flush the status block.
3021 */
3022 if ((sblk->status & SD_STATUS_UPDATED) ||
3023 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3024 /*
3025 * writing any value to intr-mbox-0 clears PCI INTA# and
3026 * chip-internal interrupt pending events.
3027 * writing non-zero to intr-mbox-0 additional tells the
3028 * NIC to stop sending us irqs, engaging "in-intr-handler"
3029 * event coalescing.
3030 */
3031 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3032 0x00000001);
3033 tp->last_tag = sblk->status_tag;
3034 sblk->status &= ~SD_STATUS_UPDATED;
3035 if (likely(tg3_has_work(tp)))
3036 netif_rx_schedule(dev); /* schedule NAPI poll */
3037 else {
3038 /* no work, shared interrupt perhaps? re-enable
3039 * interrupts, and flush that PCI write
3040 */
3041 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3042 tp->last_tag << 24);
3043 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3044 }
3045 } else { /* shared interrupt */
3046 handled = 0;
3047 }
3048
3049 spin_unlock_irqrestore(&tp->lock, flags);
3050
3051 return IRQ_RETVAL(handled);
3052 }
3053
3054 /* ISR for interrupt test */
3055 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3056 struct pt_regs *regs)
3057 {
3058 struct net_device *dev = dev_id;
3059 struct tg3 *tp = netdev_priv(dev);
3060 struct tg3_hw_status *sblk = tp->hw_status;
3061
3062 if (sblk->status & SD_STATUS_UPDATED) {
3063 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3064 0x00000001);
3065 return IRQ_RETVAL(1);
3066 }
3067 return IRQ_RETVAL(0);
3068 }
3069
3070 static int tg3_init_hw(struct tg3 *);
3071 static int tg3_halt(struct tg3 *, int);
3072
3073 #ifdef CONFIG_NET_POLL_CONTROLLER
3074 static void tg3_poll_controller(struct net_device *dev)
3075 {
3076 struct tg3 *tp = netdev_priv(dev);
3077
3078 tg3_interrupt(tp->pdev->irq, dev, NULL);
3079 }
3080 #endif
3081
3082 static void tg3_reset_task(void *_data)
3083 {
3084 struct tg3 *tp = _data;
3085 unsigned int restart_timer;
3086
3087 tg3_netif_stop(tp);
3088
3089 spin_lock_irq(&tp->lock);
3090 spin_lock(&tp->tx_lock);
3091
3092 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3093 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3094
3095 tg3_halt(tp, 0);
3096 tg3_init_hw(tp);
3097
3098 tg3_netif_start(tp);
3099
3100 spin_unlock(&tp->tx_lock);
3101 spin_unlock_irq(&tp->lock);
3102
3103 if (restart_timer)
3104 mod_timer(&tp->timer, jiffies + 1);
3105 }
3106
3107 static void tg3_tx_timeout(struct net_device *dev)
3108 {
3109 struct tg3 *tp = netdev_priv(dev);
3110
3111 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3112 dev->name);
3113
3114 schedule_work(&tp->reset_task);
3115 }
3116
3117 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3118
3119 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3120 u32 guilty_entry, int guilty_len,
3121 u32 last_plus_one, u32 *start, u32 mss)
3122 {
3123 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3124 dma_addr_t new_addr;
3125 u32 entry = *start;
3126 int i;
3127
3128 if (!new_skb) {
3129 dev_kfree_skb(skb);
3130 return -1;
3131 }
3132
3133 /* New SKB is guaranteed to be linear. */
3134 entry = *start;
3135 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3136 PCI_DMA_TODEVICE);
3137 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3138 (skb->ip_summed == CHECKSUM_HW) ?
3139 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3140 *start = NEXT_TX(entry);
3141
3142 /* Now clean up the sw ring entries. */
3143 i = 0;
3144 while (entry != last_plus_one) {
3145 int len;
3146
3147 if (i == 0)
3148 len = skb_headlen(skb);
3149 else
3150 len = skb_shinfo(skb)->frags[i-1].size;
3151 pci_unmap_single(tp->pdev,
3152 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3153 len, PCI_DMA_TODEVICE);
3154 if (i == 0) {
3155 tp->tx_buffers[entry].skb = new_skb;
3156 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3157 } else {
3158 tp->tx_buffers[entry].skb = NULL;
3159 }
3160 entry = NEXT_TX(entry);
3161 i++;
3162 }
3163
3164 dev_kfree_skb(skb);
3165
3166 return 0;
3167 }
3168
3169 static void tg3_set_txd(struct tg3 *tp, int entry,
3170 dma_addr_t mapping, int len, u32 flags,
3171 u32 mss_and_is_end)
3172 {
3173 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3174 int is_end = (mss_and_is_end & 0x1);
3175 u32 mss = (mss_and_is_end >> 1);
3176 u32 vlan_tag = 0;
3177
3178 if (is_end)
3179 flags |= TXD_FLAG_END;
3180 if (flags & TXD_FLAG_VLAN) {
3181 vlan_tag = flags >> 16;
3182 flags &= 0xffff;
3183 }
3184 vlan_tag |= (mss << TXD_MSS_SHIFT);
3185
3186 txd->addr_hi = ((u64) mapping >> 32);
3187 txd->addr_lo = ((u64) mapping & 0xffffffff);
3188 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3189 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3190 }
3191
3192 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3193 {
3194 u32 base = (u32) mapping & 0xffffffff;
3195
3196 return ((base > 0xffffdcc0) &&
3197 (base + len + 8 < base));
3198 }
3199
3200 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3201 {
3202 struct tg3 *tp = netdev_priv(dev);
3203 dma_addr_t mapping;
3204 unsigned int i;
3205 u32 len, entry, base_flags, mss;
3206 int would_hit_hwbug;
3207 unsigned long flags;
3208
3209 len = skb_headlen(skb);
3210
3211 /* No BH disabling for tx_lock here. We are running in BH disabled
3212 * context and TX reclaim runs via tp->poll inside of a software
3213 * interrupt. Rejoice!
3214 *
3215 * Actually, things are not so simple. If we are to take a hw
3216 * IRQ here, we can deadlock, consider:
3217 *
3218 * CPU1 CPU2
3219 * tg3_start_xmit
3220 * take tp->tx_lock
3221 * tg3_timer
3222 * take tp->lock
3223 * tg3_interrupt
3224 * spin on tp->lock
3225 * spin on tp->tx_lock
3226 *
3227 * So we really do need to disable interrupts when taking
3228 * tx_lock here.
3229 */
3230 local_irq_save(flags);
3231 if (!spin_trylock(&tp->tx_lock)) {
3232 local_irq_restore(flags);
3233 return NETDEV_TX_LOCKED;
3234 }
3235
3236 /* This is a hard error, log it. */
3237 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3238 netif_stop_queue(dev);
3239 spin_unlock_irqrestore(&tp->tx_lock, flags);
3240 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3241 dev->name);
3242 return NETDEV_TX_BUSY;
3243 }
3244
3245 entry = tp->tx_prod;
3246 base_flags = 0;
3247 if (skb->ip_summed == CHECKSUM_HW)
3248 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3249 #if TG3_TSO_SUPPORT != 0
3250 mss = 0;
3251 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3252 (mss = skb_shinfo(skb)->tso_size) != 0) {
3253 int tcp_opt_len, ip_tcp_len;
3254
3255 if (skb_header_cloned(skb) &&
3256 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3257 dev_kfree_skb(skb);
3258 goto out_unlock;
3259 }
3260
3261 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3262 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3263
3264 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3265 TXD_FLAG_CPU_POST_DMA);
3266
3267 skb->nh.iph->check = 0;
3268 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3269 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3270 skb->h.th->check = 0;
3271 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3272 }
3273 else {
3274 skb->h.th->check =
3275 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3276 skb->nh.iph->daddr,
3277 0, IPPROTO_TCP, 0);
3278 }
3279
3280 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3281 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3282 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3283 int tsflags;
3284
3285 tsflags = ((skb->nh.iph->ihl - 5) +
3286 (tcp_opt_len >> 2));
3287 mss |= (tsflags << 11);
3288 }
3289 } else {
3290 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3291 int tsflags;
3292
3293 tsflags = ((skb->nh.iph->ihl - 5) +
3294 (tcp_opt_len >> 2));
3295 base_flags |= tsflags << 12;
3296 }
3297 }
3298 }
3299 #else
3300 mss = 0;
3301 #endif
3302 #if TG3_VLAN_TAG_USED
3303 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3304 base_flags |= (TXD_FLAG_VLAN |
3305 (vlan_tx_tag_get(skb) << 16));
3306 #endif
3307
3308 /* Queue skb data, a.k.a. the main skb fragment. */
3309 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3310
3311 tp->tx_buffers[entry].skb = skb;
3312 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3313
3314 would_hit_hwbug = 0;
3315
3316 if (tg3_4g_overflow_test(mapping, len))
3317 would_hit_hwbug = entry + 1;
3318
3319 tg3_set_txd(tp, entry, mapping, len, base_flags,
3320 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3321
3322 entry = NEXT_TX(entry);
3323
3324 /* Now loop through additional data fragments, and queue them. */
3325 if (skb_shinfo(skb)->nr_frags > 0) {
3326 unsigned int i, last;
3327
3328 last = skb_shinfo(skb)->nr_frags - 1;
3329 for (i = 0; i <= last; i++) {
3330 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3331
3332 len = frag->size;
3333 mapping = pci_map_page(tp->pdev,
3334 frag->page,
3335 frag->page_offset,
3336 len, PCI_DMA_TODEVICE);
3337
3338 tp->tx_buffers[entry].skb = NULL;
3339 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3340
3341 if (tg3_4g_overflow_test(mapping, len)) {
3342 /* Only one should match. */
3343 if (would_hit_hwbug)
3344 BUG();
3345 would_hit_hwbug = entry + 1;
3346 }
3347
3348 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3349 tg3_set_txd(tp, entry, mapping, len,
3350 base_flags, (i == last)|(mss << 1));
3351 else
3352 tg3_set_txd(tp, entry, mapping, len,
3353 base_flags, (i == last));
3354
3355 entry = NEXT_TX(entry);
3356 }
3357 }
3358
3359 if (would_hit_hwbug) {
3360 u32 last_plus_one = entry;
3361 u32 start;
3362 unsigned int len = 0;
3363
3364 would_hit_hwbug -= 1;
3365 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3366 entry &= (TG3_TX_RING_SIZE - 1);
3367 start = entry;
3368 i = 0;
3369 while (entry != last_plus_one) {
3370 if (i == 0)
3371 len = skb_headlen(skb);
3372 else
3373 len = skb_shinfo(skb)->frags[i-1].size;
3374
3375 if (entry == would_hit_hwbug)
3376 break;
3377
3378 i++;
3379 entry = NEXT_TX(entry);
3380
3381 }
3382
3383 /* If the workaround fails due to memory/mapping
3384 * failure, silently drop this packet.
3385 */
3386 if (tigon3_4gb_hwbug_workaround(tp, skb,
3387 entry, len,
3388 last_plus_one,
3389 &start, mss))
3390 goto out_unlock;
3391
3392 entry = start;
3393 }
3394
3395 /* Packets are ready, update Tx producer idx local and on card. */
3396 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3397
3398 tp->tx_prod = entry;
3399 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3400 netif_stop_queue(dev);
3401
3402 out_unlock:
3403 mmiowb();
3404 spin_unlock_irqrestore(&tp->tx_lock, flags);
3405
3406 dev->trans_start = jiffies;
3407
3408 return NETDEV_TX_OK;
3409 }
3410
3411 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3412 int new_mtu)
3413 {
3414 dev->mtu = new_mtu;
3415
3416 if (new_mtu > ETH_DATA_LEN)
3417 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3418 else
3419 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3420 }
3421
3422 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3423 {
3424 struct tg3 *tp = netdev_priv(dev);
3425
3426 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3427 return -EINVAL;
3428
3429 if (!netif_running(dev)) {
3430 /* We'll just catch it later when the
3431 * device is up'd.
3432 */
3433 tg3_set_mtu(dev, tp, new_mtu);
3434 return 0;
3435 }
3436
3437 tg3_netif_stop(tp);
3438 spin_lock_irq(&tp->lock);
3439 spin_lock(&tp->tx_lock);
3440
3441 tg3_halt(tp, 1);
3442
3443 tg3_set_mtu(dev, tp, new_mtu);
3444
3445 tg3_init_hw(tp);
3446
3447 tg3_netif_start(tp);
3448
3449 spin_unlock(&tp->tx_lock);
3450 spin_unlock_irq(&tp->lock);
3451
3452 return 0;
3453 }
3454
3455 /* Free up pending packets in all rx/tx rings.
3456 *
3457 * The chip has been shut down and the driver detached from
3458 * the networking, so no interrupts or new tx packets will
3459 * end up in the driver. tp->{tx,}lock is not held and we are not
3460 * in an interrupt context and thus may sleep.
3461 */
3462 static void tg3_free_rings(struct tg3 *tp)
3463 {
3464 struct ring_info *rxp;
3465 int i;
3466
3467 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3468 rxp = &tp->rx_std_buffers[i];
3469
3470 if (rxp->skb == NULL)
3471 continue;
3472 pci_unmap_single(tp->pdev,
3473 pci_unmap_addr(rxp, mapping),
3474 RX_PKT_BUF_SZ - tp->rx_offset,
3475 PCI_DMA_FROMDEVICE);
3476 dev_kfree_skb_any(rxp->skb);
3477 rxp->skb = NULL;
3478 }
3479
3480 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3481 rxp = &tp->rx_jumbo_buffers[i];
3482
3483 if (rxp->skb == NULL)
3484 continue;
3485 pci_unmap_single(tp->pdev,
3486 pci_unmap_addr(rxp, mapping),
3487 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3488 PCI_DMA_FROMDEVICE);
3489 dev_kfree_skb_any(rxp->skb);
3490 rxp->skb = NULL;
3491 }
3492
3493 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3494 struct tx_ring_info *txp;
3495 struct sk_buff *skb;
3496 int j;
3497
3498 txp = &tp->tx_buffers[i];
3499 skb = txp->skb;
3500
3501 if (skb == NULL) {
3502 i++;
3503 continue;
3504 }
3505
3506 pci_unmap_single(tp->pdev,
3507 pci_unmap_addr(txp, mapping),
3508 skb_headlen(skb),
3509 PCI_DMA_TODEVICE);
3510 txp->skb = NULL;
3511
3512 i++;
3513
3514 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3515 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3516 pci_unmap_page(tp->pdev,
3517 pci_unmap_addr(txp, mapping),
3518 skb_shinfo(skb)->frags[j].size,
3519 PCI_DMA_TODEVICE);
3520 i++;
3521 }
3522
3523 dev_kfree_skb_any(skb);
3524 }
3525 }
3526
3527 /* Initialize tx/rx rings for packet processing.
3528 *
3529 * The chip has been shut down and the driver detached from
3530 * the networking, so no interrupts or new tx packets will
3531 * end up in the driver. tp->{tx,}lock are held and thus
3532 * we may not sleep.
3533 */
3534 static void tg3_init_rings(struct tg3 *tp)
3535 {
3536 u32 i;
3537
3538 /* Free up all the SKBs. */
3539 tg3_free_rings(tp);
3540
3541 /* Zero out all descriptors. */
3542 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3543 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3544 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3545 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3546
3547 /* Initialize invariants of the rings, we only set this
3548 * stuff once. This works because the card does not
3549 * write into the rx buffer posting rings.
3550 */
3551 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3552 struct tg3_rx_buffer_desc *rxd;
3553
3554 rxd = &tp->rx_std[i];
3555 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3556 << RXD_LEN_SHIFT;
3557 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3558 rxd->opaque = (RXD_OPAQUE_RING_STD |
3559 (i << RXD_OPAQUE_INDEX_SHIFT));
3560 }
3561
3562 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3563 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3564 struct tg3_rx_buffer_desc *rxd;
3565
3566 rxd = &tp->rx_jumbo[i];
3567 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3568 << RXD_LEN_SHIFT;
3569 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3570 RXD_FLAG_JUMBO;
3571 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3572 (i << RXD_OPAQUE_INDEX_SHIFT));
3573 }
3574 }
3575
3576 /* Now allocate fresh SKBs for each rx ring. */
3577 for (i = 0; i < tp->rx_pending; i++) {
3578 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3579 -1, i) < 0)
3580 break;
3581 }
3582
3583 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3584 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3585 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3586 -1, i) < 0)
3587 break;
3588 }
3589 }
3590 }
3591
3592 /*
3593 * Must not be invoked with interrupt sources disabled and
3594 * the hardware shutdown down.
3595 */
3596 static void tg3_free_consistent(struct tg3 *tp)
3597 {
3598 if (tp->rx_std_buffers) {
3599 kfree(tp->rx_std_buffers);
3600 tp->rx_std_buffers = NULL;
3601 }
3602 if (tp->rx_std) {
3603 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3604 tp->rx_std, tp->rx_std_mapping);
3605 tp->rx_std = NULL;
3606 }
3607 if (tp->rx_jumbo) {
3608 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3609 tp->rx_jumbo, tp->rx_jumbo_mapping);
3610 tp->rx_jumbo = NULL;
3611 }
3612 if (tp->rx_rcb) {
3613 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3614 tp->rx_rcb, tp->rx_rcb_mapping);
3615 tp->rx_rcb = NULL;
3616 }
3617 if (tp->tx_ring) {
3618 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3619 tp->tx_ring, tp->tx_desc_mapping);
3620 tp->tx_ring = NULL;
3621 }
3622 if (tp->hw_status) {
3623 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3624 tp->hw_status, tp->status_mapping);
3625 tp->hw_status = NULL;
3626 }
3627 if (tp->hw_stats) {
3628 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3629 tp->hw_stats, tp->stats_mapping);
3630 tp->hw_stats = NULL;
3631 }
3632 }
3633
3634 /*
3635 * Must not be invoked with interrupt sources disabled and
3636 * the hardware shutdown down. Can sleep.
3637 */
3638 static int tg3_alloc_consistent(struct tg3 *tp)
3639 {
3640 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3641 (TG3_RX_RING_SIZE +
3642 TG3_RX_JUMBO_RING_SIZE)) +
3643 (sizeof(struct tx_ring_info) *
3644 TG3_TX_RING_SIZE),
3645 GFP_KERNEL);
3646 if (!tp->rx_std_buffers)
3647 return -ENOMEM;
3648
3649 memset(tp->rx_std_buffers, 0,
3650 (sizeof(struct ring_info) *
3651 (TG3_RX_RING_SIZE +
3652 TG3_RX_JUMBO_RING_SIZE)) +
3653 (sizeof(struct tx_ring_info) *
3654 TG3_TX_RING_SIZE));
3655
3656 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3657 tp->tx_buffers = (struct tx_ring_info *)
3658 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3659
3660 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3661 &tp->rx_std_mapping);
3662 if (!tp->rx_std)
3663 goto err_out;
3664
3665 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3666 &tp->rx_jumbo_mapping);
3667
3668 if (!tp->rx_jumbo)
3669 goto err_out;
3670
3671 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3672 &tp->rx_rcb_mapping);
3673 if (!tp->rx_rcb)
3674 goto err_out;
3675
3676 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3677 &tp->tx_desc_mapping);
3678 if (!tp->tx_ring)
3679 goto err_out;
3680
3681 tp->hw_status = pci_alloc_consistent(tp->pdev,
3682 TG3_HW_STATUS_SIZE,
3683 &tp->status_mapping);
3684 if (!tp->hw_status)
3685 goto err_out;
3686
3687 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3688 sizeof(struct tg3_hw_stats),
3689 &tp->stats_mapping);
3690 if (!tp->hw_stats)
3691 goto err_out;
3692
3693 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3694 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3695
3696 return 0;
3697
3698 err_out:
3699 tg3_free_consistent(tp);
3700 return -ENOMEM;
3701 }
3702
3703 #define MAX_WAIT_CNT 1000
3704
3705 /* To stop a block, clear the enable bit and poll till it
3706 * clears. tp->lock is held.
3707 */
3708 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
3709 {
3710 unsigned int i;
3711 u32 val;
3712
3713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3714 switch (ofs) {
3715 case RCVLSC_MODE:
3716 case DMAC_MODE:
3717 case MBFREE_MODE:
3718 case BUFMGR_MODE:
3719 case MEMARB_MODE:
3720 /* We can't enable/disable these bits of the
3721 * 5705/5750, just say success.
3722 */
3723 return 0;
3724
3725 default:
3726 break;
3727 };
3728 }
3729
3730 val = tr32(ofs);
3731 val &= ~enable_bit;
3732 tw32_f(ofs, val);
3733
3734 for (i = 0; i < MAX_WAIT_CNT; i++) {
3735 udelay(100);
3736 val = tr32(ofs);
3737 if ((val & enable_bit) == 0)
3738 break;
3739 }
3740
3741 if (i == MAX_WAIT_CNT && !silent) {
3742 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3743 "ofs=%lx enable_bit=%x\n",
3744 ofs, enable_bit);
3745 return -ENODEV;
3746 }
3747
3748 return 0;
3749 }
3750
3751 /* tp->lock is held. */
3752 static int tg3_abort_hw(struct tg3 *tp, int silent)
3753 {
3754 int i, err;
3755
3756 tg3_disable_ints(tp);
3757
3758 tp->rx_mode &= ~RX_MODE_ENABLE;
3759 tw32_f(MAC_RX_MODE, tp->rx_mode);
3760 udelay(10);
3761
3762 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3763 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3764 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3765 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3766 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3767 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3768
3769 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3770 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3771 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3772 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3773 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3774 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3775 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
3776
3777 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3778 tw32_f(MAC_MODE, tp->mac_mode);
3779 udelay(40);
3780
3781 tp->tx_mode &= ~TX_MODE_ENABLE;
3782 tw32_f(MAC_TX_MODE, tp->tx_mode);
3783
3784 for (i = 0; i < MAX_WAIT_CNT; i++) {
3785 udelay(100);
3786 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3787 break;
3788 }
3789 if (i >= MAX_WAIT_CNT) {
3790 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3791 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3792 tp->dev->name, tr32(MAC_TX_MODE));
3793 err |= -ENODEV;
3794 }
3795
3796 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
3797 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3798 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
3799
3800 tw32(FTQ_RESET, 0xffffffff);
3801 tw32(FTQ_RESET, 0x00000000);
3802
3803 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3804 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
3805
3806 if (tp->hw_status)
3807 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3808 if (tp->hw_stats)
3809 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3810
3811 return err;
3812 }
3813
3814 /* tp->lock is held. */
3815 static int tg3_nvram_lock(struct tg3 *tp)
3816 {
3817 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3818 int i;
3819
3820 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3821 for (i = 0; i < 8000; i++) {
3822 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3823 break;
3824 udelay(20);
3825 }
3826 if (i == 8000)
3827 return -ENODEV;
3828 }
3829 return 0;
3830 }
3831
3832 /* tp->lock is held. */
3833 static void tg3_nvram_unlock(struct tg3 *tp)
3834 {
3835 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3836 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3837 }
3838
3839 /* tp->lock is held. */
3840 static void tg3_enable_nvram_access(struct tg3 *tp)
3841 {
3842 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3843 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3844 u32 nvaccess = tr32(NVRAM_ACCESS);
3845
3846 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3847 }
3848 }
3849
3850 /* tp->lock is held. */
3851 static void tg3_disable_nvram_access(struct tg3 *tp)
3852 {
3853 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3854 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3855 u32 nvaccess = tr32(NVRAM_ACCESS);
3856
3857 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3858 }
3859 }
3860
3861 /* tp->lock is held. */
3862 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3863 {
3864 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3865 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3866 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3867
3868 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3869 switch (kind) {
3870 case RESET_KIND_INIT:
3871 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3872 DRV_STATE_START);
3873 break;
3874
3875 case RESET_KIND_SHUTDOWN:
3876 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3877 DRV_STATE_UNLOAD);
3878 break;
3879
3880 case RESET_KIND_SUSPEND:
3881 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3882 DRV_STATE_SUSPEND);
3883 break;
3884
3885 default:
3886 break;
3887 };
3888 }
3889 }
3890
3891 /* tp->lock is held. */
3892 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3893 {
3894 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3895 switch (kind) {
3896 case RESET_KIND_INIT:
3897 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3898 DRV_STATE_START_DONE);
3899 break;
3900
3901 case RESET_KIND_SHUTDOWN:
3902 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3903 DRV_STATE_UNLOAD_DONE);
3904 break;
3905
3906 default:
3907 break;
3908 };
3909 }
3910 }
3911
3912 /* tp->lock is held. */
3913 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3914 {
3915 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3916 switch (kind) {
3917 case RESET_KIND_INIT:
3918 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3919 DRV_STATE_START);
3920 break;
3921
3922 case RESET_KIND_SHUTDOWN:
3923 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3924 DRV_STATE_UNLOAD);
3925 break;
3926
3927 case RESET_KIND_SUSPEND:
3928 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3929 DRV_STATE_SUSPEND);
3930 break;
3931
3932 default:
3933 break;
3934 };
3935 }
3936 }
3937
3938 static void tg3_stop_fw(struct tg3 *);
3939
3940 /* tp->lock is held. */
3941 static int tg3_chip_reset(struct tg3 *tp)
3942 {
3943 u32 val;
3944 u32 flags_save;
3945 int i;
3946
3947 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3948 tg3_nvram_lock(tp);
3949
3950 /*
3951 * We must avoid the readl() that normally takes place.
3952 * It locks machines, causes machine checks, and other
3953 * fun things. So, temporarily disable the 5701
3954 * hardware workaround, while we do the reset.
3955 */
3956 flags_save = tp->tg3_flags;
3957 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3958
3959 /* do the reset */
3960 val = GRC_MISC_CFG_CORECLK_RESET;
3961
3962 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3963 if (tr32(0x7e2c) == 0x60) {
3964 tw32(0x7e2c, 0x20);
3965 }
3966 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3967 tw32(GRC_MISC_CFG, (1 << 29));
3968 val |= (1 << 29);
3969 }
3970 }
3971
3972 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3973 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3974 tw32(GRC_MISC_CFG, val);
3975
3976 /* restore 5701 hardware bug workaround flag */
3977 tp->tg3_flags = flags_save;
3978
3979 /* Unfortunately, we have to delay before the PCI read back.
3980 * Some 575X chips even will not respond to a PCI cfg access
3981 * when the reset command is given to the chip.
3982 *
3983 * How do these hardware designers expect things to work
3984 * properly if the PCI write is posted for a long period
3985 * of time? It is always necessary to have some method by
3986 * which a register read back can occur to push the write
3987 * out which does the reset.
3988 *
3989 * For most tg3 variants the trick below was working.
3990 * Ho hum...
3991 */
3992 udelay(120);
3993
3994 /* Flush PCI posted writes. The normal MMIO registers
3995 * are inaccessible at this time so this is the only
3996 * way to make this reliably (actually, this is no longer
3997 * the case, see above). I tried to use indirect
3998 * register read/write but this upset some 5701 variants.
3999 */
4000 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4001
4002 udelay(120);
4003
4004 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4005 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4006 int i;
4007 u32 cfg_val;
4008
4009 /* Wait for link training to complete. */
4010 for (i = 0; i < 5000; i++)
4011 udelay(100);
4012
4013 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4014 pci_write_config_dword(tp->pdev, 0xc4,
4015 cfg_val | (1 << 15));
4016 }
4017 /* Set PCIE max payload size and clear error status. */
4018 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4019 }
4020
4021 /* Re-enable indirect register accesses. */
4022 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4023 tp->misc_host_ctrl);
4024
4025 /* Set MAX PCI retry to zero. */
4026 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4027 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4028 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4029 val |= PCISTATE_RETRY_SAME_DMA;
4030 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4031
4032 pci_restore_state(tp->pdev);
4033
4034 /* Make sure PCI-X relaxed ordering bit is clear. */
4035 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4036 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4037 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4038
4039 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4040
4041 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4042 tg3_stop_fw(tp);
4043 tw32(0x5000, 0x400);
4044 }
4045
4046 tw32(GRC_MODE, tp->grc_mode);
4047
4048 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4049 u32 val = tr32(0xc4);
4050
4051 tw32(0xc4, val | (1 << 15));
4052 }
4053
4054 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4056 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4057 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4058 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4059 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4060 }
4061
4062 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4063 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4064 tw32_f(MAC_MODE, tp->mac_mode);
4065 } else
4066 tw32_f(MAC_MODE, 0);
4067 udelay(40);
4068
4069 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4070 /* Wait for firmware initialization to complete. */
4071 for (i = 0; i < 100000; i++) {
4072 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4073 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4074 break;
4075 udelay(10);
4076 }
4077 if (i >= 100000) {
4078 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4079 "firmware will not restart magic=%08x\n",
4080 tp->dev->name, val);
4081 return -ENODEV;
4082 }
4083 }
4084
4085 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4086 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4087 u32 val = tr32(0x7c00);
4088
4089 tw32(0x7c00, val | (1 << 25));
4090 }
4091
4092 /* Reprobe ASF enable state. */
4093 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4094 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4095 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4096 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4097 u32 nic_cfg;
4098
4099 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4100 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4101 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4102 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4103 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4104 }
4105 }
4106
4107 return 0;
4108 }
4109
4110 /* tp->lock is held. */
4111 static void tg3_stop_fw(struct tg3 *tp)
4112 {
4113 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4114 u32 val;
4115 int i;
4116
4117 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4118 val = tr32(GRC_RX_CPU_EVENT);
4119 val |= (1 << 14);
4120 tw32(GRC_RX_CPU_EVENT, val);
4121
4122 /* Wait for RX cpu to ACK the event. */
4123 for (i = 0; i < 100; i++) {
4124 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4125 break;
4126 udelay(1);
4127 }
4128 }
4129 }
4130
4131 /* tp->lock is held. */
4132 static int tg3_halt(struct tg3 *tp, int silent)
4133 {
4134 int err;
4135
4136 tg3_stop_fw(tp);
4137
4138 tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
4139
4140 tg3_abort_hw(tp, silent);
4141 err = tg3_chip_reset(tp);
4142
4143 tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
4144 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4145
4146 if (err)
4147 return err;
4148
4149 return 0;
4150 }
4151
4152 #define TG3_FW_RELEASE_MAJOR 0x0
4153 #define TG3_FW_RELASE_MINOR 0x0
4154 #define TG3_FW_RELEASE_FIX 0x0
4155 #define TG3_FW_START_ADDR 0x08000000
4156 #define TG3_FW_TEXT_ADDR 0x08000000
4157 #define TG3_FW_TEXT_LEN 0x9c0
4158 #define TG3_FW_RODATA_ADDR 0x080009c0
4159 #define TG3_FW_RODATA_LEN 0x60
4160 #define TG3_FW_DATA_ADDR 0x08000a40
4161 #define TG3_FW_DATA_LEN 0x20
4162 #define TG3_FW_SBSS_ADDR 0x08000a60
4163 #define TG3_FW_SBSS_LEN 0xc
4164 #define TG3_FW_BSS_ADDR 0x08000a70
4165 #define TG3_FW_BSS_LEN 0x10
4166
4167 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4168 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4169 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4170 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4171 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4172 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4173 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4174 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4175 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4176 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4177 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4178 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4179 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4180 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4181 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4182 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4183 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4184 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4185 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4186 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4187 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4188 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4189 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4190 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4193 0, 0, 0, 0, 0, 0,
4194 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4195 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4196 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4197 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4198 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4199 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4200 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4201 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4202 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4203 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4204 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4208 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4209 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4210 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4211 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4212 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4213 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4214 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4215 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4216 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4217 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4218 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4219 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4220 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4221 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4222 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4223 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4224 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4225 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4226 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4227 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4228 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4229 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4230 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4231 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4232 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4233 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4234 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4235 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4236 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4237 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4238 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4239 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4240 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4241 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4242 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4243 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4244 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4245 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4246 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4247 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4248 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4249 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4250 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4251 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4252 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4253 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4254 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4255 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4256 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4257 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4258 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4259 };
4260
4261 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4262 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4263 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4264 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4265 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4266 0x00000000
4267 };
4268
4269 #if 0 /* All zeros, don't eat up space with it. */
4270 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4271 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4272 0x00000000, 0x00000000, 0x00000000, 0x00000000
4273 };
4274 #endif
4275
4276 #define RX_CPU_SCRATCH_BASE 0x30000
4277 #define RX_CPU_SCRATCH_SIZE 0x04000
4278 #define TX_CPU_SCRATCH_BASE 0x34000
4279 #define TX_CPU_SCRATCH_SIZE 0x04000
4280
4281 /* tp->lock is held. */
4282 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4283 {
4284 int i;
4285
4286 if (offset == TX_CPU_BASE &&
4287 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4288 BUG();
4289
4290 if (offset == RX_CPU_BASE) {
4291 for (i = 0; i < 10000; i++) {
4292 tw32(offset + CPU_STATE, 0xffffffff);
4293 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4294 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4295 break;
4296 }
4297
4298 tw32(offset + CPU_STATE, 0xffffffff);
4299 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4300 udelay(10);
4301 } else {
4302 for (i = 0; i < 10000; i++) {
4303 tw32(offset + CPU_STATE, 0xffffffff);
4304 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4305 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4306 break;
4307 }
4308 }
4309
4310 if (i >= 10000) {
4311 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4312 "and %s CPU\n",
4313 tp->dev->name,
4314 (offset == RX_CPU_BASE ? "RX" : "TX"));
4315 return -ENODEV;
4316 }
4317 return 0;
4318 }
4319
4320 struct fw_info {
4321 unsigned int text_base;
4322 unsigned int text_len;
4323 u32 *text_data;
4324 unsigned int rodata_base;
4325 unsigned int rodata_len;
4326 u32 *rodata_data;
4327 unsigned int data_base;
4328 unsigned int data_len;
4329 u32 *data_data;
4330 };
4331
4332 /* tp->lock is held. */
4333 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4334 int cpu_scratch_size, struct fw_info *info)
4335 {
4336 int err, i;
4337 u32 orig_tg3_flags = tp->tg3_flags;
4338 void (*write_op)(struct tg3 *, u32, u32);
4339
4340 if (cpu_base == TX_CPU_BASE &&
4341 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4342 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4343 "TX cpu firmware on %s which is 5705.\n",
4344 tp->dev->name);
4345 return -EINVAL;
4346 }
4347
4348 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4349 write_op = tg3_write_mem;
4350 else
4351 write_op = tg3_write_indirect_reg32;
4352
4353 /* Force use of PCI config space for indirect register
4354 * write calls.
4355 */
4356 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4357
4358 err = tg3_halt_cpu(tp, cpu_base);
4359 if (err)
4360 goto out;
4361
4362 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4363 write_op(tp, cpu_scratch_base + i, 0);
4364 tw32(cpu_base + CPU_STATE, 0xffffffff);
4365 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4366 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4367 write_op(tp, (cpu_scratch_base +
4368 (info->text_base & 0xffff) +
4369 (i * sizeof(u32))),
4370 (info->text_data ?
4371 info->text_data[i] : 0));
4372 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4373 write_op(tp, (cpu_scratch_base +
4374 (info->rodata_base & 0xffff) +
4375 (i * sizeof(u32))),
4376 (info->rodata_data ?
4377 info->rodata_data[i] : 0));
4378 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4379 write_op(tp, (cpu_scratch_base +
4380 (info->data_base & 0xffff) +
4381 (i * sizeof(u32))),
4382 (info->data_data ?
4383 info->data_data[i] : 0));
4384
4385 err = 0;
4386
4387 out:
4388 tp->tg3_flags = orig_tg3_flags;
4389 return err;
4390 }
4391
4392 /* tp->lock is held. */
4393 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4394 {
4395 struct fw_info info;
4396 int err, i;
4397
4398 info.text_base = TG3_FW_TEXT_ADDR;
4399 info.text_len = TG3_FW_TEXT_LEN;
4400 info.text_data = &tg3FwText[0];
4401 info.rodata_base = TG3_FW_RODATA_ADDR;
4402 info.rodata_len = TG3_FW_RODATA_LEN;
4403 info.rodata_data = &tg3FwRodata[0];
4404 info.data_base = TG3_FW_DATA_ADDR;
4405 info.data_len = TG3_FW_DATA_LEN;
4406 info.data_data = NULL;
4407
4408 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4409 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4410 &info);
4411 if (err)
4412 return err;
4413
4414 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4415 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4416 &info);
4417 if (err)
4418 return err;
4419
4420 /* Now startup only the RX cpu. */
4421 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4422 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4423
4424 for (i = 0; i < 5; i++) {
4425 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4426 break;
4427 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4428 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4429 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4430 udelay(1000);
4431 }
4432 if (i >= 5) {
4433 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4434 "to set RX CPU PC, is %08x should be %08x\n",
4435 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4436 TG3_FW_TEXT_ADDR);
4437 return -ENODEV;
4438 }
4439 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4440 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4441
4442 return 0;
4443 }
4444
4445 #if TG3_TSO_SUPPORT != 0
4446
4447 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
4448 #define TG3_TSO_FW_RELASE_MINOR 0x6
4449 #define TG3_TSO_FW_RELEASE_FIX 0x0
4450 #define TG3_TSO_FW_START_ADDR 0x08000000
4451 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
4452 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
4453 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4454 #define TG3_TSO_FW_RODATA_LEN 0x60
4455 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
4456 #define TG3_TSO_FW_DATA_LEN 0x30
4457 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4458 #define TG3_TSO_FW_SBSS_LEN 0x2c
4459 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
4460 #define TG3_TSO_FW_BSS_LEN 0x894
4461
4462 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4463 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4464 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4465 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4466 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4467 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4468 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4469 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4470 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4471 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4472 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4473 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4474 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4475 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4476 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4477 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4478 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4479 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4480 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4481 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4482 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4483 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4484 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4485 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4486 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4487 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4488 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4489 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4490 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4491 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4492 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4493 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4494 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4495 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4496 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4497 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4498 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4499 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4500 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4501 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4502 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4503 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4504 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4505 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4506 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4507 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4508 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4509 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4510 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4511 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4512 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4513 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4514 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4515 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4516 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4517 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4518 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4519 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4520 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4521 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4522 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4523 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4524 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4525 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4526 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4527 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4528 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4529 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4530 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4531 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4532 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4533 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4534 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4535 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4536 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4537 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4538 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4539 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4540 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4541 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4542 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4543 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4544 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4545 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4546 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4547 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4548 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4549 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4550 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4551 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4552 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4553 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4554 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4555 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4556 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4557 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4558 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4559 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4560 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4561 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4562 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4563 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4564 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4565 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4566 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4567 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4568 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4569 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4570 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4571 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4572 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4573 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4574 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4575 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4576 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4577 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4578 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4579 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4580 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4581 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4582 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4583 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4584 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4585 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4586 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4587 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4588 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4589 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4590 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4591 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4592 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4593 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4594 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4595 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4596 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4597 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4598 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4599 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4600 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4601 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4602 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4603 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4604 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4605 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4606 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4607 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4608 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4609 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4610 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4611 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4612 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4613 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4614 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4615 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4616 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4617 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4618 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4619 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4620 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4621 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4622 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4623 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4624 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4625 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4626 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4627 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4628 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4629 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4630 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4631 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4632 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4633 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4634 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4635 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4636 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4637 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4638 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4639 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4640 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4641 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4642 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4643 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4644 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4645 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4646 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4647 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4648 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4649 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4650 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4651 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4652 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4653 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4654 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4655 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4656 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4657 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4658 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4659 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4660 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4661 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4662 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4663 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4664 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4665 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4666 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4667 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4668 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4669 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4670 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4671 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4672 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4673 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4674 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4675 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4676 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4677 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4678 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4679 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4680 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4681 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4682 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4683 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4684 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4685 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4686 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4687 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4688 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4689 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4690 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4691 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4692 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4693 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4694 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4695 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4696 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4697 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4698 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4699 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4700 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4701 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4702 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4703 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4704 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4705 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4706 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4707 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4708 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4709 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4710 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4711 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4712 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4713 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4714 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4715 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4716 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4717 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4718 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4719 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4720 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4721 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4722 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4723 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4724 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4725 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4726 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4727 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4728 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4729 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4730 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4731 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4732 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4733 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4734 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4735 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4736 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4737 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4738 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4739 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4740 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4741 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4742 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4743 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4744 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4745 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4746 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4747 };
4748
4749 static u32 tg3TsoFwRodata[] = {
4750 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4751 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4752 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4753 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4754 0x00000000,
4755 };
4756
4757 static u32 tg3TsoFwData[] = {
4758 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4759 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4760 0x00000000,
4761 };
4762
4763 /* 5705 needs a special version of the TSO firmware. */
4764 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4765 #define TG3_TSO5_FW_RELASE_MINOR 0x2
4766 #define TG3_TSO5_FW_RELEASE_FIX 0x0
4767 #define TG3_TSO5_FW_START_ADDR 0x00010000
4768 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4769 #define TG3_TSO5_FW_TEXT_LEN 0xe90
4770 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4771 #define TG3_TSO5_FW_RODATA_LEN 0x50
4772 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4773 #define TG3_TSO5_FW_DATA_LEN 0x20
4774 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4775 #define TG3_TSO5_FW_SBSS_LEN 0x28
4776 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4777 #define TG3_TSO5_FW_BSS_LEN 0x88
4778
4779 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4780 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4781 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4782 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4783 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4784 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4785 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4786 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4787 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4788 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4789 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4790 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4791 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4792 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4793 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4794 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4795 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4796 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4797 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4798 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4799 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4800 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4801 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4802 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4803 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4804 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4805 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4806 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4807 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4808 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4809 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4810 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4811 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4812 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4813 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4814 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4815 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4816 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4817 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4818 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4819 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4820 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4821 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4822 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4823 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4824 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4825 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4826 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4827 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4828 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4829 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4830 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4831 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4832 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4833 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4834 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4835 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4836 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4837 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4838 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4839 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4840 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4841 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4842 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4843 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4844 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4845 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4846 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4847 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4848 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4849 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4850 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4851 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4852 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4853 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4854 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4855 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4856 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4857 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4858 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4859 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4860 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4861 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4862 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4863 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4864 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4865 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4866 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4867 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4868 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4869 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4870 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4871 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4872 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4873 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4874 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4875 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4876 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4877 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4878 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4879 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4880 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4881 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4882 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4883 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4884 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4885 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4886 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4887 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4888 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4889 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4890 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4891 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4892 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4893 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4894 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4895 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4896 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4897 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4898 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4899 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4900 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4901 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4902 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4903 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4904 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4905 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4906 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4907 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4908 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4909 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4910 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4911 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4912 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4913 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4914 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4915 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4916 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4917 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4918 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4919 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4920 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4921 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4922 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4923 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4924 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4925 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4926 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4927 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4928 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4929 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4930 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4931 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4932 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4933 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4934 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4935 0x00000000, 0x00000000, 0x00000000,
4936 };
4937
4938 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4939 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4940 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4941 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4942 0x00000000, 0x00000000, 0x00000000,
4943 };
4944
4945 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4946 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4947 0x00000000, 0x00000000, 0x00000000,
4948 };
4949
4950 /* tp->lock is held. */
4951 static int tg3_load_tso_firmware(struct tg3 *tp)
4952 {
4953 struct fw_info info;
4954 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4955 int err, i;
4956
4957 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4958 return 0;
4959
4960 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4961 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4962 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4963 info.text_data = &tg3Tso5FwText[0];
4964 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4965 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4966 info.rodata_data = &tg3Tso5FwRodata[0];
4967 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4968 info.data_len = TG3_TSO5_FW_DATA_LEN;
4969 info.data_data = &tg3Tso5FwData[0];
4970 cpu_base = RX_CPU_BASE;
4971 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4972 cpu_scratch_size = (info.text_len +
4973 info.rodata_len +
4974 info.data_len +
4975 TG3_TSO5_FW_SBSS_LEN +
4976 TG3_TSO5_FW_BSS_LEN);
4977 } else {
4978 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4979 info.text_len = TG3_TSO_FW_TEXT_LEN;
4980 info.text_data = &tg3TsoFwText[0];
4981 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4982 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4983 info.rodata_data = &tg3TsoFwRodata[0];
4984 info.data_base = TG3_TSO_FW_DATA_ADDR;
4985 info.data_len = TG3_TSO_FW_DATA_LEN;
4986 info.data_data = &tg3TsoFwData[0];
4987 cpu_base = TX_CPU_BASE;
4988 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
4989 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
4990 }
4991
4992 err = tg3_load_firmware_cpu(tp, cpu_base,
4993 cpu_scratch_base, cpu_scratch_size,
4994 &info);
4995 if (err)
4996 return err;
4997
4998 /* Now startup the cpu. */
4999 tw32(cpu_base + CPU_STATE, 0xffffffff);
5000 tw32_f(cpu_base + CPU_PC, info.text_base);
5001
5002 for (i = 0; i < 5; i++) {
5003 if (tr32(cpu_base + CPU_PC) == info.text_base)
5004 break;
5005 tw32(cpu_base + CPU_STATE, 0xffffffff);
5006 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5007 tw32_f(cpu_base + CPU_PC, info.text_base);
5008 udelay(1000);
5009 }
5010 if (i >= 5) {
5011 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5012 "to set CPU PC, is %08x should be %08x\n",
5013 tp->dev->name, tr32(cpu_base + CPU_PC),
5014 info.text_base);
5015 return -ENODEV;
5016 }
5017 tw32(cpu_base + CPU_STATE, 0xffffffff);
5018 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5019 return 0;
5020 }
5021
5022 #endif /* TG3_TSO_SUPPORT != 0 */
5023
5024 /* tp->lock is held. */
5025 static void __tg3_set_mac_addr(struct tg3 *tp)
5026 {
5027 u32 addr_high, addr_low;
5028 int i;
5029
5030 addr_high = ((tp->dev->dev_addr[0] << 8) |
5031 tp->dev->dev_addr[1]);
5032 addr_low = ((tp->dev->dev_addr[2] << 24) |
5033 (tp->dev->dev_addr[3] << 16) |
5034 (tp->dev->dev_addr[4] << 8) |
5035 (tp->dev->dev_addr[5] << 0));
5036 for (i = 0; i < 4; i++) {
5037 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5038 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5039 }
5040
5041 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5043 for (i = 0; i < 12; i++) {
5044 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5045 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5046 }
5047 }
5048
5049 addr_high = (tp->dev->dev_addr[0] +
5050 tp->dev->dev_addr[1] +
5051 tp->dev->dev_addr[2] +
5052 tp->dev->dev_addr[3] +
5053 tp->dev->dev_addr[4] +
5054 tp->dev->dev_addr[5]) &
5055 TX_BACKOFF_SEED_MASK;
5056 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5057 }
5058
5059 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5060 {
5061 struct tg3 *tp = netdev_priv(dev);
5062 struct sockaddr *addr = p;
5063
5064 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5065
5066 spin_lock_irq(&tp->lock);
5067 __tg3_set_mac_addr(tp);
5068 spin_unlock_irq(&tp->lock);
5069
5070 return 0;
5071 }
5072
5073 /* tp->lock is held. */
5074 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5075 dma_addr_t mapping, u32 maxlen_flags,
5076 u32 nic_addr)
5077 {
5078 tg3_write_mem(tp,
5079 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5080 ((u64) mapping >> 32));
5081 tg3_write_mem(tp,
5082 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5083 ((u64) mapping & 0xffffffff));
5084 tg3_write_mem(tp,
5085 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5086 maxlen_flags);
5087
5088 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5089 tg3_write_mem(tp,
5090 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5091 nic_addr);
5092 }
5093
5094 static void __tg3_set_rx_mode(struct net_device *);
5095 static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5096 {
5097 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5098 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5099 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5100 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5101 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5102 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5103 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5104 }
5105 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5106 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5107 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5108 u32 val = ec->stats_block_coalesce_usecs;
5109
5110 if (!netif_carrier_ok(tp->dev))
5111 val = 0;
5112
5113 tw32(HOSTCC_STAT_COAL_TICKS, val);
5114 }
5115 }
5116
5117 /* tp->lock is held. */
5118 static int tg3_reset_hw(struct tg3 *tp)
5119 {
5120 u32 val, rdmac_mode;
5121 int i, err, limit;
5122
5123 tg3_disable_ints(tp);
5124
5125 tg3_stop_fw(tp);
5126
5127 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5128
5129 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5130 tg3_abort_hw(tp, 1);
5131 }
5132
5133 err = tg3_chip_reset(tp);
5134 if (err)
5135 return err;
5136
5137 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5138
5139 /* This works around an issue with Athlon chipsets on
5140 * B3 tigon3 silicon. This bit has no effect on any
5141 * other revision. But do not set this on PCI Express
5142 * chips.
5143 */
5144 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5145 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5146 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5147
5148 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5149 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5150 val = tr32(TG3PCI_PCISTATE);
5151 val |= PCISTATE_RETRY_SAME_DMA;
5152 tw32(TG3PCI_PCISTATE, val);
5153 }
5154
5155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5156 /* Enable some hw fixes. */
5157 val = tr32(TG3PCI_MSI_DATA);
5158 val |= (1 << 26) | (1 << 28) | (1 << 29);
5159 tw32(TG3PCI_MSI_DATA, val);
5160 }
5161
5162 /* Descriptor ring init may make accesses to the
5163 * NIC SRAM area to setup the TX descriptors, so we
5164 * can only do this after the hardware has been
5165 * successfully reset.
5166 */
5167 tg3_init_rings(tp);
5168
5169 /* This value is determined during the probe time DMA
5170 * engine test, tg3_test_dma.
5171 */
5172 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5173
5174 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5175 GRC_MODE_4X_NIC_SEND_RINGS |
5176 GRC_MODE_NO_TX_PHDR_CSUM |
5177 GRC_MODE_NO_RX_PHDR_CSUM);
5178 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5179 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5180 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5181 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5182 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5183
5184 tw32(GRC_MODE,
5185 tp->grc_mode |
5186 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5187
5188 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5189 val = tr32(GRC_MISC_CFG);
5190 val &= ~0xff;
5191 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5192 tw32(GRC_MISC_CFG, val);
5193
5194 /* Initialize MBUF/DESC pool. */
5195 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5196 /* Do nothing. */
5197 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5198 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5200 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5201 else
5202 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5203 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5204 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5205 }
5206 #if TG3_TSO_SUPPORT != 0
5207 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5208 int fw_len;
5209
5210 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5211 TG3_TSO5_FW_RODATA_LEN +
5212 TG3_TSO5_FW_DATA_LEN +
5213 TG3_TSO5_FW_SBSS_LEN +
5214 TG3_TSO5_FW_BSS_LEN);
5215 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5216 tw32(BUFMGR_MB_POOL_ADDR,
5217 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5218 tw32(BUFMGR_MB_POOL_SIZE,
5219 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5220 }
5221 #endif
5222
5223 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5224 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5225 tp->bufmgr_config.mbuf_read_dma_low_water);
5226 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5227 tp->bufmgr_config.mbuf_mac_rx_low_water);
5228 tw32(BUFMGR_MB_HIGH_WATER,
5229 tp->bufmgr_config.mbuf_high_water);
5230 } else {
5231 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5232 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5233 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5234 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5235 tw32(BUFMGR_MB_HIGH_WATER,
5236 tp->bufmgr_config.mbuf_high_water_jumbo);
5237 }
5238 tw32(BUFMGR_DMA_LOW_WATER,
5239 tp->bufmgr_config.dma_low_water);
5240 tw32(BUFMGR_DMA_HIGH_WATER,
5241 tp->bufmgr_config.dma_high_water);
5242
5243 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5244 for (i = 0; i < 2000; i++) {
5245 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5246 break;
5247 udelay(10);
5248 }
5249 if (i >= 2000) {
5250 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5251 tp->dev->name);
5252 return -ENODEV;
5253 }
5254
5255 /* Setup replenish threshold. */
5256 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5257
5258 /* Initialize TG3_BDINFO's at:
5259 * RCVDBDI_STD_BD: standard eth size rx ring
5260 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5261 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5262 *
5263 * like so:
5264 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5265 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5266 * ring attribute flags
5267 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5268 *
5269 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5270 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5271 *
5272 * The size of each ring is fixed in the firmware, but the location is
5273 * configurable.
5274 */
5275 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5276 ((u64) tp->rx_std_mapping >> 32));
5277 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5278 ((u64) tp->rx_std_mapping & 0xffffffff));
5279 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5280 NIC_SRAM_RX_BUFFER_DESC);
5281
5282 /* Don't even try to program the JUMBO/MINI buffer descriptor
5283 * configs on 5705.
5284 */
5285 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5286 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5287 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5288 } else {
5289 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5290 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5291
5292 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5293 BDINFO_FLAGS_DISABLED);
5294
5295 /* Setup replenish threshold. */
5296 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5297
5298 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5299 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5300 ((u64) tp->rx_jumbo_mapping >> 32));
5301 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5302 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5303 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5304 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5305 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5306 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5307 } else {
5308 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5309 BDINFO_FLAGS_DISABLED);
5310 }
5311
5312 }
5313
5314 /* There is only one send ring on 5705/5750, no need to explicitly
5315 * disable the others.
5316 */
5317 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5318 /* Clear out send RCB ring in SRAM. */
5319 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5320 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5321 BDINFO_FLAGS_DISABLED);
5322 }
5323
5324 tp->tx_prod = 0;
5325 tp->tx_cons = 0;
5326 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5327 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5328
5329 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5330 tp->tx_desc_mapping,
5331 (TG3_TX_RING_SIZE <<
5332 BDINFO_FLAGS_MAXLEN_SHIFT),
5333 NIC_SRAM_TX_BUFFER_DESC);
5334
5335 /* There is only one receive return ring on 5705/5750, no need
5336 * to explicitly disable the others.
5337 */
5338 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5339 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5340 i += TG3_BDINFO_SIZE) {
5341 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5342 BDINFO_FLAGS_DISABLED);
5343 }
5344 }
5345
5346 tp->rx_rcb_ptr = 0;
5347 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5348
5349 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5350 tp->rx_rcb_mapping,
5351 (TG3_RX_RCB_RING_SIZE(tp) <<
5352 BDINFO_FLAGS_MAXLEN_SHIFT),
5353 0);
5354
5355 tp->rx_std_ptr = tp->rx_pending;
5356 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5357 tp->rx_std_ptr);
5358
5359 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5360 tp->rx_jumbo_pending : 0;
5361 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5362 tp->rx_jumbo_ptr);
5363
5364 /* Initialize MAC address and backoff seed. */
5365 __tg3_set_mac_addr(tp);
5366
5367 /* MTU + ethernet header + FCS + optional VLAN tag */
5368 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5369
5370 /* The slot time is changed by tg3_setup_phy if we
5371 * run at gigabit with half duplex.
5372 */
5373 tw32(MAC_TX_LENGTHS,
5374 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5375 (6 << TX_LENGTHS_IPG_SHIFT) |
5376 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5377
5378 /* Receive rules. */
5379 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5380 tw32(RCVLPC_CONFIG, 0x0181);
5381
5382 /* Calculate RDMAC_MODE setting early, we need it to determine
5383 * the RCVLPC_STATE_ENABLE mask.
5384 */
5385 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5386 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5387 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5388 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5389 RDMAC_MODE_LNGREAD_ENAB);
5390 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5391 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5392
5393 /* If statement applies to 5705 and 5750 PCI devices only */
5394 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5395 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5396 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5397 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5398 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5399 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5400 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5401 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5402 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5403 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5404 }
5405 }
5406
5407 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5408 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5409
5410 #if TG3_TSO_SUPPORT != 0
5411 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5412 rdmac_mode |= (1 << 27);
5413 #endif
5414
5415 /* Receive/send statistics. */
5416 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5417 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5418 val = tr32(RCVLPC_STATS_ENABLE);
5419 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5420 tw32(RCVLPC_STATS_ENABLE, val);
5421 } else {
5422 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5423 }
5424 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5425 tw32(SNDDATAI_STATSENAB, 0xffffff);
5426 tw32(SNDDATAI_STATSCTRL,
5427 (SNDDATAI_SCTRL_ENABLE |
5428 SNDDATAI_SCTRL_FASTUPD));
5429
5430 /* Setup host coalescing engine. */
5431 tw32(HOSTCC_MODE, 0);
5432 for (i = 0; i < 2000; i++) {
5433 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5434 break;
5435 udelay(10);
5436 }
5437
5438 tg3_set_coalesce(tp, &tp->coal);
5439
5440 /* set status block DMA address */
5441 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5442 ((u64) tp->status_mapping >> 32));
5443 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5444 ((u64) tp->status_mapping & 0xffffffff));
5445
5446 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5447 /* Status/statistics block address. See tg3_timer,
5448 * the tg3_periodic_fetch_stats call there, and
5449 * tg3_get_stats to see how this works for 5705/5750 chips.
5450 */
5451 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5452 ((u64) tp->stats_mapping >> 32));
5453 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5454 ((u64) tp->stats_mapping & 0xffffffff));
5455 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5456 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5457 }
5458
5459 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5460
5461 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5462 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5463 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5464 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5465
5466 /* Clear statistics/status block in chip, and status block in ram. */
5467 for (i = NIC_SRAM_STATS_BLK;
5468 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5469 i += sizeof(u32)) {
5470 tg3_write_mem(tp, i, 0);
5471 udelay(40);
5472 }
5473 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5474
5475 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5476 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5477 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5478 udelay(40);
5479
5480 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5481 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5482 * register to preserve the GPIO settings for LOMs. The GPIOs,
5483 * whether used as inputs or outputs, are set by boot code after
5484 * reset.
5485 */
5486 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5487 u32 gpio_mask;
5488
5489 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5490 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5491
5492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5493 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5494 GRC_LCLCTRL_GPIO_OUTPUT3;
5495
5496 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5497
5498 /* GPIO1 must be driven high for eeprom write protect */
5499 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5500 GRC_LCLCTRL_GPIO_OUTPUT1);
5501 }
5502 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5503 udelay(100);
5504
5505 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5506 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5507 tp->last_tag = 0;
5508
5509 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5510 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5511 udelay(40);
5512 }
5513
5514 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5515 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5516 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5517 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5518 WDMAC_MODE_LNGREAD_ENAB);
5519
5520 /* If statement applies to 5705 and 5750 PCI devices only */
5521 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5522 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5524 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5525 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5526 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5527 /* nothing */
5528 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5529 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5530 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5531 val |= WDMAC_MODE_RX_ACCEL;
5532 }
5533 }
5534
5535 tw32_f(WDMAC_MODE, val);
5536 udelay(40);
5537
5538 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5539 val = tr32(TG3PCI_X_CAPS);
5540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5541 val &= ~PCIX_CAPS_BURST_MASK;
5542 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5544 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5545 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5546 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5547 val |= (tp->split_mode_max_reqs <<
5548 PCIX_CAPS_SPLIT_SHIFT);
5549 }
5550 tw32(TG3PCI_X_CAPS, val);
5551 }
5552
5553 tw32_f(RDMAC_MODE, rdmac_mode);
5554 udelay(40);
5555
5556 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5557 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5558 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5559 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5560 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5561 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5562 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5563 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5564 #if TG3_TSO_SUPPORT != 0
5565 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5566 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5567 #endif
5568 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5569 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5570
5571 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5572 err = tg3_load_5701_a0_firmware_fix(tp);
5573 if (err)
5574 return err;
5575 }
5576
5577 #if TG3_TSO_SUPPORT != 0
5578 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5579 err = tg3_load_tso_firmware(tp);
5580 if (err)
5581 return err;
5582 }
5583 #endif
5584
5585 tp->tx_mode = TX_MODE_ENABLE;
5586 tw32_f(MAC_TX_MODE, tp->tx_mode);
5587 udelay(100);
5588
5589 tp->rx_mode = RX_MODE_ENABLE;
5590 tw32_f(MAC_RX_MODE, tp->rx_mode);
5591 udelay(10);
5592
5593 if (tp->link_config.phy_is_low_power) {
5594 tp->link_config.phy_is_low_power = 0;
5595 tp->link_config.speed = tp->link_config.orig_speed;
5596 tp->link_config.duplex = tp->link_config.orig_duplex;
5597 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5598 }
5599
5600 tp->mi_mode = MAC_MI_MODE_BASE;
5601 tw32_f(MAC_MI_MODE, tp->mi_mode);
5602 udelay(80);
5603
5604 tw32(MAC_LED_CTRL, tp->led_ctrl);
5605
5606 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5607 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5608 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5609 udelay(10);
5610 }
5611 tw32_f(MAC_RX_MODE, tp->rx_mode);
5612 udelay(10);
5613
5614 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5616 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5617 /* Set drive transmission level to 1.2V */
5618 /* only if the signal pre-emphasis bit is not set */
5619 val = tr32(MAC_SERDES_CFG);
5620 val &= 0xfffff000;
5621 val |= 0x880;
5622 tw32(MAC_SERDES_CFG, val);
5623 }
5624 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5625 tw32(MAC_SERDES_CFG, 0x616000);
5626 }
5627
5628 /* Prevent chip from dropping frames when flow control
5629 * is enabled.
5630 */
5631 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5632
5633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5634 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5635 /* Use hardware link auto-negotiation */
5636 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5637 }
5638
5639 err = tg3_setup_phy(tp, 1);
5640 if (err)
5641 return err;
5642
5643 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5644 u32 tmp;
5645
5646 /* Clear CRC stats. */
5647 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5648 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5649 tg3_readphy(tp, 0x14, &tmp);
5650 }
5651 }
5652
5653 __tg3_set_rx_mode(tp->dev);
5654
5655 /* Initialize receive rules. */
5656 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5657 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5658 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5659 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5660
5661 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5662 limit = 8;
5663 else
5664 limit = 16;
5665 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5666 limit -= 4;
5667 switch (limit) {
5668 case 16:
5669 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5670 case 15:
5671 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5672 case 14:
5673 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5674 case 13:
5675 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5676 case 12:
5677 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5678 case 11:
5679 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5680 case 10:
5681 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5682 case 9:
5683 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5684 case 8:
5685 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5686 case 7:
5687 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5688 case 6:
5689 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5690 case 5:
5691 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5692 case 4:
5693 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5694 case 3:
5695 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5696 case 2:
5697 case 1:
5698
5699 default:
5700 break;
5701 };
5702
5703 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5704
5705 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5706 tg3_enable_ints(tp);
5707
5708 return 0;
5709 }
5710
5711 /* Called at device open time to get the chip ready for
5712 * packet processing. Invoked with tp->lock held.
5713 */
5714 static int tg3_init_hw(struct tg3 *tp)
5715 {
5716 int err;
5717
5718 /* Force the chip into D0. */
5719 err = tg3_set_power_state(tp, 0);
5720 if (err)
5721 goto out;
5722
5723 tg3_switch_clocks(tp);
5724
5725 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5726
5727 err = tg3_reset_hw(tp);
5728
5729 out:
5730 return err;
5731 }
5732
5733 #define TG3_STAT_ADD32(PSTAT, REG) \
5734 do { u32 __val = tr32(REG); \
5735 (PSTAT)->low += __val; \
5736 if ((PSTAT)->low < __val) \
5737 (PSTAT)->high += 1; \
5738 } while (0)
5739
5740 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5741 {
5742 struct tg3_hw_stats *sp = tp->hw_stats;
5743
5744 if (!netif_carrier_ok(tp->dev))
5745 return;
5746
5747 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5748 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5749 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5750 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5751 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5752 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5753 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5754 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5755 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5756 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5757 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5758 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5759 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5760
5761 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5762 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5763 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5764 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5765 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5766 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5767 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5768 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5769 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5770 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5771 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5772 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5773 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5774 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5775 }
5776
5777 static void tg3_timer(unsigned long __opaque)
5778 {
5779 struct tg3 *tp = (struct tg3 *) __opaque;
5780 unsigned long flags;
5781
5782 spin_lock_irqsave(&tp->lock, flags);
5783 spin_lock(&tp->tx_lock);
5784
5785 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5786 /* All of this garbage is because when using non-tagged
5787 * IRQ status the mailbox/status_block protocol the chip
5788 * uses with the cpu is race prone.
5789 */
5790 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5791 tw32(GRC_LOCAL_CTRL,
5792 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5793 } else {
5794 tw32(HOSTCC_MODE, tp->coalesce_mode |
5795 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5796 }
5797
5798 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5799 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5800 spin_unlock(&tp->tx_lock);
5801 spin_unlock_irqrestore(&tp->lock, flags);
5802 schedule_work(&tp->reset_task);
5803 return;
5804 }
5805 }
5806
5807 /* This part only runs once per second. */
5808 if (!--tp->timer_counter) {
5809 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5810 tg3_periodic_fetch_stats(tp);
5811
5812 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5813 u32 mac_stat;
5814 int phy_event;
5815
5816 mac_stat = tr32(MAC_STATUS);
5817
5818 phy_event = 0;
5819 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5820 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5821 phy_event = 1;
5822 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5823 phy_event = 1;
5824
5825 if (phy_event)
5826 tg3_setup_phy(tp, 0);
5827 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5828 u32 mac_stat = tr32(MAC_STATUS);
5829 int need_setup = 0;
5830
5831 if (netif_carrier_ok(tp->dev) &&
5832 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5833 need_setup = 1;
5834 }
5835 if (! netif_carrier_ok(tp->dev) &&
5836 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5837 MAC_STATUS_SIGNAL_DET))) {
5838 need_setup = 1;
5839 }
5840 if (need_setup) {
5841 tw32_f(MAC_MODE,
5842 (tp->mac_mode &
5843 ~MAC_MODE_PORT_MODE_MASK));
5844 udelay(40);
5845 tw32_f(MAC_MODE, tp->mac_mode);
5846 udelay(40);
5847 tg3_setup_phy(tp, 0);
5848 }
5849 }
5850
5851 tp->timer_counter = tp->timer_multiplier;
5852 }
5853
5854 /* Heartbeat is only sent once every 120 seconds. */
5855 if (!--tp->asf_counter) {
5856 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5857 u32 val;
5858
5859 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5860 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5861 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5862 val = tr32(GRC_RX_CPU_EVENT);
5863 val |= (1 << 14);
5864 tw32(GRC_RX_CPU_EVENT, val);
5865 }
5866 tp->asf_counter = tp->asf_multiplier;
5867 }
5868
5869 spin_unlock(&tp->tx_lock);
5870 spin_unlock_irqrestore(&tp->lock, flags);
5871
5872 tp->timer.expires = jiffies + tp->timer_offset;
5873 add_timer(&tp->timer);
5874 }
5875
5876 static int tg3_test_interrupt(struct tg3 *tp)
5877 {
5878 struct net_device *dev = tp->dev;
5879 int err, i;
5880 u32 int_mbox = 0;
5881
5882 tg3_disable_ints(tp);
5883
5884 free_irq(tp->pdev->irq, dev);
5885
5886 err = request_irq(tp->pdev->irq, tg3_test_isr,
5887 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5888 if (err)
5889 return err;
5890
5891 tg3_enable_ints(tp);
5892
5893 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5894 HOSTCC_MODE_NOW);
5895
5896 for (i = 0; i < 5; i++) {
5897 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5898 if (int_mbox != 0)
5899 break;
5900 msleep(10);
5901 }
5902
5903 tg3_disable_ints(tp);
5904
5905 free_irq(tp->pdev->irq, dev);
5906
5907 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5908 err = request_irq(tp->pdev->irq, tg3_msi,
5909 SA_SAMPLE_RANDOM, dev->name, dev);
5910 else {
5911 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5912 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5913 fn = tg3_interrupt_tagged;
5914 err = request_irq(tp->pdev->irq, fn,
5915 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5916 }
5917
5918 if (err)
5919 return err;
5920
5921 if (int_mbox != 0)
5922 return 0;
5923
5924 return -EIO;
5925 }
5926
5927 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5928 * successfully restored
5929 */
5930 static int tg3_test_msi(struct tg3 *tp)
5931 {
5932 struct net_device *dev = tp->dev;
5933 int err;
5934 u16 pci_cmd;
5935
5936 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5937 return 0;
5938
5939 /* Turn off SERR reporting in case MSI terminates with Master
5940 * Abort.
5941 */
5942 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5943 pci_write_config_word(tp->pdev, PCI_COMMAND,
5944 pci_cmd & ~PCI_COMMAND_SERR);
5945
5946 err = tg3_test_interrupt(tp);
5947
5948 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5949
5950 if (!err)
5951 return 0;
5952
5953 /* other failures */
5954 if (err != -EIO)
5955 return err;
5956
5957 /* MSI test failed, go back to INTx mode */
5958 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5959 "switching to INTx mode. Please report this failure to "
5960 "the PCI maintainer and include system chipset information.\n",
5961 tp->dev->name);
5962
5963 free_irq(tp->pdev->irq, dev);
5964 pci_disable_msi(tp->pdev);
5965
5966 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5967
5968 {
5969 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5970 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5971 fn = tg3_interrupt_tagged;
5972
5973 err = request_irq(tp->pdev->irq, fn,
5974 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5975 }
5976 if (err)
5977 return err;
5978
5979 /* Need to reset the chip because the MSI cycle may have terminated
5980 * with Master Abort.
5981 */
5982 spin_lock_irq(&tp->lock);
5983 spin_lock(&tp->tx_lock);
5984
5985 tg3_halt(tp, 1);
5986 err = tg3_init_hw(tp);
5987
5988 spin_unlock(&tp->tx_lock);
5989 spin_unlock_irq(&tp->lock);
5990
5991 if (err)
5992 free_irq(tp->pdev->irq, dev);
5993
5994 return err;
5995 }
5996
5997 static int tg3_open(struct net_device *dev)
5998 {
5999 struct tg3 *tp = netdev_priv(dev);
6000 int err;
6001
6002 spin_lock_irq(&tp->lock);
6003 spin_lock(&tp->tx_lock);
6004
6005 tg3_disable_ints(tp);
6006 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6007
6008 spin_unlock(&tp->tx_lock);
6009 spin_unlock_irq(&tp->lock);
6010
6011 /* The placement of this call is tied
6012 * to the setup and use of Host TX descriptors.
6013 */
6014 err = tg3_alloc_consistent(tp);
6015 if (err)
6016 return err;
6017
6018 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6019 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6020 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6021 /* All MSI supporting chips should support tagged
6022 * status. Assert that this is the case.
6023 */
6024 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6025 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6026 "Not using MSI.\n", tp->dev->name);
6027 } else if (pci_enable_msi(tp->pdev) == 0) {
6028 u32 msi_mode;
6029
6030 msi_mode = tr32(MSGINT_MODE);
6031 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6032 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6033 }
6034 }
6035 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6036 err = request_irq(tp->pdev->irq, tg3_msi,
6037 SA_SAMPLE_RANDOM, dev->name, dev);
6038 else {
6039 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6040 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6041 fn = tg3_interrupt_tagged;
6042
6043 err = request_irq(tp->pdev->irq, fn,
6044 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6045 }
6046
6047 if (err) {
6048 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6049 pci_disable_msi(tp->pdev);
6050 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6051 }
6052 tg3_free_consistent(tp);
6053 return err;
6054 }
6055
6056 spin_lock_irq(&tp->lock);
6057 spin_lock(&tp->tx_lock);
6058
6059 err = tg3_init_hw(tp);
6060 if (err) {
6061 tg3_halt(tp, 1);
6062 tg3_free_rings(tp);
6063 } else {
6064 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6065 tp->timer_offset = HZ;
6066 else
6067 tp->timer_offset = HZ / 10;
6068
6069 BUG_ON(tp->timer_offset > HZ);
6070 tp->timer_counter = tp->timer_multiplier =
6071 (HZ / tp->timer_offset);
6072 tp->asf_counter = tp->asf_multiplier =
6073 ((HZ / tp->timer_offset) * 120);
6074
6075 init_timer(&tp->timer);
6076 tp->timer.expires = jiffies + tp->timer_offset;
6077 tp->timer.data = (unsigned long) tp;
6078 tp->timer.function = tg3_timer;
6079 }
6080
6081 spin_unlock(&tp->tx_lock);
6082 spin_unlock_irq(&tp->lock);
6083
6084 if (err) {
6085 free_irq(tp->pdev->irq, dev);
6086 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6087 pci_disable_msi(tp->pdev);
6088 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6089 }
6090 tg3_free_consistent(tp);
6091 return err;
6092 }
6093
6094 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6095 err = tg3_test_msi(tp);
6096
6097 if (err) {
6098 spin_lock_irq(&tp->lock);
6099 spin_lock(&tp->tx_lock);
6100
6101 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102 pci_disable_msi(tp->pdev);
6103 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6104 }
6105 tg3_halt(tp, 1);
6106 tg3_free_rings(tp);
6107 tg3_free_consistent(tp);
6108
6109 spin_unlock(&tp->tx_lock);
6110 spin_unlock_irq(&tp->lock);
6111
6112 return err;
6113 }
6114 }
6115
6116 spin_lock_irq(&tp->lock);
6117 spin_lock(&tp->tx_lock);
6118
6119 add_timer(&tp->timer);
6120 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6121 tg3_enable_ints(tp);
6122
6123 spin_unlock(&tp->tx_lock);
6124 spin_unlock_irq(&tp->lock);
6125
6126 netif_start_queue(dev);
6127
6128 return 0;
6129 }
6130
6131 #if 0
6132 /*static*/ void tg3_dump_state(struct tg3 *tp)
6133 {
6134 u32 val32, val32_2, val32_3, val32_4, val32_5;
6135 u16 val16;
6136 int i;
6137
6138 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6139 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6140 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6141 val16, val32);
6142
6143 /* MAC block */
6144 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6145 tr32(MAC_MODE), tr32(MAC_STATUS));
6146 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6147 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6148 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6149 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6150 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6151 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6152
6153 /* Send data initiator control block */
6154 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6155 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6156 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6157 tr32(SNDDATAI_STATSCTRL));
6158
6159 /* Send data completion control block */
6160 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6161
6162 /* Send BD ring selector block */
6163 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6164 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6165
6166 /* Send BD initiator control block */
6167 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6168 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6169
6170 /* Send BD completion control block */
6171 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6172
6173 /* Receive list placement control block */
6174 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6175 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6176 printk(" RCVLPC_STATSCTRL[%08x]\n",
6177 tr32(RCVLPC_STATSCTRL));
6178
6179 /* Receive data and receive BD initiator control block */
6180 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6181 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6182
6183 /* Receive data completion control block */
6184 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6185 tr32(RCVDCC_MODE));
6186
6187 /* Receive BD initiator control block */
6188 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6189 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6190
6191 /* Receive BD completion control block */
6192 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6193 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6194
6195 /* Receive list selector control block */
6196 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6197 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6198
6199 /* Mbuf cluster free block */
6200 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6201 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6202
6203 /* Host coalescing control block */
6204 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6205 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6206 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6207 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6208 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6209 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6210 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6211 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6212 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6213 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6214 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6215 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6216
6217 /* Memory arbiter control block */
6218 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6219 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6220
6221 /* Buffer manager control block */
6222 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6223 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6224 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6225 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6226 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6227 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6228 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6229 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6230
6231 /* Read DMA control block */
6232 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6233 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6234
6235 /* Write DMA control block */
6236 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6237 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6238
6239 /* DMA completion block */
6240 printk("DEBUG: DMAC_MODE[%08x]\n",
6241 tr32(DMAC_MODE));
6242
6243 /* GRC block */
6244 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6245 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6246 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6247 tr32(GRC_LOCAL_CTRL));
6248
6249 /* TG3_BDINFOs */
6250 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6251 tr32(RCVDBDI_JUMBO_BD + 0x0),
6252 tr32(RCVDBDI_JUMBO_BD + 0x4),
6253 tr32(RCVDBDI_JUMBO_BD + 0x8),
6254 tr32(RCVDBDI_JUMBO_BD + 0xc));
6255 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6256 tr32(RCVDBDI_STD_BD + 0x0),
6257 tr32(RCVDBDI_STD_BD + 0x4),
6258 tr32(RCVDBDI_STD_BD + 0x8),
6259 tr32(RCVDBDI_STD_BD + 0xc));
6260 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6261 tr32(RCVDBDI_MINI_BD + 0x0),
6262 tr32(RCVDBDI_MINI_BD + 0x4),
6263 tr32(RCVDBDI_MINI_BD + 0x8),
6264 tr32(RCVDBDI_MINI_BD + 0xc));
6265
6266 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6267 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6268 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6269 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6270 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6271 val32, val32_2, val32_3, val32_4);
6272
6273 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6274 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6275 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6276 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6277 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6278 val32, val32_2, val32_3, val32_4);
6279
6280 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6281 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6282 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6283 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6284 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6285 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6286 val32, val32_2, val32_3, val32_4, val32_5);
6287
6288 /* SW status block */
6289 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6290 tp->hw_status->status,
6291 tp->hw_status->status_tag,
6292 tp->hw_status->rx_jumbo_consumer,
6293 tp->hw_status->rx_consumer,
6294 tp->hw_status->rx_mini_consumer,
6295 tp->hw_status->idx[0].rx_producer,
6296 tp->hw_status->idx[0].tx_consumer);
6297
6298 /* SW statistics block */
6299 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6300 ((u32 *)tp->hw_stats)[0],
6301 ((u32 *)tp->hw_stats)[1],
6302 ((u32 *)tp->hw_stats)[2],
6303 ((u32 *)tp->hw_stats)[3]);
6304
6305 /* Mailboxes */
6306 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6307 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6308 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6309 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6310 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6311
6312 /* NIC side send descriptors. */
6313 for (i = 0; i < 6; i++) {
6314 unsigned long txd;
6315
6316 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6317 + (i * sizeof(struct tg3_tx_buffer_desc));
6318 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6319 i,
6320 readl(txd + 0x0), readl(txd + 0x4),
6321 readl(txd + 0x8), readl(txd + 0xc));
6322 }
6323
6324 /* NIC side RX descriptors. */
6325 for (i = 0; i < 6; i++) {
6326 unsigned long rxd;
6327
6328 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6329 + (i * sizeof(struct tg3_rx_buffer_desc));
6330 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6331 i,
6332 readl(rxd + 0x0), readl(rxd + 0x4),
6333 readl(rxd + 0x8), readl(rxd + 0xc));
6334 rxd += (4 * sizeof(u32));
6335 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6336 i,
6337 readl(rxd + 0x0), readl(rxd + 0x4),
6338 readl(rxd + 0x8), readl(rxd + 0xc));
6339 }
6340
6341 for (i = 0; i < 6; i++) {
6342 unsigned long rxd;
6343
6344 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6345 + (i * sizeof(struct tg3_rx_buffer_desc));
6346 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6347 i,
6348 readl(rxd + 0x0), readl(rxd + 0x4),
6349 readl(rxd + 0x8), readl(rxd + 0xc));
6350 rxd += (4 * sizeof(u32));
6351 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6352 i,
6353 readl(rxd + 0x0), readl(rxd + 0x4),
6354 readl(rxd + 0x8), readl(rxd + 0xc));
6355 }
6356 }
6357 #endif
6358
6359 static struct net_device_stats *tg3_get_stats(struct net_device *);
6360 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6361
6362 static int tg3_close(struct net_device *dev)
6363 {
6364 struct tg3 *tp = netdev_priv(dev);
6365
6366 netif_stop_queue(dev);
6367
6368 del_timer_sync(&tp->timer);
6369
6370 spin_lock_irq(&tp->lock);
6371 spin_lock(&tp->tx_lock);
6372 #if 0
6373 tg3_dump_state(tp);
6374 #endif
6375
6376 tg3_disable_ints(tp);
6377
6378 tg3_halt(tp, 1);
6379 tg3_free_rings(tp);
6380 tp->tg3_flags &=
6381 ~(TG3_FLAG_INIT_COMPLETE |
6382 TG3_FLAG_GOT_SERDES_FLOWCTL);
6383 netif_carrier_off(tp->dev);
6384
6385 spin_unlock(&tp->tx_lock);
6386 spin_unlock_irq(&tp->lock);
6387
6388 free_irq(tp->pdev->irq, dev);
6389 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6390 pci_disable_msi(tp->pdev);
6391 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6392 }
6393
6394 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6395 sizeof(tp->net_stats_prev));
6396 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6397 sizeof(tp->estats_prev));
6398
6399 tg3_free_consistent(tp);
6400
6401 return 0;
6402 }
6403
6404 static inline unsigned long get_stat64(tg3_stat64_t *val)
6405 {
6406 unsigned long ret;
6407
6408 #if (BITS_PER_LONG == 32)
6409 ret = val->low;
6410 #else
6411 ret = ((u64)val->high << 32) | ((u64)val->low);
6412 #endif
6413 return ret;
6414 }
6415
6416 static unsigned long calc_crc_errors(struct tg3 *tp)
6417 {
6418 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6419
6420 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6421 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6423 unsigned long flags;
6424 u32 val;
6425
6426 spin_lock_irqsave(&tp->lock, flags);
6427 if (!tg3_readphy(tp, 0x1e, &val)) {
6428 tg3_writephy(tp, 0x1e, val | 0x8000);
6429 tg3_readphy(tp, 0x14, &val);
6430 } else
6431 val = 0;
6432 spin_unlock_irqrestore(&tp->lock, flags);
6433
6434 tp->phy_crc_errors += val;
6435
6436 return tp->phy_crc_errors;
6437 }
6438
6439 return get_stat64(&hw_stats->rx_fcs_errors);
6440 }
6441
6442 #define ESTAT_ADD(member) \
6443 estats->member = old_estats->member + \
6444 get_stat64(&hw_stats->member)
6445
6446 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6447 {
6448 struct tg3_ethtool_stats *estats = &tp->estats;
6449 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6450 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6451
6452 if (!hw_stats)
6453 return old_estats;
6454
6455 ESTAT_ADD(rx_octets);
6456 ESTAT_ADD(rx_fragments);
6457 ESTAT_ADD(rx_ucast_packets);
6458 ESTAT_ADD(rx_mcast_packets);
6459 ESTAT_ADD(rx_bcast_packets);
6460 ESTAT_ADD(rx_fcs_errors);
6461 ESTAT_ADD(rx_align_errors);
6462 ESTAT_ADD(rx_xon_pause_rcvd);
6463 ESTAT_ADD(rx_xoff_pause_rcvd);
6464 ESTAT_ADD(rx_mac_ctrl_rcvd);
6465 ESTAT_ADD(rx_xoff_entered);
6466 ESTAT_ADD(rx_frame_too_long_errors);
6467 ESTAT_ADD(rx_jabbers);
6468 ESTAT_ADD(rx_undersize_packets);
6469 ESTAT_ADD(rx_in_length_errors);
6470 ESTAT_ADD(rx_out_length_errors);
6471 ESTAT_ADD(rx_64_or_less_octet_packets);
6472 ESTAT_ADD(rx_65_to_127_octet_packets);
6473 ESTAT_ADD(rx_128_to_255_octet_packets);
6474 ESTAT_ADD(rx_256_to_511_octet_packets);
6475 ESTAT_ADD(rx_512_to_1023_octet_packets);
6476 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6477 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6478 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6479 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6480 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6481
6482 ESTAT_ADD(tx_octets);
6483 ESTAT_ADD(tx_collisions);
6484 ESTAT_ADD(tx_xon_sent);
6485 ESTAT_ADD(tx_xoff_sent);
6486 ESTAT_ADD(tx_flow_control);
6487 ESTAT_ADD(tx_mac_errors);
6488 ESTAT_ADD(tx_single_collisions);
6489 ESTAT_ADD(tx_mult_collisions);
6490 ESTAT_ADD(tx_deferred);
6491 ESTAT_ADD(tx_excessive_collisions);
6492 ESTAT_ADD(tx_late_collisions);
6493 ESTAT_ADD(tx_collide_2times);
6494 ESTAT_ADD(tx_collide_3times);
6495 ESTAT_ADD(tx_collide_4times);
6496 ESTAT_ADD(tx_collide_5times);
6497 ESTAT_ADD(tx_collide_6times);
6498 ESTAT_ADD(tx_collide_7times);
6499 ESTAT_ADD(tx_collide_8times);
6500 ESTAT_ADD(tx_collide_9times);
6501 ESTAT_ADD(tx_collide_10times);
6502 ESTAT_ADD(tx_collide_11times);
6503 ESTAT_ADD(tx_collide_12times);
6504 ESTAT_ADD(tx_collide_13times);
6505 ESTAT_ADD(tx_collide_14times);
6506 ESTAT_ADD(tx_collide_15times);
6507 ESTAT_ADD(tx_ucast_packets);
6508 ESTAT_ADD(tx_mcast_packets);
6509 ESTAT_ADD(tx_bcast_packets);
6510 ESTAT_ADD(tx_carrier_sense_errors);
6511 ESTAT_ADD(tx_discards);
6512 ESTAT_ADD(tx_errors);
6513
6514 ESTAT_ADD(dma_writeq_full);
6515 ESTAT_ADD(dma_write_prioq_full);
6516 ESTAT_ADD(rxbds_empty);
6517 ESTAT_ADD(rx_discards);
6518 ESTAT_ADD(rx_errors);
6519 ESTAT_ADD(rx_threshold_hit);
6520
6521 ESTAT_ADD(dma_readq_full);
6522 ESTAT_ADD(dma_read_prioq_full);
6523 ESTAT_ADD(tx_comp_queue_full);
6524
6525 ESTAT_ADD(ring_set_send_prod_index);
6526 ESTAT_ADD(ring_status_update);
6527 ESTAT_ADD(nic_irqs);
6528 ESTAT_ADD(nic_avoided_irqs);
6529 ESTAT_ADD(nic_tx_threshold_hit);
6530
6531 return estats;
6532 }
6533
6534 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6535 {
6536 struct tg3 *tp = netdev_priv(dev);
6537 struct net_device_stats *stats = &tp->net_stats;
6538 struct net_device_stats *old_stats = &tp->net_stats_prev;
6539 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6540
6541 if (!hw_stats)
6542 return old_stats;
6543
6544 stats->rx_packets = old_stats->rx_packets +
6545 get_stat64(&hw_stats->rx_ucast_packets) +
6546 get_stat64(&hw_stats->rx_mcast_packets) +
6547 get_stat64(&hw_stats->rx_bcast_packets);
6548
6549 stats->tx_packets = old_stats->tx_packets +
6550 get_stat64(&hw_stats->tx_ucast_packets) +
6551 get_stat64(&hw_stats->tx_mcast_packets) +
6552 get_stat64(&hw_stats->tx_bcast_packets);
6553
6554 stats->rx_bytes = old_stats->rx_bytes +
6555 get_stat64(&hw_stats->rx_octets);
6556 stats->tx_bytes = old_stats->tx_bytes +
6557 get_stat64(&hw_stats->tx_octets);
6558
6559 stats->rx_errors = old_stats->rx_errors +
6560 get_stat64(&hw_stats->rx_errors) +
6561 get_stat64(&hw_stats->rx_discards);
6562 stats->tx_errors = old_stats->tx_errors +
6563 get_stat64(&hw_stats->tx_errors) +
6564 get_stat64(&hw_stats->tx_mac_errors) +
6565 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6566 get_stat64(&hw_stats->tx_discards);
6567
6568 stats->multicast = old_stats->multicast +
6569 get_stat64(&hw_stats->rx_mcast_packets);
6570 stats->collisions = old_stats->collisions +
6571 get_stat64(&hw_stats->tx_collisions);
6572
6573 stats->rx_length_errors = old_stats->rx_length_errors +
6574 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6575 get_stat64(&hw_stats->rx_undersize_packets);
6576
6577 stats->rx_over_errors = old_stats->rx_over_errors +
6578 get_stat64(&hw_stats->rxbds_empty);
6579 stats->rx_frame_errors = old_stats->rx_frame_errors +
6580 get_stat64(&hw_stats->rx_align_errors);
6581 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6582 get_stat64(&hw_stats->tx_discards);
6583 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6584 get_stat64(&hw_stats->tx_carrier_sense_errors);
6585
6586 stats->rx_crc_errors = old_stats->rx_crc_errors +
6587 calc_crc_errors(tp);
6588
6589 return stats;
6590 }
6591
6592 static inline u32 calc_crc(unsigned char *buf, int len)
6593 {
6594 u32 reg;
6595 u32 tmp;
6596 int j, k;
6597
6598 reg = 0xffffffff;
6599
6600 for (j = 0; j < len; j++) {
6601 reg ^= buf[j];
6602
6603 for (k = 0; k < 8; k++) {
6604 tmp = reg & 0x01;
6605
6606 reg >>= 1;
6607
6608 if (tmp) {
6609 reg ^= 0xedb88320;
6610 }
6611 }
6612 }
6613
6614 return ~reg;
6615 }
6616
6617 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6618 {
6619 /* accept or reject all multicast frames */
6620 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6621 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6622 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6623 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6624 }
6625
6626 static void __tg3_set_rx_mode(struct net_device *dev)
6627 {
6628 struct tg3 *tp = netdev_priv(dev);
6629 u32 rx_mode;
6630
6631 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6632 RX_MODE_KEEP_VLAN_TAG);
6633
6634 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6635 * flag clear.
6636 */
6637 #if TG3_VLAN_TAG_USED
6638 if (!tp->vlgrp &&
6639 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6640 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6641 #else
6642 /* By definition, VLAN is disabled always in this
6643 * case.
6644 */
6645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6646 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6647 #endif
6648
6649 if (dev->flags & IFF_PROMISC) {
6650 /* Promiscuous mode. */
6651 rx_mode |= RX_MODE_PROMISC;
6652 } else if (dev->flags & IFF_ALLMULTI) {
6653 /* Accept all multicast. */
6654 tg3_set_multi (tp, 1);
6655 } else if (dev->mc_count < 1) {
6656 /* Reject all multicast. */
6657 tg3_set_multi (tp, 0);
6658 } else {
6659 /* Accept one or more multicast(s). */
6660 struct dev_mc_list *mclist;
6661 unsigned int i;
6662 u32 mc_filter[4] = { 0, };
6663 u32 regidx;
6664 u32 bit;
6665 u32 crc;
6666
6667 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6668 i++, mclist = mclist->next) {
6669
6670 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6671 bit = ~crc & 0x7f;
6672 regidx = (bit & 0x60) >> 5;
6673 bit &= 0x1f;
6674 mc_filter[regidx] |= (1 << bit);
6675 }
6676
6677 tw32(MAC_HASH_REG_0, mc_filter[0]);
6678 tw32(MAC_HASH_REG_1, mc_filter[1]);
6679 tw32(MAC_HASH_REG_2, mc_filter[2]);
6680 tw32(MAC_HASH_REG_3, mc_filter[3]);
6681 }
6682
6683 if (rx_mode != tp->rx_mode) {
6684 tp->rx_mode = rx_mode;
6685 tw32_f(MAC_RX_MODE, rx_mode);
6686 udelay(10);
6687 }
6688 }
6689
6690 static void tg3_set_rx_mode(struct net_device *dev)
6691 {
6692 struct tg3 *tp = netdev_priv(dev);
6693
6694 spin_lock_irq(&tp->lock);
6695 spin_lock(&tp->tx_lock);
6696 __tg3_set_rx_mode(dev);
6697 spin_unlock(&tp->tx_lock);
6698 spin_unlock_irq(&tp->lock);
6699 }
6700
6701 #define TG3_REGDUMP_LEN (32 * 1024)
6702
6703 static int tg3_get_regs_len(struct net_device *dev)
6704 {
6705 return TG3_REGDUMP_LEN;
6706 }
6707
6708 static void tg3_get_regs(struct net_device *dev,
6709 struct ethtool_regs *regs, void *_p)
6710 {
6711 u32 *p = _p;
6712 struct tg3 *tp = netdev_priv(dev);
6713 u8 *orig_p = _p;
6714 int i;
6715
6716 regs->version = 0;
6717
6718 memset(p, 0, TG3_REGDUMP_LEN);
6719
6720 spin_lock_irq(&tp->lock);
6721 spin_lock(&tp->tx_lock);
6722
6723 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
6724 #define GET_REG32_LOOP(base,len) \
6725 do { p = (u32 *)(orig_p + (base)); \
6726 for (i = 0; i < len; i += 4) \
6727 __GET_REG32((base) + i); \
6728 } while (0)
6729 #define GET_REG32_1(reg) \
6730 do { p = (u32 *)(orig_p + (reg)); \
6731 __GET_REG32((reg)); \
6732 } while (0)
6733
6734 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6735 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6736 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6737 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6738 GET_REG32_1(SNDDATAC_MODE);
6739 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6740 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6741 GET_REG32_1(SNDBDC_MODE);
6742 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6743 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6744 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6745 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6746 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6747 GET_REG32_1(RCVDCC_MODE);
6748 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6749 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6750 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6751 GET_REG32_1(MBFREE_MODE);
6752 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6753 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6754 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6755 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6756 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6757 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6758 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6759 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6760 GET_REG32_LOOP(FTQ_RESET, 0x120);
6761 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6762 GET_REG32_1(DMAC_MODE);
6763 GET_REG32_LOOP(GRC_MODE, 0x4c);
6764 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6765 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6766
6767 #undef __GET_REG32
6768 #undef GET_REG32_LOOP
6769 #undef GET_REG32_1
6770
6771 spin_unlock(&tp->tx_lock);
6772 spin_unlock_irq(&tp->lock);
6773 }
6774
6775 static int tg3_get_eeprom_len(struct net_device *dev)
6776 {
6777 struct tg3 *tp = netdev_priv(dev);
6778
6779 return tp->nvram_size;
6780 }
6781
6782 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6783
6784 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6785 {
6786 struct tg3 *tp = netdev_priv(dev);
6787 int ret;
6788 u8 *pd;
6789 u32 i, offset, len, val, b_offset, b_count;
6790
6791 offset = eeprom->offset;
6792 len = eeprom->len;
6793 eeprom->len = 0;
6794
6795 eeprom->magic = TG3_EEPROM_MAGIC;
6796
6797 if (offset & 3) {
6798 /* adjustments to start on required 4 byte boundary */
6799 b_offset = offset & 3;
6800 b_count = 4 - b_offset;
6801 if (b_count > len) {
6802 /* i.e. offset=1 len=2 */
6803 b_count = len;
6804 }
6805 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6806 if (ret)
6807 return ret;
6808 val = cpu_to_le32(val);
6809 memcpy(data, ((char*)&val) + b_offset, b_count);
6810 len -= b_count;
6811 offset += b_count;
6812 eeprom->len += b_count;
6813 }
6814
6815 /* read bytes upto the last 4 byte boundary */
6816 pd = &data[eeprom->len];
6817 for (i = 0; i < (len - (len & 3)); i += 4) {
6818 ret = tg3_nvram_read(tp, offset + i, &val);
6819 if (ret) {
6820 eeprom->len += i;
6821 return ret;
6822 }
6823 val = cpu_to_le32(val);
6824 memcpy(pd + i, &val, 4);
6825 }
6826 eeprom->len += i;
6827
6828 if (len & 3) {
6829 /* read last bytes not ending on 4 byte boundary */
6830 pd = &data[eeprom->len];
6831 b_count = len & 3;
6832 b_offset = offset + len - b_count;
6833 ret = tg3_nvram_read(tp, b_offset, &val);
6834 if (ret)
6835 return ret;
6836 val = cpu_to_le32(val);
6837 memcpy(pd, ((char*)&val), b_count);
6838 eeprom->len += b_count;
6839 }
6840 return 0;
6841 }
6842
6843 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6844
6845 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6846 {
6847 struct tg3 *tp = netdev_priv(dev);
6848 int ret;
6849 u32 offset, len, b_offset, odd_len, start, end;
6850 u8 *buf;
6851
6852 if (eeprom->magic != TG3_EEPROM_MAGIC)
6853 return -EINVAL;
6854
6855 offset = eeprom->offset;
6856 len = eeprom->len;
6857
6858 if ((b_offset = (offset & 3))) {
6859 /* adjustments to start on required 4 byte boundary */
6860 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6861 if (ret)
6862 return ret;
6863 start = cpu_to_le32(start);
6864 len += b_offset;
6865 offset &= ~3;
6866 if (len < 4)
6867 len = 4;
6868 }
6869
6870 odd_len = 0;
6871 if (len & 3) {
6872 /* adjustments to end on required 4 byte boundary */
6873 odd_len = 1;
6874 len = (len + 3) & ~3;
6875 ret = tg3_nvram_read(tp, offset+len-4, &end);
6876 if (ret)
6877 return ret;
6878 end = cpu_to_le32(end);
6879 }
6880
6881 buf = data;
6882 if (b_offset || odd_len) {
6883 buf = kmalloc(len, GFP_KERNEL);
6884 if (buf == 0)
6885 return -ENOMEM;
6886 if (b_offset)
6887 memcpy(buf, &start, 4);
6888 if (odd_len)
6889 memcpy(buf+len-4, &end, 4);
6890 memcpy(buf + b_offset, data, eeprom->len);
6891 }
6892
6893 ret = tg3_nvram_write_block(tp, offset, len, buf);
6894
6895 if (buf != data)
6896 kfree(buf);
6897
6898 return ret;
6899 }
6900
6901 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6902 {
6903 struct tg3 *tp = netdev_priv(dev);
6904
6905 cmd->supported = (SUPPORTED_Autoneg);
6906
6907 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6908 cmd->supported |= (SUPPORTED_1000baseT_Half |
6909 SUPPORTED_1000baseT_Full);
6910
6911 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6912 cmd->supported |= (SUPPORTED_100baseT_Half |
6913 SUPPORTED_100baseT_Full |
6914 SUPPORTED_10baseT_Half |
6915 SUPPORTED_10baseT_Full |
6916 SUPPORTED_MII);
6917 else
6918 cmd->supported |= SUPPORTED_FIBRE;
6919
6920 cmd->advertising = tp->link_config.advertising;
6921 if (netif_running(dev)) {
6922 cmd->speed = tp->link_config.active_speed;
6923 cmd->duplex = tp->link_config.active_duplex;
6924 }
6925 cmd->port = 0;
6926 cmd->phy_address = PHY_ADDR;
6927 cmd->transceiver = 0;
6928 cmd->autoneg = tp->link_config.autoneg;
6929 cmd->maxtxpkt = 0;
6930 cmd->maxrxpkt = 0;
6931 return 0;
6932 }
6933
6934 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6935 {
6936 struct tg3 *tp = netdev_priv(dev);
6937
6938 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6939 /* These are the only valid advertisement bits allowed. */
6940 if (cmd->autoneg == AUTONEG_ENABLE &&
6941 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6942 ADVERTISED_1000baseT_Full |
6943 ADVERTISED_Autoneg |
6944 ADVERTISED_FIBRE)))
6945 return -EINVAL;
6946 }
6947
6948 spin_lock_irq(&tp->lock);
6949 spin_lock(&tp->tx_lock);
6950
6951 tp->link_config.autoneg = cmd->autoneg;
6952 if (cmd->autoneg == AUTONEG_ENABLE) {
6953 tp->link_config.advertising = cmd->advertising;
6954 tp->link_config.speed = SPEED_INVALID;
6955 tp->link_config.duplex = DUPLEX_INVALID;
6956 } else {
6957 tp->link_config.advertising = 0;
6958 tp->link_config.speed = cmd->speed;
6959 tp->link_config.duplex = cmd->duplex;
6960 }
6961
6962 if (netif_running(dev))
6963 tg3_setup_phy(tp, 1);
6964
6965 spin_unlock(&tp->tx_lock);
6966 spin_unlock_irq(&tp->lock);
6967
6968 return 0;
6969 }
6970
6971 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6972 {
6973 struct tg3 *tp = netdev_priv(dev);
6974
6975 strcpy(info->driver, DRV_MODULE_NAME);
6976 strcpy(info->version, DRV_MODULE_VERSION);
6977 strcpy(info->bus_info, pci_name(tp->pdev));
6978 }
6979
6980 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6981 {
6982 struct tg3 *tp = netdev_priv(dev);
6983
6984 wol->supported = WAKE_MAGIC;
6985 wol->wolopts = 0;
6986 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6987 wol->wolopts = WAKE_MAGIC;
6988 memset(&wol->sopass, 0, sizeof(wol->sopass));
6989 }
6990
6991 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6992 {
6993 struct tg3 *tp = netdev_priv(dev);
6994
6995 if (wol->wolopts & ~WAKE_MAGIC)
6996 return -EINVAL;
6997 if ((wol->wolopts & WAKE_MAGIC) &&
6998 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
6999 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7000 return -EINVAL;
7001
7002 spin_lock_irq(&tp->lock);
7003 if (wol->wolopts & WAKE_MAGIC)
7004 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7005 else
7006 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7007 spin_unlock_irq(&tp->lock);
7008
7009 return 0;
7010 }
7011
7012 static u32 tg3_get_msglevel(struct net_device *dev)
7013 {
7014 struct tg3 *tp = netdev_priv(dev);
7015 return tp->msg_enable;
7016 }
7017
7018 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7019 {
7020 struct tg3 *tp = netdev_priv(dev);
7021 tp->msg_enable = value;
7022 }
7023
7024 #if TG3_TSO_SUPPORT != 0
7025 static int tg3_set_tso(struct net_device *dev, u32 value)
7026 {
7027 struct tg3 *tp = netdev_priv(dev);
7028
7029 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7030 if (value)
7031 return -EINVAL;
7032 return 0;
7033 }
7034 return ethtool_op_set_tso(dev, value);
7035 }
7036 #endif
7037
7038 static int tg3_nway_reset(struct net_device *dev)
7039 {
7040 struct tg3 *tp = netdev_priv(dev);
7041 u32 bmcr;
7042 int r;
7043
7044 if (!netif_running(dev))
7045 return -EAGAIN;
7046
7047 spin_lock_irq(&tp->lock);
7048 r = -EINVAL;
7049 tg3_readphy(tp, MII_BMCR, &bmcr);
7050 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7051 (bmcr & BMCR_ANENABLE)) {
7052 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7053 r = 0;
7054 }
7055 spin_unlock_irq(&tp->lock);
7056
7057 return r;
7058 }
7059
7060 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7061 {
7062 struct tg3 *tp = netdev_priv(dev);
7063
7064 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7065 ering->rx_mini_max_pending = 0;
7066 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7067
7068 ering->rx_pending = tp->rx_pending;
7069 ering->rx_mini_pending = 0;
7070 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7071 ering->tx_pending = tp->tx_pending;
7072 }
7073
7074 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7075 {
7076 struct tg3 *tp = netdev_priv(dev);
7077
7078 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7079 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7080 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7081 return -EINVAL;
7082
7083 if (netif_running(dev))
7084 tg3_netif_stop(tp);
7085
7086 spin_lock_irq(&tp->lock);
7087 spin_lock(&tp->tx_lock);
7088
7089 tp->rx_pending = ering->rx_pending;
7090
7091 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7092 tp->rx_pending > 63)
7093 tp->rx_pending = 63;
7094 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7095 tp->tx_pending = ering->tx_pending;
7096
7097 if (netif_running(dev)) {
7098 tg3_halt(tp, 1);
7099 tg3_init_hw(tp);
7100 tg3_netif_start(tp);
7101 }
7102
7103 spin_unlock(&tp->tx_lock);
7104 spin_unlock_irq(&tp->lock);
7105
7106 return 0;
7107 }
7108
7109 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7110 {
7111 struct tg3 *tp = netdev_priv(dev);
7112
7113 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7114 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7115 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7116 }
7117
7118 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7119 {
7120 struct tg3 *tp = netdev_priv(dev);
7121
7122 if (netif_running(dev))
7123 tg3_netif_stop(tp);
7124
7125 spin_lock_irq(&tp->lock);
7126 spin_lock(&tp->tx_lock);
7127 if (epause->autoneg)
7128 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7129 else
7130 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7131 if (epause->rx_pause)
7132 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7133 else
7134 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7135 if (epause->tx_pause)
7136 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7137 else
7138 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7139
7140 if (netif_running(dev)) {
7141 tg3_halt(tp, 1);
7142 tg3_init_hw(tp);
7143 tg3_netif_start(tp);
7144 }
7145 spin_unlock(&tp->tx_lock);
7146 spin_unlock_irq(&tp->lock);
7147
7148 return 0;
7149 }
7150
7151 static u32 tg3_get_rx_csum(struct net_device *dev)
7152 {
7153 struct tg3 *tp = netdev_priv(dev);
7154 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7155 }
7156
7157 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7158 {
7159 struct tg3 *tp = netdev_priv(dev);
7160
7161 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7162 if (data != 0)
7163 return -EINVAL;
7164 return 0;
7165 }
7166
7167 spin_lock_irq(&tp->lock);
7168 if (data)
7169 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7170 else
7171 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7172 spin_unlock_irq(&tp->lock);
7173
7174 return 0;
7175 }
7176
7177 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7178 {
7179 struct tg3 *tp = netdev_priv(dev);
7180
7181 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7182 if (data != 0)
7183 return -EINVAL;
7184 return 0;
7185 }
7186
7187 if (data)
7188 dev->features |= NETIF_F_IP_CSUM;
7189 else
7190 dev->features &= ~NETIF_F_IP_CSUM;
7191
7192 return 0;
7193 }
7194
7195 static int tg3_get_stats_count (struct net_device *dev)
7196 {
7197 return TG3_NUM_STATS;
7198 }
7199
7200 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7201 {
7202 switch (stringset) {
7203 case ETH_SS_STATS:
7204 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7205 break;
7206 default:
7207 WARN_ON(1); /* we need a WARN() */
7208 break;
7209 }
7210 }
7211
7212 static void tg3_get_ethtool_stats (struct net_device *dev,
7213 struct ethtool_stats *estats, u64 *tmp_stats)
7214 {
7215 struct tg3 *tp = netdev_priv(dev);
7216 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7217 }
7218
7219 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7220 {
7221 struct mii_ioctl_data *data = if_mii(ifr);
7222 struct tg3 *tp = netdev_priv(dev);
7223 int err;
7224
7225 switch(cmd) {
7226 case SIOCGMIIPHY:
7227 data->phy_id = PHY_ADDR;
7228
7229 /* fallthru */
7230 case SIOCGMIIREG: {
7231 u32 mii_regval;
7232
7233 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7234 break; /* We have no PHY */
7235
7236 spin_lock_irq(&tp->lock);
7237 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7238 spin_unlock_irq(&tp->lock);
7239
7240 data->val_out = mii_regval;
7241
7242 return err;
7243 }
7244
7245 case SIOCSMIIREG:
7246 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7247 break; /* We have no PHY */
7248
7249 if (!capable(CAP_NET_ADMIN))
7250 return -EPERM;
7251
7252 spin_lock_irq(&tp->lock);
7253 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7254 spin_unlock_irq(&tp->lock);
7255
7256 return err;
7257
7258 default:
7259 /* do nothing */
7260 break;
7261 }
7262 return -EOPNOTSUPP;
7263 }
7264
7265 #if TG3_VLAN_TAG_USED
7266 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7267 {
7268 struct tg3 *tp = netdev_priv(dev);
7269
7270 spin_lock_irq(&tp->lock);
7271 spin_lock(&tp->tx_lock);
7272
7273 tp->vlgrp = grp;
7274
7275 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7276 __tg3_set_rx_mode(dev);
7277
7278 spin_unlock(&tp->tx_lock);
7279 spin_unlock_irq(&tp->lock);
7280 }
7281
7282 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7283 {
7284 struct tg3 *tp = netdev_priv(dev);
7285
7286 spin_lock_irq(&tp->lock);
7287 spin_lock(&tp->tx_lock);
7288 if (tp->vlgrp)
7289 tp->vlgrp->vlan_devices[vid] = NULL;
7290 spin_unlock(&tp->tx_lock);
7291 spin_unlock_irq(&tp->lock);
7292 }
7293 #endif
7294
7295 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7296 {
7297 struct tg3 *tp = netdev_priv(dev);
7298
7299 memcpy(ec, &tp->coal, sizeof(*ec));
7300 return 0;
7301 }
7302
7303 static struct ethtool_ops tg3_ethtool_ops = {
7304 .get_settings = tg3_get_settings,
7305 .set_settings = tg3_set_settings,
7306 .get_drvinfo = tg3_get_drvinfo,
7307 .get_regs_len = tg3_get_regs_len,
7308 .get_regs = tg3_get_regs,
7309 .get_wol = tg3_get_wol,
7310 .set_wol = tg3_set_wol,
7311 .get_msglevel = tg3_get_msglevel,
7312 .set_msglevel = tg3_set_msglevel,
7313 .nway_reset = tg3_nway_reset,
7314 .get_link = ethtool_op_get_link,
7315 .get_eeprom_len = tg3_get_eeprom_len,
7316 .get_eeprom = tg3_get_eeprom,
7317 .set_eeprom = tg3_set_eeprom,
7318 .get_ringparam = tg3_get_ringparam,
7319 .set_ringparam = tg3_set_ringparam,
7320 .get_pauseparam = tg3_get_pauseparam,
7321 .set_pauseparam = tg3_set_pauseparam,
7322 .get_rx_csum = tg3_get_rx_csum,
7323 .set_rx_csum = tg3_set_rx_csum,
7324 .get_tx_csum = ethtool_op_get_tx_csum,
7325 .set_tx_csum = tg3_set_tx_csum,
7326 .get_sg = ethtool_op_get_sg,
7327 .set_sg = ethtool_op_set_sg,
7328 #if TG3_TSO_SUPPORT != 0
7329 .get_tso = ethtool_op_get_tso,
7330 .set_tso = tg3_set_tso,
7331 #endif
7332 .get_strings = tg3_get_strings,
7333 .get_stats_count = tg3_get_stats_count,
7334 .get_ethtool_stats = tg3_get_ethtool_stats,
7335 .get_coalesce = tg3_get_coalesce,
7336 };
7337
7338 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7339 {
7340 u32 cursize, val;
7341
7342 tp->nvram_size = EEPROM_CHIP_SIZE;
7343
7344 if (tg3_nvram_read(tp, 0, &val) != 0)
7345 return;
7346
7347 if (swab32(val) != TG3_EEPROM_MAGIC)
7348 return;
7349
7350 /*
7351 * Size the chip by reading offsets at increasing powers of two.
7352 * When we encounter our validation signature, we know the addressing
7353 * has wrapped around, and thus have our chip size.
7354 */
7355 cursize = 0x800;
7356
7357 while (cursize < tp->nvram_size) {
7358 if (tg3_nvram_read(tp, cursize, &val) != 0)
7359 return;
7360
7361 if (swab32(val) == TG3_EEPROM_MAGIC)
7362 break;
7363
7364 cursize <<= 1;
7365 }
7366
7367 tp->nvram_size = cursize;
7368 }
7369
7370 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7371 {
7372 u32 val;
7373
7374 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7375 if (val != 0) {
7376 tp->nvram_size = (val >> 16) * 1024;
7377 return;
7378 }
7379 }
7380 tp->nvram_size = 0x20000;
7381 }
7382
7383 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7384 {
7385 u32 nvcfg1;
7386
7387 nvcfg1 = tr32(NVRAM_CFG1);
7388 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7389 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7390 }
7391 else {
7392 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7393 tw32(NVRAM_CFG1, nvcfg1);
7394 }
7395
7396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7397 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7398 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7399 tp->nvram_jedecnum = JEDEC_ATMEL;
7400 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7401 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7402 break;
7403 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7404 tp->nvram_jedecnum = JEDEC_ATMEL;
7405 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7406 break;
7407 case FLASH_VENDOR_ATMEL_EEPROM:
7408 tp->nvram_jedecnum = JEDEC_ATMEL;
7409 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7410 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7411 break;
7412 case FLASH_VENDOR_ST:
7413 tp->nvram_jedecnum = JEDEC_ST;
7414 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7415 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7416 break;
7417 case FLASH_VENDOR_SAIFUN:
7418 tp->nvram_jedecnum = JEDEC_SAIFUN;
7419 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7420 break;
7421 case FLASH_VENDOR_SST_SMALL:
7422 case FLASH_VENDOR_SST_LARGE:
7423 tp->nvram_jedecnum = JEDEC_SST;
7424 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7425 break;
7426 }
7427 }
7428 else {
7429 tp->nvram_jedecnum = JEDEC_ATMEL;
7430 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7431 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7432 }
7433 }
7434
7435 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7436 {
7437 u32 nvcfg1;
7438
7439 nvcfg1 = tr32(NVRAM_CFG1);
7440
7441 /* NVRAM protection for TPM */
7442 if (nvcfg1 & (1 << 27))
7443 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7444
7445 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7446 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7447 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7448 tp->nvram_jedecnum = JEDEC_ATMEL;
7449 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7450 break;
7451 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7452 tp->nvram_jedecnum = JEDEC_ATMEL;
7453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7454 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7455 break;
7456 case FLASH_5752VENDOR_ST_M45PE10:
7457 case FLASH_5752VENDOR_ST_M45PE20:
7458 case FLASH_5752VENDOR_ST_M45PE40:
7459 tp->nvram_jedecnum = JEDEC_ST;
7460 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7461 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7462 break;
7463 }
7464
7465 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7466 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7467 case FLASH_5752PAGE_SIZE_256:
7468 tp->nvram_pagesize = 256;
7469 break;
7470 case FLASH_5752PAGE_SIZE_512:
7471 tp->nvram_pagesize = 512;
7472 break;
7473 case FLASH_5752PAGE_SIZE_1K:
7474 tp->nvram_pagesize = 1024;
7475 break;
7476 case FLASH_5752PAGE_SIZE_2K:
7477 tp->nvram_pagesize = 2048;
7478 break;
7479 case FLASH_5752PAGE_SIZE_4K:
7480 tp->nvram_pagesize = 4096;
7481 break;
7482 case FLASH_5752PAGE_SIZE_264:
7483 tp->nvram_pagesize = 264;
7484 break;
7485 }
7486 }
7487 else {
7488 /* For eeprom, set pagesize to maximum eeprom size */
7489 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7490
7491 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7492 tw32(NVRAM_CFG1, nvcfg1);
7493 }
7494 }
7495
7496 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
7497 static void __devinit tg3_nvram_init(struct tg3 *tp)
7498 {
7499 int j;
7500
7501 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
7502 return;
7503
7504 tw32_f(GRC_EEPROM_ADDR,
7505 (EEPROM_ADDR_FSM_RESET |
7506 (EEPROM_DEFAULT_CLOCK_PERIOD <<
7507 EEPROM_ADDR_CLKPERD_SHIFT)));
7508
7509 /* XXX schedule_timeout() ... */
7510 for (j = 0; j < 100; j++)
7511 udelay(10);
7512
7513 /* Enable seeprom accesses. */
7514 tw32_f(GRC_LOCAL_CTRL,
7515 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
7516 udelay(100);
7517
7518 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7519 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7520 tp->tg3_flags |= TG3_FLAG_NVRAM;
7521
7522 tg3_enable_nvram_access(tp);
7523
7524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7525 tg3_get_5752_nvram_info(tp);
7526 else
7527 tg3_get_nvram_info(tp);
7528
7529 tg3_get_nvram_size(tp);
7530
7531 tg3_disable_nvram_access(tp);
7532
7533 } else {
7534 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
7535
7536 tg3_get_eeprom_size(tp);
7537 }
7538 }
7539
7540 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
7541 u32 offset, u32 *val)
7542 {
7543 u32 tmp;
7544 int i;
7545
7546 if (offset > EEPROM_ADDR_ADDR_MASK ||
7547 (offset % 4) != 0)
7548 return -EINVAL;
7549
7550 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
7551 EEPROM_ADDR_DEVID_MASK |
7552 EEPROM_ADDR_READ);
7553 tw32(GRC_EEPROM_ADDR,
7554 tmp |
7555 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7556 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
7557 EEPROM_ADDR_ADDR_MASK) |
7558 EEPROM_ADDR_READ | EEPROM_ADDR_START);
7559
7560 for (i = 0; i < 10000; i++) {
7561 tmp = tr32(GRC_EEPROM_ADDR);
7562
7563 if (tmp & EEPROM_ADDR_COMPLETE)
7564 break;
7565 udelay(100);
7566 }
7567 if (!(tmp & EEPROM_ADDR_COMPLETE))
7568 return -EBUSY;
7569
7570 *val = tr32(GRC_EEPROM_DATA);
7571 return 0;
7572 }
7573
7574 #define NVRAM_CMD_TIMEOUT 10000
7575
7576 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
7577 {
7578 int i;
7579
7580 tw32(NVRAM_CMD, nvram_cmd);
7581 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
7582 udelay(10);
7583 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
7584 udelay(10);
7585 break;
7586 }
7587 }
7588 if (i == NVRAM_CMD_TIMEOUT) {
7589 return -EBUSY;
7590 }
7591 return 0;
7592 }
7593
7594 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7595 {
7596 int ret;
7597
7598 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7599 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
7600 return -EINVAL;
7601 }
7602
7603 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
7604 return tg3_nvram_read_using_eeprom(tp, offset, val);
7605
7606 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
7607 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7608 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7609
7610 offset = ((offset / tp->nvram_pagesize) <<
7611 ATMEL_AT45DB0X1B_PAGE_POS) +
7612 (offset % tp->nvram_pagesize);
7613 }
7614
7615 if (offset > NVRAM_ADDR_MSK)
7616 return -EINVAL;
7617
7618 tg3_nvram_lock(tp);
7619
7620 tg3_enable_nvram_access(tp);
7621
7622 tw32(NVRAM_ADDR, offset);
7623 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
7624 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
7625
7626 if (ret == 0)
7627 *val = swab32(tr32(NVRAM_RDDATA));
7628
7629 tg3_nvram_unlock(tp);
7630
7631 tg3_disable_nvram_access(tp);
7632
7633 return ret;
7634 }
7635
7636 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
7637 u32 offset, u32 len, u8 *buf)
7638 {
7639 int i, j, rc = 0;
7640 u32 val;
7641
7642 for (i = 0; i < len; i += 4) {
7643 u32 addr, data;
7644
7645 addr = offset + i;
7646
7647 memcpy(&data, buf + i, 4);
7648
7649 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
7650
7651 val = tr32(GRC_EEPROM_ADDR);
7652 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
7653
7654 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
7655 EEPROM_ADDR_READ);
7656 tw32(GRC_EEPROM_ADDR, val |
7657 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7658 (addr & EEPROM_ADDR_ADDR_MASK) |
7659 EEPROM_ADDR_START |
7660 EEPROM_ADDR_WRITE);
7661
7662 for (j = 0; j < 10000; j++) {
7663 val = tr32(GRC_EEPROM_ADDR);
7664
7665 if (val & EEPROM_ADDR_COMPLETE)
7666 break;
7667 udelay(100);
7668 }
7669 if (!(val & EEPROM_ADDR_COMPLETE)) {
7670 rc = -EBUSY;
7671 break;
7672 }
7673 }
7674
7675 return rc;
7676 }
7677
7678 /* offset and length are dword aligned */
7679 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7680 u8 *buf)
7681 {
7682 int ret = 0;
7683 u32 pagesize = tp->nvram_pagesize;
7684 u32 pagemask = pagesize - 1;
7685 u32 nvram_cmd;
7686 u8 *tmp;
7687
7688 tmp = kmalloc(pagesize, GFP_KERNEL);
7689 if (tmp == NULL)
7690 return -ENOMEM;
7691
7692 while (len) {
7693 int j;
7694 u32 phy_addr, page_off, size;
7695
7696 phy_addr = offset & ~pagemask;
7697
7698 for (j = 0; j < pagesize; j += 4) {
7699 if ((ret = tg3_nvram_read(tp, phy_addr + j,
7700 (u32 *) (tmp + j))))
7701 break;
7702 }
7703 if (ret)
7704 break;
7705
7706 page_off = offset & pagemask;
7707 size = pagesize;
7708 if (len < size)
7709 size = len;
7710
7711 len -= size;
7712
7713 memcpy(tmp + page_off, buf, size);
7714
7715 offset = offset + (pagesize - page_off);
7716
7717 tg3_enable_nvram_access(tp);
7718
7719 /*
7720 * Before we can erase the flash page, we need
7721 * to issue a special "write enable" command.
7722 */
7723 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7724
7725 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7726 break;
7727
7728 /* Erase the target page */
7729 tw32(NVRAM_ADDR, phy_addr);
7730
7731 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
7732 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
7733
7734 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7735 break;
7736
7737 /* Issue another write enable to start the write. */
7738 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7739
7740 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7741 break;
7742
7743 for (j = 0; j < pagesize; j += 4) {
7744 u32 data;
7745
7746 data = *((u32 *) (tmp + j));
7747 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7748
7749 tw32(NVRAM_ADDR, phy_addr + j);
7750
7751 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
7752 NVRAM_CMD_WR;
7753
7754 if (j == 0)
7755 nvram_cmd |= NVRAM_CMD_FIRST;
7756 else if (j == (pagesize - 4))
7757 nvram_cmd |= NVRAM_CMD_LAST;
7758
7759 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7760 break;
7761 }
7762 if (ret)
7763 break;
7764 }
7765
7766 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7767 tg3_nvram_exec_cmd(tp, nvram_cmd);
7768
7769 kfree(tmp);
7770
7771 return ret;
7772 }
7773
7774 /* offset and length are dword aligned */
7775 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
7776 u8 *buf)
7777 {
7778 int i, ret = 0;
7779
7780 for (i = 0; i < len; i += 4, offset += 4) {
7781 u32 data, page_off, phy_addr, nvram_cmd;
7782
7783 memcpy(&data, buf + i, 4);
7784 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7785
7786 page_off = offset % tp->nvram_pagesize;
7787
7788 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7789 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7790
7791 phy_addr = ((offset / tp->nvram_pagesize) <<
7792 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
7793 }
7794 else {
7795 phy_addr = offset;
7796 }
7797
7798 tw32(NVRAM_ADDR, phy_addr);
7799
7800 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
7801
7802 if ((page_off == 0) || (i == 0))
7803 nvram_cmd |= NVRAM_CMD_FIRST;
7804 else if (page_off == (tp->nvram_pagesize - 4))
7805 nvram_cmd |= NVRAM_CMD_LAST;
7806
7807 if (i == (len - 4))
7808 nvram_cmd |= NVRAM_CMD_LAST;
7809
7810 if ((tp->nvram_jedecnum == JEDEC_ST) &&
7811 (nvram_cmd & NVRAM_CMD_FIRST)) {
7812
7813 if ((ret = tg3_nvram_exec_cmd(tp,
7814 NVRAM_CMD_WREN | NVRAM_CMD_GO |
7815 NVRAM_CMD_DONE)))
7816
7817 break;
7818 }
7819 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7820 /* We always do complete word writes to eeprom. */
7821 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
7822 }
7823
7824 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7825 break;
7826 }
7827 return ret;
7828 }
7829
7830 /* offset and length are dword aligned */
7831 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7832 {
7833 int ret;
7834
7835 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7836 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
7837 return -EINVAL;
7838 }
7839
7840 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
7841 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
7842 ~GRC_LCLCTRL_GPIO_OUTPUT1);
7843 udelay(40);
7844 }
7845
7846 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
7847 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
7848 }
7849 else {
7850 u32 grc_mode;
7851
7852 tg3_nvram_lock(tp);
7853
7854 tg3_enable_nvram_access(tp);
7855 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7856 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
7857 tw32(NVRAM_WRITE1, 0x406);
7858
7859 grc_mode = tr32(GRC_MODE);
7860 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
7861
7862 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
7863 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7864
7865 ret = tg3_nvram_write_block_buffered(tp, offset, len,
7866 buf);
7867 }
7868 else {
7869 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
7870 buf);
7871 }
7872
7873 grc_mode = tr32(GRC_MODE);
7874 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7875
7876 tg3_disable_nvram_access(tp);
7877 tg3_nvram_unlock(tp);
7878 }
7879
7880 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
7881 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7882 udelay(40);
7883 }
7884
7885 return ret;
7886 }
7887
7888 struct subsys_tbl_ent {
7889 u16 subsys_vendor, subsys_devid;
7890 u32 phy_id;
7891 };
7892
7893 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
7894 /* Broadcom boards. */
7895 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
7896 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
7897 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
7898 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
7899 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
7900 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
7901 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
7902 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
7903 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
7904 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
7905 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
7906
7907 /* 3com boards. */
7908 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
7909 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
7910 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
7911 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
7912 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
7913
7914 /* DELL boards. */
7915 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
7916 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
7917 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
7918 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
7919
7920 /* Compaq boards. */
7921 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
7922 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
7923 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
7924 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
7925 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
7926
7927 /* IBM boards. */
7928 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
7929 };
7930
7931 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
7932 {
7933 int i;
7934
7935 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
7936 if ((subsys_id_to_phy_id[i].subsys_vendor ==
7937 tp->pdev->subsystem_vendor) &&
7938 (subsys_id_to_phy_id[i].subsys_devid ==
7939 tp->pdev->subsystem_device))
7940 return &subsys_id_to_phy_id[i];
7941 }
7942 return NULL;
7943 }
7944
7945 /* Since this function may be called in D3-hot power state during
7946 * tg3_init_one(), only config cycles are allowed.
7947 */
7948 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
7949 {
7950 u32 val;
7951
7952 /* Make sure register accesses (indirect or otherwise)
7953 * will function correctly.
7954 */
7955 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7956 tp->misc_host_ctrl);
7957
7958 tp->phy_id = PHY_ID_INVALID;
7959 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7960
7961 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7962 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7963 u32 nic_cfg, led_cfg;
7964 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
7965 int eeprom_phy_serdes = 0;
7966
7967 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7968 tp->nic_sram_data_cfg = nic_cfg;
7969
7970 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
7971 ver >>= NIC_SRAM_DATA_VER_SHIFT;
7972 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7973 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7974 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
7975 (ver > 0) && (ver < 0x100))
7976 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
7977
7978 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
7979 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
7980 eeprom_phy_serdes = 1;
7981
7982 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
7983 if (nic_phy_id != 0) {
7984 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
7985 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
7986
7987 eeprom_phy_id = (id1 >> 16) << 10;
7988 eeprom_phy_id |= (id2 & 0xfc00) << 16;
7989 eeprom_phy_id |= (id2 & 0x03ff) << 0;
7990 } else
7991 eeprom_phy_id = 0;
7992
7993 tp->phy_id = eeprom_phy_id;
7994 if (eeprom_phy_serdes)
7995 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7996
7997 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7998 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7999 SHASTA_EXT_LED_MODE_MASK);
8000 else
8001 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8002
8003 switch (led_cfg) {
8004 default:
8005 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8006 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8007 break;
8008
8009 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8010 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8011 break;
8012
8013 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8014 tp->led_ctrl = LED_CTRL_MODE_MAC;
8015 break;
8016
8017 case SHASTA_EXT_LED_SHARED:
8018 tp->led_ctrl = LED_CTRL_MODE_SHARED;
8019 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8020 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8021 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8022 LED_CTRL_MODE_PHY_2);
8023 break;
8024
8025 case SHASTA_EXT_LED_MAC:
8026 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8027 break;
8028
8029 case SHASTA_EXT_LED_COMBO:
8030 tp->led_ctrl = LED_CTRL_MODE_COMBO;
8031 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8032 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8033 LED_CTRL_MODE_PHY_2);
8034 break;
8035
8036 };
8037
8038 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8040 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8041 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8042
8043 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8044 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8045 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8046 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8047
8048 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8049 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
8050 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8051 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8052 }
8053 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8054 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8055
8056 if (cfg2 & (1 << 17))
8057 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8058
8059 /* serdes signal pre-emphasis in register 0x590 set by */
8060 /* bootcode if bit 18 is set */
8061 if (cfg2 & (1 << 18))
8062 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8063 }
8064 }
8065
8066 static int __devinit tg3_phy_probe(struct tg3 *tp)
8067 {
8068 u32 hw_phy_id_1, hw_phy_id_2;
8069 u32 hw_phy_id, hw_phy_id_masked;
8070 int err;
8071
8072 /* Reading the PHY ID register can conflict with ASF
8073 * firwmare access to the PHY hardware.
8074 */
8075 err = 0;
8076 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8077 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8078 } else {
8079 /* Now read the physical PHY_ID from the chip and verify
8080 * that it is sane. If it doesn't look good, we fall back
8081 * to either the hard-coded table based PHY_ID and failing
8082 * that the value found in the eeprom area.
8083 */
8084 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8085 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8086
8087 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
8088 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8089 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
8090
8091 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8092 }
8093
8094 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8095 tp->phy_id = hw_phy_id;
8096 if (hw_phy_id_masked == PHY_ID_BCM8002)
8097 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8098 } else {
8099 if (tp->phy_id != PHY_ID_INVALID) {
8100 /* Do nothing, phy ID already set up in
8101 * tg3_get_eeprom_hw_cfg().
8102 */
8103 } else {
8104 struct subsys_tbl_ent *p;
8105
8106 /* No eeprom signature? Try the hardcoded
8107 * subsys device table.
8108 */
8109 p = lookup_by_subsys(tp);
8110 if (!p)
8111 return -ENODEV;
8112
8113 tp->phy_id = p->phy_id;
8114 if (!tp->phy_id ||
8115 tp->phy_id == PHY_ID_BCM8002)
8116 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8117 }
8118 }
8119
8120 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8121 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8122 u32 bmsr, adv_reg, tg3_ctrl;
8123
8124 tg3_readphy(tp, MII_BMSR, &bmsr);
8125 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8126 (bmsr & BMSR_LSTATUS))
8127 goto skip_phy_reset;
8128
8129 err = tg3_phy_reset(tp);
8130 if (err)
8131 return err;
8132
8133 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8134 ADVERTISE_100HALF | ADVERTISE_100FULL |
8135 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8136 tg3_ctrl = 0;
8137 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8138 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8139 MII_TG3_CTRL_ADV_1000_FULL);
8140 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8141 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8142 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8143 MII_TG3_CTRL_ENABLE_AS_MASTER);
8144 }
8145
8146 if (!tg3_copper_is_advertising_all(tp)) {
8147 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8148
8149 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8150 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8151
8152 tg3_writephy(tp, MII_BMCR,
8153 BMCR_ANENABLE | BMCR_ANRESTART);
8154 }
8155 tg3_phy_set_wirespeed(tp);
8156
8157 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8158 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8159 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8160 }
8161
8162 skip_phy_reset:
8163 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8164 err = tg3_init_5401phy_dsp(tp);
8165 if (err)
8166 return err;
8167 }
8168
8169 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8170 err = tg3_init_5401phy_dsp(tp);
8171 }
8172
8173 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8174 tp->link_config.advertising =
8175 (ADVERTISED_1000baseT_Half |
8176 ADVERTISED_1000baseT_Full |
8177 ADVERTISED_Autoneg |
8178 ADVERTISED_FIBRE);
8179 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8180 tp->link_config.advertising &=
8181 ~(ADVERTISED_1000baseT_Half |
8182 ADVERTISED_1000baseT_Full);
8183
8184 return err;
8185 }
8186
8187 static void __devinit tg3_read_partno(struct tg3 *tp)
8188 {
8189 unsigned char vpd_data[256];
8190 int i;
8191
8192 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8193 /* Sun decided not to put the necessary bits in the
8194 * NVRAM of their onboard tg3 parts :(
8195 */
8196 strcpy(tp->board_part_number, "Sun 570X");
8197 return;
8198 }
8199
8200 for (i = 0; i < 256; i += 4) {
8201 u32 tmp;
8202
8203 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8204 goto out_not_found;
8205
8206 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
8207 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
8208 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8209 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8210 }
8211
8212 /* Now parse and find the part number. */
8213 for (i = 0; i < 256; ) {
8214 unsigned char val = vpd_data[i];
8215 int block_end;
8216
8217 if (val == 0x82 || val == 0x91) {
8218 i = (i + 3 +
8219 (vpd_data[i + 1] +
8220 (vpd_data[i + 2] << 8)));
8221 continue;
8222 }
8223
8224 if (val != 0x90)
8225 goto out_not_found;
8226
8227 block_end = (i + 3 +
8228 (vpd_data[i + 1] +
8229 (vpd_data[i + 2] << 8)));
8230 i += 3;
8231 while (i < block_end) {
8232 if (vpd_data[i + 0] == 'P' &&
8233 vpd_data[i + 1] == 'N') {
8234 int partno_len = vpd_data[i + 2];
8235
8236 if (partno_len > 24)
8237 goto out_not_found;
8238
8239 memcpy(tp->board_part_number,
8240 &vpd_data[i + 3],
8241 partno_len);
8242
8243 /* Success. */
8244 return;
8245 }
8246 }
8247
8248 /* Part number not found. */
8249 goto out_not_found;
8250 }
8251
8252 out_not_found:
8253 strcpy(tp->board_part_number, "none");
8254 }
8255
8256 #ifdef CONFIG_SPARC64
8257 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8258 {
8259 struct pci_dev *pdev = tp->pdev;
8260 struct pcidev_cookie *pcp = pdev->sysdata;
8261
8262 if (pcp != NULL) {
8263 int node = pcp->prom_node;
8264 u32 venid;
8265 int err;
8266
8267 err = prom_getproperty(node, "subsystem-vendor-id",
8268 (char *) &venid, sizeof(venid));
8269 if (err == 0 || err == -1)
8270 return 0;
8271 if (venid == PCI_VENDOR_ID_SUN)
8272 return 1;
8273 }
8274 return 0;
8275 }
8276 #endif
8277
8278 static int __devinit tg3_get_invariants(struct tg3 *tp)
8279 {
8280 static struct pci_device_id write_reorder_chipsets[] = {
8281 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8282 PCI_DEVICE_ID_INTEL_82801AA_8) },
8283 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8284 PCI_DEVICE_ID_INTEL_82801AB_8) },
8285 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8286 PCI_DEVICE_ID_INTEL_82801BA_11) },
8287 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8288 PCI_DEVICE_ID_INTEL_82801BA_6) },
8289 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8290 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8291 { },
8292 };
8293 u32 misc_ctrl_reg;
8294 u32 cacheline_sz_reg;
8295 u32 pci_state_reg, grc_misc_cfg;
8296 u32 val;
8297 u16 pci_cmd;
8298 int err;
8299
8300 #ifdef CONFIG_SPARC64
8301 if (tg3_is_sun_570X(tp))
8302 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8303 #endif
8304
8305 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8306 * reordering to the mailbox registers done by the host
8307 * controller can cause major troubles. We read back from
8308 * every mailbox register write to force the writes to be
8309 * posted to the chip in order.
8310 */
8311 if (pci_dev_present(write_reorder_chipsets))
8312 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8313
8314 /* Force memory write invalidate off. If we leave it on,
8315 * then on 5700_BX chips we have to enable a workaround.
8316 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8317 * to match the cacheline size. The Broadcom driver have this
8318 * workaround but turns MWI off all the times so never uses
8319 * it. This seems to suggest that the workaround is insufficient.
8320 */
8321 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8322 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8323 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8324
8325 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8326 * has the register indirect write enable bit set before
8327 * we try to access any of the MMIO registers. It is also
8328 * critical that the PCI-X hw workaround situation is decided
8329 * before that as well.
8330 */
8331 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8332 &misc_ctrl_reg);
8333
8334 tp->pci_chip_rev_id = (misc_ctrl_reg >>
8335 MISC_HOST_CTRL_CHIPREV_SHIFT);
8336
8337 /* Wrong chip ID in 5752 A0. This code can be removed later
8338 * as A0 is not in production.
8339 */
8340 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8341 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8342
8343 /* Initialize misc host control in PCI block. */
8344 tp->misc_host_ctrl |= (misc_ctrl_reg &
8345 MISC_HOST_CTRL_CHIPREV);
8346 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8347 tp->misc_host_ctrl);
8348
8349 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8350 &cacheline_sz_reg);
8351
8352 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
8353 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
8354 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
8355 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8356
8357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8359 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8360
8361 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8362 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8363 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8364
8365 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8366 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8367
8368 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8369 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8370
8371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8372 tp->pci_lat_timer < 64) {
8373 tp->pci_lat_timer = 64;
8374
8375 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
8376 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8377 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8378 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8379
8380 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8381 cacheline_sz_reg);
8382 }
8383
8384 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8385 &pci_state_reg);
8386
8387 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8388 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8389
8390 /* If this is a 5700 BX chipset, and we are in PCI-X
8391 * mode, enable register write workaround.
8392 *
8393 * The workaround is to use indirect register accesses
8394 * for all chip writes not to mailbox registers.
8395 */
8396 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8397 u32 pm_reg;
8398 u16 pci_cmd;
8399
8400 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8401
8402 /* The chip can have it's power management PCI config
8403 * space registers clobbered due to this bug.
8404 * So explicitly force the chip into D0 here.
8405 */
8406 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8407 &pm_reg);
8408 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8409 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8410 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8411 pm_reg);
8412
8413 /* Also, force SERR#/PERR# in PCI command. */
8414 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8415 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8416 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8417 }
8418 }
8419
8420 /* Back to back register writes can cause problems on this chip,
8421 * the workaround is to read back all reg writes except those to
8422 * mailbox regs. See tg3_write_indirect_reg32().
8423 *
8424 * PCI Express 5750_A0 rev chips need this workaround too.
8425 */
8426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8427 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8428 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8429 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8430
8431 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8432 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8433 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8434 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8435
8436 /* Chip-specific fixup from Broadcom driver */
8437 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8438 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8439 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8440 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8441 }
8442
8443 /* Get eeprom hw config before calling tg3_set_power_state().
8444 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8445 * determined before calling tg3_set_power_state() so that
8446 * we know whether or not to switch out of Vaux power.
8447 * When the flag is set, it means that GPIO1 is used for eeprom
8448 * write protect and also implies that it is a LOM where GPIOs
8449 * are not used to switch power.
8450 */
8451 tg3_get_eeprom_hw_cfg(tp);
8452
8453 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8454 * GPIO1 driven high will bring 5700's external PHY out of reset.
8455 * It is also used as eeprom write protect on LOMs.
8456 */
8457 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8458 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8459 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8460 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8461 GRC_LCLCTRL_GPIO_OUTPUT1);
8462 /* Unused GPIO3 must be driven as output on 5752 because there
8463 * are no pull-up resistors on unused GPIO pins.
8464 */
8465 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8466 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
8467
8468 /* Force the chip into D0. */
8469 err = tg3_set_power_state(tp, 0);
8470 if (err) {
8471 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8472 pci_name(tp->pdev));
8473 return err;
8474 }
8475
8476 /* 5700 B0 chips do not support checksumming correctly due
8477 * to hardware bugs.
8478 */
8479 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
8480 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
8481
8482 /* Pseudo-header checksum is done by hardware logic and not
8483 * the offload processers, so make the chip do the pseudo-
8484 * header checksums on receive. For transmit it is more
8485 * convenient to do the pseudo-header checksum in software
8486 * as Linux does that on transmit for us in all cases.
8487 */
8488 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
8489 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
8490
8491 /* Derive initial jumbo mode from MTU assigned in
8492 * ether_setup() via the alloc_etherdev() call
8493 */
8494 if (tp->dev->mtu > ETH_DATA_LEN)
8495 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
8496
8497 /* Determine WakeOnLan speed to use. */
8498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8499 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8500 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
8501 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
8502 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
8503 } else {
8504 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
8505 }
8506
8507 /* A few boards don't want Ethernet@WireSpeed phy feature */
8508 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8509 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
8510 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
8511 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
8512 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
8513
8514 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
8515 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
8516 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
8517 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
8518 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8519
8520 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8521 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8522
8523 tp->coalesce_mode = 0;
8524 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8525 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8526 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
8527
8528 /* Initialize MAC MI mode, polling disabled. */
8529 tw32_f(MAC_MI_MODE, tp->mi_mode);
8530 udelay(80);
8531
8532 /* Initialize data/descriptor byte/word swapping. */
8533 val = tr32(GRC_MODE);
8534 val &= GRC_MODE_HOST_STACKUP;
8535 tw32(GRC_MODE, val | tp->grc_mode);
8536
8537 tg3_switch_clocks(tp);
8538
8539 /* Clear this out for sanity. */
8540 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8541
8542 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8543 &pci_state_reg);
8544 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
8545 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
8546 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
8547
8548 if (chiprevid == CHIPREV_ID_5701_A0 ||
8549 chiprevid == CHIPREV_ID_5701_B0 ||
8550 chiprevid == CHIPREV_ID_5701_B2 ||
8551 chiprevid == CHIPREV_ID_5701_B5) {
8552 void __iomem *sram_base;
8553
8554 /* Write some dummy words into the SRAM status block
8555 * area, see if it reads back correctly. If the return
8556 * value is bad, force enable the PCIX workaround.
8557 */
8558 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
8559
8560 writel(0x00000000, sram_base);
8561 writel(0x00000000, sram_base + 4);
8562 writel(0xffffffff, sram_base + 4);
8563 if (readl(sram_base) != 0x00000000)
8564 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8565 }
8566 }
8567
8568 udelay(50);
8569 tg3_nvram_init(tp);
8570
8571 grc_misc_cfg = tr32(GRC_MISC_CFG);
8572 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
8573
8574 /* Broadcom's driver says that CIOBE multisplit has a bug */
8575 #if 0
8576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8577 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
8578 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
8579 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
8580 }
8581 #endif
8582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8583 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
8584 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8585 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8586
8587 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8588 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
8589 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
8590 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
8591 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
8592 HOSTCC_MODE_CLRTICK_TXBD);
8593
8594 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
8595 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8596 tp->misc_host_ctrl);
8597 }
8598
8599 /* these are limited to 10/100 only */
8600 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8601 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
8602 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8603 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8604 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
8605 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
8606 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
8607 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8608 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
8609 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
8610 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
8611
8612 err = tg3_phy_probe(tp);
8613 if (err) {
8614 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
8615 pci_name(tp->pdev), err);
8616 /* ... but do not return immediately ... */
8617 }
8618
8619 tg3_read_partno(tp);
8620
8621 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8622 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8623 } else {
8624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8625 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
8626 else
8627 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8628 }
8629
8630 /* 5700 {AX,BX} chips have a broken status block link
8631 * change bit implementation, so we must use the
8632 * status register in those cases.
8633 */
8634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8635 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
8636 else
8637 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
8638
8639 /* The led_ctrl is set during tg3_phy_probe, here we might
8640 * have to force the link status polling mechanism based
8641 * upon subsystem IDs.
8642 */
8643 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
8644 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8645 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
8646 TG3_FLAG_USE_LINKCHG_REG);
8647 }
8648
8649 /* For all SERDES we poll the MAC status register. */
8650 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8651 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
8652 else
8653 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
8654
8655 /* 5700 BX chips need to have their TX producer index mailboxes
8656 * written twice to workaround a bug.
8657 */
8658 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
8659 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
8660 else
8661 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
8662
8663 /* It seems all chips can get confused if TX buffers
8664 * straddle the 4GB address boundary in some cases.
8665 */
8666 tp->dev->hard_start_xmit = tg3_start_xmit;
8667
8668 tp->rx_offset = 2;
8669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
8670 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
8671 tp->rx_offset = 0;
8672
8673 /* By default, disable wake-on-lan. User can change this
8674 * using ETHTOOL_SWOL.
8675 */
8676 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8677
8678 return err;
8679 }
8680
8681 #ifdef CONFIG_SPARC64
8682 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
8683 {
8684 struct net_device *dev = tp->dev;
8685 struct pci_dev *pdev = tp->pdev;
8686 struct pcidev_cookie *pcp = pdev->sysdata;
8687
8688 if (pcp != NULL) {
8689 int node = pcp->prom_node;
8690
8691 if (prom_getproplen(node, "local-mac-address") == 6) {
8692 prom_getproperty(node, "local-mac-address",
8693 dev->dev_addr, 6);
8694 return 0;
8695 }
8696 }
8697 return -ENODEV;
8698 }
8699
8700 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
8701 {
8702 struct net_device *dev = tp->dev;
8703
8704 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
8705 return 0;
8706 }
8707 #endif
8708
8709 static int __devinit tg3_get_device_address(struct tg3 *tp)
8710 {
8711 struct net_device *dev = tp->dev;
8712 u32 hi, lo, mac_offset;
8713
8714 #ifdef CONFIG_SPARC64
8715 if (!tg3_get_macaddr_sparc(tp))
8716 return 0;
8717 #endif
8718
8719 mac_offset = 0x7c;
8720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8721 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
8722 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
8723 mac_offset = 0xcc;
8724 if (tg3_nvram_lock(tp))
8725 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
8726 else
8727 tg3_nvram_unlock(tp);
8728 }
8729
8730 /* First try to get it from MAC address mailbox. */
8731 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
8732 if ((hi >> 16) == 0x484b) {
8733 dev->dev_addr[0] = (hi >> 8) & 0xff;
8734 dev->dev_addr[1] = (hi >> 0) & 0xff;
8735
8736 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
8737 dev->dev_addr[2] = (lo >> 24) & 0xff;
8738 dev->dev_addr[3] = (lo >> 16) & 0xff;
8739 dev->dev_addr[4] = (lo >> 8) & 0xff;
8740 dev->dev_addr[5] = (lo >> 0) & 0xff;
8741 }
8742 /* Next, try NVRAM. */
8743 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
8744 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
8745 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
8746 dev->dev_addr[0] = ((hi >> 16) & 0xff);
8747 dev->dev_addr[1] = ((hi >> 24) & 0xff);
8748 dev->dev_addr[2] = ((lo >> 0) & 0xff);
8749 dev->dev_addr[3] = ((lo >> 8) & 0xff);
8750 dev->dev_addr[4] = ((lo >> 16) & 0xff);
8751 dev->dev_addr[5] = ((lo >> 24) & 0xff);
8752 }
8753 /* Finally just fetch it out of the MAC control regs. */
8754 else {
8755 hi = tr32(MAC_ADDR_0_HIGH);
8756 lo = tr32(MAC_ADDR_0_LOW);
8757
8758 dev->dev_addr[5] = lo & 0xff;
8759 dev->dev_addr[4] = (lo >> 8) & 0xff;
8760 dev->dev_addr[3] = (lo >> 16) & 0xff;
8761 dev->dev_addr[2] = (lo >> 24) & 0xff;
8762 dev->dev_addr[1] = hi & 0xff;
8763 dev->dev_addr[0] = (hi >> 8) & 0xff;
8764 }
8765
8766 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8767 #ifdef CONFIG_SPARC64
8768 if (!tg3_get_default_macaddr_sparc(tp))
8769 return 0;
8770 #endif
8771 return -EINVAL;
8772 }
8773 return 0;
8774 }
8775
8776 #define BOUNDARY_SINGLE_CACHELINE 1
8777 #define BOUNDARY_MULTI_CACHELINE 2
8778
8779 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
8780 {
8781 int cacheline_size;
8782 u8 byte;
8783 int goal;
8784
8785 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
8786 if (byte == 0)
8787 cacheline_size = 1024;
8788 else
8789 cacheline_size = (int) byte * 4;
8790
8791 /* On 5703 and later chips, the boundary bits have no
8792 * effect.
8793 */
8794 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8795 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
8796 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8797 goto out;
8798
8799 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
8800 goal = BOUNDARY_MULTI_CACHELINE;
8801 #else
8802 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
8803 goal = BOUNDARY_SINGLE_CACHELINE;
8804 #else
8805 goal = 0;
8806 #endif
8807 #endif
8808
8809 if (!goal)
8810 goto out;
8811
8812 /* PCI controllers on most RISC systems tend to disconnect
8813 * when a device tries to burst across a cache-line boundary.
8814 * Therefore, letting tg3 do so just wastes PCI bandwidth.
8815 *
8816 * Unfortunately, for PCI-E there are only limited
8817 * write-side controls for this, and thus for reads
8818 * we will still get the disconnects. We'll also waste
8819 * these PCI cycles for both read and write for chips
8820 * other than 5700 and 5701 which do not implement the
8821 * boundary bits.
8822 */
8823 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8824 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8825 switch (cacheline_size) {
8826 case 16:
8827 case 32:
8828 case 64:
8829 case 128:
8830 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8831 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
8832 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
8833 } else {
8834 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
8835 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
8836 }
8837 break;
8838
8839 case 256:
8840 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
8841 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
8842 break;
8843
8844 default:
8845 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
8846 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
8847 break;
8848 };
8849 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8850 switch (cacheline_size) {
8851 case 16:
8852 case 32:
8853 case 64:
8854 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8855 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
8856 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
8857 break;
8858 }
8859 /* fallthrough */
8860 case 128:
8861 default:
8862 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
8863 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
8864 break;
8865 };
8866 } else {
8867 switch (cacheline_size) {
8868 case 16:
8869 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8870 val |= (DMA_RWCTRL_READ_BNDRY_16 |
8871 DMA_RWCTRL_WRITE_BNDRY_16);
8872 break;
8873 }
8874 /* fallthrough */
8875 case 32:
8876 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8877 val |= (DMA_RWCTRL_READ_BNDRY_32 |
8878 DMA_RWCTRL_WRITE_BNDRY_32);
8879 break;
8880 }
8881 /* fallthrough */
8882 case 64:
8883 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8884 val |= (DMA_RWCTRL_READ_BNDRY_64 |
8885 DMA_RWCTRL_WRITE_BNDRY_64);
8886 break;
8887 }
8888 /* fallthrough */
8889 case 128:
8890 if (goal == BOUNDARY_SINGLE_CACHELINE) {
8891 val |= (DMA_RWCTRL_READ_BNDRY_128 |
8892 DMA_RWCTRL_WRITE_BNDRY_128);
8893 break;
8894 }
8895 /* fallthrough */
8896 case 256:
8897 val |= (DMA_RWCTRL_READ_BNDRY_256 |
8898 DMA_RWCTRL_WRITE_BNDRY_256);
8899 break;
8900 case 512:
8901 val |= (DMA_RWCTRL_READ_BNDRY_512 |
8902 DMA_RWCTRL_WRITE_BNDRY_512);
8903 break;
8904 case 1024:
8905 default:
8906 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
8907 DMA_RWCTRL_WRITE_BNDRY_1024);
8908 break;
8909 };
8910 }
8911
8912 out:
8913 return val;
8914 }
8915
8916 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
8917 {
8918 struct tg3_internal_buffer_desc test_desc;
8919 u32 sram_dma_descs;
8920 int i, ret;
8921
8922 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
8923
8924 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
8925 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
8926 tw32(RDMAC_STATUS, 0);
8927 tw32(WDMAC_STATUS, 0);
8928
8929 tw32(BUFMGR_MODE, 0);
8930 tw32(FTQ_RESET, 0);
8931
8932 test_desc.addr_hi = ((u64) buf_dma) >> 32;
8933 test_desc.addr_lo = buf_dma & 0xffffffff;
8934 test_desc.nic_mbuf = 0x00002100;
8935 test_desc.len = size;
8936
8937 /*
8938 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
8939 * the *second* time the tg3 driver was getting loaded after an
8940 * initial scan.
8941 *
8942 * Broadcom tells me:
8943 * ...the DMA engine is connected to the GRC block and a DMA
8944 * reset may affect the GRC block in some unpredictable way...
8945 * The behavior of resets to individual blocks has not been tested.
8946 *
8947 * Broadcom noted the GRC reset will also reset all sub-components.
8948 */
8949 if (to_device) {
8950 test_desc.cqid_sqid = (13 << 8) | 2;
8951
8952 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
8953 udelay(40);
8954 } else {
8955 test_desc.cqid_sqid = (16 << 8) | 7;
8956
8957 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
8958 udelay(40);
8959 }
8960 test_desc.flags = 0x00000005;
8961
8962 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
8963 u32 val;
8964
8965 val = *(((u32 *)&test_desc) + i);
8966 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
8967 sram_dma_descs + (i * sizeof(u32)));
8968 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
8969 }
8970 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
8971
8972 if (to_device) {
8973 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
8974 } else {
8975 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
8976 }
8977
8978 ret = -ENODEV;
8979 for (i = 0; i < 40; i++) {
8980 u32 val;
8981
8982 if (to_device)
8983 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
8984 else
8985 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
8986 if ((val & 0xffff) == sram_dma_descs) {
8987 ret = 0;
8988 break;
8989 }
8990
8991 udelay(100);
8992 }
8993
8994 return ret;
8995 }
8996
8997 #define TEST_BUFFER_SIZE 0x400
8998
8999 static int __devinit tg3_test_dma(struct tg3 *tp)
9000 {
9001 dma_addr_t buf_dma;
9002 u32 *buf, saved_dma_rwctrl;
9003 int ret;
9004
9005 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9006 if (!buf) {
9007 ret = -ENOMEM;
9008 goto out_nofree;
9009 }
9010
9011 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9012 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9013
9014 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
9015
9016 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9017 /* DMA read watermark not used on PCIE */
9018 tp->dma_rwctrl |= 0x00180000;
9019 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
9020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
9022 tp->dma_rwctrl |= 0x003f0000;
9023 else
9024 tp->dma_rwctrl |= 0x003f000f;
9025 } else {
9026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9028 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9029
9030 if (ccval == 0x6 || ccval == 0x7)
9031 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9032
9033 /* Set bit 23 to enable PCIX hw bug fix */
9034 tp->dma_rwctrl |= 0x009f0000;
9035 } else {
9036 tp->dma_rwctrl |= 0x001b000f;
9037 }
9038 }
9039
9040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9042 tp->dma_rwctrl &= 0xfffffff0;
9043
9044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9046 /* Remove this if it causes problems for some boards. */
9047 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9048
9049 /* On 5700/5701 chips, we need to set this bit.
9050 * Otherwise the chip will issue cacheline transactions
9051 * to streamable DMA memory with not all the byte
9052 * enables turned on. This is an error on several
9053 * RISC PCI controllers, in particular sparc64.
9054 *
9055 * On 5703/5704 chips, this bit has been reassigned
9056 * a different meaning. In particular, it is used
9057 * on those chips to enable a PCI-X workaround.
9058 */
9059 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9060 }
9061
9062 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9063
9064 #if 0
9065 /* Unneeded, already done by tg3_get_invariants. */
9066 tg3_switch_clocks(tp);
9067 #endif
9068
9069 ret = 0;
9070 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9071 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9072 goto out;
9073
9074 /* It is best to perform DMA test with maximum write burst size
9075 * to expose the 5700/5701 write DMA bug.
9076 */
9077 saved_dma_rwctrl = tp->dma_rwctrl;
9078 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9079 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9080
9081 while (1) {
9082 u32 *p = buf, i;
9083
9084 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9085 p[i] = i;
9086
9087 /* Send the buffer to the chip. */
9088 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9089 if (ret) {
9090 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9091 break;
9092 }
9093
9094 #if 0
9095 /* validate data reached card RAM correctly. */
9096 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9097 u32 val;
9098 tg3_read_mem(tp, 0x2100 + (i*4), &val);
9099 if (le32_to_cpu(val) != p[i]) {
9100 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
9101 /* ret = -ENODEV here? */
9102 }
9103 p[i] = 0;
9104 }
9105 #endif
9106 /* Now read it back. */
9107 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9108 if (ret) {
9109 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9110
9111 break;
9112 }
9113
9114 /* Verify it. */
9115 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9116 if (p[i] == i)
9117 continue;
9118
9119 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9120 DMA_RWCTRL_WRITE_BNDRY_16) {
9121 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9122 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9123 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9124 break;
9125 } else {
9126 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9127 ret = -ENODEV;
9128 goto out;
9129 }
9130 }
9131
9132 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9133 /* Success. */
9134 ret = 0;
9135 break;
9136 }
9137 }
9138 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9139 DMA_RWCTRL_WRITE_BNDRY_16) {
9140 /* DMA test passed without adjusting DMA boundary,
9141 * just restore the calculated DMA boundary
9142 */
9143 tp->dma_rwctrl = saved_dma_rwctrl;
9144 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9145 }
9146
9147 out:
9148 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9149 out_nofree:
9150 return ret;
9151 }
9152
9153 static void __devinit tg3_init_link_config(struct tg3 *tp)
9154 {
9155 tp->link_config.advertising =
9156 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9157 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9158 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9159 ADVERTISED_Autoneg | ADVERTISED_MII);
9160 tp->link_config.speed = SPEED_INVALID;
9161 tp->link_config.duplex = DUPLEX_INVALID;
9162 tp->link_config.autoneg = AUTONEG_ENABLE;
9163 netif_carrier_off(tp->dev);
9164 tp->link_config.active_speed = SPEED_INVALID;
9165 tp->link_config.active_duplex = DUPLEX_INVALID;
9166 tp->link_config.phy_is_low_power = 0;
9167 tp->link_config.orig_speed = SPEED_INVALID;
9168 tp->link_config.orig_duplex = DUPLEX_INVALID;
9169 tp->link_config.orig_autoneg = AUTONEG_INVALID;
9170 }
9171
9172 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9173 {
9174 tp->bufmgr_config.mbuf_read_dma_low_water =
9175 DEFAULT_MB_RDMA_LOW_WATER;
9176 tp->bufmgr_config.mbuf_mac_rx_low_water =
9177 DEFAULT_MB_MACRX_LOW_WATER;
9178 tp->bufmgr_config.mbuf_high_water =
9179 DEFAULT_MB_HIGH_WATER;
9180
9181 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9182 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9183 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9184 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9185 tp->bufmgr_config.mbuf_high_water_jumbo =
9186 DEFAULT_MB_HIGH_WATER_JUMBO;
9187
9188 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9189 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9190 }
9191
9192 static char * __devinit tg3_phy_string(struct tg3 *tp)
9193 {
9194 switch (tp->phy_id & PHY_ID_MASK) {
9195 case PHY_ID_BCM5400: return "5400";
9196 case PHY_ID_BCM5401: return "5401";
9197 case PHY_ID_BCM5411: return "5411";
9198 case PHY_ID_BCM5701: return "5701";
9199 case PHY_ID_BCM5703: return "5703";
9200 case PHY_ID_BCM5704: return "5704";
9201 case PHY_ID_BCM5705: return "5705";
9202 case PHY_ID_BCM5750: return "5750";
9203 case PHY_ID_BCM5752: return "5752";
9204 case PHY_ID_BCM8002: return "8002/serdes";
9205 case 0: return "serdes";
9206 default: return "unknown";
9207 };
9208 }
9209
9210 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9211 {
9212 struct pci_dev *peer;
9213 unsigned int func, devnr = tp->pdev->devfn & ~7;
9214
9215 for (func = 0; func < 8; func++) {
9216 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9217 if (peer && peer != tp->pdev)
9218 break;
9219 pci_dev_put(peer);
9220 }
9221 if (!peer || peer == tp->pdev)
9222 BUG();
9223
9224 /*
9225 * We don't need to keep the refcount elevated; there's no way
9226 * to remove one half of this device without removing the other
9227 */
9228 pci_dev_put(peer);
9229
9230 return peer;
9231 }
9232
9233 static void __devinit tg3_init_coal(struct tg3 *tp)
9234 {
9235 struct ethtool_coalesce *ec = &tp->coal;
9236
9237 memset(ec, 0, sizeof(*ec));
9238 ec->cmd = ETHTOOL_GCOALESCE;
9239 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9240 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9241 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9242 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9243 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9244 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9245 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9246 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9247 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9248
9249 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9250 HOSTCC_MODE_CLRTICK_TXBD)) {
9251 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9252 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9253 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9254 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9255 }
9256 }
9257
9258 static int __devinit tg3_init_one(struct pci_dev *pdev,
9259 const struct pci_device_id *ent)
9260 {
9261 static int tg3_version_printed = 0;
9262 unsigned long tg3reg_base, tg3reg_len;
9263 struct net_device *dev;
9264 struct tg3 *tp;
9265 int i, err, pci_using_dac, pm_cap;
9266
9267 if (tg3_version_printed++ == 0)
9268 printk(KERN_INFO "%s", version);
9269
9270 err = pci_enable_device(pdev);
9271 if (err) {
9272 printk(KERN_ERR PFX "Cannot enable PCI device, "
9273 "aborting.\n");
9274 return err;
9275 }
9276
9277 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9278 printk(KERN_ERR PFX "Cannot find proper PCI device "
9279 "base address, aborting.\n");
9280 err = -ENODEV;
9281 goto err_out_disable_pdev;
9282 }
9283
9284 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9285 if (err) {
9286 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9287 "aborting.\n");
9288 goto err_out_disable_pdev;
9289 }
9290
9291 pci_set_master(pdev);
9292
9293 /* Find power-management capability. */
9294 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9295 if (pm_cap == 0) {
9296 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9297 "aborting.\n");
9298 err = -EIO;
9299 goto err_out_free_res;
9300 }
9301
9302 /* Configure DMA attributes. */
9303 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9304 if (!err) {
9305 pci_using_dac = 1;
9306 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9307 if (err < 0) {
9308 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9309 "for consistent allocations\n");
9310 goto err_out_free_res;
9311 }
9312 } else {
9313 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9314 if (err) {
9315 printk(KERN_ERR PFX "No usable DMA configuration, "
9316 "aborting.\n");
9317 goto err_out_free_res;
9318 }
9319 pci_using_dac = 0;
9320 }
9321
9322 tg3reg_base = pci_resource_start(pdev, 0);
9323 tg3reg_len = pci_resource_len(pdev, 0);
9324
9325 dev = alloc_etherdev(sizeof(*tp));
9326 if (!dev) {
9327 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9328 err = -ENOMEM;
9329 goto err_out_free_res;
9330 }
9331
9332 SET_MODULE_OWNER(dev);
9333 SET_NETDEV_DEV(dev, &pdev->dev);
9334
9335 if (pci_using_dac)
9336 dev->features |= NETIF_F_HIGHDMA;
9337 dev->features |= NETIF_F_LLTX;
9338 #if TG3_VLAN_TAG_USED
9339 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9340 dev->vlan_rx_register = tg3_vlan_rx_register;
9341 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9342 #endif
9343
9344 tp = netdev_priv(dev);
9345 tp->pdev = pdev;
9346 tp->dev = dev;
9347 tp->pm_cap = pm_cap;
9348 tp->mac_mode = TG3_DEF_MAC_MODE;
9349 tp->rx_mode = TG3_DEF_RX_MODE;
9350 tp->tx_mode = TG3_DEF_TX_MODE;
9351 tp->mi_mode = MAC_MI_MODE_BASE;
9352 if (tg3_debug > 0)
9353 tp->msg_enable = tg3_debug;
9354 else
9355 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9356
9357 /* The word/byte swap controls here control register access byte
9358 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9359 * setting below.
9360 */
9361 tp->misc_host_ctrl =
9362 MISC_HOST_CTRL_MASK_PCI_INT |
9363 MISC_HOST_CTRL_WORD_SWAP |
9364 MISC_HOST_CTRL_INDIR_ACCESS |
9365 MISC_HOST_CTRL_PCISTATE_RW;
9366
9367 /* The NONFRM (non-frame) byte/word swap controls take effect
9368 * on descriptor entries, anything which isn't packet data.
9369 *
9370 * The StrongARM chips on the board (one for tx, one for rx)
9371 * are running in big-endian mode.
9372 */
9373 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9374 GRC_MODE_WSWAP_NONFRM_DATA);
9375 #ifdef __BIG_ENDIAN
9376 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9377 #endif
9378 spin_lock_init(&tp->lock);
9379 spin_lock_init(&tp->tx_lock);
9380 spin_lock_init(&tp->indirect_lock);
9381 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9382
9383 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9384 if (tp->regs == 0UL) {
9385 printk(KERN_ERR PFX "Cannot map device registers, "
9386 "aborting.\n");
9387 err = -ENOMEM;
9388 goto err_out_free_dev;
9389 }
9390
9391 tg3_init_link_config(tp);
9392
9393 tg3_init_bufmgr_config(tp);
9394
9395 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9396 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9397 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9398
9399 dev->open = tg3_open;
9400 dev->stop = tg3_close;
9401 dev->get_stats = tg3_get_stats;
9402 dev->set_multicast_list = tg3_set_rx_mode;
9403 dev->set_mac_address = tg3_set_mac_addr;
9404 dev->do_ioctl = tg3_ioctl;
9405 dev->tx_timeout = tg3_tx_timeout;
9406 dev->poll = tg3_poll;
9407 dev->ethtool_ops = &tg3_ethtool_ops;
9408 dev->weight = 64;
9409 dev->watchdog_timeo = TG3_TX_TIMEOUT;
9410 dev->change_mtu = tg3_change_mtu;
9411 dev->irq = pdev->irq;
9412 #ifdef CONFIG_NET_POLL_CONTROLLER
9413 dev->poll_controller = tg3_poll_controller;
9414 #endif
9415
9416 err = tg3_get_invariants(tp);
9417 if (err) {
9418 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9419 "aborting.\n");
9420 goto err_out_iounmap;
9421 }
9422
9423 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9424 tp->bufmgr_config.mbuf_read_dma_low_water =
9425 DEFAULT_MB_RDMA_LOW_WATER_5705;
9426 tp->bufmgr_config.mbuf_mac_rx_low_water =
9427 DEFAULT_MB_MACRX_LOW_WATER_5705;
9428 tp->bufmgr_config.mbuf_high_water =
9429 DEFAULT_MB_HIGH_WATER_5705;
9430 }
9431
9432 #if TG3_TSO_SUPPORT != 0
9433 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9434 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9435 }
9436 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9438 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9439 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9440 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9441 } else {
9442 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9443 }
9444
9445 /* TSO is off by default, user can enable using ethtool. */
9446 #if 0
9447 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9448 dev->features |= NETIF_F_TSO;
9449 #endif
9450
9451 #endif
9452
9453 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
9454 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
9455 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
9456 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
9457 tp->rx_pending = 63;
9458 }
9459
9460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9461 tp->pdev_peer = tg3_find_5704_peer(tp);
9462
9463 err = tg3_get_device_address(tp);
9464 if (err) {
9465 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
9466 "aborting.\n");
9467 goto err_out_iounmap;
9468 }
9469
9470 /*
9471 * Reset chip in case UNDI or EFI driver did not shutdown
9472 * DMA self test will enable WDMAC and we'll see (spurious)
9473 * pending DMA on the PCI bus at that point.
9474 */
9475 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
9476 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9477 pci_save_state(tp->pdev);
9478 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
9479 tg3_halt(tp, 1);
9480 }
9481
9482 err = tg3_test_dma(tp);
9483 if (err) {
9484 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
9485 goto err_out_iounmap;
9486 }
9487
9488 /* Tigon3 can do ipv4 only... and some chips have buggy
9489 * checksumming.
9490 */
9491 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
9492 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
9493 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9494 } else
9495 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9496
9497 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
9498 dev->features &= ~NETIF_F_HIGHDMA;
9499
9500 /* flow control autonegotiation is default behavior */
9501 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9502
9503 tg3_init_coal(tp);
9504
9505 err = register_netdev(dev);
9506 if (err) {
9507 printk(KERN_ERR PFX "Cannot register net device, "
9508 "aborting.\n");
9509 goto err_out_iounmap;
9510 }
9511
9512 pci_set_drvdata(pdev, dev);
9513
9514 /* Now that we have fully setup the chip, save away a snapshot
9515 * of the PCI config space. We need to restore this after
9516 * GRC_MISC_CFG core clock resets and some resume events.
9517 */
9518 pci_save_state(tp->pdev);
9519
9520 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
9521 dev->name,
9522 tp->board_part_number,
9523 tp->pci_chip_rev_id,
9524 tg3_phy_string(tp),
9525 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
9526 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
9527 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
9528 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
9529 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
9530 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
9531
9532 for (i = 0; i < 6; i++)
9533 printk("%2.2x%c", dev->dev_addr[i],
9534 i == 5 ? '\n' : ':');
9535
9536 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
9537 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9538 "TSOcap[%d] \n",
9539 dev->name,
9540 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
9541 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
9542 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
9543 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
9544 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9545 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9546 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
9547 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
9548 dev->name, tp->dma_rwctrl);
9549
9550 return 0;
9551
9552 err_out_iounmap:
9553 iounmap(tp->regs);
9554
9555 err_out_free_dev:
9556 free_netdev(dev);
9557
9558 err_out_free_res:
9559 pci_release_regions(pdev);
9560
9561 err_out_disable_pdev:
9562 pci_disable_device(pdev);
9563 pci_set_drvdata(pdev, NULL);
9564 return err;
9565 }
9566
9567 static void __devexit tg3_remove_one(struct pci_dev *pdev)
9568 {
9569 struct net_device *dev = pci_get_drvdata(pdev);
9570
9571 if (dev) {
9572 struct tg3 *tp = netdev_priv(dev);
9573
9574 unregister_netdev(dev);
9575 iounmap(tp->regs);
9576 free_netdev(dev);
9577 pci_release_regions(pdev);
9578 pci_disable_device(pdev);
9579 pci_set_drvdata(pdev, NULL);
9580 }
9581 }
9582
9583 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9584 {
9585 struct net_device *dev = pci_get_drvdata(pdev);
9586 struct tg3 *tp = netdev_priv(dev);
9587 int err;
9588
9589 if (!netif_running(dev))
9590 return 0;
9591
9592 tg3_netif_stop(tp);
9593
9594 del_timer_sync(&tp->timer);
9595
9596 spin_lock_irq(&tp->lock);
9597 spin_lock(&tp->tx_lock);
9598 tg3_disable_ints(tp);
9599 spin_unlock(&tp->tx_lock);
9600 spin_unlock_irq(&tp->lock);
9601
9602 netif_device_detach(dev);
9603
9604 spin_lock_irq(&tp->lock);
9605 spin_lock(&tp->tx_lock);
9606 tg3_halt(tp, 1);
9607 spin_unlock(&tp->tx_lock);
9608 spin_unlock_irq(&tp->lock);
9609
9610 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9611 if (err) {
9612 spin_lock_irq(&tp->lock);
9613 spin_lock(&tp->tx_lock);
9614
9615 tg3_init_hw(tp);
9616
9617 tp->timer.expires = jiffies + tp->timer_offset;
9618 add_timer(&tp->timer);
9619
9620 netif_device_attach(dev);
9621 tg3_netif_start(tp);
9622
9623 spin_unlock(&tp->tx_lock);
9624 spin_unlock_irq(&tp->lock);
9625 }
9626
9627 return err;
9628 }
9629
9630 static int tg3_resume(struct pci_dev *pdev)
9631 {
9632 struct net_device *dev = pci_get_drvdata(pdev);
9633 struct tg3 *tp = netdev_priv(dev);
9634 int err;
9635
9636 if (!netif_running(dev))
9637 return 0;
9638
9639 pci_restore_state(tp->pdev);
9640
9641 err = tg3_set_power_state(tp, 0);
9642 if (err)
9643 return err;
9644
9645 netif_device_attach(dev);
9646
9647 spin_lock_irq(&tp->lock);
9648 spin_lock(&tp->tx_lock);
9649
9650 tg3_init_hw(tp);
9651
9652 tp->timer.expires = jiffies + tp->timer_offset;
9653 add_timer(&tp->timer);
9654
9655 tg3_enable_ints(tp);
9656
9657 tg3_netif_start(tp);
9658
9659 spin_unlock(&tp->tx_lock);
9660 spin_unlock_irq(&tp->lock);
9661
9662 return 0;
9663 }
9664
9665 static struct pci_driver tg3_driver = {
9666 .name = DRV_MODULE_NAME,
9667 .id_table = tg3_pci_tbl,
9668 .probe = tg3_init_one,
9669 .remove = __devexit_p(tg3_remove_one),
9670 .suspend = tg3_suspend,
9671 .resume = tg3_resume
9672 };
9673
9674 static int __init tg3_init(void)
9675 {
9676 return pci_module_init(&tg3_driver);
9677 }
9678
9679 static void __exit tg3_cleanup(void)
9680 {
9681 pci_unregister_driver(&tg3_driver);
9682 }
9683
9684 module_init(tg3_init);
9685 module_exit(tg3_cleanup);
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