| blob | 810ec700d9fc2b08d813c96c4e83c8a5dc5bc148 |
1 /*
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD$
41 */
42 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#39 $"
44 /*
45 * This file is processed by the aic7xxx_asm utility for use in assembling
46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
47 * a C header file for use in the kernel portion of the Aic7xxx driver.
48 *
49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
50 * Adaptec's Technical Documents Department 1-800-934-2766
51 */
53 /*
54 * SCSI Sequence Control (p. 3-11).
55 * Each bit, when set starts a specific SCSI sequence on the bus
56 */
57 register SCSISEQ {
58 address 0x000
59 access_mode RW
60 field TEMODE 0x80
61 field ENSELO 0x40
62 field ENSELI 0x20
63 field ENRSELI 0x10
64 field ENAUTOATNO 0x08
65 field ENAUTOATNI 0x04
66 field ENAUTOATNP 0x02
67 field SCSIRSTO 0x01
68 }
70 /*
71 * SCSI Transfer Control 0 Register (pp. 3-13).
72 * Controls the SCSI module data path.
73 */
74 register SXFRCTL0 {
75 address 0x001
76 access_mode RW
77 field DFON 0x80
78 field DFPEXP 0x40
79 field FAST20 0x20
80 field CLRSTCNT 0x10
81 field SPIOEN 0x08
82 field SCAMEN 0x04
83 field CLRCHN 0x02
84 }
86 /*
87 * SCSI Transfer Control 1 Register (pp. 3-14,15).
88 * Controls the SCSI module data path.
89 */
90 register SXFRCTL1 {
91 address 0x002
92 access_mode RW
93 field BITBUCKET 0x80
94 field SWRAPEN 0x40
95 field ENSPCHK 0x20
96 mask STIMESEL 0x18
97 field ENSTIMER 0x04
98 field ACTNEGEN 0x02
99 field STPWEN 0x01 /* Powered Termination */
100 }
102 /*
103 * SCSI Control Signal Read Register (p. 3-15).
104 * Reads the actual state of the SCSI bus pins
105 */
106 register SCSISIGI {
107 address 0x003
108 access_mode RO
109 field CDI 0x80
110 field IOI 0x40
111 field MSGI 0x20
112 field ATNI 0x10
113 field SELI 0x08
114 field BSYI 0x04
115 field REQI 0x02
116 field ACKI 0x01
117 /*
118 * Possible phases in SCSISIGI
119 */
120 mask PHASE_MASK CDI|IOI|MSGI
121 mask P_DATAOUT 0x00
122 mask P_DATAIN IOI
123 mask P_DATAOUT_DT P_DATAOUT|MSGI
124 mask P_DATAIN_DT P_DATAIN|MSGI
125 mask P_COMMAND CDI
126 mask P_MESGOUT CDI|MSGI
127 mask P_STATUS CDI|IOI
128 mask P_MESGIN CDI|IOI|MSGI
129 }
131 /*
132 * SCSI Control Signal Write Register (p. 3-16).
133 * Writing to this register modifies the control signals on the bus. Only
134 * those signals that are allowed in the current mode (Initiator/Target) are
135 * asserted.
136 */
137 register SCSISIGO {
138 address 0x003
139 access_mode WO
140 field CDO 0x80
141 field IOO 0x40
142 field MSGO 0x20
143 field ATNO 0x10
144 field SELO 0x08
145 field BSYO 0x04
146 field REQO 0x02
147 field ACKO 0x01
148 /*
149 * Possible phases to write into SCSISIG0
150 */
151 mask PHASE_MASK CDI|IOI|MSGI
152 mask P_DATAOUT 0x00
153 mask P_DATAIN IOI
154 mask P_COMMAND CDI
155 mask P_MESGOUT CDI|MSGI
156 mask P_STATUS CDI|IOI
157 mask P_MESGIN CDI|IOI|MSGI
158 }
160 /*
161 * SCSI Rate Control (p. 3-17).
162 * Contents of this register determine the Synchronous SCSI data transfer
163 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
164 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
165 * greater than 0 enables synchronous transfers.
166 */
167 register SCSIRATE {
168 address 0x004
169 access_mode RW
170 field WIDEXFER 0x80 /* Wide transfer control */
171 field ENABLE_CRC 0x40 /* CRC for D-Phases */
172 field SINGLE_EDGE 0x10 /* Disable DT Transfers */
173 mask SXFR 0x70 /* Sync transfer rate */
174 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
175 mask SOFS 0x0f /* Sync offset */
176 }
178 /*
179 * SCSI ID (p. 3-18).
180 * Contains the ID of the board and the current target on the
181 * selected channel.
182 */
183 register SCSIID {
184 address 0x005
185 access_mode RW
186 mask TID 0xf0 /* Target ID mask */
187 mask TWIN_TID 0x70
188 field TWIN_CHNLB 0x80
189 mask OID 0x0f /* Our ID mask */
190 /*
191 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
192 * The aic7890/91 allow an offset of up to 127 transfers in both wide
193 * and narrow mode.
194 */
195 alias SCSIOFFSET
196 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
197 }
199 /*
200 * SCSI Latched Data (p. 3-19).
201 * Read/Write latches used to transfer data on the SCSI bus during
202 * Automatic or Manual PIO mode. SCSIDATH can be used for the
203 * upper byte of a 16bit wide asynchronouse data phase transfer.
204 */
205 register SCSIDATL {
206 address 0x006
207 access_mode RW
208 }
210 register SCSIDATH {
211 address 0x007
212 access_mode RW
213 }
215 /*
216 * SCSI Transfer Count (pp. 3-19,20)
217 * These registers count down the number of bytes transferred
218 * across the SCSI bus. The counter is decremented only once
219 * the data has been safely transferred. SDONE in SSTAT0 is
220 * set when STCNT goes to 0
221 */
222 register STCNT {
223 address 0x008
224 size 3
225 access_mode RW
226 }
228 /* ALT_MODE registers (Ultra2 and Ultra160 chips) */
229 register SXFRCTL2 {
230 address 0x013
231 access_mode RW
232 field AUTORSTDIS 0x10
233 field CMDDMAEN 0x08
234 mask ASYNC_SETUP 0x07
235 }
237 /* ALT_MODE register on Ultra160 chips */
238 register OPTIONMODE {
239 address 0x008
240 access_mode RW
241 field AUTORATEEN 0x80
242 field AUTOACKEN 0x40
243 field ATNMGMNTEN 0x20
244 field BUSFREEREV 0x10
245 field EXPPHASEDIS 0x08
246 field SCSIDATL_IMGEN 0x04
247 field AUTO_MSGOUT_DE 0x02
248 field DIS_MSGIN_DUALEDGE 0x01
249 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
250 }
252 /* ALT_MODE register on Ultra160 chips */
253 register TARGCRCCNT {
254 address 0x00a
255 size 2
256 access_mode RW
257 }
259 /*
260 * Clear SCSI Interrupt 0 (p. 3-20)
261 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
262 */
263 register CLRSINT0 {
264 address 0x00b
265 access_mode WO
266 field CLRSELDO 0x40
267 field CLRSELDI 0x20
268 field CLRSELINGO 0x10
269 field CLRSWRAP 0x08
270 field CLRIOERR 0x08 /* Ultra2 Only */
271 field CLRSPIORDY 0x02
272 }
274 /*
275 * SCSI Status 0 (p. 3-21)
276 * Contains one set of SCSI Interrupt codes
277 * These are most likely of interest to the sequencer
278 */
279 register SSTAT0 {
280 address 0x00b
281 access_mode RO
282 field TARGET 0x80 /* Board acting as target */
283 field SELDO 0x40 /* Selection Done */
284 field SELDI 0x20 /* Board has been selected */
285 field SELINGO 0x10 /* Selection In Progress */
286 field SWRAP 0x08 /* 24bit counter wrap */
287 field IOERR 0x08 /* LVD Tranceiver mode changed */
288 field SDONE 0x04 /* STCNT = 0x000000 */
289 field SPIORDY 0x02 /* SCSI PIO Ready */
290 field DMADONE 0x01 /* DMA transfer completed */
291 }
293 /*
294 * Clear SCSI Interrupt 1 (p. 3-23)
295 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
296 */
297 register CLRSINT1 {
298 address 0x00c
299 access_mode WO
300 field CLRSELTIMEO 0x80
301 field CLRATNO 0x40
302 field CLRSCSIRSTI 0x20
303 field CLRBUSFREE 0x08
304 field CLRSCSIPERR 0x04
305 field CLRPHASECHG 0x02
306 field CLRREQINIT 0x01
307 }
309 /*
310 * SCSI Status 1 (p. 3-24)
311 */
312 register SSTAT1 {
313 address 0x00c
314 access_mode RO
315 field SELTO 0x80
316 field ATNTARG 0x40
317 field SCSIRSTI 0x20
318 field PHASEMIS 0x10
319 field BUSFREE 0x08
320 field SCSIPERR 0x04
321 field PHASECHG 0x02
322 field REQINIT 0x01
323 }
325 /*
326 * SCSI Status 2 (pp. 3-25,26)
327 */
328 register SSTAT2 {
329 address 0x00d
330 access_mode RO
331 field OVERRUN 0x80
332 field SHVALID 0x40 /* Shaddow Layer non-zero */
333 field EXP_ACTIVE 0x10 /* SCSI Expander Active */
334 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
335 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
336 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
337 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
338 mask SFCNT 0x1f
339 }
341 /*
342 * SCSI Status 3 (p. 3-26)
343 */
344 register SSTAT3 {
345 address 0x00e
346 access_mode RO
347 mask SCSICNT 0xf0
348 mask OFFCNT 0x0f
349 mask U2OFFCNT 0x7f
350 }
352 /*
353 * SCSI ID for the aic7890/91 chips
354 */
355 register SCSIID_ULTRA2 {
356 address 0x00f
357 access_mode RW
358 mask TID 0xf0 /* Target ID mask */
359 mask OID 0x0f /* Our ID mask */
360 }
362 /*
363 * SCSI Interrupt Mode 1 (p. 3-28)
364 * Setting any bit will enable the corresponding function
365 * in SIMODE0 to interrupt via the IRQ pin.
366 */
367 register SIMODE0 {
368 address 0x010
369 access_mode RW
370 field ENSELDO 0x40
371 field ENSELDI 0x20
372 field ENSELINGO 0x10
373 field ENSWRAP 0x08
374 field ENIOERR 0x08 /* LVD Tranceiver mode changes */
375 field ENSDONE 0x04
376 field ENSPIORDY 0x02
377 field ENDMADONE 0x01
378 }
380 /*
381 * SCSI Interrupt Mode 1 (pp. 3-28,29)
382 * Setting any bit will enable the corresponding function
383 * in SIMODE1 to interrupt via the IRQ pin.
384 */
385 register SIMODE1 {
386 address 0x011
387 access_mode RW
388 field ENSELTIMO 0x80
389 field ENATNTARG 0x40
390 field ENSCSIRST 0x20
391 field ENPHASEMIS 0x10
392 field ENBUSFREE 0x08
393 field ENSCSIPERR 0x04
394 field ENPHASECHG 0x02
395 field ENREQINIT 0x01
396 }
398 /*
399 * SCSI Data Bus (High) (p. 3-29)
400 * This register reads data on the SCSI Data bus directly.
401 */
402 register SCSIBUSL {
403 address 0x012
404 access_mode RW
405 }
407 register SCSIBUSH {
408 address 0x013
409 access_mode RW
410 }
412 /*
413 * SCSI/Host Address (p. 3-30)
414 * These registers hold the host address for the byte about to be
415 * transferred on the SCSI bus. They are counted up in the same
416 * manner as STCNT is counted down. SHADDR should always be used
417 * to determine the address of the last byte transferred since HADDR
418 * can be skewed by write ahead.
419 */
420 register SHADDR {
421 address 0x014
422 size 4
423 access_mode RO
424 }
426 /*
427 * Selection Timeout Timer (p. 3-30)
428 */
429 register SELTIMER {
430 address 0x018
431 access_mode RW
432 field STAGE6 0x20
433 field STAGE5 0x10
434 field STAGE4 0x08
435 field STAGE3 0x04
436 field STAGE2 0x02
437 field STAGE1 0x01
438 alias TARGIDIN
439 }
441 /*
442 * Selection/Reselection ID (p. 3-31)
443 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
444 * device did not set its own ID.
445 */
446 register SELID {
447 address 0x019
448 access_mode RW
449 mask SELID_MASK 0xf0
450 field ONEBIT 0x08
451 }
453 register SCAMCTL {
454 address 0x01a
455 access_mode RW
456 field ENSCAMSELO 0x80
457 field CLRSCAMSELID 0x40
458 field ALTSTIM 0x20
459 field DFLTTID 0x10
460 mask SCAMLVL 0x03
461 }
463 /*
464 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
465 */
466 register TARGID {
467 address 0x01b
468 size 2
469 access_mode RW
470 }
472 /*
473 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
474 * Indicates if external logic has been attached to the chip to
475 * perform the tasks of accessing a serial eeprom, testing termination
476 * strength, and performing cable detection. On the aic7860, most of
477 * these features are handled on chip, but on the aic7855 an attached
478 * aic3800 does the grunt work.
479 */
480 register SPIOCAP {
481 address 0x01b
482 access_mode RW
483 field SOFT1 0x80
484 field SOFT0 0x40
485 field SOFTCMDEN 0x20
486 field EXT_BRDCTL 0x10 /* External Board control */
487 field SEEPROM 0x08 /* External serial eeprom logic */
488 field EEPROM 0x04 /* Writable external BIOS ROM */
489 field ROM 0x02 /* Logic for accessing external ROM */
490 field SSPIOCPS 0x01 /* Termination and cable detection */
491 }
493 register BRDCTL {
494 address 0x01d
495 field BRDDAT7 0x80
496 field BRDDAT6 0x40
497 field BRDDAT5 0x20
498 field BRDSTB 0x10
499 field BRDCS 0x08
500 field BRDRW 0x04
501 field BRDCTL1 0x02
502 field BRDCTL0 0x01
503 /* 7890 Definitions */
504 field BRDDAT4 0x10
505 field BRDDAT3 0x08
506 field BRDDAT2 0x04
507 field BRDRW_ULTRA2 0x02
508 field BRDSTB_ULTRA2 0x01
509 }
511 /*
512 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
513 * Controls the reading and writing of an external serial 1-bit
514 * EEPROM Device. In order to access the serial EEPROM, you must
515 * first set the SEEMS bit that generates a request to the memory
516 * port for access to the serial EEPROM device. When the memory
517 * port is not busy servicing another request, it reconfigures
518 * to allow access to the serial EEPROM. When this happens, SEERDY
519 * gets set high to verify that the memory port access has been
520 * granted.
521 *
522 * After successful arbitration for the memory port, the SEECS bit of
523 * the SEECTL register is connected to the chip select. The SEECK,
524 * SEEDO, and SEEDI are connected to the clock, data out, and data in
525 * lines respectively. The SEERDY bit of SEECTL is useful in that it
526 * gives us an 800 nsec timer. After a write to the SEECTL register,
527 * the SEERDY goes high 800 nsec later. The one exception to this is
528 * when we first request access to the memory port. The SEERDY goes
529 * high to signify that access has been granted and, for this case, has
530 * no implied timing.
531 *
532 * See 93cx6.c for detailed information on the protocol necessary to
533 * read the serial EEPROM.
534 */
535 register SEECTL {
536 address 0x01e
537 field EXTARBACK 0x80
538 field EXTARBREQ 0x40
539 field SEEMS 0x20
540 field SEERDY 0x10
541 field SEECS 0x08
542 field SEECK 0x04
543 field SEEDO 0x02
544 field SEEDI 0x01
545 }
546 /*
547 * SCSI Block Control (p. 3-32)
548 * Controls Bus type and channel selection. In a twin channel configuration
549 * addresses 0x00-0x1e are gated to the appropriate channel based on this
550 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
551 * on a wide bus.
552 */
553 register SBLKCTL {
554 address 0x01f
555 access_mode RW
556 field DIAGLEDEN 0x80 /* Aic78X0 only */
557 field DIAGLEDON 0x40 /* Aic78X0 only */
558 field AUTOFLUSHDIS 0x20
559 field SELBUSB 0x08
560 field ENAB40 0x08 /* LVD transceiver active */
561 field ENAB20 0x04 /* SE/HVD transceiver active */
562 field SELWIDE 0x02
563 field XCVR 0x01 /* External transceiver active */
564 }
566 /*
567 * Sequencer Control (p. 3-33)
568 * Error detection mode and speed configuration
569 */
570 register SEQCTL {
571 address 0x060
572 access_mode RW
573 field PERRORDIS 0x80
574 field PAUSEDIS 0x40
575 field FAILDIS 0x20
576 field FASTMODE 0x10
577 field BRKADRINTEN 0x08
578 field STEP 0x04
579 field SEQRESET 0x02
580 field LOADRAM 0x01
581 }
583 /*
584 * Sequencer RAM Data (p. 3-34)
585 * Single byte window into the Scratch Ram area starting at the address
586 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
587 * four bytes in succession. The SEQADDRs will increment after the most
588 * significant byte is written
589 */
590 register SEQRAM {
591 address 0x061
592 access_mode RW
593 }
595 /*
596 * Sequencer Address Registers (p. 3-35)
597 * Only the first bit of SEQADDR1 holds addressing information
598 */
599 register SEQADDR0 {
600 address 0x062
601 access_mode RW
602 }
604 register SEQADDR1 {
605 address 0x063
606 access_mode RW
607 mask SEQADDR1_MASK 0x01
608 }
610 /*
611 * Accumulator
612 * We cheat by passing arguments in the Accumulator up to the kernel driver
613 */
614 register ACCUM {
615 address 0x064
616 access_mode RW
617 accumulator
618 }
620 register SINDEX {
621 address 0x065
622 access_mode RW
623 sindex
624 }
626 register DINDEX {
627 address 0x066
628 access_mode RW
629 }
631 register ALLONES {
632 address 0x069
633 access_mode RO
634 allones
635 }
637 register ALLZEROS {
638 address 0x06a
639 access_mode RO
640 allzeros
641 }
643 register NONE {
644 address 0x06a
645 access_mode WO
646 none
647 }
649 register FLAGS {
650 address 0x06b
651 access_mode RO
652 field ZERO 0x02
653 field CARRY 0x01
654 }
656 register SINDIR {
657 address 0x06c
658 access_mode RO
659 }
661 register DINDIR {
662 address 0x06d
663 access_mode WO
664 }
666 register FUNCTION1 {
667 address 0x06e
668 access_mode RW
669 }
671 register STACK {
672 address 0x06f
673 access_mode RO
674 }
676 const STACK_SIZE 4
678 /*
679 * Board Control (p. 3-43)
680 */
681 register BCTL {
682 address 0x084
683 access_mode RW
684 field ACE 0x08
685 field ENABLE 0x01
686 }
688 /*
689 * On the aic78X0 chips, Board Control is replaced by the DSCommand
690 * register (p. 4-64)
691 */
692 register DSCOMMAND0 {
693 address 0x084
694 access_mode RW
695 field CACHETHEN 0x80 /* Cache Threshold enable */
696 field DPARCKEN 0x40 /* Data Parity Check Enable */
697 field MPARCKEN 0x20 /* Memory Parity Check Enable */
698 field EXTREQLCK 0x10 /* External Request Lock */
699 /* aic7890/91/96/97 only */
700 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
701 field RAMPS 0x04 /* External SCB RAM Present */
702 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
703 field CIOPARCKEN 0x01 /* Internal bus parity error enable */
704 }
706 register DSCOMMAND1 {
707 address 0x085
708 access_mode RW
709 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
710 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
711 field HADDLDSEL0 0x01
712 }
714 /*
715 * Bus On/Off Time (p. 3-44) aic7770 only
716 */
717 register BUSTIME {
718 address 0x085
719 access_mode RW
720 mask BOFF 0xf0
721 mask BON 0x0f
722 }
724 /*
725 * Bus Speed (p. 3-45) aic7770 only
726 */
727 register BUSSPD {
728 address 0x086
729 access_mode RW
730 mask DFTHRSH 0xc0
731 mask STBOFF 0x38
732 mask STBON 0x07
733 mask DFTHRSH_100 0xc0
734 mask DFTHRSH_75 0x80
735 }
737 /* aic7850/55/60/70/80/95 only */
738 register DSPCISTATUS {
739 address 0x086
740 mask DFTHRSH_100 0xc0
741 }
743 /* aic7890/91/96/97 only */
744 register HS_MAILBOX {
745 address 0x086
746 mask HOST_MAILBOX 0xF0
747 mask SEQ_MAILBOX 0x0F
748 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
749 }
751 const HOST_MAILBOX_SHIFT 4
752 const SEQ_MAILBOX_SHIFT 0
754 /*
755 * Host Control (p. 3-47) R/W
756 * Overall host control of the device.
757 */
758 register HCNTRL {
759 address 0x087
760 access_mode RW
761 field POWRDN 0x40
762 field SWINT 0x10
763 field IRQMS 0x08
764 field PAUSE 0x04
765 field INTEN 0x02
766 field CHIPRST 0x01
767 field CHIPRSTACK 0x01
768 }
770 /*
771 * Host Address (p. 3-48)
772 * This register contains the address of the byte about
773 * to be transferred across the host bus.
774 */
775 register HADDR {
776 address 0x088
777 size 4
778 access_mode RW
779 }
781 register HCNT {
782 address 0x08c
783 size 3
784 access_mode RW
785 }
787 /*
788 * SCB Pointer (p. 3-49)
789 * Gate one of the SCBs into the SCBARRAY window.
790 */
791 register SCBPTR {
792 address 0x090
793 access_mode RW
794 }
796 /*
797 * Interrupt Status (p. 3-50)
798 * Status for system interrupts
799 */
800 register INTSTAT {
801 address 0x091
802 access_mode RW
803 field BRKADRINT 0x08
804 field SCSIINT 0x04
805 field CMDCMPLT 0x02
806 field SEQINT 0x01
807 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
808 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
809 mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */
810 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
811 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
812 mask PDATA_REINIT 0x50|SEQINT /*
813 * Returned to data phase
814 * that requires data
815 * transfer pointers to be
816 * recalculated from the
817 * transfer residual.
818 */
819 mask HOST_MSG_LOOP 0x60|SEQINT /*
820 * The bus is ready for the
821 * host to perform another
822 * message transaction. This
823 * mechanism is used for things
824 * like sync/wide negotiation
825 * that require a kernel based
826 * message state engine.
827 */
828 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
829 mask PERR_DETECTED 0x80|SEQINT /*
830 * Either the phase_lock
831 * or inb_next routine has
832 * noticed a parity error.
833 */
834 mask DATA_OVERRUN 0x90|SEQINT /*
835 * Target attempted to write
836 * beyond the bounds of its
837 * command.
838 */
839 mask MKMSG_FAILED 0xa0|SEQINT /*
840 * Target completed command
841 * without honoring our ATN
842 * request to issue a message.
843 */
844 mask MISSED_BUSFREE 0xb0|SEQINT /*
845 * The sequencer never saw
846 * the bus go free after
847 * either a command complete
848 * or disconnect message.
849 */
850 mask SCB_MISMATCH 0xc0|SEQINT /*
851 * Downloaded SCB's tag does
852 * not match the entry we
853 * intended to download.
854 */
855 mask NO_FREE_SCB 0xd0|SEQINT /*
856 * get_free_or_disc_scb failed.
857 */
858 mask OUT_OF_RANGE 0xe0|SEQINT
860 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
861 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
862 }
864 /*
865 * Hard Error (p. 3-53)
866 * Reporting of catastrophic errors. You usually cannot recover from
867 * these without a full board reset.
868 */
869 register ERROR {
870 address 0x092
871 access_mode RO
872 field CIOPARERR 0x80 /* Ultra2 only */
873 field PCIERRSTAT 0x40 /* PCI only */
874 field MPARERR 0x20 /* PCI only */
875 field DPARERR 0x10 /* PCI only */
876 field SQPARERR 0x08
877 field ILLOPCODE 0x04
878 field ILLSADDR 0x02
879 field ILLHADDR 0x01
880 }
882 /*
883 * Clear Interrupt Status (p. 3-52)
884 */
885 register CLRINT {
886 address 0x092
887 access_mode WO
888 field CLRPARERR 0x10 /* PCI only */
889 field CLRBRKADRINT 0x08
890 field CLRSCSIINT 0x04
891 field CLRCMDINT 0x02
892 field CLRSEQINT 0x01
893 }
895 register DFCNTRL {
896 address 0x093
897 access_mode RW
898 field PRELOADEN 0x80 /* aic7890 only */
899 field WIDEODD 0x40
900 field SCSIEN 0x20
901 field SDMAEN 0x10
902 field SDMAENACK 0x10
903 field HDMAEN 0x08
904 field HDMAENACK 0x08
905 field DIRECTION 0x04
906 field FIFOFLUSH 0x02
907 field FIFORESET 0x01
908 }
910 register DFSTATUS {
911 address 0x094
912 access_mode RO
913 field PRELOAD_AVAIL 0x80
914 field DFCACHETH 0x40
915 field FIFOQWDEMP 0x20
916 field MREQPEND 0x10
917 field HDONE 0x08
918 field DFTHRESH 0x04
919 field FIFOFULL 0x02
920 field FIFOEMP 0x01
921 }
923 register DFWADDR {
924 address 0x95
925 access_mode RW
926 }
928 register DFRADDR {
929 address 0x97
930 access_mode RW
931 }
933 register DFDAT {
934 address 0x099
935 access_mode RW
936 }
938 /*
939 * SCB Auto Increment (p. 3-59)
940 * Byte offset into the SCB Array and an optional bit to allow auto
941 * incrementing of the address during download and upload operations
942 */
943 register SCBCNT {
944 address 0x09a
945 access_mode RW
946 field SCBAUTO 0x80
947 mask SCBCNT_MASK 0x1f
948 }
950 /*
951 * Queue In FIFO (p. 3-60)
952 * Input queue for queued SCBs (commands that the seqencer has yet to start)
953 */
954 register QINFIFO {
955 address 0x09b
956 access_mode RW
957 }
959 /*
960 * Queue In Count (p. 3-60)
961 * Number of queued SCBs
962 */
963 register QINCNT {
964 address 0x09c
965 access_mode RO
966 }
968 /*
969 * Queue Out FIFO (p. 3-61)
970 * Queue of SCBs that have completed and await the host
971 */
972 register QOUTFIFO {
973 address 0x09d
974 access_mode WO
975 }
977 register CRCCONTROL1 {
978 address 0x09d
979 access_mode RW
980 field CRCONSEEN 0x80
981 field CRCVALCHKEN 0x40
982 field CRCENDCHKEN 0x20
983 field CRCREQCHKEN 0x10
984 field TARGCRCENDEN 0x08
985 field TARGCRCCNTEN 0x04
986 }
989 /*
990 * Queue Out Count (p. 3-61)
991 * Number of queued SCBs in the Out FIFO
992 */
993 register QOUTCNT {
994 address 0x09e
995 access_mode RO
996 }
998 register SCSIPHASE {
999 address 0x09e
1000 access_mode RO
1001 field STATUS_PHASE 0x20
1002 field COMMAND_PHASE 0x10
1003 field MSG_IN_PHASE 0x08
1004 field MSG_OUT_PHASE 0x04
1005 field DATA_IN_PHASE 0x02
1006 field DATA_OUT_PHASE 0x01
1007 mask DATA_PHASE_MASK 0x03
1008 }
1010 /*
1011 * Special Function
1012 */
1013 register SFUNCT {
1014 address 0x09f
1015 access_mode RW
1016 field ALT_MODE 0x80
1017 }
1019 /*
1020 * SCB Definition (p. 5-4)
1021 */
1022 scb {
1023 address 0x0a0
1024 size 64
1026 SCB_CDB_PTR {
1027 size 4
1028 alias SCB_RESIDUAL_DATACNT
1029 alias SCB_CDB_STORE
1030 }
1031 SCB_RESIDUAL_SGPTR {
1032 size 4
1033 }
1034 SCB_SCSI_STATUS {
1035 size 1
1036 }
1037 SCB_TARGET_PHASES {
1038 size 1
1039 }
1040 SCB_TARGET_DATA_DIR {
1041 size 1
1042 }
1043 SCB_TARGET_ITAG {
1044 size 1
1045 }
1046 SCB_DATAPTR {
1047 size 4
1048 }
1049 SCB_DATACNT {
1050 /*
1051 * The last byte is really the high address bits for
1052 * the data address.
1053 */
1054 size 4
1055 field SG_LAST_SEG 0x80 /* In the fourth byte */
1056 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
1057 }
1058 SCB_SGPTR {
1059 size 4
1060 field SG_RESID_VALID 0x04 /* In the first byte */
1061 field SG_FULL_RESID 0x02 /* In the first byte */
1062 field SG_LIST_NULL 0x01 /* In the first byte */
1063 }
1064 SCB_CONTROL {
1065 size 1
1066 field TARGET_SCB 0x80
1067 field STATUS_RCVD 0x80
1068 field DISCENB 0x40
1069 field TAG_ENB 0x20
1070 field MK_MESSAGE 0x10
1071 field ULTRAENB 0x08
1072 field DISCONNECTED 0x04
1073 mask SCB_TAG_TYPE 0x03
1074 }
1075 SCB_SCSIID {
1076 size 1
1077 field TWIN_CHNLB 0x80
1078 mask TWIN_TID 0x70
1079 mask TID 0xf0
1080 mask OID 0x0f
1081 }
1082 SCB_LUN {
1083 field SCB_XFERLEN_ODD 0x80
1084 mask LID 0x3f
1085 size 1
1086 }
1087 SCB_TAG {
1088 size 1
1089 }
1090 SCB_CDB_LEN {
1091 size 1
1092 }
1093 SCB_SCSIRATE {
1094 size 1
1095 }
1096 SCB_SCSIOFFSET {
1097 size 1
1098 }
1099 SCB_NEXT {
1100 size 1
1101 }
1102 SCB_64_SPARE {
1103 size 16
1104 }
1105 SCB_64_BTT {
1106 size 16
1107 }
1108 }
1110 const SCB_UPLOAD_SIZE 32
1111 const SCB_DOWNLOAD_SIZE 32
1112 const SCB_DOWNLOAD_SIZE_64 48
1114 const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1116 /* --------------------- AHA-2840-only definitions -------------------- */
1118 register SEECTL_2840 {
1119 address 0x0c0
1120 access_mode RW
1121 field CS_2840 0x04
1122 field CK_2840 0x02
1123 field DO_2840 0x01
1124 }
1126 register STATUS_2840 {
1127 address 0x0c1
1128 access_mode RW
1129 field EEPROM_TF 0x80
1130 mask BIOS_SEL 0x60
1131 mask ADSEL 0x1e
1132 field DI_2840 0x01
1133 }
1135 /* --------------------- AIC-7870-only definitions -------------------- */
1137 register CCHADDR {
1138 address 0x0E0
1139 size 8
1140 }
1142 register CCHCNT {
1143 address 0x0E8
1144 }
1146 register CCSGRAM {
1147 address 0x0E9
1148 }
1150 register CCSGADDR {
1151 address 0x0EA
1152 }
1154 register CCSGCTL {
1155 address 0x0EB
1156 field CCSGDONE 0x80
1157 field CCSGEN 0x08
1158 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
1159 field CCSGRESET 0x01
1160 }
1162 register CCSCBCNT {
1163 address 0xEF
1164 }
1166 register CCSCBCTL {
1167 address 0x0EE
1168 field CCSCBDONE 0x80
1169 field ARRDONE 0x40 /* SCB Array prefetch done */
1170 field CCARREN 0x10
1171 field CCSCBEN 0x08
1172 field CCSCBDIR 0x04
1173 field CCSCBRESET 0x01
1174 }
1176 register CCSCBADDR {
1177 address 0x0ED
1178 }
1180 register CCSCBRAM {
1181 address 0xEC
1182 }
1184 /*
1185 * SCB bank address (7895/7896/97 only)
1186 */
1187 register SCBBADDR {
1188 address 0x0F0
1189 access_mode RW
1190 }
1192 register CCSCBPTR {
1193 address 0x0F1
1194 }
1196 register HNSCB_QOFF {
1197 address 0x0F4
1198 }
1200 register SNSCB_QOFF {
1201 address 0x0F6
1202 }
1204 register SDSCB_QOFF {
1205 address 0x0F8
1206 }
1208 register QOFF_CTLSTA {
1209 address 0x0FA
1210 field SCB_AVAIL 0x40
1211 field SNSCB_ROLLOVER 0x20
1212 field SDSCB_ROLLOVER 0x10
1213 mask SCB_QSIZE 0x07
1214 mask SCB_QSIZE_256 0x06
1215 }
1217 register DFF_THRSH {
1218 address 0x0FB
1219 mask WR_DFTHRSH 0x70
1220 mask RD_DFTHRSH 0x07
1221 mask RD_DFTHRSH_MIN 0x00
1222 mask RD_DFTHRSH_25 0x01
1223 mask RD_DFTHRSH_50 0x02
1224 mask RD_DFTHRSH_63 0x03
1225 mask RD_DFTHRSH_75 0x04
1226 mask RD_DFTHRSH_85 0x05
1227 mask RD_DFTHRSH_90 0x06
1228 mask RD_DFTHRSH_MAX 0x07
1229 mask WR_DFTHRSH_MIN 0x00
1230 mask WR_DFTHRSH_25 0x10
1231 mask WR_DFTHRSH_50 0x20
1232 mask WR_DFTHRSH_63 0x30
1233 mask WR_DFTHRSH_75 0x40
1234 mask WR_DFTHRSH_85 0x50
1235 mask WR_DFTHRSH_90 0x60
1236 mask WR_DFTHRSH_MAX 0x70
1237 }
1239 register SG_CACHE_PRE {
1240 access_mode WO
1241 address 0x0fc
1242 mask SG_ADDR_MASK 0xf8
1243 field LAST_SEG 0x02
1244 field LAST_SEG_DONE 0x01
1245 }
1247 register SG_CACHE_SHADOW {
1248 access_mode RO
1249 address 0x0fc
1250 mask SG_ADDR_MASK 0xf8
1251 field LAST_SEG 0x02
1252 field LAST_SEG_DONE 0x01
1253 }
1254 /* ---------------------- Scratch RAM Offsets ------------------------- */
1255 /* These offsets are either to values that are initialized by the board's
1256 * BIOS or are specified by the sequencer code.
1257 *
1258 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1259 * device information, 32-33 and 5a-5f as well. As it turns out, the
1260 * BIOS trashes 20-2f, writing the synchronous negotiation results
1261 * on top of the BIOS values, so we re-use those for our per-target
1262 * scratchspace (actually a value that can be copied directly into
1263 * SCSIRATE). The kernel driver will enable synchronous negotiation
1264 * for all targets that have a value other than 0 in the lower four
1265 * bits of the target scratch space. This should work regardless of
1266 * whether the bios has been installed.
1267 */
1269 scratch_ram {
1270 address 0x020
1271 size 58
1273 /*
1274 * 1 byte per target starting at this address for configuration values
1275 */
1276 BUSY_TARGETS {
1277 alias TARG_SCSIRATE
1278 size 16
1279 }
1280 /*
1281 * Bit vector of targets that have ULTRA enabled as set by
1282 * the BIOS. The Sequencer relies on a per-SCB field to
1283 * control whether to enable Ultra transfers or not. During
1284 * initialization, we read this field and reuse it for 2
1285 * entries in the busy target table.
1286 */
1287 ULTRA_ENB {
1288 alias CMDSIZE_TABLE
1289 size 2
1290 }
1291 /*
1292 * Bit vector of targets that have disconnection disabled as set by
1293 * the BIOS. The Sequencer relies in a per-SCB field to control the
1294 * disconnect priveldge. During initialization, we read this field
1295 * and reuse it for 2 entries in the busy target table.
1296 */
1297 DISC_DSB {
1298 size 2
1299 }
1300 CMDSIZE_TABLE_TAIL {
1301 size 4
1302 }
1303 /*
1304 * Partial transfer past cacheline end to be
1305 * transferred using an extra S/G.
1306 */
1307 MWI_RESIDUAL {
1308 size 1
1309 alias TARG_IMMEDIATE_SCB
1310 }
1311 /*
1312 * SCBID of the next SCB to be started by the controller.
1313 */
1314 NEXT_QUEUED_SCB {
1315 size 1
1316 }
1317 /*
1318 * Single byte buffer used to designate the type or message
1319 * to send to a target.
1320 */
1321 MSG_OUT {
1322 size 1
1323 }
1324 /* Parameters for DMA Logic */
1325 DMAPARAMS {
1326 size 1
1327 field PRELOADEN 0x80
1328 field WIDEODD 0x40
1329 field SCSIEN 0x20
1330 field SDMAEN 0x10
1331 field SDMAENACK 0x10
1332 field HDMAEN 0x08
1333 field HDMAENACK 0x08
1334 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
1335 field FIFOFLUSH 0x02
1336 field FIFORESET 0x01
1337 }
1338 SEQ_FLAGS {
1339 size 1
1340 field NOT_IDENTIFIED 0x80
1341 field NO_CDB_SENT 0x40
1342 field TARGET_CMD_IS_TAGGED 0x40
1343 field DPHASE 0x20
1344 /* Target flags */
1345 field TARG_CMD_PENDING 0x10
1346 field CMDPHASE_PENDING 0x08
1347 field DPHASE_PENDING 0x04
1348 field SPHASE_PENDING 0x02
1349 field NO_DISCONNECT 0x01
1350 }
1351 /*
1352 * Temporary storage for the
1353 * target/channel/lun of a
1354 * reconnecting target
1355 */
1356 SAVED_SCSIID {
1357 size 1
1358 }
1359 SAVED_LUN {
1360 size 1
1361 }
1362 /*
1363 * The last bus phase as seen by the sequencer.
1364 */
1365 LASTPHASE {
1366 size 1
1367 field CDI 0x80
1368 field IOI 0x40
1369 field MSGI 0x20
1370 mask PHASE_MASK CDI|IOI|MSGI
1371 mask P_DATAOUT 0x00
1372 mask P_DATAIN IOI
1373 mask P_COMMAND CDI
1374 mask P_MESGOUT CDI|MSGI
1375 mask P_STATUS CDI|IOI
1376 mask P_MESGIN CDI|IOI|MSGI
1377 mask P_BUSFREE 0x01
1378 }
1379 /*
1380 * head of list of SCBs awaiting
1381 * selection
1382 */
1383 WAITING_SCBH {
1384 size 1
1385 }
1386 /*
1387 * head of list of SCBs that are
1388 * disconnected. Used for SCB
1389 * paging.
1390 */
1391 DISCONNECTED_SCBH {
1392 size 1
1393 }
1394 /*
1395 * head of list of SCBs that are
1396 * not in use. Used for SCB paging.
1397 */
1398 FREE_SCBH {
1399 size 1
1400 }
1401 /*
1402 * head of list of SCBs that have
1403 * completed but have not been
1404 * put into the qoutfifo.
1405 */
1406 COMPLETE_SCBH {
1407 size 1
1408 }
1409 /*
1410 * Address of the hardware scb array in the host.
1411 */
1412 HSCB_ADDR {
1413 size 4
1414 }
1415 /*
1416 * Base address of our shared data with the kernel driver in host
1417 * memory. This includes the qoutfifo and target mode
1418 * incoming command queue.
1419 */
1420 SHARED_DATA_ADDR {
1421 size 4
1422 }
1423 KERNEL_QINPOS {
1424 size 1
1425 }
1426 QINPOS {
1427 size 1
1428 }
1429 QOUTPOS {
1430 size 1
1431 }
1432 /*
1433 * Kernel and sequencer offsets into the queue of
1434 * incoming target mode command descriptors. The
1435 * queue is full when the KERNEL_TQINPOS == TQINPOS.
1436 */
1437 KERNEL_TQINPOS {
1438 size 1
1439 }
1440 TQINPOS {
1441 size 1
1442 }
1443 ARG_1 {
1444 size 1
1445 mask SEND_MSG 0x80
1446 mask SEND_SENSE 0x40
1447 mask SEND_REJ 0x20
1448 mask MSGOUT_PHASEMIS 0x10
1449 mask EXIT_MSG_LOOP 0x08
1450 mask CONT_MSG_LOOP 0x04
1451 mask CONT_TARG_SESSION 0x02
1452 alias RETURN_1
1453 }
1454 ARG_2 {
1455 size 1
1456 alias RETURN_2
1457 }
1459 /*
1460 * Snapshot of MSG_OUT taken after each message is sent.
1461 */
1462 LAST_MSG {
1463 size 1
1464 }
1466 /*
1467 * Sequences the kernel driver has okayed for us. This allows
1468 * the driver to do things like prevent initiator or target
1469 * operations.
1470 */
1471 SCSISEQ_TEMPLATE {
1472 size 1
1473 field ENSELO 0x40
1474 field ENSELI 0x20
1475 field ENRSELI 0x10
1476 field ENAUTOATNO 0x08
1477 field ENAUTOATNI 0x04
1478 field ENAUTOATNP 0x02
1479 }
1480 }
1482 scratch_ram {
1483 address 0x056
1484 size 4
1485 /*
1486 * These scratch ram locations are initialized by the 274X BIOS.
1487 * We reuse them after capturing the BIOS settings during
1488 * initialization.
1489 */
1491 /*
1492 * The initiator specified tag for this target mode transaction.
1493 */
1494 HA_274_BIOSGLOBAL {
1495 size 1
1496 field HA_274_EXTENDED_TRANS 0x01
1497 alias INITIATOR_TAG
1498 }
1500 SEQ_FLAGS2 {
1501 size 1
1502 field SCB_DMA 0x01
1503 field TARGET_MSG_PENDING 0x02
1504 }
1505 }
1507 scratch_ram {
1508 address 0x05a
1509 size 6
1510 /*
1511 * These are reserved registers in the card's scratch ram on the 2742.
1512 * The EISA configuraiton chip is mapped here. On Rev E. of the
1513 * aic7770, the sequencer can use this area for scratch, but the
1514 * host cannot directly access these registers. On later chips, this
1515 * area can be read and written by both the host and the sequencer.
1516 * Even on later chips, many of these locations are initialized by
1517 * the BIOS.
1518 */
1519 SCSICONF {
1520 size 1
1521 field TERM_ENB 0x80
1522 field RESET_SCSI 0x40
1523 field ENSPCHK 0x20
1524 mask HSCSIID 0x07 /* our SCSI ID */
1525 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1526 }
1527 INTDEF {
1528 address 0x05c
1529 size 1
1530 field EDGE_TRIG 0x80
1531 mask VECTOR 0x0f
1532 }
1533 HOSTCONF {
1534 address 0x05d
1535 size 1
1536 }
1537 HA_274_BIOSCTRL {
1538 address 0x05f
1539 size 1
1540 mask BIOSMODE 0x30
1541 mask BIOSDISABLED 0x30
1542 field CHANNEL_B_PRIMARY 0x08
1543 }
1544 }
1546 scratch_ram {
1547 address 0x070
1548 size 16
1550 /*
1551 * Per target SCSI offset values for Ultra2 controllers.
1552 */
1553 TARG_OFFSET {
1554 size 16
1555 }
1556 }
1558 const TID_SHIFT 4
1559 const SCB_LIST_NULL 0xff
1560 const TARGET_CMD_CMPLT 0xfe
1562 const CCSGADDR_MAX 0x80
1563 const CCSGRAM_MAXSEGS 16
1565 /* WDTR Message values */
1566 const BUS_8_BIT 0x00
1567 const BUS_16_BIT 0x01
1568 const BUS_32_BIT 0x02
1570 /* Offset maximums */
1571 const MAX_OFFSET_8BIT 0x0f
1572 const MAX_OFFSET_16BIT 0x08
1573 const MAX_OFFSET_ULTRA2 0x7f
1574 const MAX_OFFSET 0x7f
1575 const HOST_MSG 0xff
1577 /* Target mode command processing constants */
1578 const CMD_GROUP_CODE_SHIFT 0x05
1580 const STATUS_BUSY 0x08
1581 const STATUS_QUEUE_FULL 0x28
1582 const TARGET_DATA_IN 1
1584 /*
1585 * Downloaded (kernel inserted) constants
1586 */
1587 /* Offsets into the SCBID array where different data is stored */
1588 const QOUTFIFO_OFFSET download
1589 const QINFIFO_OFFSET download
1590 const CACHESIZE_MASK download
1591 const INVERTED_CACHESIZE_MASK download
1592 const SG_PREFETCH_CNT download
1593 const SG_PREFETCH_ALIGN_MASK download
1594 const SG_PREFETCH_ADDR_MASK download