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[XFRM]: skb_cow_data() does not set proper owner for new skbs.
[linux-2.6/verdex.git] / drivers / serial / s3c2410.c
blob2a9f7ade2c9d58faa134e84d698d9025af5365b1
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78
79 #include <asm/hardware.h>
80 #include <asm/hardware/clock.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 #include <asm/mach-types.h>
86
87 /* structures */
88
89 struct s3c24xx_uart_info {
90 char *name;
91 unsigned int type;
92 unsigned int fifosize;
93 unsigned long rx_fifomask;
94 unsigned long rx_fifoshift;
95 unsigned long rx_fifofull;
96 unsigned long tx_fifomask;
97 unsigned long tx_fifoshift;
98 unsigned long tx_fifofull;
99
100 /* clock source control */
101
102 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
103 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
104
105 /* uart controls */
106 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
107 };
108
109 struct s3c24xx_uart_port {
110 unsigned char rx_claimed;
111 unsigned char tx_claimed;
112
113 struct s3c24xx_uart_info *info;
114 struct s3c24xx_uart_clksrc *clksrc;
115 struct clk *clk;
116 struct clk *baudclk;
117 struct uart_port port;
118 };
119
120
121 /* configuration defines */
122
123 #if 0
124 #if 1
125 /* send debug to the low-level output routines */
126
127 extern void printascii(const char *);
128
129 static void
130 s3c24xx_serial_dbg(const char *fmt, ...)
131 {
132 va_list va;
133 char buff[256];
134
135 va_start(va, fmt);
136 vsprintf(buff, fmt, va);
137 va_end(va);
138
139 printascii(buff);
140 }
141
142 #define dbg(x...) s3c24xx_serial_dbg(x)
143
144 #else
145 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
146 #endif
147 #else /* no debug */
148 #define dbg(x...) do {} while(0)
149 #endif
150
151 /* UART name and device definitions */
152
153 #define S3C24XX_SERIAL_NAME "ttySAC"
154 #define S3C24XX_SERIAL_DEVFS "tts/"
155 #define S3C24XX_SERIAL_MAJOR 204
156 #define S3C24XX_SERIAL_MINOR 64
157
158
159 /* conversion functions */
160
161 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
162 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
163
164 /* we can support 3 uarts, but not always use them */
165
166 #define NR_PORTS (3)
167
168 /* port irq numbers */
169
170 #define TX_IRQ(port) ((port)->irq + 1)
171 #define RX_IRQ(port) ((port)->irq)
172
173 /* register access controls */
174
175 #define portaddr(port, reg) ((port)->membase + (reg))
176
177 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
178 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
179
180 #define wr_regb(port, reg, val) \
181 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
182
183 #define wr_regl(port, reg, val) \
184 do { __raw_writel(val, portaddr(port, reg)); } while(0)
185
186 /* macros to change one thing to another */
187
188 #define tx_enabled(port) ((port)->unused[0])
189 #define rx_enabled(port) ((port)->unused[1])
190
191 /* flag to ignore all characters comming in */
192 #define RXSTAT_DUMMY_READ (0x10000000)
193
194 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
195 {
196 return container_of(port, struct s3c24xx_uart_port, port);
197 }
198
199 /* translate a port to the device name */
200
201 static inline char *s3c24xx_serial_portname(struct uart_port *port)
202 {
203 return to_platform_device(port->dev)->name;
204 }
205
206 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
207 {
208 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
209 }
210
211 static void s3c24xx_serial_rx_enable(struct uart_port *port)
212 {
213 unsigned long flags;
214 unsigned int ucon, ufcon;
215 int count = 10000;
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 while (--count && !s3c24xx_serial_txempty_nofifo(port))
220 udelay(100);
221
222 ufcon = rd_regl(port, S3C2410_UFCON);
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225
226 ucon = rd_regl(port, S3C2410_UCON);
227 ucon |= S3C2410_UCON_RXIRQMODE;
228 wr_regl(port, S3C2410_UCON, ucon);
229
230 rx_enabled(port) = 1;
231 spin_unlock_irqrestore(&port->lock, flags);
232 }
233
234 static void s3c24xx_serial_rx_disable(struct uart_port *port)
235 {
236 unsigned long flags;
237 unsigned int ucon;
238
239 spin_lock_irqsave(&port->lock, flags);
240
241 ucon = rd_regl(port, S3C2410_UCON);
242 ucon &= ~S3C2410_UCON_RXIRQMODE;
243 wr_regl(port, S3C2410_UCON, ucon);
244
245 rx_enabled(port) = 0;
246 spin_unlock_irqrestore(&port->lock, flags);
247 }
248
249 static void
250 s3c24xx_serial_stop_tx(struct uart_port *port, unsigned int tty_stop)
251 {
252 if (tx_enabled(port)) {
253 disable_irq(TX_IRQ(port));
254 tx_enabled(port) = 0;
255 if (port->flags & UPF_CONS_FLOW)
256 s3c24xx_serial_rx_enable(port);
257 }
258 }
259
260 static void
261 s3c24xx_serial_start_tx(struct uart_port *port, unsigned int tty_start)
262 {
263 if (!tx_enabled(port)) {
264 if (port->flags & UPF_CONS_FLOW)
265 s3c24xx_serial_rx_disable(port);
266
267 enable_irq(TX_IRQ(port));
268 tx_enabled(port) = 1;
269 }
270 }
271
272
273 static void s3c24xx_serial_stop_rx(struct uart_port *port)
274 {
275 if (rx_enabled(port)) {
276 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
277 disable_irq(RX_IRQ(port));
278 rx_enabled(port) = 0;
279 }
280 }
281
282 static void s3c24xx_serial_enable_ms(struct uart_port *port)
283 {
284 }
285
286 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
287 {
288 return to_ourport(port)->info;
289 }
290
291 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
292 {
293 if (port->dev == NULL)
294 return NULL;
295
296 return (struct s3c2410_uartcfg *)port->dev->platform_data;
297 }
298
299 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
300 unsigned long ufstat)
301 {
302 struct s3c24xx_uart_info *info = ourport->info;
303
304 if (ufstat & info->rx_fifofull)
305 return info->fifosize;
306
307 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
308 }
309
310
311 /* ? - where has parity gone?? */
312 #define S3C2410_UERSTAT_PARITY (0x1000)
313
314 static irqreturn_t
315 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
316 {
317 struct s3c24xx_uart_port *ourport = dev_id;
318 struct uart_port *port = &ourport->port;
319 struct tty_struct *tty = port->info->tty;
320 unsigned int ufcon, ch, flag, ufstat, uerstat;
321 int max_count = 64;
322
323 while (max_count-- > 0) {
324 ufcon = rd_regl(port, S3C2410_UFCON);
325 ufstat = rd_regl(port, S3C2410_UFSTAT);
326
327 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
328 break;
329
330 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
331 if (tty->low_latency)
332 tty_flip_buffer_push(tty);
333
334 /*
335 * If this failed then we will throw away the
336 * bytes but must do so to clear interrupts
337 */
338 }
339
340 uerstat = rd_regl(port, S3C2410_UERSTAT);
341 ch = rd_regb(port, S3C2410_URXH);
342
343 if (port->flags & UPF_CONS_FLOW) {
344 int txe = s3c24xx_serial_txempty_nofifo(port);
345
346 if (rx_enabled(port)) {
347 if (!txe) {
348 rx_enabled(port) = 0;
349 continue;
350 }
351 } else {
352 if (txe) {
353 ufcon |= S3C2410_UFCON_RESETRX;
354 wr_regl(port, S3C2410_UFCON, ufcon);
355 rx_enabled(port) = 1;
356 goto out;
357 }
358 continue;
359 }
360 }
361
362 /* insert the character into the buffer */
363
364 flag = TTY_NORMAL;
365 port->icount.rx++;
366
367 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
368 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
369 ch, uerstat);
370
371 /* check for break */
372 if (uerstat & S3C2410_UERSTAT_BREAK) {
373 dbg("break!\n");
374 port->icount.brk++;
375 if (uart_handle_break(port))
376 goto ignore_char;
377 }
378
379 if (uerstat & S3C2410_UERSTAT_FRAME)
380 port->icount.frame++;
381 if (uerstat & S3C2410_UERSTAT_OVERRUN)
382 port->icount.overrun++;
383
384 uerstat &= port->read_status_mask;
385
386 if (uerstat & S3C2410_UERSTAT_BREAK)
387 flag = TTY_BREAK;
388 else if (uerstat & S3C2410_UERSTAT_PARITY)
389 flag = TTY_PARITY;
390 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
391 flag = TTY_FRAME;
392 }
393
394 if (uart_handle_sysrq_char(port, ch, regs))
395 goto ignore_char;
396
397 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
398
399 ignore_char:
400 continue;
401 }
402 tty_flip_buffer_push(tty);
403
404 out:
405 return IRQ_HANDLED;
406 }
407
408 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
409 {
410 struct s3c24xx_uart_port *ourport = id;
411 struct uart_port *port = &ourport->port;
412 struct circ_buf *xmit = &port->info->xmit;
413 int count = 256;
414
415 if (port->x_char) {
416 wr_regb(port, S3C2410_UTXH, port->x_char);
417 port->icount.tx++;
418 port->x_char = 0;
419 goto out;
420 }
421
422 /* if there isnt anything more to transmit, or the uart is now
423 * stopped, disable the uart and exit
424 */
425
426 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
427 s3c24xx_serial_stop_tx(port, 0);
428 goto out;
429 }
430
431 /* try and drain the buffer... */
432
433 while (!uart_circ_empty(xmit) && count-- > 0) {
434 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
435 break;
436
437 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
439 port->icount.tx++;
440 }
441
442 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
443 uart_write_wakeup(port);
444
445 if (uart_circ_empty(xmit))
446 s3c24xx_serial_stop_tx(port, 0);
447
448 out:
449 return IRQ_HANDLED;
450 }
451
452 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
453 {
454 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
455 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
456 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
457
458 if (ufcon & S3C2410_UFCON_FIFOMODE) {
459 if ((ufstat & info->tx_fifomask) != 0 ||
460 (ufstat & info->tx_fifofull))
461 return 0;
462
463 return 1;
464 }
465
466 return s3c24xx_serial_txempty_nofifo(port);
467 }
468
469 /* no modem control lines */
470 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
471 {
472 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
473
474 if (umstat & S3C2410_UMSTAT_CTS)
475 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
476 else
477 return TIOCM_CAR | TIOCM_DSR;
478 }
479
480 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
481 {
482 /* todo - possibly remove AFC and do manual CTS */
483 }
484
485 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
486 {
487 unsigned long flags;
488 unsigned int ucon;
489
490 spin_lock_irqsave(&port->lock, flags);
491
492 ucon = rd_regl(port, S3C2410_UCON);
493
494 if (break_state)
495 ucon |= S3C2410_UCON_SBREAK;
496 else
497 ucon &= ~S3C2410_UCON_SBREAK;
498
499 wr_regl(port, S3C2410_UCON, ucon);
500
501 spin_unlock_irqrestore(&port->lock, flags);
502 }
503
504 static void s3c24xx_serial_shutdown(struct uart_port *port)
505 {
506 struct s3c24xx_uart_port *ourport = to_ourport(port);
507
508 if (ourport->tx_claimed) {
509 free_irq(TX_IRQ(port), ourport);
510 tx_enabled(port) = 0;
511 ourport->tx_claimed = 0;
512 }
513
514 if (ourport->rx_claimed) {
515 free_irq(RX_IRQ(port), ourport);
516 ourport->rx_claimed = 0;
517 rx_enabled(port) = 0;
518 }
519 }
520
521
522 static int s3c24xx_serial_startup(struct uart_port *port)
523 {
524 struct s3c24xx_uart_port *ourport = to_ourport(port);
525 unsigned long flags;
526 int ret;
527
528 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
529 port->mapbase, port->membase);
530
531 local_irq_save(flags);
532
533 rx_enabled(port) = 1;
534
535 ret = request_irq(RX_IRQ(port),
536 s3c24xx_serial_rx_chars, 0,
537 s3c24xx_serial_portname(port), ourport);
538
539 if (ret != 0) {
540 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
541 return ret;
542 }
543
544 ourport->rx_claimed = 1;
545
546 dbg("requesting tx irq...\n");
547
548 tx_enabled(port) = 1;
549
550 ret = request_irq(TX_IRQ(port),
551 s3c24xx_serial_tx_chars, 0,
552 s3c24xx_serial_portname(port), ourport);
553
554 if (ret) {
555 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
556 goto err;
557 }
558
559 ourport->tx_claimed = 1;
560
561 dbg("s3c24xx_serial_startup ok\n");
562
563 /* the port reset code should have done the correct
564 * register setup for the port controls */
565
566 local_irq_restore(flags);
567 return ret;
568
569 err:
570 s3c24xx_serial_shutdown(port);
571 local_irq_restore(flags);
572 return ret;
573 }
574
575 /* power power management control */
576
577 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
578 unsigned int old)
579 {
580 struct s3c24xx_uart_port *ourport = to_ourport(port);
581
582 switch (level) {
583 case 3:
584 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
585 clk_disable(ourport->baudclk);
586
587 clk_disable(ourport->clk);
588 break;
589
590 case 0:
591 clk_enable(ourport->clk);
592
593 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
594 clk_enable(ourport->baudclk);
595
596 break;
597 default:
598 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
599 }
600 }
601
602 /* baud rate calculation
603 *
604 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
605 * of different sources, including the peripheral clock ("pclk") and an
606 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
607 * with a programmable extra divisor.
608 *
609 * The following code goes through the clock sources, and calculates the
610 * baud clocks (and the resultant actual baud rates) and then tries to
611 * pick the closest one and select that.
612 *
613 */
614
615
616 #define MAX_CLKS (8)
617
618 static struct s3c24xx_uart_clksrc tmp_clksrc = {
619 .name = "pclk",
620 .min_baud = 0,
621 .max_baud = 0,
622 .divisor = 1,
623 };
624
625 static inline int
626 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
627 {
628 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
629
630 return (info->get_clksrc)(port, c);
631 }
632
633 static inline int
634 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
635 {
636 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
637
638 return (info->set_clksrc)(port, c);
639 }
640
641 struct baud_calc {
642 struct s3c24xx_uart_clksrc *clksrc;
643 unsigned int calc;
644 unsigned int quot;
645 struct clk *src;
646 };
647
648 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
649 struct uart_port *port,
650 struct s3c24xx_uart_clksrc *clksrc,
651 unsigned int baud)
652 {
653 unsigned long rate;
654
655 calc->src = clk_get(port->dev, clksrc->name);
656 if (calc->src == NULL || IS_ERR(calc->src))
657 return 0;
658
659 rate = clk_get_rate(calc->src);
660 rate /= clksrc->divisor;
661
662 calc->clksrc = clksrc;
663 calc->quot = (rate + (8 * baud)) / (16 * baud);
664 calc->calc = (rate / (calc->quot * 16));
665
666 calc->quot--;
667 return 1;
668 }
669
670 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
671 struct s3c24xx_uart_clksrc **clksrc,
672 struct clk **clk,
673 unsigned int baud)
674 {
675 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
676 struct s3c24xx_uart_clksrc *clkp;
677 struct baud_calc res[MAX_CLKS];
678 struct baud_calc *resptr, *best, *sptr;
679 int i;
680
681 clkp = cfg->clocks;
682 best = NULL;
683
684 if (cfg->clocks_size < 2) {
685 if (cfg->clocks_size == 0)
686 clkp = &tmp_clksrc;
687
688 /* check to see if we're sourcing fclk, and if so we're
689 * going to have to update the clock source
690 */
691
692 if (strcmp(clkp->name, "fclk") == 0) {
693 struct s3c24xx_uart_clksrc src;
694
695 s3c24xx_serial_getsource(port, &src);
696
697 /* check that the port already using fclk, and if
698 * not, then re-select fclk
699 */
700
701 if (strcmp(src.name, clkp->name) == 0) {
702 s3c24xx_serial_setsource(port, clkp);
703 s3c24xx_serial_getsource(port, &src);
704 }
705
706 clkp->divisor = src.divisor;
707 }
708
709 s3c24xx_serial_calcbaud(res, port, clkp, baud);
710 best = res;
711 resptr = best + 1;
712 } else {
713 resptr = res;
714
715 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
716 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
717 resptr++;
718 }
719 }
720
721 /* ok, we now need to select the best clock we found */
722
723 if (!best) {
724 unsigned int deviation = (1<<30)|((1<<30)-1);
725 int calc_deviation;
726
727 for (sptr = res; sptr < resptr; sptr++) {
728 printk(KERN_DEBUG
729 "found clk %p (%s) quot %d, calc %d\n",
730 sptr->clksrc, sptr->clksrc->name,
731 sptr->quot, sptr->calc);
732
733 calc_deviation = baud - sptr->calc;
734 if (calc_deviation < 0)
735 calc_deviation = -calc_deviation;
736
737 if (calc_deviation < deviation) {
738 best = sptr;
739 deviation = calc_deviation;
740 }
741 }
742
743 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
744 }
745
746 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
747 best->clksrc, best->clksrc->name, best->quot, best->calc);
748
749 /* store results to pass back */
750
751 *clksrc = best->clksrc;
752 *clk = best->src;
753
754 return best->quot;
755 }
756
757 static void s3c24xx_serial_set_termios(struct uart_port *port,
758 struct termios *termios,
759 struct termios *old)
760 {
761 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
762 struct s3c24xx_uart_port *ourport = to_ourport(port);
763 struct s3c24xx_uart_clksrc *clksrc;
764 struct clk *clk;
765 unsigned long flags;
766 unsigned int baud, quot;
767 unsigned int ulcon;
768 unsigned int umcon;
769
770 /*
771 * We don't support modem control lines.
772 */
773 termios->c_cflag &= ~(HUPCL | CMSPAR);
774 termios->c_cflag |= CLOCAL;
775
776 /*
777 * Ask the core to calculate the divisor for us.
778 */
779
780 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
781
782 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
783 quot = port->custom_divisor;
784 else
785 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
786
787 /* check to see if we need to change clock source */
788
789 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
790 s3c24xx_serial_setsource(port, clksrc);
791
792 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
793 clk_disable(ourport->baudclk);
794 clk_unuse(ourport->baudclk);
795 ourport->baudclk = NULL;
796 }
797
798 clk_use(clk);
799 clk_enable(clk);
800
801 ourport->clksrc = clksrc;
802 ourport->baudclk = clk;
803 }
804
805 switch (termios->c_cflag & CSIZE) {
806 case CS5:
807 dbg("config: 5bits/char\n");
808 ulcon = S3C2410_LCON_CS5;
809 break;
810 case CS6:
811 dbg("config: 6bits/char\n");
812 ulcon = S3C2410_LCON_CS6;
813 break;
814 case CS7:
815 dbg("config: 7bits/char\n");
816 ulcon = S3C2410_LCON_CS7;
817 break;
818 case CS8:
819 default:
820 dbg("config: 8bits/char\n");
821 ulcon = S3C2410_LCON_CS8;
822 break;
823 }
824
825 /* preserve original lcon IR settings */
826 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
827
828 if (termios->c_cflag & CSTOPB)
829 ulcon |= S3C2410_LCON_STOPB;
830
831 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
832
833 if (termios->c_cflag & PARENB) {
834 if (termios->c_cflag & PARODD)
835 ulcon |= S3C2410_LCON_PODD;
836 else
837 ulcon |= S3C2410_LCON_PEVEN;
838 } else {
839 ulcon |= S3C2410_LCON_PNONE;
840 }
841
842 spin_lock_irqsave(&port->lock, flags);
843
844 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
845
846 wr_regl(port, S3C2410_ULCON, ulcon);
847 wr_regl(port, S3C2410_UBRDIV, quot);
848 wr_regl(port, S3C2410_UMCON, umcon);
849
850 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
851 rd_regl(port, S3C2410_ULCON),
852 rd_regl(port, S3C2410_UCON),
853 rd_regl(port, S3C2410_UFCON));
854
855 /*
856 * Update the per-port timeout.
857 */
858 uart_update_timeout(port, termios->c_cflag, baud);
859
860 /*
861 * Which character status flags are we interested in?
862 */
863 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
864 if (termios->c_iflag & INPCK)
865 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
866
867 /*
868 * Which character status flags should we ignore?
869 */
870 port->ignore_status_mask = 0;
871 if (termios->c_iflag & IGNPAR)
872 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
873 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
874 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
875
876 /*
877 * Ignore all characters if CREAD is not set.
878 */
879 if ((termios->c_cflag & CREAD) == 0)
880 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
881
882 spin_unlock_irqrestore(&port->lock, flags);
883 }
884
885 static const char *s3c24xx_serial_type(struct uart_port *port)
886 {
887 switch (port->type) {
888 case PORT_S3C2410:
889 return "S3C2410";
890 case PORT_S3C2440:
891 return "S3C2440";
892 default:
893 return NULL;
894 }
895 }
896
897 #define MAP_SIZE (0x100)
898
899 static void s3c24xx_serial_release_port(struct uart_port *port)
900 {
901 release_mem_region(port->mapbase, MAP_SIZE);
902 }
903
904 static int s3c24xx_serial_request_port(struct uart_port *port)
905 {
906 char *name = s3c24xx_serial_portname(port);
907 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
908 }
909
910 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
911 {
912 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
913
914 if (flags & UART_CONFIG_TYPE &&
915 s3c24xx_serial_request_port(port) == 0)
916 port->type = info->type;
917 }
918
919 /*
920 * verify the new serial_struct (for TIOCSSERIAL).
921 */
922 static int
923 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
924 {
925 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
926
927 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
928 return -EINVAL;
929
930 return 0;
931 }
932
933
934 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
935
936 static struct console s3c24xx_serial_console;
937
938 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
939 #else
940 #define S3C24XX_SERIAL_CONSOLE NULL
941 #endif
942
943 static struct uart_ops s3c24xx_serial_ops = {
944 .pm = s3c24xx_serial_pm,
945 .tx_empty = s3c24xx_serial_tx_empty,
946 .get_mctrl = s3c24xx_serial_get_mctrl,
947 .set_mctrl = s3c24xx_serial_set_mctrl,
948 .stop_tx = s3c24xx_serial_stop_tx,
949 .start_tx = s3c24xx_serial_start_tx,
950 .stop_rx = s3c24xx_serial_stop_rx,
951 .enable_ms = s3c24xx_serial_enable_ms,
952 .break_ctl = s3c24xx_serial_break_ctl,
953 .startup = s3c24xx_serial_startup,
954 .shutdown = s3c24xx_serial_shutdown,
955 .set_termios = s3c24xx_serial_set_termios,
956 .type = s3c24xx_serial_type,
957 .release_port = s3c24xx_serial_release_port,
958 .request_port = s3c24xx_serial_request_port,
959 .config_port = s3c24xx_serial_config_port,
960 .verify_port = s3c24xx_serial_verify_port,
961 };
962
963
964 static struct uart_driver s3c24xx_uart_drv = {
965 .owner = THIS_MODULE,
966 .dev_name = "s3c2410_serial",
967 .nr = 3,
968 .cons = S3C24XX_SERIAL_CONSOLE,
969 .driver_name = S3C24XX_SERIAL_NAME,
970 .devfs_name = S3C24XX_SERIAL_DEVFS,
971 .major = S3C24XX_SERIAL_MAJOR,
972 .minor = S3C24XX_SERIAL_MINOR,
973 };
974
975 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
976 [0] = {
977 .port = {
978 .lock = SPIN_LOCK_UNLOCKED,
979 .iotype = UPIO_MEM,
980 .irq = IRQ_S3CUART_RX0,
981 .uartclk = 0,
982 .fifosize = 16,
983 .ops = &s3c24xx_serial_ops,
984 .flags = UPF_BOOT_AUTOCONF,
985 .line = 0,
986 }
987 },
988 [1] = {
989 .port = {
990 .lock = SPIN_LOCK_UNLOCKED,
991 .iotype = UPIO_MEM,
992 .irq = IRQ_S3CUART_RX1,
993 .uartclk = 0,
994 .fifosize = 16,
995 .ops = &s3c24xx_serial_ops,
996 .flags = UPF_BOOT_AUTOCONF,
997 .line = 1,
998 }
999 },
1000 #if NR_PORTS > 2
1001
1002 [2] = {
1003 .port = {
1004 .lock = SPIN_LOCK_UNLOCKED,
1005 .iotype = UPIO_MEM,
1006 .irq = IRQ_S3CUART_RX2,
1007 .uartclk = 0,
1008 .fifosize = 16,
1009 .ops = &s3c24xx_serial_ops,
1010 .flags = UPF_BOOT_AUTOCONF,
1011 .line = 2,
1012 }
1013 }
1014 #endif
1015 };
1016
1017 /* s3c24xx_serial_resetport
1018 *
1019 * wrapper to call the specific reset for this port (reset the fifos
1020 * and the settings)
1021 */
1022
1023 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1024 struct s3c2410_uartcfg *cfg)
1025 {
1026 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1027
1028 return (info->reset_port)(port, cfg);
1029 }
1030
1031 /* s3c24xx_serial_init_port
1032 *
1033 * initialise a single serial port from the platform device given
1034 */
1035
1036 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1037 struct s3c24xx_uart_info *info,
1038 struct platform_device *platdev)
1039 {
1040 struct uart_port *port = &ourport->port;
1041 struct s3c2410_uartcfg *cfg;
1042 struct resource *res;
1043
1044 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1045
1046 if (platdev == NULL)
1047 return -ENODEV;
1048
1049 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1050
1051 if (port->mapbase != 0)
1052 return 0;
1053
1054 if (cfg->hwport > 3)
1055 return -EINVAL;
1056
1057 /* setup info for port */
1058 port->dev = &platdev->dev;
1059 ourport->info = info;
1060
1061 /* copy the info in from provided structure */
1062 ourport->port.fifosize = info->fifosize;
1063
1064 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1065
1066 port->uartclk = 1;
1067
1068 if (cfg->uart_flags & UPF_CONS_FLOW) {
1069 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1070 port->flags |= UPF_CONS_FLOW;
1071 }
1072
1073 /* sort our the physical and virtual addresses for each UART */
1074
1075 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1076 if (res == NULL) {
1077 printk(KERN_ERR "failed to find memory resource for uart\n");
1078 return -EINVAL;
1079 }
1080
1081 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1082
1083 port->mapbase = res->start;
1084 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1085 port->irq = platform_get_irq(platdev, 0);
1086
1087 ourport->clk = clk_get(&platdev->dev, "uart");
1088
1089 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1090 clk_use(ourport->clk);
1091
1092 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1093 port->mapbase, port->membase, port->irq, port->uartclk);
1094
1095 /* reset the fifos (and setup the uart) */
1096 s3c24xx_serial_resetport(port, cfg);
1097 return 0;
1098 }
1099
1100 /* Device driver serial port probe */
1101
1102 static int probe_index = 0;
1103
1104 int s3c24xx_serial_probe(struct device *_dev,
1105 struct s3c24xx_uart_info *info)
1106 {
1107 struct s3c24xx_uart_port *ourport;
1108 struct platform_device *dev = to_platform_device(_dev);
1109 int ret;
1110
1111 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1112
1113 ourport = &s3c24xx_serial_ports[probe_index];
1114 probe_index++;
1115
1116 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1117
1118 ret = s3c24xx_serial_init_port(ourport, info, dev);
1119 if (ret < 0)
1120 goto probe_err;
1121
1122 dbg("%s: adding port\n", __FUNCTION__);
1123 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1124 dev_set_drvdata(_dev, &ourport->port);
1125
1126 return 0;
1127
1128 probe_err:
1129 return ret;
1130 }
1131
1132 int s3c24xx_serial_remove(struct device *_dev)
1133 {
1134 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1135
1136 if (port)
1137 uart_remove_one_port(&s3c24xx_uart_drv, port);
1138
1139 return 0;
1140 }
1141
1142 /* UART power management code */
1143
1144 #ifdef CONFIG_PM
1145
1146 int s3c24xx_serial_suspend(struct device *dev, pm_message_t state, u32 level)
1147 {
1148 struct uart_port *port = s3c24xx_dev_to_port(dev);
1149
1150 if (port && level == SUSPEND_DISABLE)
1151 uart_suspend_port(&s3c24xx_uart_drv, port);
1152
1153 return 0;
1154 }
1155
1156 int s3c24xx_serial_resume(struct device *dev, u32 level)
1157 {
1158 struct uart_port *port = s3c24xx_dev_to_port(dev);
1159 struct s3c24xx_uart_port *ourport = to_ourport(port);
1160
1161 if (port && level == RESUME_ENABLE) {
1162 clk_enable(ourport->clk);
1163 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1164 clk_disable(ourport->clk);
1165
1166 uart_resume_port(&s3c24xx_uart_drv, port);
1167 }
1168
1169 return 0;
1170 }
1171
1172 #else
1173 #define s3c24xx_serial_suspend NULL
1174 #define s3c24xx_serial_resume NULL
1175 #endif
1176
1177 int s3c24xx_serial_init(struct device_driver *drv,
1178 struct s3c24xx_uart_info *info)
1179 {
1180 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1181 return driver_register(drv);
1182 }
1183
1184
1185 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1186 * port information
1187 */
1188
1189 /* cpu specific variations on the serial port support */
1190
1191 #ifdef CONFIG_CPU_S3C2400
1192
1193 static int s3c2400_serial_getsource(struct uart_port *port,
1194 struct s3c24xx_uart_clksrc *clk)
1195 {
1196 clk->divisor = 1;
1197 clk->name = "pclk";
1198
1199 return 0;
1200 }
1201
1202 static int s3c2400_serial_setsource(struct uart_port *port,
1203 struct s3c24xx_uart_clksrc *clk)
1204 {
1205 return 0;
1206 }
1207
1208 static int s3c2400_serial_resetport(struct uart_port *port,
1209 struct s3c2410_uartcfg *cfg)
1210 {
1211 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1212 port, port->mapbase, cfg);
1213
1214 wr_regl(port, S3C2410_UCON, cfg->ucon);
1215 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1216
1217 /* reset both fifos */
1218
1219 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1220 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1221
1222 return 0;
1223 }
1224
1225 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1226 .name = "Samsung S3C2400 UART",
1227 .type = PORT_S3C2400,
1228 .fifosize = 16,
1229 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1230 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1231 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1232 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1233 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1234 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1235 .get_clksrc = s3c2400_serial_getsource,
1236 .set_clksrc = s3c2400_serial_setsource,
1237 .reset_port = s3c2400_serial_resetport,
1238 };
1239
1240 static int s3c2400_serial_probe(struct device *dev)
1241 {
1242 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1243 }
1244
1245 static struct device_driver s3c2400_serial_drv = {
1246 .name = "s3c2400-uart",
1247 .bus = &platform_bus_type,
1248 .probe = s3c2400_serial_probe,
1249 .remove = s3c24xx_serial_remove,
1250 .suspend = s3c24xx_serial_suspend,
1251 .resume = s3c24xx_serial_resume,
1252 };
1253
1254 static inline int s3c2400_serial_init(void)
1255 {
1256 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1257 }
1258
1259 static inline void s3c2400_serial_exit(void)
1260 {
1261 driver_unregister(&s3c2400_serial_drv);
1262 }
1263
1264 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1265 #else
1266
1267 static inline int s3c2400_serial_init(void)
1268 {
1269 return 0;
1270 }
1271
1272 static inline void s3c2400_serial_exit(void)
1273 {
1274 }
1275
1276 #define s3c2400_uart_inf_at NULL
1277
1278 #endif /* CONFIG_CPU_S3C2400 */
1279
1280 /* S3C2410 support */
1281
1282 #ifdef CONFIG_CPU_S3C2410
1283
1284 static int s3c2410_serial_setsource(struct uart_port *port,
1285 struct s3c24xx_uart_clksrc *clk)
1286 {
1287 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1288
1289 if (strcmp(clk->name, "uclk") == 0)
1290 ucon |= S3C2410_UCON_UCLK;
1291 else
1292 ucon &= ~S3C2410_UCON_UCLK;
1293
1294 wr_regl(port, S3C2410_UCON, ucon);
1295 return 0;
1296 }
1297
1298 static int s3c2410_serial_getsource(struct uart_port *port,
1299 struct s3c24xx_uart_clksrc *clk)
1300 {
1301 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1302
1303 clk->divisor = 1;
1304 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1305
1306 return 0;
1307 }
1308
1309 static int s3c2410_serial_resetport(struct uart_port *port,
1310 struct s3c2410_uartcfg *cfg)
1311 {
1312 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1313 port, port->mapbase, cfg);
1314
1315 wr_regl(port, S3C2410_UCON, cfg->ucon);
1316 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1317
1318 /* reset both fifos */
1319
1320 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1321 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1322
1323 return 0;
1324 }
1325
1326 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1327 .name = "Samsung S3C2410 UART",
1328 .type = PORT_S3C2410,
1329 .fifosize = 16,
1330 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1331 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1332 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1333 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1334 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1335 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1336 .get_clksrc = s3c2410_serial_getsource,
1337 .set_clksrc = s3c2410_serial_setsource,
1338 .reset_port = s3c2410_serial_resetport,
1339 };
1340
1341 /* device management */
1342
1343 static int s3c2410_serial_probe(struct device *dev)
1344 {
1345 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1346 }
1347
1348 static struct device_driver s3c2410_serial_drv = {
1349 .name = "s3c2410-uart",
1350 .bus = &platform_bus_type,
1351 .probe = s3c2410_serial_probe,
1352 .remove = s3c24xx_serial_remove,
1353 .suspend = s3c24xx_serial_suspend,
1354 .resume = s3c24xx_serial_resume,
1355 };
1356
1357 static inline int s3c2410_serial_init(void)
1358 {
1359 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1360 }
1361
1362 static inline void s3c2410_serial_exit(void)
1363 {
1364 driver_unregister(&s3c2410_serial_drv);
1365 }
1366
1367 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1368 #else
1369
1370 static inline int s3c2410_serial_init(void)
1371 {
1372 return 0;
1373 }
1374
1375 static inline void s3c2410_serial_exit(void)
1376 {
1377 }
1378
1379 #define s3c2410_uart_inf_at NULL
1380
1381 #endif /* CONFIG_CPU_S3C2410 */
1382
1383 #ifdef CONFIG_CPU_S3C2440
1384
1385 static int s3c2440_serial_setsource(struct uart_port *port,
1386 struct s3c24xx_uart_clksrc *clk)
1387 {
1388 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1389
1390 // todo - proper fclk<>nonfclk switch //
1391
1392 ucon &= ~S3C2440_UCON_CLKMASK;
1393
1394 if (strcmp(clk->name, "uclk") == 0)
1395 ucon |= S3C2440_UCON_UCLK;
1396 else if (strcmp(clk->name, "pclk") == 0)
1397 ucon |= S3C2440_UCON_PCLK;
1398 else if (strcmp(clk->name, "fclk") == 0)
1399 ucon |= S3C2440_UCON_FCLK;
1400 else {
1401 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1402 return -EINVAL;
1403 }
1404
1405 wr_regl(port, S3C2410_UCON, ucon);
1406 return 0;
1407 }
1408
1409
1410 static int s3c2440_serial_getsource(struct uart_port *port,
1411 struct s3c24xx_uart_clksrc *clk)
1412 {
1413 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1414 unsigned long ucon0, ucon1, ucon2;
1415
1416 switch (ucon & S3C2440_UCON_CLKMASK) {
1417 case S3C2440_UCON_UCLK:
1418 clk->divisor = 1;
1419 clk->name = "uclk";
1420 break;
1421
1422 case S3C2440_UCON_PCLK:
1423 case S3C2440_UCON_PCLK2:
1424 clk->divisor = 1;
1425 clk->name = "pclk";
1426 break;
1427
1428 case S3C2440_UCON_FCLK:
1429 /* the fun of calculating the uart divisors on
1430 * the s3c2440 */
1431
1432 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1433 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1434 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1435
1436 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1437
1438 ucon0 &= S3C2440_UCON0_DIVMASK;
1439 ucon1 &= S3C2440_UCON1_DIVMASK;
1440 ucon2 &= S3C2440_UCON2_DIVMASK;
1441
1442 if (ucon0 != 0) {
1443 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1444 clk->divisor += 6;
1445 } else if (ucon1 != 0) {
1446 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1447 clk->divisor += 21;
1448 } else if (ucon2 != 0) {
1449 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1450 clk->divisor += 36;
1451 } else {
1452 /* manual calims 44, seems to be 9 */
1453 clk->divisor = 9;
1454 }
1455
1456 clk->name = "fclk";
1457 break;
1458 }
1459
1460 return 0;
1461 }
1462
1463 static int s3c2440_serial_resetport(struct uart_port *port,
1464 struct s3c2410_uartcfg *cfg)
1465 {
1466 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1467
1468 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1469 port, port->mapbase, cfg);
1470
1471 /* ensure we don't change the clock settings... */
1472
1473 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1474
1475 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1476 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1477
1478 /* reset both fifos */
1479
1480 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1481 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1482
1483 return 0;
1484 }
1485
1486 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1487 .name = "Samsung S3C2440 UART",
1488 .type = PORT_S3C2440,
1489 .fifosize = 64,
1490 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1491 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1492 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1493 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1494 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1495 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1496 .get_clksrc = s3c2440_serial_getsource,
1497 .set_clksrc = s3c2440_serial_setsource,
1498 .reset_port = s3c2440_serial_resetport,
1499 };
1500
1501 /* device management */
1502
1503 static int s3c2440_serial_probe(struct device *dev)
1504 {
1505 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1506 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1507 }
1508
1509 static struct device_driver s3c2440_serial_drv = {
1510 .name = "s3c2440-uart",
1511 .bus = &platform_bus_type,
1512 .probe = s3c2440_serial_probe,
1513 .remove = s3c24xx_serial_remove,
1514 .suspend = s3c24xx_serial_suspend,
1515 .resume = s3c24xx_serial_resume,
1516 };
1517
1518
1519 static inline int s3c2440_serial_init(void)
1520 {
1521 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1522 }
1523
1524 static inline void s3c2440_serial_exit(void)
1525 {
1526 driver_unregister(&s3c2440_serial_drv);
1527 }
1528
1529 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1530 #else
1531
1532 static inline int s3c2440_serial_init(void)
1533 {
1534 return 0;
1535 }
1536
1537 static inline void s3c2440_serial_exit(void)
1538 {
1539 }
1540
1541 #define s3c2440_uart_inf_at NULL
1542 #endif /* CONFIG_CPU_S3C2440 */
1543
1544 /* module initialisation code */
1545
1546 static int __init s3c24xx_serial_modinit(void)
1547 {
1548 int ret;
1549
1550 ret = uart_register_driver(&s3c24xx_uart_drv);
1551 if (ret < 0) {
1552 printk(KERN_ERR "failed to register UART driver\n");
1553 return -1;
1554 }
1555
1556 s3c2400_serial_init();
1557 s3c2410_serial_init();
1558 s3c2440_serial_init();
1559
1560 return 0;
1561 }
1562
1563 static void __exit s3c24xx_serial_modexit(void)
1564 {
1565 s3c2400_serial_exit();
1566 s3c2410_serial_exit();
1567 s3c2440_serial_exit();
1568
1569 uart_unregister_driver(&s3c24xx_uart_drv);
1570 }
1571
1572
1573 module_init(s3c24xx_serial_modinit);
1574 module_exit(s3c24xx_serial_modexit);
1575
1576 /* Console code */
1577
1578 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1579
1580 static struct uart_port *cons_uart;
1581
1582 static int
1583 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1584 {
1585 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1586 unsigned long ufstat, utrstat;
1587
1588 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1589 /* fifo mode - check ammount of data in fifo registers... */
1590
1591 ufstat = rd_regl(port, S3C2410_UFSTAT);
1592 return (ufstat & info->tx_fifofull) ? 0 : 1;
1593 }
1594
1595 /* in non-fifo mode, we go and use the tx buffer empty */
1596
1597 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1598 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1599 }
1600
1601 static void
1602 s3c24xx_serial_console_write(struct console *co, const char *s,
1603 unsigned int count)
1604 {
1605 int i;
1606 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1607
1608 for (i = 0; i < count; i++) {
1609 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1610 barrier();
1611
1612 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1613
1614 if (s[i] == '\n') {
1615 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1616 barrier();
1617
1618 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1619 }
1620 }
1621 }
1622
1623 static void __init
1624 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1625 int *parity, int *bits)
1626 {
1627 struct s3c24xx_uart_clksrc clksrc;
1628 struct clk *clk;
1629 unsigned int ulcon;
1630 unsigned int ucon;
1631 unsigned int ubrdiv;
1632 unsigned long rate;
1633
1634 ulcon = rd_regl(port, S3C2410_ULCON);
1635 ucon = rd_regl(port, S3C2410_UCON);
1636 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1637
1638 dbg("s3c24xx_serial_get_options: port=%p\n"
1639 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1640 port, ulcon, ucon, ubrdiv);
1641
1642 if ((ucon & 0xf) != 0) {
1643 /* consider the serial port configured if the tx/rx mode set */
1644
1645 switch (ulcon & S3C2410_LCON_CSMASK) {
1646 case S3C2410_LCON_CS5:
1647 *bits = 5;
1648 break;
1649 case S3C2410_LCON_CS6:
1650 *bits = 6;
1651 break;
1652 case S3C2410_LCON_CS7:
1653 *bits = 7;
1654 break;
1655 default:
1656 case S3C2410_LCON_CS8:
1657 *bits = 8;
1658 break;
1659 }
1660
1661 switch (ulcon & S3C2410_LCON_PMASK) {
1662 case S3C2410_LCON_PEVEN:
1663 *parity = 'e';
1664 break;
1665
1666 case S3C2410_LCON_PODD:
1667 *parity = 'o';
1668 break;
1669
1670 case S3C2410_LCON_PNONE:
1671 default:
1672 *parity = 'n';
1673 }
1674
1675 /* now calculate the baud rate */
1676
1677 s3c24xx_serial_getsource(port, &clksrc);
1678
1679 clk = clk_get(port->dev, clksrc.name);
1680 if (!IS_ERR(clk) && clk != NULL)
1681 rate = clk_get_rate(clk) / clksrc.divisor;
1682 else
1683 rate = 1;
1684
1685
1686 *baud = rate / ( 16 * (ubrdiv + 1));
1687 dbg("calculated baud %d\n", *baud);
1688 }
1689
1690 }
1691
1692 /* s3c24xx_serial_init_ports
1693 *
1694 * initialise the serial ports from the machine provided initialisation
1695 * data.
1696 */
1697
1698 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1699 {
1700 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1701 struct platform_device **platdev_ptr;
1702 int i;
1703
1704 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1705
1706 platdev_ptr = s3c24xx_uart_devs;
1707
1708 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1709 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1710 }
1711
1712 return 0;
1713 }
1714
1715 static int __init
1716 s3c24xx_serial_console_setup(struct console *co, char *options)
1717 {
1718 struct uart_port *port;
1719 int baud = 9600;
1720 int bits = 8;
1721 int parity = 'n';
1722 int flow = 'n';
1723
1724 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1725 co, co->index, options);
1726
1727 /* is this a valid port */
1728
1729 if (co->index == -1 || co->index >= NR_PORTS)
1730 co->index = 0;
1731
1732 port = &s3c24xx_serial_ports[co->index].port;
1733
1734 /* is the port configured? */
1735
1736 if (port->mapbase == 0x0) {
1737 co->index = 0;
1738 port = &s3c24xx_serial_ports[co->index].port;
1739 }
1740
1741 cons_uart = port;
1742
1743 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1744
1745 /*
1746 * Check whether an invalid uart number has been specified, and
1747 * if so, search for the first available port that does have
1748 * console support.
1749 */
1750 if (options)
1751 uart_parse_options(options, &baud, &parity, &bits, &flow);
1752 else
1753 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1754
1755 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1756
1757 return uart_set_options(port, co, baud, parity, bits, flow);
1758 }
1759
1760 /* s3c24xx_serial_initconsole
1761 *
1762 * initialise the console from one of the uart drivers
1763 */
1764
1765 static struct console s3c24xx_serial_console =
1766 {
1767 .name = S3C24XX_SERIAL_NAME,
1768 .device = uart_console_device,
1769 .flags = CON_PRINTBUFFER,
1770 .index = -1,
1771 .write = s3c24xx_serial_console_write,
1772 .setup = s3c24xx_serial_console_setup
1773 };
1774
1775 static int s3c24xx_serial_initconsole(void)
1776 {
1777 struct s3c24xx_uart_info *info;
1778 struct platform_device *dev = s3c24xx_uart_devs[0];
1779
1780 dbg("s3c24xx_serial_initconsole\n");
1781
1782 /* select driver based on the cpu */
1783
1784 if (dev == NULL) {
1785 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1786 return 0;
1787 }
1788
1789 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1790 info = s3c2400_uart_inf_at;
1791 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1792 info = s3c2410_uart_inf_at;
1793 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1794 info = s3c2440_uart_inf_at;
1795 } else {
1796 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1797 return 0;
1798 }
1799
1800 if (info == NULL) {
1801 printk(KERN_ERR "s3c24xx: no driver for console\n");
1802 return 0;
1803 }
1804
1805 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1806 s3c24xx_serial_init_ports(info);
1807
1808 register_console(&s3c24xx_serial_console);
1809 return 0;
1810 }
1811
1812 console_initcall(s3c24xx_serial_initconsole);
1813
1814 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1815
1816 MODULE_LICENSE("GPL");
1817 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1818 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
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