drivers/ide/pci/sl82c105.c

   1 /*
   2  * linux/drivers/ide/pci/sl82c105.c
   3  *
   4  * SL82C105/Winbond 553 IDE driver
   5  *
   6  * Maintainer unknown.
   7  *
   8  * Drive tuning added from Rebel.com's kernel sources
   9  *  -- Russell King (15/11/98) linux@arm.linux.org.uk
  10  *
  11  * Merge in Russell's HW workarounds, fix various problems
  12  * with the timing registers setup.
  13  *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/timer.h>
  21 #include <linux/mm.h>
  22 #include <linux/ioport.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/pci.h>
  27 #include <linux/ide.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/dma.h>
  31
  32 #undef DEBUG
  33
  34 #ifdef DEBUG
  35 #define DBG(arg) printk arg
  36 #else
  37 #define DBG(fmt,...)
  38 #endif
  39 /*
  40  * SL82C105 PCI config register 0x40 bits.
  41  */
  42 #define CTRL_IDE_IRQB   (1 << 30)
  43 #define CTRL_IDE_IRQA   (1 << 28)
  44 #define CTRL_LEGIRQ     (1 << 11)
  45 #define CTRL_P1F16      (1 << 5)
  46 #define CTRL_P1EN       (1 << 4)
  47 #define CTRL_P0F16      (1 << 1)
  48 #define CTRL_P0EN       (1 << 0)
  49
  50 /*
  51  * Convert a PIO mode and cycle time to the required on/off
  52  * times for the interface.  This has protection against run-away
  53  * timings.
  54  */
  55 static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
  56 {
  57         unsigned int cmd_on;
  58         unsigned int cmd_off;
  59
  60         cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
  61         cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
  62
  63         if (cmd_on > 32)
  64                 cmd_on = 32;
  65         if (cmd_on == 0)
  66                 cmd_on = 1;
  67
  68         if (cmd_off > 32)
  69                 cmd_off = 32;
  70         if (cmd_off == 0)
  71                 cmd_off = 1;
  72
  73         return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
  74 }
  75
  76 /*
  77  * Configure the drive and chipset for PIO
  78  */
  79 static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
  80 {
  81         ide_hwif_t *hwif = HWIF(drive);
  82         struct pci_dev *dev = hwif->pci_dev;
  83         ide_pio_data_t p;
  84         u16 drv_ctrl = 0x909;
  85         unsigned int xfer_mode, reg;
  86
  87         DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
  88                 drive->name, pio, report, chipset_only));
  89
  90         reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
  91
  92         pio = ide_get_best_pio_mode(drive, pio, 5, &p);
  93
  94         xfer_mode = XFER_PIO_0 + pio;
  95
  96         if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
  97                 drv_ctrl = get_timing_sl82c105(&p);
  98                 drive->pio_speed = xfer_mode;
  99         } else
 100                 drive->pio_speed = XFER_PIO_0;
 101
 102         if (drive->using_dma == 0) {
 103                 /*
 104                  * If we are actually using MW DMA, then we can not
 105                  * reprogram the interface drive control register.
 106                  */
 107                 pci_write_config_word(dev, reg, drv_ctrl);
 108                 pci_read_config_word(dev, reg, &drv_ctrl);
 109
 110                 if (report) {
 111                         printk("%s: selected %s (%dns) (%04X)\n", drive->name,
 112                                ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
 113                 }
 114         }
 115 }
 116
 117 /*
 118  * Configure the drive and the chipset for DMA
 119  */
 120 static int config_for_dma (ide_drive_t *drive)
 121 {
 122         ide_hwif_t *hwif = HWIF(drive);
 123         struct pci_dev *dev = hwif->pci_dev;
 124         unsigned int reg;
 125
 126         DBG(("config_for_dma(drive:%s)\n", drive->name));
 127
 128         reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
 129
 130         if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
 131                 return 1;
 132
 133         pci_write_config_word(dev, reg, 0x0240);
 134
 135         return 0;
 136 }
 137
 138 /*
 139  * Check to see if the drive and
 140  * chipset is capable of DMA mode
 141  */
 142
 143 static int sl82c105_check_drive (ide_drive_t *drive)
 144 {
 145         ide_hwif_t *hwif        = HWIF(drive);
 146
 147         DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
 148
 149         do {
 150                 struct hd_driveid *id = drive->id;
 151
 152                 if (!drive->autodma)
 153                         break;
 154
 155                 if (!id || !(id->capability & 1))
 156                         break;
 157
 158                 /* Consult the list of known "bad" drives */
 159                 if (__ide_dma_bad_drive(drive))
 160                         break;
 161
 162                 if (id->field_valid & 2) {
 163                         if ((id->dma_mword & hwif->mwdma_mask) ||
 164                             (id->dma_1word & hwif->swdma_mask))
 165                                 return hwif->ide_dma_on(drive);
 166                 }
 167
 168                 if (__ide_dma_good_drive(drive))
 169                         return hwif->ide_dma_on(drive);
 170         } while (0);
 171
 172         return hwif->ide_dma_off_quietly(drive);
 173 }
 174
 175 /*
 176  * The SL82C105 holds off all IDE interrupts while in DMA mode until
 177  * all DMA activity is completed.  Sometimes this causes problems (eg,
 178  * when the drive wants to report an error condition).
 179  *
 180  * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 181  * state machine.  We need to kick this to work around various bugs.
 182  */
 183 static inline void sl82c105_reset_host(struct pci_dev *dev)
 184 {
 185         u16 val;
 186
 187         pci_read_config_word(dev, 0x7e, &val);
 188         pci_write_config_word(dev, 0x7e, val | (1 << 2));
 189         pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
 190 }
 191
 192 /*
 193  * If we get an IRQ timeout, it might be that the DMA state machine
 194  * got confused.  Fix from Todd Inglett.  Details from Winbond.
 195  *
 196  * This function is called when the IDE timer expires, the drive
 197  * indicates that it is READY, and we were waiting for DMA to complete.
 198  */
 199 static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
 200 {
 201         ide_hwif_t *hwif = HWIF(drive);
 202         struct pci_dev *dev = hwif->pci_dev;
 203         u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
 204         unsigned long dma_base = hwif->dma_base;
 205
 206         printk("sl82c105: lost IRQ: resetting host\n");
 207
 208         /*
 209          * Check the raw interrupt from the drive.
 210          */
 211         pci_read_config_dword(dev, 0x40, &val);
 212         if (val & mask)
 213                 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
 214
 215         /*
 216          * Was DMA enabled?  If so, disable it - we're resetting the
 217          * host.  The IDE layer will be handling the drive for us.
 218          */
 219         val = hwif->INB(dma_base);
 220         if (val & 1) {
 221                 outb(val & ~1, dma_base);
 222                 printk("sl82c105: DMA was enabled\n");
 223         }
 224
 225         sl82c105_reset_host(dev);
 226
 227         /* ide_dmaproc would return 1, so we do as well */
 228         return 1;
 229 }
 230
 231 /*
 232  * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 233  * Winbond recommend that the DMA state machine is reset prior to
 234  * setting the bus master DMA enable bit.
 235  *
 236  * The generic IDE core will have disabled the BMEN bit before this
 237  * function is called.
 238  */
 239 static void sl82c105_ide_dma_start(ide_drive_t *drive)
 240 {
 241         ide_hwif_t *hwif = HWIF(drive);
 242         struct pci_dev *dev = hwif->pci_dev;
 243
 244         sl82c105_reset_host(dev);
 245         ide_dma_start(drive);
 246 }
 247
 248 static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
 249 {
 250         ide_hwif_t *hwif = HWIF(drive);
 251         struct pci_dev *dev = hwif->pci_dev;
 252
 253         DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
 254
 255         sl82c105_reset_host(dev);
 256         return __ide_dma_timeout(drive);
 257 }
 258
 259 static int sl82c105_ide_dma_on (ide_drive_t *drive)
 260 {
 261         DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
 262
 263         if (config_for_dma(drive)) {
 264                 config_for_pio(drive, 4, 0, 0);
 265                 return HWIF(drive)->ide_dma_off_quietly(drive);
 266         }
 267         printk(KERN_INFO "%s: DMA enabled\n", drive->name);
 268         return __ide_dma_on(drive);
 269 }
 270
 271 static int sl82c105_ide_dma_off_quietly (ide_drive_t *drive)
 272 {
 273         u8 speed = XFER_PIO_0;
 274         int rc;
 275
 276         DBG(("sl82c105_ide_dma_off_quietly(drive:%s)\n", drive->name));
 277
 278         rc = __ide_dma_off_quietly(drive);
 279         if (drive->pio_speed)
 280                 speed = drive->pio_speed - XFER_PIO_0;
 281         config_for_pio(drive, speed, 0, 1);
 282         drive->current_speed = drive->pio_speed;
 283
 284         return rc;
 285 }
 286
 287 /*
 288  * Ok, that is nasty, but we must make sure the DMA timings
 289  * won't be used for a PIO access. The solution here is
 290  * to make sure the 16 bits mode is diabled on the channel
 291  * when DMA is enabled, thus causing the chip to use PIO0
 292  * timings for those operations.
 293  */
 294 static void sl82c105_selectproc(ide_drive_t *drive)
 295 {
 296         ide_hwif_t *hwif = HWIF(drive);
 297         struct pci_dev *dev = hwif->pci_dev;
 298         u32 val, old, mask;
 299
 300         //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
 301
 302         mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
 303         old = val = *((u32 *)&hwif->hwif_data);
 304         if (drive->using_dma)
 305                 val &= ~mask;
 306         else
 307                 val |= mask;
 308         if (old != val) {
 309                 pci_write_config_dword(dev, 0x40, val);
 310                 *((u32 *)&hwif->hwif_data) = val;
 311         }
 312 }
 313
 314 /*
 315  * ATA reset will clear the 16 bits mode in the control
 316  * register, we need to update our cache
 317  */
 318 static void sl82c105_resetproc(ide_drive_t *drive)
 319 {
 320         ide_hwif_t *hwif = HWIF(drive);
 321         struct pci_dev *dev = hwif->pci_dev;
 322         u32 val;
 323
 324         DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
 325
 326         pci_read_config_dword(dev, 0x40, &val);
 327         *((u32 *)&hwif->hwif_data) = val;
 328 }
 329
 330 /*
 331  * We only deal with PIO mode here - DMA mode 'using_dma' is not
 332  * initialised at the point that this function is called.
 333  */
 334 static void tune_sl82c105(ide_drive_t *drive, u8 pio)
 335 {
 336         DBG(("tune_sl82c105(drive:%s)\n", drive->name));
 337
 338         config_for_pio(drive, pio, 1, 0);
 339
 340         /*
 341          * We support 32-bit I/O on this interface, and it
 342          * doesn't have problems with interrupts.
 343          */
 344         drive->io_32bit = 1;
 345         drive->unmask = 1;
 346 }
 347
 348 /*
 349  * Return the revision of the Winbond bridge
 350  * which this function is part of.
 351  */
 352 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
 353 {
 354         struct pci_dev *bridge;
 355         u8 rev;
 356
 357         /*
 358          * The bridge should be part of the same device, but function 0.
 359          */
 360         bridge = pci_find_slot(dev->bus->number,
 361                                PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 362         if (!bridge)
 363                 return -1;
 364
 365         /*
 366          * Make sure it is a Winbond 553 and is an ISA bridge.
 367          */
 368         if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
 369             bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
 370             bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
 371                 return -1;
 372
 373         /*
 374          * We need to find function 0's revision, not function 1
 375          */
 376         pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
 377
 378         return rev;
 379 }
 380
 381 /*
 382  * Enable the PCI device
 383  *
 384  * --BenH: It's arch fixup code that should enable channels that
 385  * have not been enabled by firmware. I decided we can still enable
 386  * channel 0 here at least, but channel 1 has to be enabled by
 387  * firmware or arch code. We still set both to 16 bits mode.
 388  */
 389 static unsigned int __init init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
 390 {
 391         u32 val;
 392
 393         DBG(("init_chipset_sl82c105()\n"));
 394
 395         pci_read_config_dword(dev, 0x40, &val);
 396         val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
 397         pci_write_config_dword(dev, 0x40, val);
 398
 399         return dev->irq;
 400 }
 401
 402 static void __init init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
 403 {
 404         unsigned int rev;
 405         u8 dma_state;
 406
 407         DBG(("init_dma_sl82c105(hwif: ide%d, dma_base: 0x%08x)\n", hwif->index, dma_base));
 408
 409         hwif->autodma = 0;
 410
 411         if (!dma_base)
 412                 return;
 413
 414         dma_state = hwif->INB(dma_base + 2);
 415         rev = sl82c105_bridge_revision(hwif->pci_dev);
 416         if (rev <= 5) {
 417                 printk("    %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
 418                        hwif->name, rev);
 419                 dma_state &= ~0x60;
 420         } else {
 421                 dma_state |= 0x60;
 422                 if (!noautodma)
 423                         hwif->autodma = 1;
 424         }
 425         hwif->OUTB(dma_state, dma_base + 2);
 426
 427         ide_setup_dma(hwif, dma_base, 8);
 428 }
 429
 430 /*
 431  * Initialise the chip
 432  */
 433
 434 static void __init init_hwif_sl82c105(ide_hwif_t *hwif)
 435 {
 436         struct pci_dev *dev = hwif->pci_dev;
 437         u32 val;
 438
 439         DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
 440
 441         hwif->tuneproc = tune_sl82c105;
 442         hwif->selectproc = sl82c105_selectproc;
 443         hwif->resetproc = sl82c105_resetproc;
 444
 445         /* Default to PIO 0 for fallback unless tuned otherwise,
 446          * we always autotune PIO, this is done before DMA is
 447          * checked, so there is no risk of accidentally disabling
 448          * DMA
 449           */
 450         hwif->drives[0].pio_speed = XFER_PIO_0;
 451         hwif->drives[0].autotune = 1;
 452         hwif->drives[1].pio_speed = XFER_PIO_1;
 453         hwif->drives[1].autotune = 1;
 454
 455         pci_read_config_dword(dev, 0x40, &val);
 456         *((u32 *)&hwif->hwif_data) = val;
 457
 458         if (!hwif->dma_base)
 459                 return;
 460
 461         hwif->atapi_dma = 1;
 462         hwif->mwdma_mask = 0x07;
 463         hwif->swdma_mask = 0x07;
 464
 465 #ifdef CONFIG_BLK_DEV_IDEDMA
 466         hwif->ide_dma_check = &sl82c105_check_drive;
 467         hwif->ide_dma_on = &sl82c105_ide_dma_on;
 468         hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
 469         hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
 470         hwif->dma_start = &sl82c105_ide_dma_start;
 471         hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
 472
 473         if (!noautodma)
 474                 hwif->autodma = 1;
 475         hwif->drives[0].autodma = hwif->autodma;
 476         hwif->drives[1].autodma = hwif->autodma;
 477 #endif /* CONFIG_BLK_DEV_IDEDMA */
 478 }
 479
 480 static ide_pci_device_t sl82c105_chipset __devinitdata = {
 481         .name           = "W82C105",
 482         .init_chipset   = init_chipset_sl82c105,
 483         .init_hwif      = init_hwif_sl82c105,
 484         .init_dma       = init_dma_sl82c105,
 485         .channels       = 2,
 486         .autodma        = NOAUTODMA,
 487         .enablebits     = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
 488         .bootable       = ON_BOARD,
 489 };
 490
 491 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 492 {
 493         return ide_setup_pci_device(dev, &sl82c105_chipset);
 494 }
 495
 496 static struct pci_device_id sl82c105_pci_tbl[] = {
 497         { PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 498         { 0, },
 499 };
 500 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
 501
 502 static struct pci_driver driver = {
 503         .name           = "W82C105_IDE",
 504         .id_table       = sl82c105_pci_tbl,
 505         .probe          = sl82c105_init_one,
 506 };
 507
 508 static int sl82c105_ide_init(void)
 509 {
 510         return ide_pci_register_driver(&driver);
 511 }
 512
 513 module_init(sl82c105_ide_init);
 514
 515 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
 516 MODULE_LICENSE("GPL");