drivers/ieee1394/pcilynx.h

   1 #ifndef __PCILYNX_H__
   2 #define __PCILYNX_H__
   3
   4 #include <linux/config.h>
   5
   6 #define PCILYNX_DRIVER_NAME      "pcilynx"
   7 #define PCILYNX_MAJOR            177
   8
   9 #define PCILYNX_MINOR_AUX_START  0
  10 #define PCILYNX_MINOR_ROM_START  16
  11 #define PCILYNX_MINOR_RAM_START  32
  12
  13 #define PCILYNX_MAX_REGISTER     0xfff
  14 #define PCILYNX_MAX_MEMORY       0xffff
  15
  16 #define PCI_DEVICE_ID_TI_PCILYNX 0x8000
  17 #define MAX_PCILYNX_CARDS        4
  18 #define LOCALRAM_SIZE            4096
  19
  20 #define NUM_ISORCV_PCL           4
  21 #define MAX_ISORCV_SIZE          2048
  22 #define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
  23 #define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
  24
  25 #define CHANNEL_LOCALBUS         0
  26 #define CHANNEL_ASYNC_RCV        1
  27 #define CHANNEL_ISO_RCV          2
  28 #define CHANNEL_ASYNC_SEND       3
  29 #define CHANNEL_ISO_SEND         4
  30
  31 #define PCILYNX_CONFIG_ROM_LENGTH   1024
  32
  33 typedef int pcl_t;
  34
  35 struct ti_lynx {
  36         int id; /* sequential card number */
  37
  38         spinlock_t lock;
  39
  40         struct pci_dev *dev;
  41
  42         struct {
  43                 unsigned reg_1394a:1;
  44                 u32 vendor;
  45                 u32 product;
  46         } phyic;
  47
  48         enum { clear, have_intr, have_aux_buf, have_pcl_mem,
  49                have_1394_buffers, have_iomappings, is_host } state;
  50
  51         /* remapped memory spaces */
  52         void __iomem *registers;
  53         void __iomem *local_rom;
  54         void __iomem *local_ram;
  55         void __iomem *aux_port;
  56         quadlet_t bus_info_block[5];
  57
  58 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
  59         atomic_t aux_intr_seen;
  60         wait_queue_head_t aux_intr_wait;
  61
  62         void *mem_dma_buffer;
  63         dma_addr_t mem_dma_buffer_dma;
  64         struct semaphore mem_dma_mutex;
  65         wait_queue_head_t mem_dma_intr_wait;
  66 #endif
  67
  68         /*
  69          * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
  70          * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
  71          * the following is an allocation bitmap
  72          */
  73         u8 pcl_bmap[LOCALRAM_SIZE / 1024];
  74
  75 #ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
  76         /* point to PCLs memory area if needed */
  77         void *pcl_mem;
  78         dma_addr_t pcl_mem_dma;
  79 #endif
  80
  81         /* PCLs for local mem / aux transfers */
  82         pcl_t dmem_pcl;
  83
  84         /* IEEE-1394 part follows */
  85         struct hpsb_host *host;
  86
  87         int phyid, isroot;
  88         int selfid_size;
  89         int phy_reg0;
  90
  91         spinlock_t phy_reg_lock;
  92
  93         pcl_t rcv_pcl_start, rcv_pcl;
  94         void *rcv_page;
  95         dma_addr_t rcv_page_dma;
  96         int rcv_active;
  97
  98         struct lynx_send_data {
  99                 pcl_t pcl_start, pcl;
 100                 struct list_head queue;
 101                 struct list_head pcl_queue; /* this queue contains at most one packet */
 102                 spinlock_t queue_lock;
 103                 dma_addr_t header_dma, data_dma;
 104                 int channel;
 105         } async, iso_send;
 106
 107         struct {
 108                 pcl_t pcl[NUM_ISORCV_PCL];
 109                 u32 stat[NUM_ISORCV_PCL];
 110                 void *page[ISORCV_PAGES];
 111                 dma_addr_t page_dma[ISORCV_PAGES];
 112                 pcl_t pcl_start;
 113                 int chan_count;
 114                 int next, last, used, running;
 115                 struct tasklet_struct tq;
 116                 spinlock_t lock;
 117         } iso_rcv;
 118
 119         u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
 120 };
 121
 122 /* the per-file data structure for mem space access */
 123 struct memdata {
 124         struct ti_lynx *lynx;
 125         int cid;
 126         atomic_t aux_intr_last_seen;
 127         /* enum values are the same as LBUS_ADDR_SEL_* values below */
 128         enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
 129 };
 130
 131
 132
 133 /*
 134  * Register read and write helper functions.
 135  */
 136 static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
 137 {
 138         writel(data, lynx->registers + offset);
 139 }
 140
 141 static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
 142 {
 143         return readl(lynx->registers + offset);
 144 }
 145
 146 static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
 147                                 u32 mask)
 148 {
 149         reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
 150 }
 151
 152 static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
 153                                   u32 mask)
 154 {
 155         reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
 156 }
 157
 158
 159
 160 /* chip register definitions follow */
 161
 162 #define PCI_LATENCY_CACHELINE             0x0c
 163
 164 #define MISC_CONTROL                      0x40
 165 #define MISC_CONTROL_SWRESET              (1<<0)
 166
 167 #define SERIAL_EEPROM_CONTROL             0x44
 168
 169 #define PCI_INT_STATUS                    0x48
 170 #define PCI_INT_ENABLE                    0x4c
 171 /* status and enable have identical bit numbers */
 172 #define PCI_INT_INT_PEND                  (1<<31)
 173 #define PCI_INT_FORCED_INT                (1<<30)
 174 #define PCI_INT_SLV_ADR_PERR              (1<<28)
 175 #define PCI_INT_SLV_DAT_PERR              (1<<27)
 176 #define PCI_INT_MST_DAT_PERR              (1<<26)
 177 #define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
 178 #define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
 179 #define PCI_INT_AUX_TIMEOUT               (1<<18)
 180 #define PCI_INT_AUX_INT                   (1<<17)
 181 #define PCI_INT_1394                      (1<<16)
 182 #define PCI_INT_DMA4_PCL                  (1<<9)
 183 #define PCI_INT_DMA4_HLT                  (1<<8)
 184 #define PCI_INT_DMA3_PCL                  (1<<7)
 185 #define PCI_INT_DMA3_HLT                  (1<<6)
 186 #define PCI_INT_DMA2_PCL                  (1<<5)
 187 #define PCI_INT_DMA2_HLT                  (1<<4)
 188 #define PCI_INT_DMA1_PCL                  (1<<3)
 189 #define PCI_INT_DMA1_HLT                  (1<<2)
 190 #define PCI_INT_DMA0_PCL                  (1<<1)
 191 #define PCI_INT_DMA0_HLT                  (1<<0)
 192 /* all DMA interrupts combined: */
 193 #define PCI_INT_DMA_ALL                   0x3ff
 194
 195 #define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
 196 #define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
 197
 198 #define LBUS_ADDR                         0xb4
 199 #define LBUS_ADDR_SEL_RAM                 (0x0<<16)
 200 #define LBUS_ADDR_SEL_ROM                 (0x1<<16)
 201 #define LBUS_ADDR_SEL_AUX                 (0x2<<16)
 202 #define LBUS_ADDR_SEL_ZV                  (0x3<<16)
 203
 204 #define GPIO_CTRL_A                       0xb8
 205 #define GPIO_CTRL_B                       0xbc
 206 #define GPIO_DATA_BASE                    0xc0
 207
 208 #define DMA_BREG(base, chan)              (base + chan * 0x20)
 209 #define DMA_SREG(base, chan)              (base + chan * 0x10)
 210
 211 #define DMA0_PREV_PCL                     0x100
 212 #define DMA1_PREV_PCL                     0x120
 213 #define DMA2_PREV_PCL                     0x140
 214 #define DMA3_PREV_PCL                     0x160
 215 #define DMA4_PREV_PCL                     0x180
 216 #define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
 217
 218 #define DMA0_CURRENT_PCL                  0x104
 219 #define DMA1_CURRENT_PCL                  0x124
 220 #define DMA2_CURRENT_PCL                  0x144
 221 #define DMA3_CURRENT_PCL                  0x164
 222 #define DMA4_CURRENT_PCL                  0x184
 223 #define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
 224
 225 #define DMA0_CHAN_STAT                    0x10c
 226 #define DMA1_CHAN_STAT                    0x12c
 227 #define DMA2_CHAN_STAT                    0x14c
 228 #define DMA3_CHAN_STAT                    0x16c
 229 #define DMA4_CHAN_STAT                    0x18c
 230 #define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
 231 /* CHAN_STATUS registers share bits */
 232 #define DMA_CHAN_STAT_SELFID              (1<<31)
 233 #define DMA_CHAN_STAT_ISOPKT              (1<<30)
 234 #define DMA_CHAN_STAT_PCIERR              (1<<29)
 235 #define DMA_CHAN_STAT_PKTERR              (1<<28)
 236 #define DMA_CHAN_STAT_PKTCMPL             (1<<27)
 237 #define DMA_CHAN_STAT_SPECIALACK          (1<<14)
 238
 239
 240 #define DMA0_CHAN_CTRL                    0x110
 241 #define DMA1_CHAN_CTRL                    0x130
 242 #define DMA2_CHAN_CTRL                    0x150
 243 #define DMA3_CHAN_CTRL                    0x170
 244 #define DMA4_CHAN_CTRL                    0x190
 245 #define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
 246 /* CHAN_CTRL registers share bits */
 247 #define DMA_CHAN_CTRL_ENABLE              (1<<31)
 248 #define DMA_CHAN_CTRL_BUSY                (1<<30)
 249 #define DMA_CHAN_CTRL_LINK                (1<<29)
 250
 251 #define DMA0_READY                        0x114
 252 #define DMA1_READY                        0x134
 253 #define DMA2_READY                        0x154
 254 #define DMA3_READY                        0x174
 255 #define DMA4_READY                        0x194
 256 #define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
 257
 258 #define DMA_GLOBAL_REGISTER               0x908
 259
 260 #define FIFO_SIZES                        0xa00
 261
 262 #define FIFO_CONTROL                      0xa10
 263 #define FIFO_CONTROL_GRF_FLUSH            (1<<4)
 264 #define FIFO_CONTROL_ITF_FLUSH            (1<<3)
 265 #define FIFO_CONTROL_ATF_FLUSH            (1<<2)
 266
 267 #define FIFO_XMIT_THRESHOLD               0xa14
 268
 269 #define DMA0_WORD0_CMP_VALUE              0xb00
 270 #define DMA1_WORD0_CMP_VALUE              0xb10
 271 #define DMA2_WORD0_CMP_VALUE              0xb20
 272 #define DMA3_WORD0_CMP_VALUE              0xb30
 273 #define DMA4_WORD0_CMP_VALUE              0xb40
 274 #define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
 275
 276 #define DMA0_WORD0_CMP_ENABLE             0xb04
 277 #define DMA1_WORD0_CMP_ENABLE             0xb14
 278 #define DMA2_WORD0_CMP_ENABLE             0xb24
 279 #define DMA3_WORD0_CMP_ENABLE             0xb34
 280 #define DMA4_WORD0_CMP_ENABLE             0xb44
 281 #define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
 282
 283 #define DMA0_WORD1_CMP_VALUE              0xb08
 284 #define DMA1_WORD1_CMP_VALUE              0xb18
 285 #define DMA2_WORD1_CMP_VALUE              0xb28
 286 #define DMA3_WORD1_CMP_VALUE              0xb38
 287 #define DMA4_WORD1_CMP_VALUE              0xb48
 288 #define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
 289
 290 #define DMA0_WORD1_CMP_ENABLE             0xb0c
 291 #define DMA1_WORD1_CMP_ENABLE             0xb1c
 292 #define DMA2_WORD1_CMP_ENABLE             0xb2c
 293 #define DMA3_WORD1_CMP_ENABLE             0xb3c
 294 #define DMA4_WORD1_CMP_ENABLE             0xb4c
 295 #define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
 296 /* word 1 compare enable flags */
 297 #define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
 298 #define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
 299 #define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
 300 #define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
 301 #define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
 302 #define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
 303 #define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
 304
 305 #define LINK_ID                           0xf00
 306 #define LINK_ID_BUS(id)                   (id<<22)
 307 #define LINK_ID_NODE(id)                  (id<<16)
 308
 309 #define LINK_CONTROL                      0xf04
 310 #define LINK_CONTROL_BUSY                 (1<<29)
 311 #define LINK_CONTROL_TX_ISO_EN            (1<<26)
 312 #define LINK_CONTROL_RX_ISO_EN            (1<<25)
 313 #define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
 314 #define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
 315 #define LINK_CONTROL_RESET_TX             (1<<21)
 316 #define LINK_CONTROL_RESET_RX             (1<<20)
 317 #define LINK_CONTROL_CYCMASTER            (1<<11)
 318 #define LINK_CONTROL_CYCSOURCE            (1<<10)
 319 #define LINK_CONTROL_CYCTIMEREN           (1<<9)
 320 #define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
 321 #define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
 322
 323 #define CYCLE_TIMER                       0xf08
 324
 325 #define LINK_PHY                          0xf0c
 326 #define LINK_PHY_READ                     (1<<31)
 327 #define LINK_PHY_WRITE                    (1<<30)
 328 #define LINK_PHY_ADDR(addr)               (addr<<24)
 329 #define LINK_PHY_WDATA(data)              (data<<16)
 330 #define LINK_PHY_RADDR(addr)              (addr<<8)
 331
 332
 333 #define LINK_INT_STATUS                   0xf14
 334 #define LINK_INT_ENABLE                   0xf18
 335 /* status and enable have identical bit numbers */
 336 #define LINK_INT_LINK_INT                 (1<<31)
 337 #define LINK_INT_PHY_TIMEOUT              (1<<30)
 338 #define LINK_INT_PHY_REG_RCVD             (1<<29)
 339 #define LINK_INT_PHY_BUSRESET             (1<<28)
 340 #define LINK_INT_TX_RDY                   (1<<26)
 341 #define LINK_INT_RX_DATA_RDY              (1<<25)
 342 #define LINK_INT_ISO_STUCK                (1<<20)
 343 #define LINK_INT_ASYNC_STUCK              (1<<19)
 344 #define LINK_INT_SENT_REJECT              (1<<17)
 345 #define LINK_INT_HDR_ERR                  (1<<16)
 346 #define LINK_INT_TX_INVALID_TC            (1<<15)
 347 #define LINK_INT_CYC_SECOND               (1<<11)
 348 #define LINK_INT_CYC_START                (1<<10)
 349 #define LINK_INT_CYC_DONE                 (1<<9)
 350 #define LINK_INT_CYC_PENDING              (1<<8)
 351 #define LINK_INT_CYC_LOST                 (1<<7)
 352 #define LINK_INT_CYC_ARB_FAILED           (1<<6)
 353 #define LINK_INT_GRF_OVERFLOW             (1<<5)
 354 #define LINK_INT_ITF_UNDERFLOW            (1<<4)
 355 #define LINK_INT_ATF_UNDERFLOW            (1<<3)
 356 #define LINK_INT_ISOARB_FAILED            (1<<0)
 357
 358 /* PHY specifics */
 359 #define PHY_VENDORID_TI                 0x800028
 360 #define PHY_PRODUCTID_TSB41LV03         0x000000
 361
 362
 363 /* this is the physical layout of a PCL, its size is 128 bytes */
 364 struct ti_pcl {
 365         u32 next;
 366         u32 async_error_next;
 367         u32 user_data;
 368         u32 pcl_status;
 369         u32 remaining_transfer_count;
 370         u32 next_data_buffer;
 371         struct {
 372                 u32 control;
 373                 u32 pointer;
 374         } buffer[13] __attribute__ ((packed));
 375 } __attribute__ ((packed));
 376
 377 #include <linux/stddef.h>
 378 #define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
 379
 380
 381 #ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
 382
 383 static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 384                            const struct ti_pcl *pcl)
 385 {
 386         int i;
 387         u32 *in = (u32 *)pcl;
 388         u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
 389
 390         for (i = 0; i < 32; i++, out++, in++) {
 391                 writel(*in, out);
 392         }
 393 }
 394
 395 static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 396                            struct ti_pcl *pcl)
 397 {
 398         int i;
 399         u32 *out = (u32 *)pcl;
 400         u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
 401
 402         for (i = 0; i < 32; i++, out++, in++) {
 403                 *out = readl(in);
 404         }
 405 }
 406
 407 static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
 408 {
 409         return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
 410 }
 411
 412 #else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
 413
 414 static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 415                            const struct ti_pcl *pcl)
 416 {
 417         memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 418                     (u32 *)pcl, sizeof(struct ti_pcl));
 419 }
 420
 421 static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 422                            struct ti_pcl *pcl)
 423 {
 424         memcpy_le32((u32 *)pcl,
 425                     (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 426                     sizeof(struct ti_pcl));
 427 }
 428
 429 static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
 430 {
 431         return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
 432 }
 433
 434 #endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
 435
 436
 437 #if defined (CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined (__BIG_ENDIAN)
 438 typedef struct ti_pcl pcltmp_t;
 439
 440 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 441                                       pcltmp_t *tmp)
 442 {
 443         get_pcl(lynx, pclid, tmp);
 444         return tmp;
 445 }
 446
 447 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 448                               pcltmp_t *tmp)
 449 {
 450         put_pcl(lynx, pclid, tmp);
 451 }
 452
 453 #else
 454 typedef int pcltmp_t; /* just a dummy */
 455
 456 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 457                                       pcltmp_t *tmp)
 458 {
 459         return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
 460 }
 461
 462 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 463                               pcltmp_t *tmp)
 464 {
 465 }
 466 #endif
 467
 468
 469 static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
 470                                int dmachan)
 471 {
 472         reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
 473                   pcl_bus(lynx, pclid) + idx * 4);
 474         reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
 475                   DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
 476 }
 477
 478 static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
 479 {
 480         run_sub_pcl(lynx, pclid, 0, dmachan);
 481 }
 482
 483 #define PCL_NEXT_INVALID (1<<0)
 484
 485 /* transfer commands */
 486 #define PCL_CMD_RCV            (0x1<<24)
 487 #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
 488 #define PCL_CMD_XMT            (0x2<<24)
 489 #define PCL_CMD_UNFXMT         (0xc<<24)
 490 #define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
 491 #define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
 492
 493 /* aux commands */
 494 #define PCL_CMD_NOP            (0x0<<24)
 495 #define PCL_CMD_LOAD           (0x3<<24)
 496 #define PCL_CMD_STOREQ         (0x4<<24)
 497 #define PCL_CMD_STORED         (0xb<<24)
 498 #define PCL_CMD_STORE0         (0x5<<24)
 499 #define PCL_CMD_STORE1         (0x6<<24)
 500 #define PCL_CMD_COMPARE        (0xe<<24)
 501 #define PCL_CMD_SWAP_COMPARE   (0xf<<24)
 502 #define PCL_CMD_ADD            (0xd<<24)
 503 #define PCL_CMD_BRANCH         (0x7<<24)
 504
 505 /* BRANCH condition codes */
 506 #define PCL_COND_DMARDY_SET    (0x1<<20)
 507 #define PCL_COND_DMARDY_CLEAR  (0x2<<20)
 508
 509 #define PCL_GEN_INTR           (1<<19)
 510 #define PCL_LAST_BUFF          (1<<18)
 511 #define PCL_LAST_CMD           (PCL_LAST_BUFF)
 512 #define PCL_WAITSTAT           (1<<17)
 513 #define PCL_BIGENDIAN          (1<<16)
 514 #define PCL_ISOMODE            (1<<12)
 515
 516 #endif