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[PATCH] ppc32: Fix address checking on lmw/stmw align exception
[linux-2.6/verdex.git] / drivers / scsi / ahci.c
blobda5bd33d982d7e521b6b0603adcb0911395b184d
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Copyright 2004 Red Hat, Inc.
5 *
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
9 * by reference.
10 *
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
21 *
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24 *
25 */
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include "scsi.h"
36 #include <scsi/scsi_host.h>
37 #include <linux/libata.h>
38 #include <asm/io.h>
39
40 #define DRV_NAME "ahci"
41 #define DRV_VERSION "1.00"
42
43
44 enum {
45 AHCI_PCI_BAR = 5,
46 AHCI_MAX_SG = 168, /* hardware max is 64K */
47 AHCI_DMA_BOUNDARY = 0xffffffff,
48 AHCI_USE_CLUSTERING = 0,
49 AHCI_CMD_SLOT_SZ = 32 * 32,
50 AHCI_RX_FIS_SZ = 256,
51 AHCI_CMD_TBL_HDR = 0x80,
52 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
53 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
54 AHCI_RX_FIS_SZ,
55 AHCI_IRQ_ON_SG = (1 << 31),
56 AHCI_CMD_ATAPI = (1 << 5),
57 AHCI_CMD_WRITE = (1 << 6),
58
59 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
60
61 board_ahci = 0,
62
63 /* global controller registers */
64 HOST_CAP = 0x00, /* host capabilities */
65 HOST_CTL = 0x04, /* global host control */
66 HOST_IRQ_STAT = 0x08, /* interrupt status */
67 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
68 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
69
70 /* HOST_CTL bits */
71 HOST_RESET = (1 << 0), /* reset controller; self-clear */
72 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
73 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
74
75 /* HOST_CAP bits */
76 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
77
78 /* registers for each SATA port */
79 PORT_LST_ADDR = 0x00, /* command list DMA addr */
80 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
81 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
82 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
83 PORT_IRQ_STAT = 0x10, /* interrupt status */
84 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
85 PORT_CMD = 0x18, /* port command */
86 PORT_TFDATA = 0x20, /* taskfile data */
87 PORT_SIG = 0x24, /* device TF signature */
88 PORT_CMD_ISSUE = 0x38, /* command issue */
89 PORT_SCR = 0x28, /* SATA phy register block */
90 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
91 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
92 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
93 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
94
95 /* PORT_IRQ_{STAT,MASK} bits */
96 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
97 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
98 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
99 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
100 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
101 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
102 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
103 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
104
105 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
106 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
107 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
108 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
109 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
110 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
111 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
112 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
113 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
114
115 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
116 PORT_IRQ_HBUS_ERR |
117 PORT_IRQ_HBUS_DATA_ERR |
118 PORT_IRQ_IF_ERR,
119 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
120 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
121 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
122 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
123 PORT_IRQ_D2H_REG_FIS,
124
125 /* PORT_CMD bits */
126 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
127 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
128 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
129 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
130 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
131 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
132
133 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
134 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
135 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
136 };
137
138 struct ahci_cmd_hdr {
139 u32 opts;
140 u32 status;
141 u32 tbl_addr;
142 u32 tbl_addr_hi;
143 u32 reserved[4];
144 };
145
146 struct ahci_sg {
147 u32 addr;
148 u32 addr_hi;
149 u32 reserved;
150 u32 flags_size;
151 };
152
153 struct ahci_host_priv {
154 unsigned long flags;
155 u32 cap; /* cache of HOST_CAP register */
156 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
157 };
158
159 struct ahci_port_priv {
160 struct ahci_cmd_hdr *cmd_slot;
161 dma_addr_t cmd_slot_dma;
162 void *cmd_tbl;
163 dma_addr_t cmd_tbl_dma;
164 struct ahci_sg *cmd_tbl_sg;
165 void *rx_fis;
166 dma_addr_t rx_fis_dma;
167 };
168
169 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
170 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
171 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
172 static int ahci_qc_issue(struct ata_queued_cmd *qc);
173 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
174 static void ahci_phy_reset(struct ata_port *ap);
175 static void ahci_irq_clear(struct ata_port *ap);
176 static void ahci_eng_timeout(struct ata_port *ap);
177 static int ahci_port_start(struct ata_port *ap);
178 static void ahci_port_stop(struct ata_port *ap);
179 static void ahci_host_stop(struct ata_host_set *host_set);
180 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
181 static void ahci_qc_prep(struct ata_queued_cmd *qc);
182 static u8 ahci_check_status(struct ata_port *ap);
183 static u8 ahci_check_err(struct ata_port *ap);
184 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
185
186 static Scsi_Host_Template ahci_sht = {
187 .module = THIS_MODULE,
188 .name = DRV_NAME,
189 .ioctl = ata_scsi_ioctl,
190 .queuecommand = ata_scsi_queuecmd,
191 .eh_strategy_handler = ata_scsi_error,
192 .can_queue = ATA_DEF_QUEUE,
193 .this_id = ATA_SHT_THIS_ID,
194 .sg_tablesize = AHCI_MAX_SG,
195 .max_sectors = ATA_MAX_SECTORS,
196 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
197 .emulated = ATA_SHT_EMULATED,
198 .use_clustering = AHCI_USE_CLUSTERING,
199 .proc_name = DRV_NAME,
200 .dma_boundary = AHCI_DMA_BOUNDARY,
201 .slave_configure = ata_scsi_slave_config,
202 .bios_param = ata_std_bios_param,
203 .ordered_flush = 1,
204 };
205
206 static struct ata_port_operations ahci_ops = {
207 .port_disable = ata_port_disable,
208
209 .check_status = ahci_check_status,
210 .check_altstatus = ahci_check_status,
211 .check_err = ahci_check_err,
212 .dev_select = ata_noop_dev_select,
213
214 .tf_read = ahci_tf_read,
215
216 .phy_reset = ahci_phy_reset,
217
218 .qc_prep = ahci_qc_prep,
219 .qc_issue = ahci_qc_issue,
220
221 .eng_timeout = ahci_eng_timeout,
222
223 .irq_handler = ahci_interrupt,
224 .irq_clear = ahci_irq_clear,
225
226 .scr_read = ahci_scr_read,
227 .scr_write = ahci_scr_write,
228
229 .port_start = ahci_port_start,
230 .port_stop = ahci_port_stop,
231 .host_stop = ahci_host_stop,
232 };
233
234 static struct ata_port_info ahci_port_info[] = {
235 /* board_ahci */
236 {
237 .sht = &ahci_sht,
238 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
240 ATA_FLAG_PIO_DMA,
241 .pio_mask = 0x03, /* pio3-4 */
242 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
243 .port_ops = &ahci_ops,
244 },
245 };
246
247 static struct pci_device_id ahci_pci_tbl[] = {
248 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
249 board_ahci }, /* ICH6 */
250 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
251 board_ahci }, /* ICH6M */
252 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
253 board_ahci }, /* ICH7 */
254 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 board_ahci }, /* ICH7M */
256 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_ahci }, /* ICH7R */
258 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_ahci }, /* ULi M5288 */
260 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ESB2 */
262 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ESB2 */
264 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ESB2 */
266 { } /* terminate list */
267 };
268
269
270 static struct pci_driver ahci_pci_driver = {
271 .name = DRV_NAME,
272 .id_table = ahci_pci_tbl,
273 .probe = ahci_init_one,
274 .remove = ata_pci_remove_one,
275 };
276
277
278 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
279 {
280 return base + 0x100 + (port * 0x80);
281 }
282
283 static inline void *ahci_port_base (void *base, unsigned int port)
284 {
285 return (void *) ahci_port_base_ul((unsigned long)base, port);
286 }
287
288 static void ahci_host_stop(struct ata_host_set *host_set)
289 {
290 struct ahci_host_priv *hpriv = host_set->private_data;
291 kfree(hpriv);
292 }
293
294 static int ahci_port_start(struct ata_port *ap)
295 {
296 struct device *dev = ap->host_set->dev;
297 struct ahci_host_priv *hpriv = ap->host_set->private_data;
298 struct ahci_port_priv *pp;
299 int rc;
300 void *mem, *mmio = ap->host_set->mmio_base;
301 void *port_mmio = ahci_port_base(mmio, ap->port_no);
302 dma_addr_t mem_dma;
303
304 rc = ata_port_start(ap);
305 if (rc)
306 return rc;
307
308 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
309 if (!pp) {
310 rc = -ENOMEM;
311 goto err_out;
312 }
313 memset(pp, 0, sizeof(*pp));
314
315 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
316 if (!mem) {
317 rc = -ENOMEM;
318 goto err_out_kfree;
319 }
320 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
321
322 /*
323 * First item in chunk of DMA memory: 32-slot command table,
324 * 32 bytes each in size
325 */
326 pp->cmd_slot = mem;
327 pp->cmd_slot_dma = mem_dma;
328
329 mem += AHCI_CMD_SLOT_SZ;
330 mem_dma += AHCI_CMD_SLOT_SZ;
331
332 /*
333 * Second item: Received-FIS area
334 */
335 pp->rx_fis = mem;
336 pp->rx_fis_dma = mem_dma;
337
338 mem += AHCI_RX_FIS_SZ;
339 mem_dma += AHCI_RX_FIS_SZ;
340
341 /*
342 * Third item: data area for storing a single command
343 * and its scatter-gather table
344 */
345 pp->cmd_tbl = mem;
346 pp->cmd_tbl_dma = mem_dma;
347
348 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
349
350 ap->private_data = pp;
351
352 if (hpriv->cap & HOST_CAP_64)
353 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
354 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
355 readl(port_mmio + PORT_LST_ADDR); /* flush */
356
357 if (hpriv->cap & HOST_CAP_64)
358 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
359 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
360 readl(port_mmio + PORT_FIS_ADDR); /* flush */
361
362 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
363 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
364 PORT_CMD_START, port_mmio + PORT_CMD);
365 readl(port_mmio + PORT_CMD); /* flush */
366
367 return 0;
368
369 err_out_kfree:
370 kfree(pp);
371 err_out:
372 ata_port_stop(ap);
373 return rc;
374 }
375
376
377 static void ahci_port_stop(struct ata_port *ap)
378 {
379 struct device *dev = ap->host_set->dev;
380 struct ahci_port_priv *pp = ap->private_data;
381 void *mmio = ap->host_set->mmio_base;
382 void *port_mmio = ahci_port_base(mmio, ap->port_no);
383 u32 tmp;
384
385 tmp = readl(port_mmio + PORT_CMD);
386 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
387 writel(tmp, port_mmio + PORT_CMD);
388 readl(port_mmio + PORT_CMD); /* flush */
389
390 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
391 * this is slightly incorrect.
392 */
393 msleep(500);
394
395 ap->private_data = NULL;
396 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
397 pp->cmd_slot, pp->cmd_slot_dma);
398 kfree(pp);
399 ata_port_stop(ap);
400 }
401
402 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
403 {
404 unsigned int sc_reg;
405
406 switch (sc_reg_in) {
407 case SCR_STATUS: sc_reg = 0; break;
408 case SCR_CONTROL: sc_reg = 1; break;
409 case SCR_ERROR: sc_reg = 2; break;
410 case SCR_ACTIVE: sc_reg = 3; break;
411 default:
412 return 0xffffffffU;
413 }
414
415 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
416 }
417
418
419 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
420 u32 val)
421 {
422 unsigned int sc_reg;
423
424 switch (sc_reg_in) {
425 case SCR_STATUS: sc_reg = 0; break;
426 case SCR_CONTROL: sc_reg = 1; break;
427 case SCR_ERROR: sc_reg = 2; break;
428 case SCR_ACTIVE: sc_reg = 3; break;
429 default:
430 return;
431 }
432
433 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
434 }
435
436 static void ahci_phy_reset(struct ata_port *ap)
437 {
438 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
439 struct ata_taskfile tf;
440 struct ata_device *dev = &ap->device[0];
441 u32 tmp;
442
443 __sata_phy_reset(ap);
444
445 if (ap->flags & ATA_FLAG_PORT_DISABLED)
446 return;
447
448 tmp = readl(port_mmio + PORT_SIG);
449 tf.lbah = (tmp >> 24) & 0xff;
450 tf.lbam = (tmp >> 16) & 0xff;
451 tf.lbal = (tmp >> 8) & 0xff;
452 tf.nsect = (tmp) & 0xff;
453
454 dev->class = ata_dev_classify(&tf);
455 if (!ata_dev_present(dev))
456 ata_port_disable(ap);
457 }
458
459 static u8 ahci_check_status(struct ata_port *ap)
460 {
461 void *mmio = (void *) ap->ioaddr.cmd_addr;
462
463 return readl(mmio + PORT_TFDATA) & 0xFF;
464 }
465
466 static u8 ahci_check_err(struct ata_port *ap)
467 {
468 void *mmio = (void *) ap->ioaddr.cmd_addr;
469
470 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
471 }
472
473 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
474 {
475 struct ahci_port_priv *pp = ap->private_data;
476 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
477
478 ata_tf_from_fis(d2h_fis, tf);
479 }
480
481 static void ahci_fill_sg(struct ata_queued_cmd *qc)
482 {
483 struct ahci_port_priv *pp = qc->ap->private_data;
484 unsigned int i;
485
486 VPRINTK("ENTER\n");
487
488 /*
489 * Next, the S/G list.
490 */
491 for (i = 0; i < qc->n_elem; i++) {
492 u32 sg_len;
493 dma_addr_t addr;
494
495 addr = sg_dma_address(&qc->sg[i]);
496 sg_len = sg_dma_len(&qc->sg[i]);
497
498 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
499 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
500 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
501 }
502 }
503
504 static void ahci_qc_prep(struct ata_queued_cmd *qc)
505 {
506 struct ahci_port_priv *pp = qc->ap->private_data;
507 u32 opts;
508 const u32 cmd_fis_len = 5; /* five dwords */
509
510 /*
511 * Fill in command slot information (currently only one slot,
512 * slot 0, is currently since we don't do queueing)
513 */
514
515 opts = (qc->n_elem << 16) | cmd_fis_len;
516 if (qc->tf.flags & ATA_TFLAG_WRITE)
517 opts |= AHCI_CMD_WRITE;
518
519 switch (qc->tf.protocol) {
520 case ATA_PROT_ATAPI:
521 case ATA_PROT_ATAPI_NODATA:
522 case ATA_PROT_ATAPI_DMA:
523 opts |= AHCI_CMD_ATAPI;
524 break;
525
526 default:
527 /* do nothing */
528 break;
529 }
530
531 pp->cmd_slot[0].opts = cpu_to_le32(opts);
532 pp->cmd_slot[0].status = 0;
533 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
534 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
535
536 /*
537 * Fill in command table information. First, the header,
538 * a SATA Register - Host to Device command FIS.
539 */
540 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
541
542 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
543 return;
544
545 ahci_fill_sg(qc);
546 }
547
548 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
549 {
550 void *mmio = ap->host_set->mmio_base;
551 void *port_mmio = ahci_port_base(mmio, ap->port_no);
552 u32 tmp;
553 int work;
554
555 /* stop DMA */
556 tmp = readl(port_mmio + PORT_CMD);
557 tmp &= ~PORT_CMD_START;
558 writel(tmp, port_mmio + PORT_CMD);
559
560 /* wait for engine to stop. TODO: this could be
561 * as long as 500 msec
562 */
563 work = 1000;
564 while (work-- > 0) {
565 tmp = readl(port_mmio + PORT_CMD);
566 if ((tmp & PORT_CMD_LIST_ON) == 0)
567 break;
568 udelay(10);
569 }
570
571 /* clear SATA phy error, if any */
572 tmp = readl(port_mmio + PORT_SCR_ERR);
573 writel(tmp, port_mmio + PORT_SCR_ERR);
574
575 /* if DRQ/BSY is set, device needs to be reset.
576 * if so, issue COMRESET
577 */
578 tmp = readl(port_mmio + PORT_TFDATA);
579 if (tmp & (ATA_BUSY | ATA_DRQ)) {
580 writel(0x301, port_mmio + PORT_SCR_CTL);
581 readl(port_mmio + PORT_SCR_CTL); /* flush */
582 udelay(10);
583 writel(0x300, port_mmio + PORT_SCR_CTL);
584 readl(port_mmio + PORT_SCR_CTL); /* flush */
585 }
586
587 /* re-start DMA */
588 tmp = readl(port_mmio + PORT_CMD);
589 tmp |= PORT_CMD_START;
590 writel(tmp, port_mmio + PORT_CMD);
591 readl(port_mmio + PORT_CMD); /* flush */
592
593 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
594 }
595
596 static void ahci_eng_timeout(struct ata_port *ap)
597 {
598 void *mmio = ap->host_set->mmio_base;
599 void *port_mmio = ahci_port_base(mmio, ap->port_no);
600 struct ata_queued_cmd *qc;
601
602 DPRINTK("ENTER\n");
603
604 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
605
606 qc = ata_qc_from_tag(ap, ap->active_tag);
607 if (!qc) {
608 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
609 ap->id);
610 } else {
611 /* hack alert! We cannot use the supplied completion
612 * function from inside the ->eh_strategy_handler() thread.
613 * libata is the only user of ->eh_strategy_handler() in
614 * any kernel, so the default scsi_done() assumes it is
615 * not being called from the SCSI EH.
616 */
617 qc->scsidone = scsi_finish_command;
618 ata_qc_complete(qc, ATA_ERR);
619 }
620
621 }
622
623 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
624 {
625 void *mmio = ap->host_set->mmio_base;
626 void *port_mmio = ahci_port_base(mmio, ap->port_no);
627 u32 status, serr, ci;
628
629 serr = readl(port_mmio + PORT_SCR_ERR);
630 writel(serr, port_mmio + PORT_SCR_ERR);
631
632 status = readl(port_mmio + PORT_IRQ_STAT);
633 writel(status, port_mmio + PORT_IRQ_STAT);
634
635 ci = readl(port_mmio + PORT_CMD_ISSUE);
636 if (likely((ci & 0x1) == 0)) {
637 if (qc) {
638 ata_qc_complete(qc, 0);
639 qc = NULL;
640 }
641 }
642
643 if (status & PORT_IRQ_FATAL) {
644 ahci_intr_error(ap, status);
645 if (qc)
646 ata_qc_complete(qc, ATA_ERR);
647 }
648
649 return 1;
650 }
651
652 static void ahci_irq_clear(struct ata_port *ap)
653 {
654 /* TODO */
655 }
656
657 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
658 {
659 struct ata_host_set *host_set = dev_instance;
660 struct ahci_host_priv *hpriv;
661 unsigned int i, handled = 0;
662 void *mmio;
663 u32 irq_stat, irq_ack = 0;
664
665 VPRINTK("ENTER\n");
666
667 hpriv = host_set->private_data;
668 mmio = host_set->mmio_base;
669
670 /* sigh. 0xffffffff is a valid return from h/w */
671 irq_stat = readl(mmio + HOST_IRQ_STAT);
672 irq_stat &= hpriv->port_map;
673 if (!irq_stat)
674 return IRQ_NONE;
675
676 spin_lock(&host_set->lock);
677
678 for (i = 0; i < host_set->n_ports; i++) {
679 struct ata_port *ap;
680 u32 tmp;
681
682 VPRINTK("port %u\n", i);
683 ap = host_set->ports[i];
684 tmp = irq_stat & (1 << i);
685 if (tmp && ap) {
686 struct ata_queued_cmd *qc;
687 qc = ata_qc_from_tag(ap, ap->active_tag);
688 if (ahci_host_intr(ap, qc))
689 irq_ack |= (1 << i);
690 }
691 }
692
693 if (irq_ack) {
694 writel(irq_ack, mmio + HOST_IRQ_STAT);
695 handled = 1;
696 }
697
698 spin_unlock(&host_set->lock);
699
700 VPRINTK("EXIT\n");
701
702 return IRQ_RETVAL(handled);
703 }
704
705 static int ahci_qc_issue(struct ata_queued_cmd *qc)
706 {
707 struct ata_port *ap = qc->ap;
708 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
709
710 writel(1, port_mmio + PORT_SCR_ACT);
711 readl(port_mmio + PORT_SCR_ACT); /* flush */
712
713 writel(1, port_mmio + PORT_CMD_ISSUE);
714 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
715
716 return 0;
717 }
718
719 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
720 unsigned int port_idx)
721 {
722 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
723 base = ahci_port_base_ul(base, port_idx);
724 VPRINTK("base now==0x%lx\n", base);
725
726 port->cmd_addr = base;
727 port->scr_addr = base + PORT_SCR;
728
729 VPRINTK("EXIT\n");
730 }
731
732 static int ahci_host_init(struct ata_probe_ent *probe_ent)
733 {
734 struct ahci_host_priv *hpriv = probe_ent->private_data;
735 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
736 void __iomem *mmio = probe_ent->mmio_base;
737 u32 tmp, cap_save;
738 u16 tmp16;
739 unsigned int i, j, using_dac;
740 int rc;
741 void __iomem *port_mmio;
742
743 cap_save = readl(mmio + HOST_CAP);
744 cap_save &= ( (1<<28) | (1<<17) );
745 cap_save |= (1 << 27);
746
747 /* global controller reset */
748 tmp = readl(mmio + HOST_CTL);
749 if ((tmp & HOST_RESET) == 0) {
750 writel(tmp | HOST_RESET, mmio + HOST_CTL);
751 readl(mmio + HOST_CTL); /* flush */
752 }
753
754 /* reset must complete within 1 second, or
755 * the hardware should be considered fried.
756 */
757 ssleep(1);
758
759 tmp = readl(mmio + HOST_CTL);
760 if (tmp & HOST_RESET) {
761 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
762 pci_name(pdev), tmp);
763 return -EIO;
764 }
765
766 writel(HOST_AHCI_EN, mmio + HOST_CTL);
767 (void) readl(mmio + HOST_CTL); /* flush */
768 writel(cap_save, mmio + HOST_CAP);
769 writel(0xf, mmio + HOST_PORTS_IMPL);
770 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
771
772 pci_read_config_word(pdev, 0x92, &tmp16);
773 tmp16 |= 0xf;
774 pci_write_config_word(pdev, 0x92, tmp16);
775
776 hpriv->cap = readl(mmio + HOST_CAP);
777 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
778 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
779
780 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
781 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
782
783 using_dac = hpriv->cap & HOST_CAP_64;
784 if (using_dac &&
785 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
786 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
787 if (rc) {
788 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
789 if (rc) {
790 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
791 pci_name(pdev));
792 return rc;
793 }
794 }
795
796 hpriv->flags |= HOST_CAP_64;
797 } else {
798 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
799 if (rc) {
800 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
801 pci_name(pdev));
802 return rc;
803 }
804 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
805 if (rc) {
806 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
807 pci_name(pdev));
808 return rc;
809 }
810 }
811
812 for (i = 0; i < probe_ent->n_ports; i++) {
813 #if 0 /* BIOSen initialize this incorrectly */
814 if (!(hpriv->port_map & (1 << i)))
815 continue;
816 #endif
817
818 port_mmio = ahci_port_base(mmio, i);
819 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
820
821 ahci_setup_port(&probe_ent->port[i],
822 (unsigned long) mmio, i);
823
824 /* make sure port is not active */
825 tmp = readl(port_mmio + PORT_CMD);
826 VPRINTK("PORT_CMD 0x%x\n", tmp);
827 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
828 PORT_CMD_FIS_RX | PORT_CMD_START)) {
829 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
830 PORT_CMD_FIS_RX | PORT_CMD_START);
831 writel(tmp, port_mmio + PORT_CMD);
832 readl(port_mmio + PORT_CMD); /* flush */
833
834 /* spec says 500 msecs for each bit, so
835 * this is slightly incorrect.
836 */
837 msleep(500);
838 }
839
840 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
841
842 j = 0;
843 while (j < 100) {
844 msleep(10);
845 tmp = readl(port_mmio + PORT_SCR_STAT);
846 if ((tmp & 0xf) == 0x3)
847 break;
848 j++;
849 }
850
851 tmp = readl(port_mmio + PORT_SCR_ERR);
852 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
853 writel(tmp, port_mmio + PORT_SCR_ERR);
854
855 /* ack any pending irq events for this port */
856 tmp = readl(port_mmio + PORT_IRQ_STAT);
857 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
858 if (tmp)
859 writel(tmp, port_mmio + PORT_IRQ_STAT);
860
861 writel(1 << i, mmio + HOST_IRQ_STAT);
862
863 /* set irq mask (enables interrupts) */
864 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
865 }
866
867 tmp = readl(mmio + HOST_CTL);
868 VPRINTK("HOST_CTL 0x%x\n", tmp);
869 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
870 tmp = readl(mmio + HOST_CTL);
871 VPRINTK("HOST_CTL 0x%x\n", tmp);
872
873 pci_set_master(pdev);
874
875 return 0;
876 }
877
878 /* move to PCI layer, integrate w/ MSI stuff */
879 static void pci_enable_intx(struct pci_dev *pdev)
880 {
881 u16 pci_command;
882
883 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
884 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
885 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
886 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
887 }
888 }
889
890 static void ahci_print_info(struct ata_probe_ent *probe_ent)
891 {
892 struct ahci_host_priv *hpriv = probe_ent->private_data;
893 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
894 void *mmio = probe_ent->mmio_base;
895 u32 vers, cap, impl, speed;
896 const char *speed_s;
897 u16 cc;
898 const char *scc_s;
899
900 vers = readl(mmio + HOST_VERSION);
901 cap = hpriv->cap;
902 impl = hpriv->port_map;
903
904 speed = (cap >> 20) & 0xf;
905 if (speed == 1)
906 speed_s = "1.5";
907 else if (speed == 2)
908 speed_s = "3";
909 else
910 speed_s = "?";
911
912 pci_read_config_word(pdev, 0x0a, &cc);
913 if (cc == 0x0101)
914 scc_s = "IDE";
915 else if (cc == 0x0106)
916 scc_s = "SATA";
917 else if (cc == 0x0104)
918 scc_s = "RAID";
919 else
920 scc_s = "unknown";
921
922 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
923 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
924 ,
925 pci_name(pdev),
926
927 (vers >> 24) & 0xff,
928 (vers >> 16) & 0xff,
929 (vers >> 8) & 0xff,
930 vers & 0xff,
931
932 ((cap >> 8) & 0x1f) + 1,
933 (cap & 0x1f) + 1,
934 speed_s,
935 impl,
936 scc_s);
937
938 printk(KERN_INFO DRV_NAME "(%s) flags: "
939 "%s%s%s%s%s%s"
940 "%s%s%s%s%s%s%s\n"
941 ,
942 pci_name(pdev),
943
944 cap & (1 << 31) ? "64bit " : "",
945 cap & (1 << 30) ? "ncq " : "",
946 cap & (1 << 28) ? "ilck " : "",
947 cap & (1 << 27) ? "stag " : "",
948 cap & (1 << 26) ? "pm " : "",
949 cap & (1 << 25) ? "led " : "",
950
951 cap & (1 << 24) ? "clo " : "",
952 cap & (1 << 19) ? "nz " : "",
953 cap & (1 << 18) ? "only " : "",
954 cap & (1 << 17) ? "pmp " : "",
955 cap & (1 << 15) ? "pio " : "",
956 cap & (1 << 14) ? "slum " : "",
957 cap & (1 << 13) ? "part " : ""
958 );
959 }
960
961 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
962 {
963 static int printed_version;
964 struct ata_probe_ent *probe_ent = NULL;
965 struct ahci_host_priv *hpriv;
966 unsigned long base;
967 void *mmio_base;
968 unsigned int board_idx = (unsigned int) ent->driver_data;
969 int pci_dev_busy = 0;
970 int rc;
971
972 VPRINTK("ENTER\n");
973
974 if (!printed_version++)
975 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
976
977 rc = pci_enable_device(pdev);
978 if (rc)
979 return rc;
980
981 rc = pci_request_regions(pdev, DRV_NAME);
982 if (rc) {
983 pci_dev_busy = 1;
984 goto err_out;
985 }
986
987 pci_enable_intx(pdev);
988
989 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
990 if (probe_ent == NULL) {
991 rc = -ENOMEM;
992 goto err_out_regions;
993 }
994
995 memset(probe_ent, 0, sizeof(*probe_ent));
996 probe_ent->dev = pci_dev_to_dev(pdev);
997 INIT_LIST_HEAD(&probe_ent->node);
998
999 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1000 pci_resource_len(pdev, AHCI_PCI_BAR));
1001 if (mmio_base == NULL) {
1002 rc = -ENOMEM;
1003 goto err_out_free_ent;
1004 }
1005 base = (unsigned long) mmio_base;
1006
1007 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1008 if (!hpriv) {
1009 rc = -ENOMEM;
1010 goto err_out_iounmap;
1011 }
1012 memset(hpriv, 0, sizeof(*hpriv));
1013
1014 probe_ent->sht = ahci_port_info[board_idx].sht;
1015 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1016 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1017 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1018 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1019
1020 probe_ent->irq = pdev->irq;
1021 probe_ent->irq_flags = SA_SHIRQ;
1022 probe_ent->mmio_base = mmio_base;
1023 probe_ent->private_data = hpriv;
1024
1025 /* initialize adapter */
1026 rc = ahci_host_init(probe_ent);
1027 if (rc)
1028 goto err_out_hpriv;
1029
1030 ahci_print_info(probe_ent);
1031
1032 /* FIXME: check ata_device_add return value */
1033 ata_device_add(probe_ent);
1034 kfree(probe_ent);
1035
1036 return 0;
1037
1038 err_out_hpriv:
1039 kfree(hpriv);
1040 err_out_iounmap:
1041 iounmap(mmio_base);
1042 err_out_free_ent:
1043 kfree(probe_ent);
1044 err_out_regions:
1045 pci_release_regions(pdev);
1046 err_out:
1047 if (!pci_dev_busy)
1048 pci_disable_device(pdev);
1049 return rc;
1050 }
1051
1052
1053 static int __init ahci_init(void)
1054 {
1055 return pci_module_init(&ahci_pci_driver);
1056 }
1057
1058
1059 static void __exit ahci_exit(void)
1060 {
1061 pci_unregister_driver(&ahci_pci_driver);
1062 }
1063
1064
1065 MODULE_AUTHOR("Jeff Garzik");
1066 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1067 MODULE_LICENSE("GPL");
1068 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1069
1070 module_init(ahci_init);
1071 module_exit(ahci_exit);
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