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[PATCH] ppc32: Fix address checking on lmw/stmw align exception
[linux-2.6/verdex.git] / drivers / scsi / lpfc / lpfc_hw.h
blobfc958a99dadb38dafb61c450d933e197da06311e
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Enterprise Fibre Channel Host Bus Adapters. *
4 * Refer to the README file included with this package for *
5 * driver version and adapter support. *
6 * Copyright (C) 2004 Emulex Corporation. *
7 * www.emulex.com *
8 * *
9 * This program is free software; you can redistribute it and/or *
10 * modify it under the terms of the GNU General Public License *
11 * as published by the Free Software Foundation; either version 2 *
12 * of the License, or (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details, a copy of which *
18 * can be found in the file COPYING included with this package. *
19 *******************************************************************/
20
21 /*
22 * $Id: lpfc_hw.h 1.37 2005/03/29 19:51:45EST sf_support Exp $
23 */
24
25 #define FDMI_DID 0xfffffaU
26 #define NameServer_DID 0xfffffcU
27 #define SCR_DID 0xfffffdU
28 #define Fabric_DID 0xfffffeU
29 #define Bcast_DID 0xffffffU
30 #define Mask_DID 0xffffffU
31 #define CT_DID_MASK 0xffff00U
32 #define Fabric_DID_MASK 0xfff000U
33 #define WELL_KNOWN_DID_MASK 0xfffff0U
34
35 #define PT2PT_LocalID 1
36 #define PT2PT_RemoteID 2
37
38 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
39 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
40 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
41 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
42
43 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
44 0 */
45
46 #define FCELSSIZE 1024 /* maximum ELS transfer size */
47
48 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
49 #define LPFC_IP_RING 1 /* ring 1 for IP commands */
50 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
51 #define LPFC_FCP_NEXT_RING 3
52
53 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
54 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
55 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */
56 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */
57 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
58 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
59 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
60 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
61 #define SLI2_IOCB_CMD_R3_ENTRIES 0
62 #define SLI2_IOCB_RSP_R3_ENTRIES 0
63 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
64 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
65
66 /* Common Transport structures and definitions */
67
68 union CtRevisionId {
69 /* Structure is in Big Endian format */
70 struct {
71 uint32_t Revision:8;
72 uint32_t InId:24;
73 } bits;
74 uint32_t word;
75 };
76
77 union CtCommandResponse {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t CmdRsp:16;
81 uint32_t Size:16;
82 } bits;
83 uint32_t word;
84 };
85
86 struct lpfc_sli_ct_request {
87 /* Structure is in Big Endian format */
88 union CtRevisionId RevisionId;
89 uint8_t FsType;
90 uint8_t FsSubType;
91 uint8_t Options;
92 uint8_t Rsrvd1;
93 union CtCommandResponse CommandResponse;
94 uint8_t Rsrvd2;
95 uint8_t ReasonCode;
96 uint8_t Explanation;
97 uint8_t VendorUnique;
98
99 union {
100 uint32_t PortID;
101 struct gid {
102 uint8_t PortType; /* for GID_PT requests */
103 uint8_t DomainScope;
104 uint8_t AreaScope;
105 uint8_t Fc4Type; /* for GID_FT requests */
106 } gid;
107 struct rft {
108 uint32_t PortId; /* For RFT_ID requests */
109
110 #ifdef __BIG_ENDIAN_BITFIELD
111 uint32_t rsvd0:16;
112 uint32_t rsvd1:7;
113 uint32_t fcpReg:1; /* Type 8 */
114 uint32_t rsvd2:2;
115 uint32_t ipReg:1; /* Type 5 */
116 uint32_t rsvd3:5;
117 #else /* __LITTLE_ENDIAN_BITFIELD */
118 uint32_t rsvd0:16;
119 uint32_t fcpReg:1; /* Type 8 */
120 uint32_t rsvd1:7;
121 uint32_t rsvd3:5;
122 uint32_t ipReg:1; /* Type 5 */
123 uint32_t rsvd2:2;
124 #endif
125
126 uint32_t rsvd[7];
127 } rft;
128 struct rnn {
129 uint32_t PortId; /* For RNN_ID requests */
130 uint8_t wwnn[8];
131 } rnn;
132 struct rsnn { /* For RSNN_ID requests */
133 uint8_t wwnn[8];
134 uint8_t len;
135 uint8_t symbname[255];
136 } rsnn;
137 } un;
138 };
139
140 #define SLI_CT_REVISION 1
141 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260)
142 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228)
143 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252)
144 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request))
145
146 /*
147 * FsType Definitions
148 */
149
150 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
151 #define SLI_CT_TIME_SERVICE 0xFB
152 #define SLI_CT_DIRECTORY_SERVICE 0xFC
153 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
154
155 /*
156 * Directory Service Subtypes
157 */
158
159 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
160
161 /*
162 * Response Codes
163 */
164
165 #define SLI_CT_RESPONSE_FS_RJT 0x8001
166 #define SLI_CT_RESPONSE_FS_ACC 0x8002
167
168 /*
169 * Reason Codes
170 */
171
172 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
173 #define SLI_CT_INVALID_COMMAND 0x01
174 #define SLI_CT_INVALID_VERSION 0x02
175 #define SLI_CT_LOGICAL_ERROR 0x03
176 #define SLI_CT_INVALID_IU_SIZE 0x04
177 #define SLI_CT_LOGICAL_BUSY 0x05
178 #define SLI_CT_PROTOCOL_ERROR 0x07
179 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
180 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
181 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
182 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
183 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
184 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
185 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
186 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
187 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
188 #define SLI_CT_VENDOR_UNIQUE 0xff
189
190 /*
191 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
192 */
193
194 #define SLI_CT_NO_PORT_ID 0x01
195 #define SLI_CT_NO_PORT_NAME 0x02
196 #define SLI_CT_NO_NODE_NAME 0x03
197 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
198 #define SLI_CT_NO_IP_ADDRESS 0x05
199 #define SLI_CT_NO_IPA 0x06
200 #define SLI_CT_NO_FC4_TYPES 0x07
201 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
202 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
203 #define SLI_CT_NO_PORT_TYPE 0x0A
204 #define SLI_CT_ACCESS_DENIED 0x10
205 #define SLI_CT_INVALID_PORT_ID 0x11
206 #define SLI_CT_DATABASE_EMPTY 0x12
207
208 /*
209 * Name Server Command Codes
210 */
211
212 #define SLI_CTNS_GA_NXT 0x0100
213 #define SLI_CTNS_GPN_ID 0x0112
214 #define SLI_CTNS_GNN_ID 0x0113
215 #define SLI_CTNS_GCS_ID 0x0114
216 #define SLI_CTNS_GFT_ID 0x0117
217 #define SLI_CTNS_GSPN_ID 0x0118
218 #define SLI_CTNS_GPT_ID 0x011A
219 #define SLI_CTNS_GID_PN 0x0121
220 #define SLI_CTNS_GID_NN 0x0131
221 #define SLI_CTNS_GIP_NN 0x0135
222 #define SLI_CTNS_GIPA_NN 0x0136
223 #define SLI_CTNS_GSNN_NN 0x0139
224 #define SLI_CTNS_GNN_IP 0x0153
225 #define SLI_CTNS_GIPA_IP 0x0156
226 #define SLI_CTNS_GID_FT 0x0171
227 #define SLI_CTNS_GID_PT 0x01A1
228 #define SLI_CTNS_RPN_ID 0x0212
229 #define SLI_CTNS_RNN_ID 0x0213
230 #define SLI_CTNS_RCS_ID 0x0214
231 #define SLI_CTNS_RFT_ID 0x0217
232 #define SLI_CTNS_RSPN_ID 0x0218
233 #define SLI_CTNS_RPT_ID 0x021A
234 #define SLI_CTNS_RIP_NN 0x0235
235 #define SLI_CTNS_RIPA_NN 0x0236
236 #define SLI_CTNS_RSNN_NN 0x0239
237 #define SLI_CTNS_DA_ID 0x0300
238
239 /*
240 * Port Types
241 */
242
243 #define SLI_CTPT_N_PORT 0x01
244 #define SLI_CTPT_NL_PORT 0x02
245 #define SLI_CTPT_FNL_PORT 0x03
246 #define SLI_CTPT_IP 0x04
247 #define SLI_CTPT_FCP 0x08
248 #define SLI_CTPT_NX_PORT 0x7F
249 #define SLI_CTPT_F_PORT 0x81
250 #define SLI_CTPT_FL_PORT 0x82
251 #define SLI_CTPT_E_PORT 0x84
252
253 #define SLI_CT_LAST_ENTRY 0x80000000
254
255 /* Fibre Channel Service Parameter definitions */
256
257 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
258 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
259 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
260 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
261
262 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
263 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
264 #define FC_PH3 0x20 /* FC-PH-3 version */
265
266 #define FF_FRAME_SIZE 2048
267
268 struct lpfc_name {
269 #ifdef __BIG_ENDIAN_BITFIELD
270 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
271 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */
272 #else /* __LITTLE_ENDIAN_BITFIELD */
273 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */
274 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
275 #endif
276
277 #define NAME_IEEE 0x1 /* IEEE name - nameType */
278 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
279 #define NAME_FC_TYPE 0x3 /* FC native name type */
280 #define NAME_IP_TYPE 0x4 /* IP address */
281 #define NAME_CCITT_TYPE 0xC
282 #define NAME_CCITT_GR_TYPE 0xE
283 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE extended Lsb */
284 uint8_t IEEE[6]; /* FC IEEE address */
285 };
286
287 struct csp {
288 uint8_t fcphHigh; /* FC Word 0, byte 0 */
289 uint8_t fcphLow;
290 uint8_t bbCreditMsb;
291 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
292
293 #ifdef __BIG_ENDIAN_BITFIELD
294 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
295 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
296 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
297 uint16_t fPort:1; /* FC Word 1, bit 28 */
298 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
299 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
300 uint16_t multicast:1; /* FC Word 1, bit 25 */
301 uint16_t broadcast:1; /* FC Word 1, bit 24 */
302
303 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
304 uint16_t simplex:1; /* FC Word 1, bit 22 */
305 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
306 uint16_t dhd:1; /* FC Word 1, bit 18 */
307 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
308 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
309 #else /* __LITTLE_ENDIAN_BITFIELD */
310 uint16_t broadcast:1; /* FC Word 1, bit 24 */
311 uint16_t multicast:1; /* FC Word 1, bit 25 */
312 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
313 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
314 uint16_t fPort:1; /* FC Word 1, bit 28 */
315 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
316 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
317 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
318
319 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
320 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
321 uint16_t dhd:1; /* FC Word 1, bit 18 */
322 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
323 uint16_t simplex:1; /* FC Word 1, bit 22 */
324 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
325 #endif
326
327 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
328 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
329 union {
330 struct {
331 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
332
333 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
334 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
335
336 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
337 } nPort;
338 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
339 } w2;
340
341 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
342 };
343
344 struct class_parms {
345 #ifdef __BIG_ENDIAN_BITFIELD
346 uint8_t classValid:1; /* FC Word 0, bit 31 */
347 uint8_t intermix:1; /* FC Word 0, bit 30 */
348 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
349 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
350 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
351 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
352 #else /* __LITTLE_ENDIAN_BITFIELD */
353 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
354 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
355 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
356 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
357 uint8_t intermix:1; /* FC Word 0, bit 30 */
358 uint8_t classValid:1; /* FC Word 0, bit 31 */
359
360 #endif
361
362 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
363
364 #ifdef __BIG_ENDIAN_BITFIELD
365 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
366 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
367 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
368 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
369 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
370 #else /* __LITTLE_ENDIAN_BITFIELD */
371 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
372 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
373 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
374 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
375 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
376 #endif
377
378 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
379
380 #ifdef __BIG_ENDIAN_BITFIELD
381 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
382 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
383 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
384 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
385 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
386 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
387 #else /* __LITTLE_ENDIAN_BITFIELD */
388 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
389 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
390 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
391 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
392 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
393 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
394 #endif
395
396 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
397 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
398 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
399
400 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
401 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
402 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
403 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
404
405 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
406 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
407 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
408 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
409 };
410
411 struct serv_parm { /* Structure is in Big Endian format */
412 struct csp cmn;
413 struct lpfc_name portName;
414 struct lpfc_name nodeName;
415 struct class_parms cls1;
416 struct class_parms cls2;
417 struct class_parms cls3;
418 struct class_parms cls4;
419 uint8_t vendorVersion[16];
420 };
421
422 /*
423 * Extended Link Service LS_COMMAND codes (Payload Word 0)
424 */
425 #ifdef __BIG_ENDIAN_BITFIELD
426 #define ELS_CMD_MASK 0xffff0000
427 #define ELS_RSP_MASK 0xff000000
428 #define ELS_CMD_LS_RJT 0x01000000
429 #define ELS_CMD_ACC 0x02000000
430 #define ELS_CMD_PLOGI 0x03000000
431 #define ELS_CMD_FLOGI 0x04000000
432 #define ELS_CMD_LOGO 0x05000000
433 #define ELS_CMD_ABTX 0x06000000
434 #define ELS_CMD_RCS 0x07000000
435 #define ELS_CMD_RES 0x08000000
436 #define ELS_CMD_RSS 0x09000000
437 #define ELS_CMD_RSI 0x0A000000
438 #define ELS_CMD_ESTS 0x0B000000
439 #define ELS_CMD_ESTC 0x0C000000
440 #define ELS_CMD_ADVC 0x0D000000
441 #define ELS_CMD_RTV 0x0E000000
442 #define ELS_CMD_RLS 0x0F000000
443 #define ELS_CMD_ECHO 0x10000000
444 #define ELS_CMD_TEST 0x11000000
445 #define ELS_CMD_RRQ 0x12000000
446 #define ELS_CMD_PRLI 0x20100014
447 #define ELS_CMD_PRLO 0x21100014
448 #define ELS_CMD_PDISC 0x50000000
449 #define ELS_CMD_FDISC 0x51000000
450 #define ELS_CMD_ADISC 0x52000000
451 #define ELS_CMD_FARP 0x54000000
452 #define ELS_CMD_FARPR 0x55000000
453 #define ELS_CMD_FAN 0x60000000
454 #define ELS_CMD_RSCN 0x61040000
455 #define ELS_CMD_SCR 0x62000000
456 #define ELS_CMD_RNID 0x78000000
457 #else /* __LITTLE_ENDIAN_BITFIELD */
458 #define ELS_CMD_MASK 0xffff
459 #define ELS_RSP_MASK 0xff
460 #define ELS_CMD_LS_RJT 0x01
461 #define ELS_CMD_ACC 0x02
462 #define ELS_CMD_PLOGI 0x03
463 #define ELS_CMD_FLOGI 0x04
464 #define ELS_CMD_LOGO 0x05
465 #define ELS_CMD_ABTX 0x06
466 #define ELS_CMD_RCS 0x07
467 #define ELS_CMD_RES 0x08
468 #define ELS_CMD_RSS 0x09
469 #define ELS_CMD_RSI 0x0A
470 #define ELS_CMD_ESTS 0x0B
471 #define ELS_CMD_ESTC 0x0C
472 #define ELS_CMD_ADVC 0x0D
473 #define ELS_CMD_RTV 0x0E
474 #define ELS_CMD_RLS 0x0F
475 #define ELS_CMD_ECHO 0x10
476 #define ELS_CMD_TEST 0x11
477 #define ELS_CMD_RRQ 0x12
478 #define ELS_CMD_PRLI 0x14001020
479 #define ELS_CMD_PRLO 0x14001021
480 #define ELS_CMD_PDISC 0x50
481 #define ELS_CMD_FDISC 0x51
482 #define ELS_CMD_ADISC 0x52
483 #define ELS_CMD_FARP 0x54
484 #define ELS_CMD_FARPR 0x55
485 #define ELS_CMD_FAN 0x60
486 #define ELS_CMD_RSCN 0x0461
487 #define ELS_CMD_SCR 0x62
488 #define ELS_CMD_RNID 0x78
489 #endif
490
491 /*
492 * LS_RJT Payload Definition
493 */
494
495 struct ls_rjt { /* Structure is in Big Endian format */
496 union {
497 uint32_t lsRjtError;
498 struct {
499 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
500
501 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
502 /* LS_RJT reason codes */
503 #define LSRJT_INVALID_CMD 0x01
504 #define LSRJT_LOGICAL_ERR 0x03
505 #define LSRJT_LOGICAL_BSY 0x05
506 #define LSRJT_PROTOCOL_ERR 0x07
507 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
508 #define LSRJT_CMD_UNSUPPORTED 0x0B
509 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
510
511 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
512 /* LS_RJT reason explanation */
513 #define LSEXP_NOTHING_MORE 0x00
514 #define LSEXP_SPARM_OPTIONS 0x01
515 #define LSEXP_SPARM_ICTL 0x03
516 #define LSEXP_SPARM_RCTL 0x05
517 #define LSEXP_SPARM_RCV_SIZE 0x07
518 #define LSEXP_SPARM_CONCUR_SEQ 0x09
519 #define LSEXP_SPARM_CREDIT 0x0B
520 #define LSEXP_INVALID_PNAME 0x0D
521 #define LSEXP_INVALID_NNAME 0x0E
522 #define LSEXP_INVALID_CSP 0x0F
523 #define LSEXP_INVALID_ASSOC_HDR 0x11
524 #define LSEXP_ASSOC_HDR_REQ 0x13
525 #define LSEXP_INVALID_O_SID 0x15
526 #define LSEXP_INVALID_OX_RX 0x17
527 #define LSEXP_CMD_IN_PROGRESS 0x19
528 #define LSEXP_INVALID_NPORT_ID 0x1F
529 #define LSEXP_INVALID_SEQ_ID 0x21
530 #define LSEXP_INVALID_XCHG 0x23
531 #define LSEXP_INACTIVE_XCHG 0x25
532 #define LSEXP_RQ_REQUIRED 0x27
533 #define LSEXP_OUT_OF_RESOURCE 0x29
534 #define LSEXP_CANT_GIVE_DATA 0x2A
535 #define LSEXP_REQ_UNSUPPORTED 0x2C
536 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
537 } b;
538 } un;
539 };
540
541 /*
542 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
543 */
544
545 typedef struct _LOGO { /* Structure is in Big Endian format */
546 union {
547 uint32_t nPortId32; /* Access nPortId as a word */
548 struct {
549 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
550 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
551 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
552 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
553 } b;
554 } un;
555 struct lpfc_name portName; /* N_port name field */
556 } LOGO;
557
558 /*
559 * FCP Login (PRLI Request / ACC) Payload Definition
560 */
561
562 #define PRLX_PAGE_LEN 0x10
563 #define TPRLO_PAGE_LEN 0x14
564
565 typedef struct _PRLI { /* Structure is in Big Endian format */
566 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
567
568 #define PRLI_FCP_TYPE 0x08
569 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
570
571 #ifdef __BIG_ENDIAN_BITFIELD
572 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
573 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
574 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
575
576 /* ACC = imagePairEstablished */
577 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
578 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
579 #else /* __LITTLE_ENDIAN_BITFIELD */
580 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
581 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
582 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
583 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
584 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
585 /* ACC = imagePairEstablished */
586 #endif
587
588 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
589 #define PRLI_NO_RESOURCES 0x2
590 #define PRLI_INIT_INCOMPLETE 0x3
591 #define PRLI_NO_SUCH_PA 0x4
592 #define PRLI_PREDEF_CONFIG 0x5
593 #define PRLI_PARTIAL_SUCCESS 0x6
594 #define PRLI_INVALID_PAGE_CNT 0x7
595 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
596
597 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
598
599 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
600
601 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
602 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
603
604 #ifdef __BIG_ENDIAN_BITFIELD
605 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
606 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
607 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
608 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
609 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
610 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
611 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
612 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
613 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
614 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
615 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
616 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
617 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
618 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
619 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
620 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
621 #else /* __LITTLE_ENDIAN_BITFIELD */
622 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
623 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
624 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
625 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
626 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
627 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
628 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
629 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
630 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
631 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
632 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
633 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
634 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
635 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
636 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
637 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
638 #endif
639 } PRLI;
640
641 /*
642 * FCP Logout (PRLO Request / ACC) Payload Definition
643 */
644
645 typedef struct _PRLO { /* Structure is in Big Endian format */
646 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
647
648 #define PRLO_FCP_TYPE 0x08
649 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
650
651 #ifdef __BIG_ENDIAN_BITFIELD
652 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
653 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
654 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
655 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
656 #else /* __LITTLE_ENDIAN_BITFIELD */
657 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
658 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
659 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
660 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
661 #endif
662
663 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
664 #define PRLO_NO_SUCH_IMAGE 0x4
665 #define PRLO_INVALID_PAGE_CNT 0x7
666
667 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
668
669 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
670
671 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
672
673 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
674 } PRLO;
675
676 typedef struct _ADISC { /* Structure is in Big Endian format */
677 uint32_t hardAL_PA;
678 struct lpfc_name portName;
679 struct lpfc_name nodeName;
680 uint32_t DID;
681 } ADISC;
682
683 typedef struct _FARP { /* Structure is in Big Endian format */
684 uint32_t Mflags:8;
685 uint32_t Odid:24;
686 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
687 action */
688 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
689 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
690 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
691 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
692 supported */
693 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
694 supported */
695 uint32_t Rflags:8;
696 uint32_t Rdid:24;
697 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
698 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
699 struct lpfc_name OportName;
700 struct lpfc_name OnodeName;
701 struct lpfc_name RportName;
702 struct lpfc_name RnodeName;
703 uint8_t Oipaddr[16];
704 uint8_t Ripaddr[16];
705 } FARP;
706
707 typedef struct _FAN { /* Structure is in Big Endian format */
708 uint32_t Fdid;
709 struct lpfc_name FportName;
710 struct lpfc_name FnodeName;
711 } FAN;
712
713 typedef struct _SCR { /* Structure is in Big Endian format */
714 uint8_t resvd1;
715 uint8_t resvd2;
716 uint8_t resvd3;
717 uint8_t Function;
718 #define SCR_FUNC_FABRIC 0x01
719 #define SCR_FUNC_NPORT 0x02
720 #define SCR_FUNC_FULL 0x03
721 #define SCR_CLEAR 0xff
722 } SCR;
723
724 typedef struct _RNID_TOP_DISC {
725 struct lpfc_name portName;
726 uint8_t resvd[8];
727 uint32_t unitType;
728 #define RNID_HBA 0x7
729 #define RNID_HOST 0xa
730 #define RNID_DRIVER 0xd
731 uint32_t physPort;
732 uint32_t attachedNodes;
733 uint16_t ipVersion;
734 #define RNID_IPV4 0x1
735 #define RNID_IPV6 0x2
736 uint16_t UDPport;
737 uint8_t ipAddr[16];
738 uint16_t resvd1;
739 uint16_t flags;
740 #define RNID_TD_SUPPORT 0x1
741 #define RNID_LP_VALID 0x2
742 } RNID_TOP_DISC;
743
744 typedef struct _RNID { /* Structure is in Big Endian format */
745 uint8_t Format;
746 #define RNID_TOPOLOGY_DISC 0xdf
747 uint8_t CommonLen;
748 uint8_t resvd1;
749 uint8_t SpecificLen;
750 struct lpfc_name portName;
751 struct lpfc_name nodeName;
752 union {
753 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
754 } un;
755 } RNID;
756
757 typedef struct _RRQ { /* Structure is in Big Endian format */
758 uint32_t SID;
759 uint16_t Oxid;
760 uint16_t Rxid;
761 uint8_t resv[32]; /* optional association hdr */
762 } RRQ;
763
764 /* This is used for RSCN command */
765 typedef struct _D_ID { /* Structure is in Big Endian format */
766 union {
767 uint32_t word;
768 struct {
769 #ifdef __BIG_ENDIAN_BITFIELD
770 uint8_t resv;
771 uint8_t domain;
772 uint8_t area;
773 uint8_t id;
774 #else /* __LITTLE_ENDIAN_BITFIELD */
775 uint8_t id;
776 uint8_t area;
777 uint8_t domain;
778 uint8_t resv;
779 #endif
780 } b;
781 } un;
782 } D_ID;
783
784 /*
785 * Structure to define all ELS Payload types
786 */
787
788 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
789 uint8_t elsCode; /* FC Word 0, bit 24:31 */
790 uint8_t elsByte1;
791 uint8_t elsByte2;
792 uint8_t elsByte3;
793 union {
794 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
795 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
796 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
797 PRLI prli; /* Payload for PRLI/ACC */
798 PRLO prlo; /* Payload for PRLO/ACC */
799 ADISC adisc; /* Payload for ADISC/ACC */
800 FARP farp; /* Payload for FARP/ACC */
801 FAN fan; /* Payload for FAN */
802 SCR scr; /* Payload for SCR/ACC */
803 RRQ rrq; /* Payload for RRQ */
804 RNID rnid; /* Payload for RNID */
805 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
806 } un;
807 } ELS_PKT;
808
809 /*
810 * FDMI
811 * HBA MAnagement Operations Command Codes
812 */
813 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
814 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
815 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
816 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
817 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
818 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
819 #define SLI_MGMT_RPRT 0x210 /* Register Port */
820 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
821 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
822 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
823
824 /*
825 * Management Service Subtypes
826 */
827 #define SLI_CT_FDMI_Subtypes 0x10
828
829 /*
830 * HBA Management Service Reject Code
831 */
832 #define REJECT_CODE 0x9 /* Unable to perform command request */
833
834 /*
835 * HBA Management Service Reject Reason Code
836 * Please refer to the Reason Codes above
837 */
838
839 /*
840 * HBA Attribute Types
841 */
842 #define NODE_NAME 0x1
843 #define MANUFACTURER 0x2
844 #define SERIAL_NUMBER 0x3
845 #define MODEL 0x4
846 #define MODEL_DESCRIPTION 0x5
847 #define HARDWARE_VERSION 0x6
848 #define DRIVER_VERSION 0x7
849 #define OPTION_ROM_VERSION 0x8
850 #define FIRMWARE_VERSION 0x9
851 #define OS_NAME_VERSION 0xa
852 #define MAX_CT_PAYLOAD_LEN 0xb
853
854 /*
855 * Port Attrubute Types
856 */
857 #define SUPPORTED_FC4_TYPES 0x1
858 #define SUPPORTED_SPEED 0x2
859 #define PORT_SPEED 0x3
860 #define MAX_FRAME_SIZE 0x4
861 #define OS_DEVICE_NAME 0x5
862 #define HOST_NAME 0x6
863
864 union AttributesDef {
865 /* Structure is in Big Endian format */
866 struct {
867 uint32_t AttrType:16;
868 uint32_t AttrLen:16;
869 } bits;
870 uint32_t word;
871 };
872
873
874 /*
875 * HBA Attribute Entry (8 - 260 bytes)
876 */
877 typedef struct {
878 union AttributesDef ad;
879 union {
880 uint32_t VendorSpecific;
881 uint8_t Manufacturer[64];
882 uint8_t SerialNumber[64];
883 uint8_t Model[256];
884 uint8_t ModelDescription[256];
885 uint8_t HardwareVersion[256];
886 uint8_t DriverVersion[256];
887 uint8_t OptionROMVersion[256];
888 uint8_t FirmwareVersion[256];
889 struct lpfc_name NodeName;
890 uint8_t SupportFC4Types[32];
891 uint32_t SupportSpeed;
892 uint32_t PortSpeed;
893 uint32_t MaxFrameSize;
894 uint8_t OsDeviceName[256];
895 uint8_t OsNameVersion[256];
896 uint32_t MaxCTPayloadLen;
897 uint8_t HostName[256];
898 } un;
899 } ATTRIBUTE_ENTRY;
900
901 /*
902 * HBA Attribute Block
903 */
904 typedef struct {
905 uint32_t EntryCnt; /* Number of HBA attribute entries */
906 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
907 } ATTRIBUTE_BLOCK;
908
909 /*
910 * Port Entry
911 */
912 typedef struct {
913 struct lpfc_name PortName;
914 } PORT_ENTRY;
915
916 /*
917 * HBA Identifier
918 */
919 typedef struct {
920 struct lpfc_name PortName;
921 } HBA_IDENTIFIER;
922
923 /*
924 * Registered Port List Format
925 */
926 typedef struct {
927 uint32_t EntryCnt;
928 PORT_ENTRY pe; /* Variable-length array */
929 } REG_PORT_LIST;
930
931 /*
932 * Register HBA(RHBA)
933 */
934 typedef struct {
935 HBA_IDENTIFIER hi;
936 REG_PORT_LIST rpl; /* variable-length array */
937 /* ATTRIBUTE_BLOCK ab; */
938 } REG_HBA;
939
940 /*
941 * Register HBA Attributes (RHAT)
942 */
943 typedef struct {
944 struct lpfc_name HBA_PortName;
945 ATTRIBUTE_BLOCK ab;
946 } REG_HBA_ATTRIBUTE;
947
948 /*
949 * Register Port Attributes (RPA)
950 */
951 typedef struct {
952 struct lpfc_name PortName;
953 ATTRIBUTE_BLOCK ab;
954 } REG_PORT_ATTRIBUTE;
955
956 /*
957 * Get Registered HBA List (GRHL) Accept Payload Format
958 */
959 typedef struct {
960 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
961 struct lpfc_name HBA_PortName; /* Variable-length array */
962 } GRHL_ACC_PAYLOAD;
963
964 /*
965 * Get Registered Port List (GRPL) Accept Payload Format
966 */
967 typedef struct {
968 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
969 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
970 } GRPL_ACC_PAYLOAD;
971
972 /*
973 * Get Port Attributes (GPAT) Accept Payload Format
974 */
975
976 typedef struct {
977 ATTRIBUTE_BLOCK pab;
978 } GPAT_ACC_PAYLOAD;
979
980
981 /*
982 * Begin HBA configuration parameters.
983 * The PCI configuration register BAR assignments are:
984 * BAR0, offset 0x10 - SLIM base memory address
985 * BAR1, offset 0x14 - SLIM base memory high address
986 * BAR2, offset 0x18 - REGISTER base memory address
987 * BAR3, offset 0x1c - REGISTER base memory high address
988 * BAR4, offset 0x20 - BIU I/O registers
989 * BAR5, offset 0x24 - REGISTER base io high address
990 */
991
992 /* Number of rings currently used and available. */
993 #define MAX_CONFIGURED_RINGS 3
994 #define MAX_RINGS 4
995
996 /* IOCB / Mailbox is owned by FireFly */
997 #define OWN_CHIP 1
998
999 /* IOCB / Mailbox is owned by Host */
1000 #define OWN_HOST 0
1001
1002 /* Number of 4-byte words in an IOCB. */
1003 #define IOCB_WORD_SZ 8
1004
1005 /* defines for type field in fc header */
1006 #define FC_ELS_DATA 0x1
1007 #define FC_LLC_SNAP 0x5
1008 #define FC_FCP_DATA 0x8
1009 #define FC_COMMON_TRANSPORT_ULP 0x20
1010
1011 /* defines for rctl field in fc header */
1012 #define FC_DEV_DATA 0x0
1013 #define FC_UNSOL_CTL 0x2
1014 #define FC_SOL_CTL 0x3
1015 #define FC_UNSOL_DATA 0x4
1016 #define FC_FCP_CMND 0x6
1017 #define FC_ELS_REQ 0x22
1018 #define FC_ELS_RSP 0x23
1019
1020 /* network headers for Dfctl field */
1021 #define FC_NET_HDR 0x20
1022
1023 /* Start FireFly Register definitions */
1024 #define PCI_VENDOR_ID_EMULEX 0x10df
1025 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1026 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1027 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1028 #define PCI_DEVICE_ID_RFLY 0xf095
1029 #define PCI_DEVICE_ID_PFLY 0xf098
1030 #define PCI_DEVICE_ID_TFLY 0xf0a5
1031 #define PCI_DEVICE_ID_CENTAUR 0xf900
1032 #define PCI_DEVICE_ID_PEGASUS 0xf980
1033 #define PCI_DEVICE_ID_THOR 0xfa00
1034 #define PCI_DEVICE_ID_VIPER 0xfb00
1035 #define PCI_DEVICE_ID_HELIOS 0xfd00
1036 #define PCI_DEVICE_ID_BMID 0xf0d5
1037 #define PCI_DEVICE_ID_BSMB 0xf0d1
1038 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1039 #define PCI_DEVICE_ID_ZMID 0xf0e5
1040 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1041 #define PCI_DEVICE_ID_LP101 0xf0a1
1042 #define PCI_DEVICE_ID_LP10000S 0xfc00
1043
1044 #define JEDEC_ID_ADDRESS 0x0080001c
1045 #define FIREFLY_JEDEC_ID 0x1ACC
1046 #define SUPERFLY_JEDEC_ID 0x0020
1047 #define DRAGONFLY_JEDEC_ID 0x0021
1048 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1049 #define CENTAUR_2G_JEDEC_ID 0x0026
1050 #define CENTAUR_1G_JEDEC_ID 0x0028
1051 #define PEGASUS_ORION_JEDEC_ID 0x0036
1052 #define PEGASUS_JEDEC_ID 0x0038
1053 #define THOR_JEDEC_ID 0x0012
1054 #define HELIOS_JEDEC_ID 0x0364
1055 #define ZEPHYR_JEDEC_ID 0x0577
1056 #define VIPER_JEDEC_ID 0x4838
1057
1058 #define JEDEC_ID_MASK 0x0FFFF000
1059 #define JEDEC_ID_SHIFT 12
1060 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1061
1062 typedef struct { /* FireFly BIU registers */
1063 uint32_t hostAtt; /* See definitions for Host Attention
1064 register */
1065 uint32_t chipAtt; /* See definitions for Chip Attention
1066 register */
1067 uint32_t hostStatus; /* See definitions for Host Status register */
1068 uint32_t hostControl; /* See definitions for Host Control register */
1069 uint32_t buiConfig; /* See definitions for BIU configuration
1070 register */
1071 } FF_REGS;
1072
1073 /* IO Register size in bytes */
1074 #define FF_REG_AREA_SIZE 256
1075
1076 /* Host Attention Register */
1077
1078 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1079
1080 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1081 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1082 #define HA_R0ATT 0x00000008 /* Bit 3 */
1083 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1084 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1085 #define HA_R1ATT 0x00000080 /* Bit 7 */
1086 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1087 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1088 #define HA_R2ATT 0x00000800 /* Bit 11 */
1089 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1090 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1091 #define HA_R3ATT 0x00008000 /* Bit 15 */
1092 #define HA_LATT 0x20000000 /* Bit 29 */
1093 #define HA_MBATT 0x40000000 /* Bit 30 */
1094 #define HA_ERATT 0x80000000 /* Bit 31 */
1095
1096 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1097 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1098 #define HA_RXATT 0x00000008 /* Bit 3 */
1099 #define HA_RXMASK 0x0000000f
1100
1101 /* Chip Attention Register */
1102
1103 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1104
1105 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1106 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1107 #define CA_R0ATT 0x00000008 /* Bit 3 */
1108 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1109 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1110 #define CA_R1ATT 0x00000080 /* Bit 7 */
1111 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1112 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1113 #define CA_R2ATT 0x00000800 /* Bit 11 */
1114 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1115 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1116 #define CA_R3ATT 0x00008000 /* Bit 15 */
1117 #define CA_MBATT 0x40000000 /* Bit 30 */
1118
1119 /* Host Status Register */
1120
1121 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1122
1123 #define HS_MBRDY 0x00400000 /* Bit 22 */
1124 #define HS_FFRDY 0x00800000 /* Bit 23 */
1125 #define HS_FFER8 0x01000000 /* Bit 24 */
1126 #define HS_FFER7 0x02000000 /* Bit 25 */
1127 #define HS_FFER6 0x04000000 /* Bit 26 */
1128 #define HS_FFER5 0x08000000 /* Bit 27 */
1129 #define HS_FFER4 0x10000000 /* Bit 28 */
1130 #define HS_FFER3 0x20000000 /* Bit 29 */
1131 #define HS_FFER2 0x40000000 /* Bit 30 */
1132 #define HS_FFER1 0x80000000 /* Bit 31 */
1133 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1134
1135 /* Host Control Register */
1136
1137 #define HC_REG_OFFSET 12 /* Word offset from register base address */
1138
1139 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1140 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1141 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1142 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1143 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1144 #define HC_INITHBI 0x02000000 /* Bit 25 */
1145 #define HC_INITMB 0x04000000 /* Bit 26 */
1146 #define HC_INITFF 0x08000000 /* Bit 27 */
1147 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1148 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1149
1150 /* Mailbox Commands */
1151 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1152 #define MBX_LOAD_SM 0x01
1153 #define MBX_READ_NV 0x02
1154 #define MBX_WRITE_NV 0x03
1155 #define MBX_RUN_BIU_DIAG 0x04
1156 #define MBX_INIT_LINK 0x05
1157 #define MBX_DOWN_LINK 0x06
1158 #define MBX_CONFIG_LINK 0x07
1159 #define MBX_CONFIG_RING 0x09
1160 #define MBX_RESET_RING 0x0A
1161 #define MBX_READ_CONFIG 0x0B
1162 #define MBX_READ_RCONFIG 0x0C
1163 #define MBX_READ_SPARM 0x0D
1164 #define MBX_READ_STATUS 0x0E
1165 #define MBX_READ_RPI 0x0F
1166 #define MBX_READ_XRI 0x10
1167 #define MBX_READ_REV 0x11
1168 #define MBX_READ_LNK_STAT 0x12
1169 #define MBX_REG_LOGIN 0x13
1170 #define MBX_UNREG_LOGIN 0x14
1171 #define MBX_READ_LA 0x15
1172 #define MBX_CLEAR_LA 0x16
1173 #define MBX_DUMP_MEMORY 0x17
1174 #define MBX_DUMP_CONTEXT 0x18
1175 #define MBX_RUN_DIAGS 0x19
1176 #define MBX_RESTART 0x1A
1177 #define MBX_UPDATE_CFG 0x1B
1178 #define MBX_DOWN_LOAD 0x1C
1179 #define MBX_DEL_LD_ENTRY 0x1D
1180 #define MBX_RUN_PROGRAM 0x1E
1181 #define MBX_SET_MASK 0x20
1182 #define MBX_SET_SLIM 0x21
1183 #define MBX_UNREG_D_ID 0x23
1184 #define MBX_CONFIG_FARP 0x25
1185
1186 #define MBX_LOAD_AREA 0x81
1187 #define MBX_RUN_BIU_DIAG64 0x84
1188 #define MBX_CONFIG_PORT 0x88
1189 #define MBX_READ_SPARM64 0x8D
1190 #define MBX_READ_RPI64 0x8F
1191 #define MBX_REG_LOGIN64 0x93
1192 #define MBX_READ_LA64 0x95
1193
1194 #define MBX_FLASH_WR_ULA 0x98
1195 #define MBX_SET_DEBUG 0x99
1196 #define MBX_LOAD_EXP_ROM 0x9C
1197
1198 #define MBX_MAX_CMDS 0x9D
1199 #define MBX_SLI2_CMD_MASK 0x80
1200
1201 /* IOCB Commands */
1202
1203 #define CMD_RCV_SEQUENCE_CX 0x01
1204 #define CMD_XMIT_SEQUENCE_CR 0x02
1205 #define CMD_XMIT_SEQUENCE_CX 0x03
1206 #define CMD_XMIT_BCAST_CN 0x04
1207 #define CMD_XMIT_BCAST_CX 0x05
1208 #define CMD_QUE_RING_BUF_CN 0x06
1209 #define CMD_QUE_XRI_BUF_CX 0x07
1210 #define CMD_IOCB_CONTINUE_CN 0x08
1211 #define CMD_RET_XRI_BUF_CX 0x09
1212 #define CMD_ELS_REQUEST_CR 0x0A
1213 #define CMD_ELS_REQUEST_CX 0x0B
1214 #define CMD_RCV_ELS_REQ_CX 0x0D
1215 #define CMD_ABORT_XRI_CN 0x0E
1216 #define CMD_ABORT_XRI_CX 0x0F
1217 #define CMD_CLOSE_XRI_CN 0x10
1218 #define CMD_CLOSE_XRI_CX 0x11
1219 #define CMD_CREATE_XRI_CR 0x12
1220 #define CMD_CREATE_XRI_CX 0x13
1221 #define CMD_GET_RPI_CN 0x14
1222 #define CMD_XMIT_ELS_RSP_CX 0x15
1223 #define CMD_GET_RPI_CR 0x16
1224 #define CMD_XRI_ABORTED_CX 0x17
1225 #define CMD_FCP_IWRITE_CR 0x18
1226 #define CMD_FCP_IWRITE_CX 0x19
1227 #define CMD_FCP_IREAD_CR 0x1A
1228 #define CMD_FCP_IREAD_CX 0x1B
1229 #define CMD_FCP_ICMND_CR 0x1C
1230 #define CMD_FCP_ICMND_CX 0x1D
1231
1232 #define CMD_ADAPTER_MSG 0x20
1233 #define CMD_ADAPTER_DUMP 0x22
1234
1235 /* SLI_2 IOCB Command Set */
1236
1237 #define CMD_RCV_SEQUENCE64_CX 0x81
1238 #define CMD_XMIT_SEQUENCE64_CR 0x82
1239 #define CMD_XMIT_SEQUENCE64_CX 0x83
1240 #define CMD_XMIT_BCAST64_CN 0x84
1241 #define CMD_XMIT_BCAST64_CX 0x85
1242 #define CMD_QUE_RING_BUF64_CN 0x86
1243 #define CMD_QUE_XRI_BUF64_CX 0x87
1244 #define CMD_IOCB_CONTINUE64_CN 0x88
1245 #define CMD_RET_XRI_BUF64_CX 0x89
1246 #define CMD_ELS_REQUEST64_CR 0x8A
1247 #define CMD_ELS_REQUEST64_CX 0x8B
1248 #define CMD_ABORT_MXRI64_CN 0x8C
1249 #define CMD_RCV_ELS_REQ64_CX 0x8D
1250 #define CMD_XMIT_ELS_RSP64_CX 0x95
1251 #define CMD_FCP_IWRITE64_CR 0x98
1252 #define CMD_FCP_IWRITE64_CX 0x99
1253 #define CMD_FCP_IREAD64_CR 0x9A
1254 #define CMD_FCP_IREAD64_CX 0x9B
1255 #define CMD_FCP_ICMND64_CR 0x9C
1256 #define CMD_FCP_ICMND64_CX 0x9D
1257
1258 #define CMD_GEN_REQUEST64_CR 0xC2
1259 #define CMD_GEN_REQUEST64_CX 0xC3
1260
1261 #define CMD_MAX_IOCB_CMD 0xE6
1262 #define CMD_IOCB_MASK 0xff
1263
1264 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1265 iocb */
1266 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1267 /*
1268 * Define Status
1269 */
1270 #define MBX_SUCCESS 0
1271 #define MBXERR_NUM_RINGS 1
1272 #define MBXERR_NUM_IOCBS 2
1273 #define MBXERR_IOCBS_EXCEEDED 3
1274 #define MBXERR_BAD_RING_NUMBER 4
1275 #define MBXERR_MASK_ENTRIES_RANGE 5
1276 #define MBXERR_MASKS_EXCEEDED 6
1277 #define MBXERR_BAD_PROFILE 7
1278 #define MBXERR_BAD_DEF_CLASS 8
1279 #define MBXERR_BAD_MAX_RESPONDER 9
1280 #define MBXERR_BAD_MAX_ORIGINATOR 10
1281 #define MBXERR_RPI_REGISTERED 11
1282 #define MBXERR_RPI_FULL 12
1283 #define MBXERR_NO_RESOURCES 13
1284 #define MBXERR_BAD_RCV_LENGTH 14
1285 #define MBXERR_DMA_ERROR 15
1286 #define MBXERR_ERROR 16
1287 #define MBX_NOT_FINISHED 255
1288
1289 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1290 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1291
1292 /*
1293 * Begin Structure Definitions for Mailbox Commands
1294 */
1295
1296 typedef struct {
1297 #ifdef __BIG_ENDIAN_BITFIELD
1298 uint8_t tval;
1299 uint8_t tmask;
1300 uint8_t rval;
1301 uint8_t rmask;
1302 #else /* __LITTLE_ENDIAN_BITFIELD */
1303 uint8_t rmask;
1304 uint8_t rval;
1305 uint8_t tmask;
1306 uint8_t tval;
1307 #endif
1308 } RR_REG;
1309
1310 struct ulp_bde {
1311 uint32_t bdeAddress;
1312 #ifdef __BIG_ENDIAN_BITFIELD
1313 uint32_t bdeReserved:4;
1314 uint32_t bdeAddrHigh:4;
1315 uint32_t bdeSize:24;
1316 #else /* __LITTLE_ENDIAN_BITFIELD */
1317 uint32_t bdeSize:24;
1318 uint32_t bdeAddrHigh:4;
1319 uint32_t bdeReserved:4;
1320 #endif
1321 };
1322
1323 struct ulp_bde64 { /* SLI-2 */
1324 union ULP_BDE_TUS {
1325 uint32_t w;
1326 struct {
1327 #ifdef __BIG_ENDIAN_BITFIELD
1328 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1329 VALUE !! */
1330 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1331 #else /* __LITTLE_ENDIAN_BITFIELD */
1332 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1333 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1334 VALUE !! */
1335 #endif
1336
1337 #define BUFF_USE_RSVD 0x01 /* bdeFlags */
1338 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1339 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1340 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1341 buffer */
1342 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1343 addr */
1344 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1345 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1346 #define BUFF_TYPE_INVALID 0x80 /* "" "" */
1347 } f;
1348 } tus;
1349 uint32_t addrLow;
1350 uint32_t addrHigh;
1351 };
1352 #define BDE64_SIZE_WORD 0
1353 #define BPL64_SIZE_WORD 0x40
1354
1355 typedef struct ULP_BDL { /* SLI-2 */
1356 #ifdef __BIG_ENDIAN_BITFIELD
1357 uint32_t bdeFlags:8; /* BDL Flags */
1358 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1359 #else /* __LITTLE_ENDIAN_BITFIELD */
1360 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1361 uint32_t bdeFlags:8; /* BDL Flags */
1362 #endif
1363
1364 uint32_t addrLow; /* Address 0:31 */
1365 uint32_t addrHigh; /* Address 32:63 */
1366 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1367 } ULP_BDL;
1368
1369 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1370
1371 typedef struct {
1372 #ifdef __BIG_ENDIAN_BITFIELD
1373 uint32_t rsvd2:25;
1374 uint32_t acknowledgment:1;
1375 uint32_t version:1;
1376 uint32_t erase_or_prog:1;
1377 uint32_t update_flash:1;
1378 uint32_t update_ram:1;
1379 uint32_t method:1;
1380 uint32_t load_cmplt:1;
1381 #else /* __LITTLE_ENDIAN_BITFIELD */
1382 uint32_t load_cmplt:1;
1383 uint32_t method:1;
1384 uint32_t update_ram:1;
1385 uint32_t update_flash:1;
1386 uint32_t erase_or_prog:1;
1387 uint32_t version:1;
1388 uint32_t acknowledgment:1;
1389 uint32_t rsvd2:25;
1390 #endif
1391
1392 uint32_t dl_to_adr_low;
1393 uint32_t dl_to_adr_high;
1394 uint32_t dl_len;
1395 union {
1396 uint32_t dl_from_mbx_offset;
1397 struct ulp_bde dl_from_bde;
1398 struct ulp_bde64 dl_from_bde64;
1399 } un;
1400
1401 } LOAD_SM_VAR;
1402
1403 /* Structure for MB Command READ_NVPARM (02) */
1404
1405 typedef struct {
1406 uint32_t rsvd1[3]; /* Read as all one's */
1407 uint32_t rsvd2; /* Read as all zero's */
1408 uint32_t portname[2]; /* N_PORT name */
1409 uint32_t nodename[2]; /* NODE name */
1410
1411 #ifdef __BIG_ENDIAN_BITFIELD
1412 uint32_t pref_DID:24;
1413 uint32_t hardAL_PA:8;
1414 #else /* __LITTLE_ENDIAN_BITFIELD */
1415 uint32_t hardAL_PA:8;
1416 uint32_t pref_DID:24;
1417 #endif
1418
1419 uint32_t rsvd3[21]; /* Read as all one's */
1420 } READ_NV_VAR;
1421
1422 /* Structure for MB Command WRITE_NVPARMS (03) */
1423
1424 typedef struct {
1425 uint32_t rsvd1[3]; /* Must be all one's */
1426 uint32_t rsvd2; /* Must be all zero's */
1427 uint32_t portname[2]; /* N_PORT name */
1428 uint32_t nodename[2]; /* NODE name */
1429
1430 #ifdef __BIG_ENDIAN_BITFIELD
1431 uint32_t pref_DID:24;
1432 uint32_t hardAL_PA:8;
1433 #else /* __LITTLE_ENDIAN_BITFIELD */
1434 uint32_t hardAL_PA:8;
1435 uint32_t pref_DID:24;
1436 #endif
1437
1438 uint32_t rsvd3[21]; /* Must be all one's */
1439 } WRITE_NV_VAR;
1440
1441 /* Structure for MB Command RUN_BIU_DIAG (04) */
1442 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1443
1444 typedef struct {
1445 uint32_t rsvd1;
1446 union {
1447 struct {
1448 struct ulp_bde xmit_bde;
1449 struct ulp_bde rcv_bde;
1450 } s1;
1451 struct {
1452 struct ulp_bde64 xmit_bde64;
1453 struct ulp_bde64 rcv_bde64;
1454 } s2;
1455 } un;
1456 } BIU_DIAG_VAR;
1457
1458 /* Structure for MB Command INIT_LINK (05) */
1459
1460 typedef struct {
1461 #ifdef __BIG_ENDIAN_BITFIELD
1462 uint32_t rsvd1:24;
1463 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1464 #else /* __LITTLE_ENDIAN_BITFIELD */
1465 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1466 uint32_t rsvd1:24;
1467 #endif
1468
1469 #ifdef __BIG_ENDIAN_BITFIELD
1470 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1471 uint8_t rsvd2;
1472 uint16_t link_flags;
1473 #else /* __LITTLE_ENDIAN_BITFIELD */
1474 uint16_t link_flags;
1475 uint8_t rsvd2;
1476 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1477 #endif
1478
1479 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1480 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1481 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1482 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1483 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1484 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1485
1486 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1487 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1488
1489 uint32_t link_speed;
1490 #define LINK_SPEED_AUTO 0 /* Auto selection */
1491 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1492 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1493 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1494 #define LINK_SPEED_8G 8 /* 4 Gigabaud */
1495 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1496
1497 } INIT_LINK_VAR;
1498
1499 /* Structure for MB Command DOWN_LINK (06) */
1500
1501 typedef struct {
1502 uint32_t rsvd1;
1503 } DOWN_LINK_VAR;
1504
1505 /* Structure for MB Command CONFIG_LINK (07) */
1506
1507 typedef struct {
1508 #ifdef __BIG_ENDIAN_BITFIELD
1509 uint32_t cr:1;
1510 uint32_t ci:1;
1511 uint32_t cr_delay:6;
1512 uint32_t cr_count:8;
1513 uint32_t rsvd1:8;
1514 uint32_t MaxBBC:8;
1515 #else /* __LITTLE_ENDIAN_BITFIELD */
1516 uint32_t MaxBBC:8;
1517 uint32_t rsvd1:8;
1518 uint32_t cr_count:8;
1519 uint32_t cr_delay:6;
1520 uint32_t ci:1;
1521 uint32_t cr:1;
1522 #endif
1523
1524 uint32_t myId;
1525 uint32_t rsvd2;
1526 uint32_t edtov;
1527 uint32_t arbtov;
1528 uint32_t ratov;
1529 uint32_t rttov;
1530 uint32_t altov;
1531 uint32_t crtov;
1532 uint32_t citov;
1533 #ifdef __BIG_ENDIAN_BITFIELD
1534 uint32_t rrq_enable:1;
1535 uint32_t rrq_immed:1;
1536 uint32_t rsvd4:29;
1537 uint32_t ack0_enable:1;
1538 #else /* __LITTLE_ENDIAN_BITFIELD */
1539 uint32_t ack0_enable:1;
1540 uint32_t rsvd4:29;
1541 uint32_t rrq_immed:1;
1542 uint32_t rrq_enable:1;
1543 #endif
1544 } CONFIG_LINK;
1545
1546 /* Structure for MB Command PART_SLIM (08)
1547 * will be removed since SLI1 is no longer supported!
1548 */
1549 typedef struct {
1550 #ifdef __BIG_ENDIAN_BITFIELD
1551 uint16_t offCiocb;
1552 uint16_t numCiocb;
1553 uint16_t offRiocb;
1554 uint16_t numRiocb;
1555 #else /* __LITTLE_ENDIAN_BITFIELD */
1556 uint16_t numCiocb;
1557 uint16_t offCiocb;
1558 uint16_t numRiocb;
1559 uint16_t offRiocb;
1560 #endif
1561 } RING_DEF;
1562
1563 typedef struct {
1564 #ifdef __BIG_ENDIAN_BITFIELD
1565 uint32_t unused1:24;
1566 uint32_t numRing:8;
1567 #else /* __LITTLE_ENDIAN_BITFIELD */
1568 uint32_t numRing:8;
1569 uint32_t unused1:24;
1570 #endif
1571
1572 RING_DEF ringdef[4];
1573 uint32_t hbainit;
1574 } PART_SLIM_VAR;
1575
1576 /* Structure for MB Command CONFIG_RING (09) */
1577
1578 typedef struct {
1579 #ifdef __BIG_ENDIAN_BITFIELD
1580 uint32_t unused2:6;
1581 uint32_t recvSeq:1;
1582 uint32_t recvNotify:1;
1583 uint32_t numMask:8;
1584 uint32_t profile:8;
1585 uint32_t unused1:4;
1586 uint32_t ring:4;
1587 #else /* __LITTLE_ENDIAN_BITFIELD */
1588 uint32_t ring:4;
1589 uint32_t unused1:4;
1590 uint32_t profile:8;
1591 uint32_t numMask:8;
1592 uint32_t recvNotify:1;
1593 uint32_t recvSeq:1;
1594 uint32_t unused2:6;
1595 #endif
1596
1597 #ifdef __BIG_ENDIAN_BITFIELD
1598 uint16_t maxRespXchg;
1599 uint16_t maxOrigXchg;
1600 #else /* __LITTLE_ENDIAN_BITFIELD */
1601 uint16_t maxOrigXchg;
1602 uint16_t maxRespXchg;
1603 #endif
1604
1605 RR_REG rrRegs[6];
1606 } CONFIG_RING_VAR;
1607
1608 /* Structure for MB Command RESET_RING (10) */
1609
1610 typedef struct {
1611 uint32_t ring_no;
1612 } RESET_RING_VAR;
1613
1614 /* Structure for MB Command READ_CONFIG (11) */
1615
1616 typedef struct {
1617 #ifdef __BIG_ENDIAN_BITFIELD
1618 uint32_t cr:1;
1619 uint32_t ci:1;
1620 uint32_t cr_delay:6;
1621 uint32_t cr_count:8;
1622 uint32_t InitBBC:8;
1623 uint32_t MaxBBC:8;
1624 #else /* __LITTLE_ENDIAN_BITFIELD */
1625 uint32_t MaxBBC:8;
1626 uint32_t InitBBC:8;
1627 uint32_t cr_count:8;
1628 uint32_t cr_delay:6;
1629 uint32_t ci:1;
1630 uint32_t cr:1;
1631 #endif
1632
1633 #ifdef __BIG_ENDIAN_BITFIELD
1634 uint32_t topology:8;
1635 uint32_t myDid:24;
1636 #else /* __LITTLE_ENDIAN_BITFIELD */
1637 uint32_t myDid:24;
1638 uint32_t topology:8;
1639 #endif
1640
1641 /* Defines for topology (defined previously) */
1642 #ifdef __BIG_ENDIAN_BITFIELD
1643 uint32_t AR:1;
1644 uint32_t IR:1;
1645 uint32_t rsvd1:29;
1646 uint32_t ack0:1;
1647 #else /* __LITTLE_ENDIAN_BITFIELD */
1648 uint32_t ack0:1;
1649 uint32_t rsvd1:29;
1650 uint32_t IR:1;
1651 uint32_t AR:1;
1652 #endif
1653
1654 uint32_t edtov;
1655 uint32_t arbtov;
1656 uint32_t ratov;
1657 uint32_t rttov;
1658 uint32_t altov;
1659 uint32_t lmt;
1660 #define LMT_RESERVED 0x0 /* Not used */
1661 #define LMT_266_10bit 0x1 /* 265.625 Mbaud 10 bit iface */
1662 #define LMT_532_10bit 0x2 /* 531.25 Mbaud 10 bit iface */
1663 #define LMT_1063_20bit 0x3 /* 1062.5 Mbaud 20 bit iface */
1664 #define LMT_1063_10bit 0x4 /* 1062.5 Mbaud 10 bit iface */
1665 #define LMT_2125_10bit 0x8 /* 2125 Mbaud 10 bit iface */
1666 #define LMT_4250_10bit 0x40 /* 4250 Mbaud 10 bit iface */
1667
1668 uint32_t rsvd2;
1669 uint32_t rsvd3;
1670 uint32_t max_xri;
1671 uint32_t max_iocb;
1672 uint32_t max_rpi;
1673 uint32_t avail_xri;
1674 uint32_t avail_iocb;
1675 uint32_t avail_rpi;
1676 uint32_t default_rpi;
1677 } READ_CONFIG_VAR;
1678
1679 /* Structure for MB Command READ_RCONFIG (12) */
1680
1681 typedef struct {
1682 #ifdef __BIG_ENDIAN_BITFIELD
1683 uint32_t rsvd2:7;
1684 uint32_t recvNotify:1;
1685 uint32_t numMask:8;
1686 uint32_t profile:8;
1687 uint32_t rsvd1:4;
1688 uint32_t ring:4;
1689 #else /* __LITTLE_ENDIAN_BITFIELD */
1690 uint32_t ring:4;
1691 uint32_t rsvd1:4;
1692 uint32_t profile:8;
1693 uint32_t numMask:8;
1694 uint32_t recvNotify:1;
1695 uint32_t rsvd2:7;
1696 #endif
1697
1698 #ifdef __BIG_ENDIAN_BITFIELD
1699 uint16_t maxResp;
1700 uint16_t maxOrig;
1701 #else /* __LITTLE_ENDIAN_BITFIELD */
1702 uint16_t maxOrig;
1703 uint16_t maxResp;
1704 #endif
1705
1706 RR_REG rrRegs[6];
1707
1708 #ifdef __BIG_ENDIAN_BITFIELD
1709 uint16_t cmdRingOffset;
1710 uint16_t cmdEntryCnt;
1711 uint16_t rspRingOffset;
1712 uint16_t rspEntryCnt;
1713 uint16_t nextCmdOffset;
1714 uint16_t rsvd3;
1715 uint16_t nextRspOffset;
1716 uint16_t rsvd4;
1717 #else /* __LITTLE_ENDIAN_BITFIELD */
1718 uint16_t cmdEntryCnt;
1719 uint16_t cmdRingOffset;
1720 uint16_t rspEntryCnt;
1721 uint16_t rspRingOffset;
1722 uint16_t rsvd3;
1723 uint16_t nextCmdOffset;
1724 uint16_t rsvd4;
1725 uint16_t nextRspOffset;
1726 #endif
1727 } READ_RCONF_VAR;
1728
1729 /* Structure for MB Command READ_SPARM (13) */
1730 /* Structure for MB Command READ_SPARM64 (0x8D) */
1731
1732 typedef struct {
1733 uint32_t rsvd1;
1734 uint32_t rsvd2;
1735 union {
1736 struct ulp_bde sp; /* This BDE points to struct serv_parm
1737 structure */
1738 struct ulp_bde64 sp64;
1739 } un;
1740 } READ_SPARM_VAR;
1741
1742 /* Structure for MB Command READ_STATUS (14) */
1743
1744 typedef struct {
1745 #ifdef __BIG_ENDIAN_BITFIELD
1746 uint32_t rsvd1:31;
1747 uint32_t clrCounters:1;
1748 uint16_t activeXriCnt;
1749 uint16_t activeRpiCnt;
1750 #else /* __LITTLE_ENDIAN_BITFIELD */
1751 uint32_t clrCounters:1;
1752 uint32_t rsvd1:31;
1753 uint16_t activeRpiCnt;
1754 uint16_t activeXriCnt;
1755 #endif
1756
1757 uint32_t xmitByteCnt;
1758 uint32_t rcvByteCnt;
1759 uint32_t xmitFrameCnt;
1760 uint32_t rcvFrameCnt;
1761 uint32_t xmitSeqCnt;
1762 uint32_t rcvSeqCnt;
1763 uint32_t totalOrigExchanges;
1764 uint32_t totalRespExchanges;
1765 uint32_t rcvPbsyCnt;
1766 uint32_t rcvFbsyCnt;
1767 } READ_STATUS_VAR;
1768
1769 /* Structure for MB Command READ_RPI (15) */
1770 /* Structure for MB Command READ_RPI64 (0x8F) */
1771
1772 typedef struct {
1773 #ifdef __BIG_ENDIAN_BITFIELD
1774 uint16_t nextRpi;
1775 uint16_t reqRpi;
1776 uint32_t rsvd2:8;
1777 uint32_t DID:24;
1778 #else /* __LITTLE_ENDIAN_BITFIELD */
1779 uint16_t reqRpi;
1780 uint16_t nextRpi;
1781 uint32_t DID:24;
1782 uint32_t rsvd2:8;
1783 #endif
1784
1785 union {
1786 struct ulp_bde sp;
1787 struct ulp_bde64 sp64;
1788 } un;
1789
1790 } READ_RPI_VAR;
1791
1792 /* Structure for MB Command READ_XRI (16) */
1793
1794 typedef struct {
1795 #ifdef __BIG_ENDIAN_BITFIELD
1796 uint16_t nextXri;
1797 uint16_t reqXri;
1798 uint16_t rsvd1;
1799 uint16_t rpi;
1800 uint32_t rsvd2:8;
1801 uint32_t DID:24;
1802 uint32_t rsvd3:8;
1803 uint32_t SID:24;
1804 uint32_t rsvd4;
1805 uint8_t seqId;
1806 uint8_t rsvd5;
1807 uint16_t seqCount;
1808 uint16_t oxId;
1809 uint16_t rxId;
1810 uint32_t rsvd6:30;
1811 uint32_t si:1;
1812 uint32_t exchOrig:1;
1813 #else /* __LITTLE_ENDIAN_BITFIELD */
1814 uint16_t reqXri;
1815 uint16_t nextXri;
1816 uint16_t rpi;
1817 uint16_t rsvd1;
1818 uint32_t DID:24;
1819 uint32_t rsvd2:8;
1820 uint32_t SID:24;
1821 uint32_t rsvd3:8;
1822 uint32_t rsvd4;
1823 uint16_t seqCount;
1824 uint8_t rsvd5;
1825 uint8_t seqId;
1826 uint16_t rxId;
1827 uint16_t oxId;
1828 uint32_t exchOrig:1;
1829 uint32_t si:1;
1830 uint32_t rsvd6:30;
1831 #endif
1832 } READ_XRI_VAR;
1833
1834 /* Structure for MB Command READ_REV (17) */
1835
1836 typedef struct {
1837 #ifdef __BIG_ENDIAN_BITFIELD
1838 uint32_t cv:1;
1839 uint32_t rr:1;
1840 uint32_t rsvd1:29;
1841 uint32_t rv:1;
1842 #else /* __LITTLE_ENDIAN_BITFIELD */
1843 uint32_t rv:1;
1844 uint32_t rsvd1:29;
1845 uint32_t rr:1;
1846 uint32_t cv:1;
1847 #endif
1848
1849 uint32_t biuRev;
1850 uint32_t smRev;
1851 union {
1852 uint32_t smFwRev;
1853 struct {
1854 #ifdef __BIG_ENDIAN_BITFIELD
1855 uint8_t ProgType;
1856 uint8_t ProgId;
1857 uint16_t ProgVer:4;
1858 uint16_t ProgRev:4;
1859 uint16_t ProgFixLvl:2;
1860 uint16_t ProgDistType:2;
1861 uint16_t DistCnt:4;
1862 #else /* __LITTLE_ENDIAN_BITFIELD */
1863 uint16_t DistCnt:4;
1864 uint16_t ProgDistType:2;
1865 uint16_t ProgFixLvl:2;
1866 uint16_t ProgRev:4;
1867 uint16_t ProgVer:4;
1868 uint8_t ProgId;
1869 uint8_t ProgType;
1870 #endif
1871
1872 } b;
1873 } un;
1874 uint32_t endecRev;
1875 #ifdef __BIG_ENDIAN_BITFIELD
1876 uint8_t feaLevelHigh;
1877 uint8_t feaLevelLow;
1878 uint8_t fcphHigh;
1879 uint8_t fcphLow;
1880 #else /* __LITTLE_ENDIAN_BITFIELD */
1881 uint8_t fcphLow;
1882 uint8_t fcphHigh;
1883 uint8_t feaLevelLow;
1884 uint8_t feaLevelHigh;
1885 #endif
1886
1887 uint32_t postKernRev;
1888 uint32_t opFwRev;
1889 uint8_t opFwName[16];
1890 uint32_t sli1FwRev;
1891 uint8_t sli1FwName[16];
1892 uint32_t sli2FwRev;
1893 uint8_t sli2FwName[16];
1894 uint32_t rsvd2;
1895 uint32_t RandomData[7];
1896 } READ_REV_VAR;
1897
1898 /* Structure for MB Command READ_LINK_STAT (18) */
1899
1900 typedef struct {
1901 uint32_t rsvd1;
1902 uint32_t linkFailureCnt;
1903 uint32_t lossSyncCnt;
1904
1905 uint32_t lossSignalCnt;
1906 uint32_t primSeqErrCnt;
1907 uint32_t invalidXmitWord;
1908 uint32_t crcCnt;
1909 uint32_t primSeqTimeout;
1910 uint32_t elasticOverrun;
1911 uint32_t arbTimeout;
1912 } READ_LNK_VAR;
1913
1914 /* Structure for MB Command REG_LOGIN (19) */
1915 /* Structure for MB Command REG_LOGIN64 (0x93) */
1916
1917 typedef struct {
1918 #ifdef __BIG_ENDIAN_BITFIELD
1919 uint16_t rsvd1;
1920 uint16_t rpi;
1921 uint32_t rsvd2:8;
1922 uint32_t did:24;
1923 #else /* __LITTLE_ENDIAN_BITFIELD */
1924 uint16_t rpi;
1925 uint16_t rsvd1;
1926 uint32_t did:24;
1927 uint32_t rsvd2:8;
1928 #endif
1929
1930 union {
1931 struct ulp_bde sp;
1932 struct ulp_bde64 sp64;
1933 } un;
1934
1935 } REG_LOGIN_VAR;
1936
1937 /* Word 30 contents for REG_LOGIN */
1938 typedef union {
1939 struct {
1940 #ifdef __BIG_ENDIAN_BITFIELD
1941 uint16_t rsvd1:12;
1942 uint16_t wd30_class:4;
1943 uint16_t xri;
1944 #else /* __LITTLE_ENDIAN_BITFIELD */
1945 uint16_t xri;
1946 uint16_t wd30_class:4;
1947 uint16_t rsvd1:12;
1948 #endif
1949 } f;
1950 uint32_t word;
1951 } REG_WD30;
1952
1953 /* Structure for MB Command UNREG_LOGIN (20) */
1954
1955 typedef struct {
1956 #ifdef __BIG_ENDIAN_BITFIELD
1957 uint16_t rsvd1;
1958 uint16_t rpi;
1959 #else /* __LITTLE_ENDIAN_BITFIELD */
1960 uint16_t rpi;
1961 uint16_t rsvd1;
1962 #endif
1963 } UNREG_LOGIN_VAR;
1964
1965 /* Structure for MB Command UNREG_D_ID (0x23) */
1966
1967 typedef struct {
1968 uint32_t did;
1969 } UNREG_D_ID_VAR;
1970
1971 /* Structure for MB Command READ_LA (21) */
1972 /* Structure for MB Command READ_LA64 (0x95) */
1973
1974 typedef struct {
1975 uint32_t eventTag; /* Event tag */
1976 #ifdef __BIG_ENDIAN_BITFIELD
1977 uint32_t rsvd1:22;
1978 uint32_t pb:1;
1979 uint32_t il:1;
1980 uint32_t attType:8;
1981 #else /* __LITTLE_ENDIAN_BITFIELD */
1982 uint32_t attType:8;
1983 uint32_t il:1;
1984 uint32_t pb:1;
1985 uint32_t rsvd1:22;
1986 #endif
1987
1988 #define AT_RESERVED 0x00 /* Reserved - attType */
1989 #define AT_LINK_UP 0x01 /* Link is up */
1990 #define AT_LINK_DOWN 0x02 /* Link is down */
1991
1992 #ifdef __BIG_ENDIAN_BITFIELD
1993 uint8_t granted_AL_PA;
1994 uint8_t lipAlPs;
1995 uint8_t lipType;
1996 uint8_t topology;
1997 #else /* __LITTLE_ENDIAN_BITFIELD */
1998 uint8_t topology;
1999 uint8_t lipType;
2000 uint8_t lipAlPs;
2001 uint8_t granted_AL_PA;
2002 #endif
2003
2004 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2005 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2006
2007 union {
2008 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2009 to */
2010 /* store the LILP AL_PA position map into */
2011 struct ulp_bde64 lilpBde64;
2012 } un;
2013
2014 #ifdef __BIG_ENDIAN_BITFIELD
2015 uint32_t Dlu:1;
2016 uint32_t Dtf:1;
2017 uint32_t Drsvd2:14;
2018 uint32_t DlnkSpeed:8;
2019 uint32_t DnlPort:4;
2020 uint32_t Dtx:2;
2021 uint32_t Drx:2;
2022 #else /* __LITTLE_ENDIAN_BITFIELD */
2023 uint32_t Drx:2;
2024 uint32_t Dtx:2;
2025 uint32_t DnlPort:4;
2026 uint32_t DlnkSpeed:8;
2027 uint32_t Drsvd2:14;
2028 uint32_t Dtf:1;
2029 uint32_t Dlu:1;
2030 #endif
2031
2032 #ifdef __BIG_ENDIAN_BITFIELD
2033 uint32_t Ulu:1;
2034 uint32_t Utf:1;
2035 uint32_t Ursvd2:14;
2036 uint32_t UlnkSpeed:8;
2037 uint32_t UnlPort:4;
2038 uint32_t Utx:2;
2039 uint32_t Urx:2;
2040 #else /* __LITTLE_ENDIAN_BITFIELD */
2041 uint32_t Urx:2;
2042 uint32_t Utx:2;
2043 uint32_t UnlPort:4;
2044 uint32_t UlnkSpeed:8;
2045 uint32_t Ursvd2:14;
2046 uint32_t Utf:1;
2047 uint32_t Ulu:1;
2048 #endif
2049
2050 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2051 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2052 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2053 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2054 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2055 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2056
2057 } READ_LA_VAR;
2058
2059 /* Structure for MB Command CLEAR_LA (22) */
2060
2061 typedef struct {
2062 uint32_t eventTag; /* Event tag */
2063 uint32_t rsvd1;
2064 } CLEAR_LA_VAR;
2065
2066 /* Structure for MB Command DUMP */
2067
2068 typedef struct {
2069 #ifdef __BIG_ENDIAN_BITFIELD
2070 uint32_t rsvd:25;
2071 uint32_t ra:1;
2072 uint32_t co:1;
2073 uint32_t cv:1;
2074 uint32_t type:4;
2075 uint32_t entry_index:16;
2076 uint32_t region_id:16;
2077 #else /* __LITTLE_ENDIAN_BITFIELD */
2078 uint32_t type:4;
2079 uint32_t cv:1;
2080 uint32_t co:1;
2081 uint32_t ra:1;
2082 uint32_t rsvd:25;
2083 uint32_t region_id:16;
2084 uint32_t entry_index:16;
2085 #endif
2086
2087 uint32_t rsvd1;
2088 uint32_t word_cnt;
2089 uint32_t resp_offset;
2090 } DUMP_VAR;
2091
2092 #define DMP_MEM_REG 0x1
2093 #define DMP_NV_PARAMS 0x2
2094
2095 #define DMP_REGION_VPD 0xe
2096 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2097 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2098 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2099
2100 /* Structure for MB Command CONFIG_PORT (0x88) */
2101
2102 typedef struct {
2103 uint32_t pcbLen;
2104 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2105 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2106 uint32_t hbainit[5];
2107 } CONFIG_PORT_VAR;
2108
2109 /* SLI-2 Port Control Block */
2110
2111 /* SLIM POINTER */
2112 #define SLIMOFF 0x30 /* WORD */
2113
2114 typedef struct _SLI2_RDSC {
2115 uint32_t cmdEntries;
2116 uint32_t cmdAddrLow;
2117 uint32_t cmdAddrHigh;
2118
2119 uint32_t rspEntries;
2120 uint32_t rspAddrLow;
2121 uint32_t rspAddrHigh;
2122 } SLI2_RDSC;
2123
2124 typedef struct _PCB {
2125 #ifdef __BIG_ENDIAN_BITFIELD
2126 uint32_t type:8;
2127 #define TYPE_NATIVE_SLI2 0x01;
2128 uint32_t feature:8;
2129 #define FEATURE_INITIAL_SLI2 0x01;
2130 uint32_t rsvd:12;
2131 uint32_t maxRing:4;
2132 #else /* __LITTLE_ENDIAN_BITFIELD */
2133 uint32_t maxRing:4;
2134 uint32_t rsvd:12;
2135 uint32_t feature:8;
2136 #define FEATURE_INITIAL_SLI2 0x01;
2137 uint32_t type:8;
2138 #define TYPE_NATIVE_SLI2 0x01;
2139 #endif
2140
2141 uint32_t mailBoxSize;
2142 uint32_t mbAddrLow;
2143 uint32_t mbAddrHigh;
2144
2145 uint32_t hgpAddrLow;
2146 uint32_t hgpAddrHigh;
2147
2148 uint32_t pgpAddrLow;
2149 uint32_t pgpAddrHigh;
2150 SLI2_RDSC rdsc[MAX_RINGS];
2151 } PCB_t;
2152
2153 /* NEW_FEATURE */
2154 typedef struct {
2155 #ifdef __BIG_ENDIAN_BITFIELD
2156 uint32_t rsvd0:27;
2157 uint32_t discardFarp:1;
2158 uint32_t IPEnable:1;
2159 uint32_t nodeName:1;
2160 uint32_t portName:1;
2161 uint32_t filterEnable:1;
2162 #else /* __LITTLE_ENDIAN_BITFIELD */
2163 uint32_t filterEnable:1;
2164 uint32_t portName:1;
2165 uint32_t nodeName:1;
2166 uint32_t IPEnable:1;
2167 uint32_t discardFarp:1;
2168 uint32_t rsvd:27;
2169 #endif
2170
2171 uint8_t portname[8]; /* Used to be struct lpfc_name */
2172 uint8_t nodename[8];
2173 uint32_t rsvd1;
2174 uint32_t rsvd2;
2175 uint32_t rsvd3;
2176 uint32_t IPAddress;
2177 } CONFIG_FARP_VAR;
2178
2179 /* Union of all Mailbox Command types */
2180 #define MAILBOX_CMD_WSIZE 32
2181 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2182
2183 typedef union {
2184 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2185 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2186 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2187 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2188 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2189 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2190 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2191 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2192 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2193 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2194 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2195 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2196 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2197 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2198 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2199 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2200 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2201 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2202 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2203 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2204 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2205 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2206 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2207 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2208 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2209 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */
2210 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2211 } MAILVARIANTS;
2212
2213 /*
2214 * SLI-2 specific structures
2215 */
2216
2217 typedef struct {
2218 uint32_t cmdPutInx;
2219 uint32_t rspGetInx;
2220 } HGP;
2221
2222 typedef struct {
2223 uint32_t cmdGetInx;
2224 uint32_t rspPutInx;
2225 } PGP;
2226
2227 typedef struct _SLI2_DESC {
2228 HGP host[MAX_RINGS];
2229 uint32_t unused1[16];
2230 PGP port[MAX_RINGS];
2231 } SLI2_DESC;
2232
2233 typedef union {
2234 SLI2_DESC s2;
2235 } SLI_VAR;
2236
2237 typedef struct {
2238 #ifdef __BIG_ENDIAN_BITFIELD
2239 uint16_t mbxStatus;
2240 uint8_t mbxCommand;
2241 uint8_t mbxReserved:6;
2242 uint8_t mbxHc:1;
2243 uint8_t mbxOwner:1; /* Low order bit first word */
2244 #else /* __LITTLE_ENDIAN_BITFIELD */
2245 uint8_t mbxOwner:1; /* Low order bit first word */
2246 uint8_t mbxHc:1;
2247 uint8_t mbxReserved:6;
2248 uint8_t mbxCommand;
2249 uint16_t mbxStatus;
2250 #endif
2251
2252 MAILVARIANTS un;
2253 SLI_VAR us;
2254 } MAILBOX_t;
2255
2256 /*
2257 * Begin Structure Definitions for IOCB Commands
2258 */
2259
2260 typedef struct {
2261 #ifdef __BIG_ENDIAN_BITFIELD
2262 uint8_t statAction;
2263 uint8_t statRsn;
2264 uint8_t statBaExp;
2265 uint8_t statLocalError;
2266 #else /* __LITTLE_ENDIAN_BITFIELD */
2267 uint8_t statLocalError;
2268 uint8_t statBaExp;
2269 uint8_t statRsn;
2270 uint8_t statAction;
2271 #endif
2272 /* statRsn P/F_RJT reason codes */
2273 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2274 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2275 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2276 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2277 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2278 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2279 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2280 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2281 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2282 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2283 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2284 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2285 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2286 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2287 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2288 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2289 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2290 #define RJT_PROT_ERR 0x12 /* Protocol error */
2291 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2292 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2293 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2294 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2295 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2296 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2297 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2298 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2299
2300 #define IOERR_SUCCESS 0x00 /* statLocalError */
2301 #define IOERR_MISSING_CONTINUE 0x01
2302 #define IOERR_SEQUENCE_TIMEOUT 0x02
2303 #define IOERR_INTERNAL_ERROR 0x03
2304 #define IOERR_INVALID_RPI 0x04
2305 #define IOERR_NO_XRI 0x05
2306 #define IOERR_ILLEGAL_COMMAND 0x06
2307 #define IOERR_XCHG_DROPPED 0x07
2308 #define IOERR_ILLEGAL_FIELD 0x08
2309 #define IOERR_BAD_CONTINUE 0x09
2310 #define IOERR_TOO_MANY_BUFFERS 0x0A
2311 #define IOERR_RCV_BUFFER_WAITING 0x0B
2312 #define IOERR_NO_CONNECTION 0x0C
2313 #define IOERR_TX_DMA_FAILED 0x0D
2314 #define IOERR_RX_DMA_FAILED 0x0E
2315 #define IOERR_ILLEGAL_FRAME 0x0F
2316 #define IOERR_EXTRA_DATA 0x10
2317 #define IOERR_NO_RESOURCES 0x11
2318 #define IOERR_RESERVED 0x12
2319 #define IOERR_ILLEGAL_LENGTH 0x13
2320 #define IOERR_UNSUPPORTED_FEATURE 0x14
2321 #define IOERR_ABORT_IN_PROGRESS 0x15
2322 #define IOERR_ABORT_REQUESTED 0x16
2323 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2324 #define IOERR_LOOP_OPEN_FAILURE 0x18
2325 #define IOERR_RING_RESET 0x19
2326 #define IOERR_LINK_DOWN 0x1A
2327 #define IOERR_CORRUPTED_DATA 0x1B
2328 #define IOERR_CORRUPTED_RPI 0x1C
2329 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2330 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2331 #define IOERR_DUP_FRAME 0x1F
2332 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2333 #define IOERR_BAD_HOST_ADDRESS 0x21
2334 #define IOERR_RCV_HDRBUF_WAITING 0x22
2335 #define IOERR_MISSING_HDR_BUFFER 0x23
2336 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2337 #define IOERR_ABORTMULT_REQUESTED 0x25
2338 #define IOERR_BUFFER_SHORTAGE 0x28
2339 #define IOERR_DEFAULT 0x29
2340 #define IOERR_CNT 0x2A
2341
2342 #define IOERR_DRVR_MASK 0x100
2343 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2344 #define IOERR_SLI_BRESET 0x102
2345 #define IOERR_SLI_ABORTED 0x103
2346 } PARM_ERR;
2347
2348 typedef union {
2349 struct {
2350 #ifdef __BIG_ENDIAN_BITFIELD
2351 uint8_t Rctl; /* R_CTL field */
2352 uint8_t Type; /* TYPE field */
2353 uint8_t Dfctl; /* DF_CTL field */
2354 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2355 #else /* __LITTLE_ENDIAN_BITFIELD */
2356 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2357 uint8_t Dfctl; /* DF_CTL field */
2358 uint8_t Type; /* TYPE field */
2359 uint8_t Rctl; /* R_CTL field */
2360 #endif
2361
2362 #define BC 0x02 /* Broadcast Received - Fctl */
2363 #define SI 0x04 /* Sequence Initiative */
2364 #define LA 0x08 /* Ignore Link Attention state */
2365 #define LS 0x80 /* Last Sequence */
2366 } hcsw;
2367 uint32_t reserved;
2368 } WORD5;
2369
2370 /* IOCB Command template for a generic response */
2371 typedef struct {
2372 uint32_t reserved[4];
2373 PARM_ERR perr;
2374 } GENERIC_RSP;
2375
2376 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2377 typedef struct {
2378 struct ulp_bde xrsqbde[2];
2379 uint32_t xrsqRo; /* Starting Relative Offset */
2380 WORD5 w5; /* Header control/status word */
2381 } XR_SEQ_FIELDS;
2382
2383 /* IOCB Command template for ELS_REQUEST */
2384 typedef struct {
2385 struct ulp_bde elsReq;
2386 struct ulp_bde elsRsp;
2387
2388 #ifdef __BIG_ENDIAN_BITFIELD
2389 uint32_t word4Rsvd:7;
2390 uint32_t fl:1;
2391 uint32_t myID:24;
2392 uint32_t word5Rsvd:8;
2393 uint32_t remoteID:24;
2394 #else /* __LITTLE_ENDIAN_BITFIELD */
2395 uint32_t myID:24;
2396 uint32_t fl:1;
2397 uint32_t word4Rsvd:7;
2398 uint32_t remoteID:24;
2399 uint32_t word5Rsvd:8;
2400 #endif
2401 } ELS_REQUEST;
2402
2403 /* IOCB Command template for RCV_ELS_REQ */
2404 typedef struct {
2405 struct ulp_bde elsReq[2];
2406 uint32_t parmRo;
2407
2408 #ifdef __BIG_ENDIAN_BITFIELD
2409 uint32_t word5Rsvd:8;
2410 uint32_t remoteID:24;
2411 #else /* __LITTLE_ENDIAN_BITFIELD */
2412 uint32_t remoteID:24;
2413 uint32_t word5Rsvd:8;
2414 #endif
2415 } RCV_ELS_REQ;
2416
2417 /* IOCB Command template for ABORT / CLOSE_XRI */
2418 typedef struct {
2419 uint32_t rsvd[3];
2420 uint32_t abortType;
2421 #define ABORT_TYPE_ABTX 0x00000000
2422 #define ABORT_TYPE_ABTS 0x00000001
2423 uint32_t parm;
2424 #ifdef __BIG_ENDIAN_BITFIELD
2425 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2426 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2427 #else /* __LITTLE_ENDIAN_BITFIELD */
2428 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2429 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2430 #endif
2431 } AC_XRI;
2432
2433 /* IOCB Command template for ABORT_MXRI64 */
2434 typedef struct {
2435 uint32_t rsvd[3];
2436 uint32_t abortType;
2437 uint32_t parm;
2438 uint32_t iotag32;
2439 } A_MXRI64;
2440
2441 /* IOCB Command template for GET_RPI */
2442 typedef struct {
2443 uint32_t rsvd[4];
2444 uint32_t parmRo;
2445 #ifdef __BIG_ENDIAN_BITFIELD
2446 uint32_t word5Rsvd:8;
2447 uint32_t remoteID:24;
2448 #else /* __LITTLE_ENDIAN_BITFIELD */
2449 uint32_t remoteID:24;
2450 uint32_t word5Rsvd:8;
2451 #endif
2452 } GET_RPI;
2453
2454 /* IOCB Command template for all FCP Initiator commands */
2455 typedef struct {
2456 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2457 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2458 uint32_t fcpi_parm;
2459 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2460 } FCPI_FIELDS;
2461
2462 /* IOCB Command template for all FCP Target commands */
2463 typedef struct {
2464 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2465 uint32_t fcpt_Offset;
2466 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2467 } FCPT_FIELDS;
2468
2469 /* SLI-2 IOCB structure definitions */
2470
2471 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2472 typedef struct {
2473 ULP_BDL bdl;
2474 uint32_t xrsqRo; /* Starting Relative Offset */
2475 WORD5 w5; /* Header control/status word */
2476 } XMT_SEQ_FIELDS64;
2477
2478 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2479 typedef struct {
2480 struct ulp_bde64 rcvBde;
2481 uint32_t rsvd1;
2482 uint32_t xrsqRo; /* Starting Relative Offset */
2483 WORD5 w5; /* Header control/status word */
2484 } RCV_SEQ_FIELDS64;
2485
2486 /* IOCB Command template for ELS_REQUEST64 */
2487 typedef struct {
2488 ULP_BDL bdl;
2489 #ifdef __BIG_ENDIAN_BITFIELD
2490 uint32_t word4Rsvd:7;
2491 uint32_t fl:1;
2492 uint32_t myID:24;
2493 uint32_t word5Rsvd:8;
2494 uint32_t remoteID:24;
2495 #else /* __LITTLE_ENDIAN_BITFIELD */
2496 uint32_t myID:24;
2497 uint32_t fl:1;
2498 uint32_t word4Rsvd:7;
2499 uint32_t remoteID:24;
2500 uint32_t word5Rsvd:8;
2501 #endif
2502 } ELS_REQUEST64;
2503
2504 /* IOCB Command template for GEN_REQUEST64 */
2505 typedef struct {
2506 ULP_BDL bdl;
2507 uint32_t xrsqRo; /* Starting Relative Offset */
2508 WORD5 w5; /* Header control/status word */
2509 } GEN_REQUEST64;
2510
2511 /* IOCB Command template for RCV_ELS_REQ64 */
2512 typedef struct {
2513 struct ulp_bde64 elsReq;
2514 uint32_t rcvd1;
2515 uint32_t parmRo;
2516
2517 #ifdef __BIG_ENDIAN_BITFIELD
2518 uint32_t word5Rsvd:8;
2519 uint32_t remoteID:24;
2520 #else /* __LITTLE_ENDIAN_BITFIELD */
2521 uint32_t remoteID:24;
2522 uint32_t word5Rsvd:8;
2523 #endif
2524 } RCV_ELS_REQ64;
2525
2526 /* IOCB Command template for all 64 bit FCP Initiator commands */
2527 typedef struct {
2528 ULP_BDL bdl;
2529 uint32_t fcpi_parm;
2530 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2531 } FCPI_FIELDS64;
2532
2533 /* IOCB Command template for all 64 bit FCP Target commands */
2534 typedef struct {
2535 ULP_BDL bdl;
2536 uint32_t fcpt_Offset;
2537 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2538 } FCPT_FIELDS64;
2539
2540 typedef struct _IOCB { /* IOCB structure */
2541 union {
2542 GENERIC_RSP grsp; /* Generic response */
2543 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2544 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2545 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2546 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2547 A_MXRI64 amxri; /* abort multiple xri command overlay */
2548 GET_RPI getrpi; /* GET_RPI template */
2549 FCPI_FIELDS fcpi; /* FCP Initiator template */
2550 FCPT_FIELDS fcpt; /* FCP target template */
2551
2552 /* SLI-2 structures */
2553
2554 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2555 bde_64s */
2556 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2557 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2558 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2559 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2560 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2561 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2562
2563 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
2564 } un;
2565 union {
2566 struct {
2567 #ifdef __BIG_ENDIAN_BITFIELD
2568 uint16_t ulpContext; /* High order bits word 6 */
2569 uint16_t ulpIoTag; /* Low order bits word 6 */
2570 #else /* __LITTLE_ENDIAN_BITFIELD */
2571 uint16_t ulpIoTag; /* Low order bits word 6 */
2572 uint16_t ulpContext; /* High order bits word 6 */
2573 #endif
2574 } t1;
2575 struct {
2576 #ifdef __BIG_ENDIAN_BITFIELD
2577 uint16_t ulpContext; /* High order bits word 6 */
2578 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2579 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2580 #else /* __LITTLE_ENDIAN_BITFIELD */
2581 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2582 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2583 uint16_t ulpContext; /* High order bits word 6 */
2584 #endif
2585 } t2;
2586 } un1;
2587 #define ulpContext un1.t1.ulpContext
2588 #define ulpIoTag un1.t1.ulpIoTag
2589 #define ulpIoTag0 un1.t2.ulpIoTag0
2590
2591 #ifdef __BIG_ENDIAN_BITFIELD
2592 uint32_t ulpTimeout:8;
2593 uint32_t ulpXS:1;
2594 uint32_t ulpFCP2Rcvy:1;
2595 uint32_t ulpPU:2;
2596 uint32_t ulpIr:1;
2597 uint32_t ulpClass:3;
2598 uint32_t ulpCommand:8;
2599 uint32_t ulpStatus:4;
2600 uint32_t ulpBdeCount:2;
2601 uint32_t ulpLe:1;
2602 uint32_t ulpOwner:1; /* Low order bit word 7 */
2603 #else /* __LITTLE_ENDIAN_BITFIELD */
2604 uint32_t ulpOwner:1; /* Low order bit word 7 */
2605 uint32_t ulpLe:1;
2606 uint32_t ulpBdeCount:2;
2607 uint32_t ulpStatus:4;
2608 uint32_t ulpCommand:8;
2609 uint32_t ulpClass:3;
2610 uint32_t ulpIr:1;
2611 uint32_t ulpPU:2;
2612 uint32_t ulpFCP2Rcvy:1;
2613 uint32_t ulpXS:1;
2614 uint32_t ulpTimeout:8;
2615 #endif
2616
2617 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
2618 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2619 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
2620 #define CLASS1 0 /* Class 1 */
2621 #define CLASS2 1 /* Class 2 */
2622 #define CLASS3 2 /* Class 3 */
2623 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
2624
2625 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
2626 #define IOSTAT_FCP_RSP_ERROR 0x1
2627 #define IOSTAT_REMOTE_STOP 0x2
2628 #define IOSTAT_LOCAL_REJECT 0x3
2629 #define IOSTAT_NPORT_RJT 0x4
2630 #define IOSTAT_FABRIC_RJT 0x5
2631 #define IOSTAT_NPORT_BSY 0x6
2632 #define IOSTAT_FABRIC_BSY 0x7
2633 #define IOSTAT_INTERMED_RSP 0x8
2634 #define IOSTAT_LS_RJT 0x9
2635 #define IOSTAT_BA_RJT 0xA
2636 #define IOSTAT_RSVD1 0xB
2637 #define IOSTAT_RSVD2 0xC
2638 #define IOSTAT_RSVD3 0xD
2639 #define IOSTAT_RSVD4 0xE
2640 #define IOSTAT_RSVD5 0xF
2641 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2642 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2643 #define IOSTAT_CNT 0x11
2644
2645 } IOCB_t;
2646
2647
2648 #define SLI1_SLIM_SIZE (4 * 1024)
2649
2650 /* Up to 498 IOCBs will fit into 16k
2651 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2652 */
2653 #define SLI2_SLIM_SIZE (16 * 1024)
2654
2655 /* Maximum IOCBs that will fit in SLI2 slim */
2656 #define MAX_SLI2_IOCB 498
2657
2658 struct lpfc_sli2_slim {
2659 MAILBOX_t mbx;
2660 PCB_t pcb;
2661 IOCB_t IOCBs[MAX_SLI2_IOCB];
2662 };
2663
2664 /*******************************************************************
2665 This macro check PCI device to allow special handling for LC HBAs.
2666
2667 Parameters:
2668 device : struct pci_dev 's device field
2669
2670 return 1 => TRUE
2671 0 => FALSE
2672 *******************************************************************/
2673 static inline int
2674 lpfc_is_LC_HBA(unsigned short device)
2675 {
2676 if ((device == PCI_DEVICE_ID_TFLY) ||
2677 (device == PCI_DEVICE_ID_PFLY) ||
2678 (device == PCI_DEVICE_ID_LP101) ||
2679 (device == PCI_DEVICE_ID_BMID) ||
2680 (device == PCI_DEVICE_ID_BSMB) ||
2681 (device == PCI_DEVICE_ID_ZMID) ||
2682 (device == PCI_DEVICE_ID_ZSMB) ||
2683 (device == PCI_DEVICE_ID_RFLY))
2684 return 1;
2685 else
2686 return 0;
2687 }
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