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[PATCH] ppc32: Fix address checking on lmw/stmw align exception
[linux-2.6/verdex.git] / drivers / scsi / sata_sil.c
blobf0489dc302a03054d6461ba54c9705f30190a8f4
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 * The contents of this file are subject to the Open
12 * Software License version 1.1 that can be found at
13 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
14 * by reference.
15 *
16 * Alternatively, the contents of this file may be used under the terms
17 * of the GNU General Public License version 2 (the "GPL") as distributed
18 * in the kernel source COPYING file, in which case the provisions of
19 * the GPL are applicable instead of the above. If you wish to allow
20 * the use of your version of this file only under the terms of the
21 * GPL and not to allow others to use your version of this file under
22 * the OSL, indicate your decision by deleting the provisions above and
23 * replace them with the notice and other provisions required by the GPL.
24 * If you do not delete the provisions above, a recipient may use your
25 * version of this file under either the OSL or the GPL.
26 *
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include "scsi.h"
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
39
40 #define DRV_NAME "sata_sil"
41 #define DRV_VERSION "0.9"
42
43 enum {
44 sil_3112 = 0,
45 sil_3114 = 1,
46
47 SIL_FIFO_R0 = 0x40,
48 SIL_FIFO_W0 = 0x41,
49 SIL_FIFO_R1 = 0x44,
50 SIL_FIFO_W1 = 0x45,
51 SIL_FIFO_R2 = 0x240,
52 SIL_FIFO_W2 = 0x241,
53 SIL_FIFO_R3 = 0x244,
54 SIL_FIFO_W3 = 0x245,
55
56 SIL_SYSCFG = 0x48,
57 SIL_MASK_IDE0_INT = (1 << 22),
58 SIL_MASK_IDE1_INT = (1 << 23),
59 SIL_MASK_IDE2_INT = (1 << 24),
60 SIL_MASK_IDE3_INT = (1 << 25),
61 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
62 SIL_MASK_4PORT = SIL_MASK_2PORT |
63 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
64
65 SIL_IDE2_BMDMA = 0x200,
66
67 SIL_INTR_STEERING = (1 << 1),
68 SIL_QUIRK_MOD15WRITE = (1 << 0),
69 SIL_QUIRK_UDMA5MAX = (1 << 1),
70 };
71
72 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
73 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
74 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
75 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76 static void sil_post_set_mode (struct ata_port *ap);
77
78 static struct pci_device_id sil_pci_tbl[] = {
79 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
80 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
81 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
82 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
83 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
84 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
85 { } /* terminate list */
86 };
87
88
89 /* TODO firmware versions should be added - eric */
90 static const struct sil_drivelist {
91 const char * product;
92 unsigned int quirk;
93 } sil_blacklist [] = {
94 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
95 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
96 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
97 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
98 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
99 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
100 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
101 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
102 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
103 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
104 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
105 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
106 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
107 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
108 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
109 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
110 { }
111 };
112
113 static struct pci_driver sil_pci_driver = {
114 .name = DRV_NAME,
115 .id_table = sil_pci_tbl,
116 .probe = sil_init_one,
117 .remove = ata_pci_remove_one,
118 };
119
120 static Scsi_Host_Template sil_sht = {
121 .module = THIS_MODULE,
122 .name = DRV_NAME,
123 .ioctl = ata_scsi_ioctl,
124 .queuecommand = ata_scsi_queuecmd,
125 .eh_strategy_handler = ata_scsi_error,
126 .can_queue = ATA_DEF_QUEUE,
127 .this_id = ATA_SHT_THIS_ID,
128 .sg_tablesize = LIBATA_MAX_PRD,
129 .max_sectors = ATA_MAX_SECTORS,
130 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
131 .emulated = ATA_SHT_EMULATED,
132 .use_clustering = ATA_SHT_USE_CLUSTERING,
133 .proc_name = DRV_NAME,
134 .dma_boundary = ATA_DMA_BOUNDARY,
135 .slave_configure = ata_scsi_slave_config,
136 .bios_param = ata_std_bios_param,
137 .ordered_flush = 1,
138 };
139
140 static struct ata_port_operations sil_ops = {
141 .port_disable = ata_port_disable,
142 .dev_config = sil_dev_config,
143 .tf_load = ata_tf_load,
144 .tf_read = ata_tf_read,
145 .check_status = ata_check_status,
146 .exec_command = ata_exec_command,
147 .dev_select = ata_std_dev_select,
148 .phy_reset = sata_phy_reset,
149 .post_set_mode = sil_post_set_mode,
150 .bmdma_setup = ata_bmdma_setup,
151 .bmdma_start = ata_bmdma_start,
152 .bmdma_stop = ata_bmdma_stop,
153 .bmdma_status = ata_bmdma_status,
154 .qc_prep = ata_qc_prep,
155 .qc_issue = ata_qc_issue_prot,
156 .eng_timeout = ata_eng_timeout,
157 .irq_handler = ata_interrupt,
158 .irq_clear = ata_bmdma_irq_clear,
159 .scr_read = sil_scr_read,
160 .scr_write = sil_scr_write,
161 .port_start = ata_port_start,
162 .port_stop = ata_port_stop,
163 };
164
165 static struct ata_port_info sil_port_info[] = {
166 /* sil_3112 */
167 {
168 .sht = &sil_sht,
169 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
170 ATA_FLAG_SRST | ATA_FLAG_MMIO,
171 .pio_mask = 0x1f, /* pio0-4 */
172 .mwdma_mask = 0x07, /* mwdma0-2 */
173 .udma_mask = 0x3f, /* udma0-5 */
174 .port_ops = &sil_ops,
175 }, /* sil_3114 */
176 {
177 .sht = &sil_sht,
178 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_SRST | ATA_FLAG_MMIO,
180 .pio_mask = 0x1f, /* pio0-4 */
181 .mwdma_mask = 0x07, /* mwdma0-2 */
182 .udma_mask = 0x3f, /* udma0-5 */
183 .port_ops = &sil_ops,
184 },
185 };
186
187 /* per-port register offsets */
188 /* TODO: we can probably calculate rather than use a table */
189 static const struct {
190 unsigned long tf; /* ATA taskfile register block */
191 unsigned long ctl; /* ATA control/altstatus register block */
192 unsigned long bmdma; /* DMA register block */
193 unsigned long scr; /* SATA control register block */
194 unsigned long sien; /* SATA Interrupt Enable register */
195 unsigned long xfer_mode;/* data transfer mode register */
196 } sil_port[] = {
197 /* port 0 ... */
198 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
199 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
200 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
201 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
202 /* ... port 3 */
203 };
204
205 MODULE_AUTHOR("Jeff Garzik");
206 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
207 MODULE_LICENSE("GPL");
208 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
209 MODULE_VERSION(DRV_VERSION);
210
211 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
212 {
213 u8 cache_line = 0;
214 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
215 return cache_line;
216 }
217
218 static void sil_post_set_mode (struct ata_port *ap)
219 {
220 struct ata_host_set *host_set = ap->host_set;
221 struct ata_device *dev;
222 void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
223 u32 tmp, dev_mode[2];
224 unsigned int i;
225
226 for (i = 0; i < 2; i++) {
227 dev = &ap->device[i];
228 if (!ata_dev_present(dev))
229 dev_mode[i] = 0; /* PIO0/1/2 */
230 else if (dev->flags & ATA_DFLAG_PIO)
231 dev_mode[i] = 1; /* PIO3/4 */
232 else
233 dev_mode[i] = 3; /* UDMA */
234 /* value 2 indicates MDMA */
235 }
236
237 tmp = readl(addr);
238 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
239 tmp |= dev_mode[0];
240 tmp |= (dev_mode[1] << 4);
241 writel(tmp, addr);
242 readl(addr); /* flush */
243 }
244
245 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
246 {
247 unsigned long offset = ap->ioaddr.scr_addr;
248
249 switch (sc_reg) {
250 case SCR_STATUS:
251 return offset + 4;
252 case SCR_ERROR:
253 return offset + 8;
254 case SCR_CONTROL:
255 return offset;
256 default:
257 /* do nothing */
258 break;
259 }
260
261 return 0;
262 }
263
264 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
265 {
266 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
267 if (mmio)
268 return readl(mmio);
269 return 0xffffffffU;
270 }
271
272 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
273 {
274 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
275 if (mmio)
276 writel(val, mmio);
277 }
278
279 /**
280 * sil_dev_config - Apply device/host-specific errata fixups
281 * @ap: Port containing device to be examined
282 * @dev: Device to be examined
283 *
284 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
285 * device is known to be present, this function is called.
286 * We apply two errata fixups which are specific to Silicon Image,
287 * a Seagate and a Maxtor fixup.
288 *
289 * For certain Seagate devices, we must limit the maximum sectors
290 * to under 8K.
291 *
292 * For certain Maxtor devices, we must not program the drive
293 * beyond udma5.
294 *
295 * Both fixups are unfairly pessimistic. As soon as I get more
296 * information on these errata, I will create a more exhaustive
297 * list, and apply the fixups to only the specific
298 * devices/hosts/firmwares that need it.
299 *
300 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
301 * The Maxtor quirk is in the blacklist, but I'm keeping the original
302 * pessimistic fix for the following reasons...
303 * - There seems to be less info on it, only one device gleaned off the
304 * Windows driver, maybe only one is affected. More info would be greatly
305 * appreciated.
306 * - But then again UDMA5 is hardly anything to complain about
307 */
308 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
309 {
310 unsigned int n, quirks = 0;
311 unsigned char model_num[40];
312 const char *s;
313 unsigned int len;
314
315 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
316 sizeof(model_num));
317 s = &model_num[0];
318 len = strnlen(s, sizeof(model_num));
319
320 /* ATAPI specifies that empty space is blank-filled; remove blanks */
321 while ((len > 0) && (s[len - 1] == ' '))
322 len--;
323
324 for (n = 0; sil_blacklist[n].product; n++)
325 if (!memcmp(sil_blacklist[n].product, s,
326 strlen(sil_blacklist[n].product))) {
327 quirks = sil_blacklist[n].quirk;
328 break;
329 }
330
331 /* limit requests to 15 sectors */
332 if (quirks & SIL_QUIRK_MOD15WRITE) {
333 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
334 ap->id, dev->devno);
335 ap->host->max_sectors = 15;
336 ap->host->hostt->max_sectors = 15;
337 dev->flags |= ATA_DFLAG_LOCK_SECTORS;
338 return;
339 }
340
341 /* limit to udma5 */
342 if (quirks & SIL_QUIRK_UDMA5MAX) {
343 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
344 ap->id, dev->devno, s);
345 ap->udma_mask &= ATA_UDMA5;
346 return;
347 }
348 }
349
350 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
351 {
352 static int printed_version;
353 struct ata_probe_ent *probe_ent = NULL;
354 unsigned long base;
355 void *mmio_base;
356 int rc;
357 unsigned int i;
358 int pci_dev_busy = 0;
359 u32 tmp, irq_mask;
360 u8 cls;
361
362 if (!printed_version++)
363 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
364
365 /*
366 * If this driver happens to only be useful on Apple's K2, then
367 * we should check that here as it has a normal Serverworks ID
368 */
369 rc = pci_enable_device(pdev);
370 if (rc)
371 return rc;
372
373 rc = pci_request_regions(pdev, DRV_NAME);
374 if (rc) {
375 pci_dev_busy = 1;
376 goto err_out;
377 }
378
379 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
380 if (rc)
381 goto err_out_regions;
382 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
383 if (rc)
384 goto err_out_regions;
385
386 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
387 if (probe_ent == NULL) {
388 rc = -ENOMEM;
389 goto err_out_regions;
390 }
391
392 memset(probe_ent, 0, sizeof(*probe_ent));
393 INIT_LIST_HEAD(&probe_ent->node);
394 probe_ent->dev = pci_dev_to_dev(pdev);
395 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
396 probe_ent->sht = sil_port_info[ent->driver_data].sht;
397 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
398 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
399 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
400 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
401 probe_ent->irq = pdev->irq;
402 probe_ent->irq_flags = SA_SHIRQ;
403 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
404
405 mmio_base = ioremap(pci_resource_start(pdev, 5),
406 pci_resource_len(pdev, 5));
407 if (mmio_base == NULL) {
408 rc = -ENOMEM;
409 goto err_out_free_ent;
410 }
411
412 probe_ent->mmio_base = mmio_base;
413
414 base = (unsigned long) mmio_base;
415
416 for (i = 0; i < probe_ent->n_ports; i++) {
417 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
418 probe_ent->port[i].altstatus_addr =
419 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
420 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
421 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
422 ata_std_ports(&probe_ent->port[i]);
423 }
424
425 /* Initialize FIFO PCI bus arbitration */
426 cls = sil_get_device_cache_line(pdev);
427 if (cls) {
428 cls >>= 3;
429 cls++; /* cls = (line_size/8)+1 */
430 writeb(cls, mmio_base + SIL_FIFO_R0);
431 writeb(cls, mmio_base + SIL_FIFO_W0);
432 writeb(cls, mmio_base + SIL_FIFO_R1);
433 writeb(cls, mmio_base + SIL_FIFO_W2);
434 } else
435 printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
436 pci_name(pdev));
437
438 if (ent->driver_data == sil_3114) {
439 irq_mask = SIL_MASK_4PORT;
440
441 /* flip the magic "make 4 ports work" bit */
442 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
443 if ((tmp & SIL_INTR_STEERING) == 0)
444 writel(tmp | SIL_INTR_STEERING,
445 mmio_base + SIL_IDE2_BMDMA);
446
447 } else {
448 irq_mask = SIL_MASK_2PORT;
449 }
450
451 /* make sure IDE0/1/2/3 interrupts are not masked */
452 tmp = readl(mmio_base + SIL_SYSCFG);
453 if (tmp & irq_mask) {
454 tmp &= ~irq_mask;
455 writel(tmp, mmio_base + SIL_SYSCFG);
456 readl(mmio_base + SIL_SYSCFG); /* flush */
457 }
458
459 /* mask all SATA phy-related interrupts */
460 /* TODO: unmask bit 6 (SError N bit) for hotplug */
461 for (i = 0; i < probe_ent->n_ports; i++)
462 writel(0, mmio_base + sil_port[i].sien);
463
464 pci_set_master(pdev);
465
466 /* FIXME: check ata_device_add return value */
467 ata_device_add(probe_ent);
468 kfree(probe_ent);
469
470 return 0;
471
472 err_out_free_ent:
473 kfree(probe_ent);
474 err_out_regions:
475 pci_release_regions(pdev);
476 err_out:
477 if (!pci_dev_busy)
478 pci_disable_device(pdev);
479 return rc;
480 }
481
482 static int __init sil_init(void)
483 {
484 return pci_module_init(&sil_pci_driver);
485 }
486
487 static void __exit sil_exit(void)
488 {
489 pci_unregister_driver(&sil_pci_driver);
490 }
491
492
493 module_init(sil_init);
494 module_exit(sil_exit);
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