2 * sata_svw.c - ServerWorks / Apple K2 SATA
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This driver probably works with non-Apple versions of the
16 * The contents of this file are subject to the Open
17 * Software License version 1.1 that can be found at
18 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
21 * Alternatively, the contents of this file may be used under the terms
22 * of the GNU General Public License version 2 (the "GPL") as distributed
23 * in the kernel source COPYING file, in which case the provisions of
24 * the GPL are applicable instead of the above. If you wish to allow
25 * the use of your version of this file only under the terms of the
26 * GPL and not to allow others to use your version of this file under
27 * the OSL, indicate your decision by deleting the provisions above and
28 * replace them with the notice and other provisions required by the GPL.
29 * If you do not delete the provisions above, a recipient may use your
30 * version of this file under either the OSL or the GPL.
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
48 #include <asm/pci-bridge.h>
49 #endif /* CONFIG_PPC_OF */
51 #define DRV_NAME "sata_svw"
52 #define DRV_VERSION "1.05"
54 /* Taskfile registers offsets */
55 #define K2_SATA_TF_CMD_OFFSET 0x00
56 #define K2_SATA_TF_DATA_OFFSET 0x00
57 #define K2_SATA_TF_ERROR_OFFSET 0x04
58 #define K2_SATA_TF_NSECT_OFFSET 0x08
59 #define K2_SATA_TF_LBAL_OFFSET 0x0c
60 #define K2_SATA_TF_LBAM_OFFSET 0x10
61 #define K2_SATA_TF_LBAH_OFFSET 0x14
62 #define K2_SATA_TF_DEVICE_OFFSET 0x18
63 #define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
64 #define K2_SATA_TF_CTL_OFFSET 0x20
67 #define K2_SATA_DMA_CMD_OFFSET 0x30
70 #define K2_SATA_SCR_STATUS_OFFSET 0x40
71 #define K2_SATA_SCR_ERROR_OFFSET 0x44
72 #define K2_SATA_SCR_CONTROL_OFFSET 0x48
75 #define K2_SATA_SICR1_OFFSET 0x80
76 #define K2_SATA_SICR2_OFFSET 0x84
77 #define K2_SATA_SIM_OFFSET 0x88
80 #define K2_SATA_PORT_OFFSET 0x100
83 static u32
k2_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
85 if (sc_reg
> SCR_CONTROL
)
87 return readl((void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
91 static void k2_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
,
94 if (sc_reg
> SCR_CONTROL
)
96 writel(val
, (void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
100 static void k2_sata_tf_load(struct ata_port
*ap
, struct ata_taskfile
*tf
)
102 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
103 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
105 if (tf
->ctl
!= ap
->last_ctl
) {
106 writeb(tf
->ctl
, ioaddr
->ctl_addr
);
107 ap
->last_ctl
= tf
->ctl
;
110 if (is_addr
&& (tf
->flags
& ATA_TFLAG_LBA48
)) {
111 writew(tf
->feature
| (((u16
)tf
->hob_feature
) << 8), ioaddr
->feature_addr
);
112 writew(tf
->nsect
| (((u16
)tf
->hob_nsect
) << 8), ioaddr
->nsect_addr
);
113 writew(tf
->lbal
| (((u16
)tf
->hob_lbal
) << 8), ioaddr
->lbal_addr
);
114 writew(tf
->lbam
| (((u16
)tf
->hob_lbam
) << 8), ioaddr
->lbam_addr
);
115 writew(tf
->lbah
| (((u16
)tf
->hob_lbah
) << 8), ioaddr
->lbah_addr
);
116 } else if (is_addr
) {
117 writew(tf
->feature
, ioaddr
->feature_addr
);
118 writew(tf
->nsect
, ioaddr
->nsect_addr
);
119 writew(tf
->lbal
, ioaddr
->lbal_addr
);
120 writew(tf
->lbam
, ioaddr
->lbam_addr
);
121 writew(tf
->lbah
, ioaddr
->lbah_addr
);
124 if (tf
->flags
& ATA_TFLAG_DEVICE
)
125 writeb(tf
->device
, ioaddr
->device_addr
);
131 static void k2_sata_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
133 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
134 u16 nsect
, lbal
, lbam
, lbah
;
136 nsect
= tf
->nsect
= readw(ioaddr
->nsect_addr
);
137 lbal
= tf
->lbal
= readw(ioaddr
->lbal_addr
);
138 lbam
= tf
->lbam
= readw(ioaddr
->lbam_addr
);
139 lbah
= tf
->lbah
= readw(ioaddr
->lbah_addr
);
140 tf
->device
= readw(ioaddr
->device_addr
);
142 if (tf
->flags
& ATA_TFLAG_LBA48
) {
143 tf
->hob_feature
= readw(ioaddr
->error_addr
) >> 8;
144 tf
->hob_nsect
= nsect
>> 8;
145 tf
->hob_lbal
= lbal
>> 8;
146 tf
->hob_lbam
= lbam
>> 8;
147 tf
->hob_lbah
= lbah
>> 8;
152 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
153 * @qc: Info associated with this ATA transaction.
156 * spin_lock_irqsave(host_set lock)
159 static void k2_bmdma_setup_mmio (struct ata_queued_cmd
*qc
)
161 struct ata_port
*ap
= qc
->ap
;
162 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
164 void *mmio
= (void *) ap
->ioaddr
.bmdma_addr
;
165 /* load PRD table addr. */
166 mb(); /* make sure PRD table writes are visible to controller */
167 writel(ap
->prd_dma
, mmio
+ ATA_DMA_TABLE_OFS
);
169 /* specify data direction, triple-check start bit is clear */
170 dmactl
= readb(mmio
+ ATA_DMA_CMD
);
171 dmactl
&= ~(ATA_DMA_WR
| ATA_DMA_START
);
173 dmactl
|= ATA_DMA_WR
;
174 writeb(dmactl
, mmio
+ ATA_DMA_CMD
);
176 /* issue r/w command if this is not a ATA DMA command*/
177 if (qc
->tf
.protocol
!= ATA_PROT_DMA
)
178 ap
->ops
->exec_command(ap
, &qc
->tf
);
182 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
183 * @qc: Info associated with this ATA transaction.
186 * spin_lock_irqsave(host_set lock)
189 static void k2_bmdma_start_mmio (struct ata_queued_cmd
*qc
)
191 struct ata_port
*ap
= qc
->ap
;
192 void *mmio
= (void *) ap
->ioaddr
.bmdma_addr
;
195 /* start host DMA transaction */
196 dmactl
= readb(mmio
+ ATA_DMA_CMD
);
197 writeb(dmactl
| ATA_DMA_START
, mmio
+ ATA_DMA_CMD
);
198 /* There is a race condition in certain SATA controllers that can
199 be seen when the r/w command is given to the controller before the
200 host DMA is started. On a Read command, the controller would initiate
201 the command to the drive even before it sees the DMA start. When there
202 are very fast drives connected to the controller, or when the data request
203 hits in the drive cache, there is the possibility that the drive returns a part
204 or all of the requested data to the controller before the DMA start is issued.
205 In this case, the controller would become confused as to what to do with the data.
206 In the worst case when all the data is returned back to the controller, the
207 controller could hang. In other cases it could return partial data returning
208 in data corruption. This problem has been seen in PPC systems and can also appear
209 on an system with very fast disks, where the SATA controller is sitting behind a
210 number of bridges, and hence there is significant latency between the r/w command
211 and the start command. */
212 /* issue r/w command if the access is to ATA*/
213 if (qc
->tf
.protocol
== ATA_PROT_DMA
)
214 ap
->ops
->exec_command(ap
, &qc
->tf
);
218 static u8
k2_stat_check_status(struct ata_port
*ap
)
220 return readl((void *) ap
->ioaddr
.status_addr
);
226 * inout : decides on the direction of the dataflow and the meaning of the
228 * buffer: If inout==FALSE data is being written to it else read from it
229 * *start: If inout==FALSE start of the valid data in the buffer
230 * offset: If inout==FALSE offset from the beginning of the imaginary file
231 * from which we start writing into the buffer
232 * length: If inout==FALSE max number of bytes to be written into the buffer
233 * else number of bytes in the buffer
235 static int k2_sata_proc_info(struct Scsi_Host
*shost
, char *page
, char **start
,
236 off_t offset
, int count
, int inout
)
239 struct device_node
*np
;
242 /* Find the ata_port */
243 ap
= (struct ata_port
*) &shost
->hostdata
[0];
247 /* Find the OF node for the PCI device proper */
248 np
= pci_device_to_OF_node(to_pci_dev(ap
->host_set
->dev
));
252 /* Match it to a port node */
253 index
= (ap
== ap
->host_set
->ports
[0]) ? 0 : 1;
254 for (np
= np
->child
; np
!= NULL
; np
= np
->sibling
) {
255 u32
*reg
= (u32
*)get_property(np
, "reg", NULL
);
264 len
= sprintf(page
, "devspec: %s\n", np
->full_name
);
268 #endif /* CONFIG_PPC_OF */
271 static Scsi_Host_Template k2_sata_sht
= {
272 .module
= THIS_MODULE
,
274 .ioctl
= ata_scsi_ioctl
,
275 .queuecommand
= ata_scsi_queuecmd
,
276 .eh_strategy_handler
= ata_scsi_error
,
277 .can_queue
= ATA_DEF_QUEUE
,
278 .this_id
= ATA_SHT_THIS_ID
,
279 .sg_tablesize
= LIBATA_MAX_PRD
,
280 .max_sectors
= ATA_MAX_SECTORS
,
281 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
282 .emulated
= ATA_SHT_EMULATED
,
283 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
284 .proc_name
= DRV_NAME
,
285 .dma_boundary
= ATA_DMA_BOUNDARY
,
286 .slave_configure
= ata_scsi_slave_config
,
288 .proc_info
= k2_sata_proc_info
,
290 .bios_param
= ata_std_bios_param
,
295 static struct ata_port_operations k2_sata_ops
= {
296 .port_disable
= ata_port_disable
,
297 .tf_load
= k2_sata_tf_load
,
298 .tf_read
= k2_sata_tf_read
,
299 .check_status
= k2_stat_check_status
,
300 .exec_command
= ata_exec_command
,
301 .dev_select
= ata_std_dev_select
,
302 .phy_reset
= sata_phy_reset
,
303 .bmdma_setup
= k2_bmdma_setup_mmio
,
304 .bmdma_start
= k2_bmdma_start_mmio
,
305 .bmdma_stop
= ata_bmdma_stop
,
306 .bmdma_status
= ata_bmdma_status
,
307 .qc_prep
= ata_qc_prep
,
308 .qc_issue
= ata_qc_issue_prot
,
309 .eng_timeout
= ata_eng_timeout
,
310 .irq_handler
= ata_interrupt
,
311 .irq_clear
= ata_bmdma_irq_clear
,
312 .scr_read
= k2_sata_scr_read
,
313 .scr_write
= k2_sata_scr_write
,
314 .port_start
= ata_port_start
,
315 .port_stop
= ata_port_stop
,
318 static void k2_sata_setup_port(struct ata_ioports
*port
, unsigned long base
)
320 port
->cmd_addr
= base
+ K2_SATA_TF_CMD_OFFSET
;
321 port
->data_addr
= base
+ K2_SATA_TF_DATA_OFFSET
;
323 port
->error_addr
= base
+ K2_SATA_TF_ERROR_OFFSET
;
324 port
->nsect_addr
= base
+ K2_SATA_TF_NSECT_OFFSET
;
325 port
->lbal_addr
= base
+ K2_SATA_TF_LBAL_OFFSET
;
326 port
->lbam_addr
= base
+ K2_SATA_TF_LBAM_OFFSET
;
327 port
->lbah_addr
= base
+ K2_SATA_TF_LBAH_OFFSET
;
328 port
->device_addr
= base
+ K2_SATA_TF_DEVICE_OFFSET
;
330 port
->status_addr
= base
+ K2_SATA_TF_CMDSTAT_OFFSET
;
331 port
->altstatus_addr
=
332 port
->ctl_addr
= base
+ K2_SATA_TF_CTL_OFFSET
;
333 port
->bmdma_addr
= base
+ K2_SATA_DMA_CMD_OFFSET
;
334 port
->scr_addr
= base
+ K2_SATA_SCR_STATUS_OFFSET
;
338 static int k2_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
340 static int printed_version
;
341 struct ata_probe_ent
*probe_ent
= NULL
;
344 int pci_dev_busy
= 0;
347 if (!printed_version
++)
348 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
351 * If this driver happens to only be useful on Apple's K2, then
352 * we should check that here as it has a normal Serverworks ID
354 rc
= pci_enable_device(pdev
);
358 * Check if we have resources mapped at all (second function may
359 * have been disabled by firmware)
361 if (pci_resource_len(pdev
, 5) == 0)
364 /* Request PCI regions */
365 rc
= pci_request_regions(pdev
, DRV_NAME
);
371 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
373 goto err_out_regions
;
374 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
376 goto err_out_regions
;
378 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
379 if (probe_ent
== NULL
) {
381 goto err_out_regions
;
384 memset(probe_ent
, 0, sizeof(*probe_ent
));
385 probe_ent
->dev
= pci_dev_to_dev(pdev
);
386 INIT_LIST_HEAD(&probe_ent
->node
);
388 mmio_base
= ioremap(pci_resource_start(pdev
, 5),
389 pci_resource_len(pdev
, 5));
390 if (mmio_base
== NULL
) {
392 goto err_out_free_ent
;
394 base
= (unsigned long) mmio_base
;
396 /* Clear a magic bit in SCR1 according to Darwin, those help
397 * some funky seagate drives (though so far, those were already
398 * set by the firmware on the machines I had access to
400 writel(readl(mmio_base
+ K2_SATA_SICR1_OFFSET
) & ~0x00040000,
401 mmio_base
+ K2_SATA_SICR1_OFFSET
);
403 /* Clear SATA error & interrupts we don't use */
404 writel(0xffffffff, mmio_base
+ K2_SATA_SCR_ERROR_OFFSET
);
405 writel(0x0, mmio_base
+ K2_SATA_SIM_OFFSET
);
407 probe_ent
->sht
= &k2_sata_sht
;
408 probe_ent
->host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SATA_RESET
|
409 ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
;
410 probe_ent
->port_ops
= &k2_sata_ops
;
411 probe_ent
->n_ports
= 4;
412 probe_ent
->irq
= pdev
->irq
;
413 probe_ent
->irq_flags
= SA_SHIRQ
;
414 probe_ent
->mmio_base
= mmio_base
;
416 /* We don't care much about the PIO/UDMA masks, but the core won't like us
417 * if we don't fill these
419 probe_ent
->pio_mask
= 0x1f;
420 probe_ent
->mwdma_mask
= 0x7;
421 probe_ent
->udma_mask
= 0x7f;
423 /* We have 4 ports per PCI function */
424 k2_sata_setup_port(&probe_ent
->port
[0], base
+ 0 * K2_SATA_PORT_OFFSET
);
425 k2_sata_setup_port(&probe_ent
->port
[1], base
+ 1 * K2_SATA_PORT_OFFSET
);
426 k2_sata_setup_port(&probe_ent
->port
[2], base
+ 2 * K2_SATA_PORT_OFFSET
);
427 k2_sata_setup_port(&probe_ent
->port
[3], base
+ 3 * K2_SATA_PORT_OFFSET
);
429 pci_set_master(pdev
);
431 /* FIXME: check ata_device_add return value */
432 ata_device_add(probe_ent
);
440 pci_release_regions(pdev
);
443 pci_disable_device(pdev
);
448 static struct pci_device_id k2_sata_pci_tbl
[] = {
449 { 0x1166, 0x0240, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
450 { 0x1166, 0x0241, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
451 { 0x1166, 0x0242, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
456 static struct pci_driver k2_sata_pci_driver
= {
458 .id_table
= k2_sata_pci_tbl
,
459 .probe
= k2_sata_init_one
,
460 .remove
= ata_pci_remove_one
,
464 static int __init
k2_sata_init(void)
466 return pci_module_init(&k2_sata_pci_driver
);
470 static void __exit
k2_sata_exit(void)
472 pci_unregister_driver(&k2_sata_pci_driver
);
476 MODULE_AUTHOR("Benjamin Herrenschmidt");
477 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
478 MODULE_LICENSE("GPL");
479 MODULE_DEVICE_TABLE(pci
, k2_sata_pci_tbl
);
480 MODULE_VERSION(DRV_VERSION
);
482 module_init(k2_sata_init
);
483 module_exit(k2_sata_exit
);