drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 /*
   8  * Driver debug definitions.
   9  */
  10 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  11 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  12 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  13 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  14 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  15 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  16 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  17 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  18 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  19 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  20 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  21 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  22 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  23 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  24 /*
  25  *  Local Macro Definitions.
  26  */
  27 #if defined(QL_DEBUG_LEVEL_1)  || defined(QL_DEBUG_LEVEL_2) || \
  28     defined(QL_DEBUG_LEVEL_3)  || defined(QL_DEBUG_LEVEL_4) || \
  29     defined(QL_DEBUG_LEVEL_5)  || defined(QL_DEBUG_LEVEL_6) || \
  30     defined(QL_DEBUG_LEVEL_7)  || defined(QL_DEBUG_LEVEL_8) || \
  31     defined(QL_DEBUG_LEVEL_9)  || defined(QL_DEBUG_LEVEL_10) || \
  32     defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
  33     defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14)
  34     #define QL_DEBUG_ROUTINES
  35 #endif
  36
  37 /*
  38 * Macros use for debugging the driver.
  39 */
  40 #undef ENTER_TRACE
  41 #if defined(ENTER_TRACE)
  42 #define ENTER(x)        do { printk("qla2100 : Entering %s()\n", x); } while (0)
  43 #define LEAVE(x)        do { printk("qla2100 : Leaving %s()\n", x);  } while (0)
  44 #define ENTER_INTR(x)   do { printk("qla2100 : Entering %s()\n", x); } while (0)
  45 #define LEAVE_INTR(x)   do { printk("qla2100 : Leaving %s()\n", x);  } while (0)
  46 #else
  47 #define ENTER(x)        do {} while (0)
  48 #define LEAVE(x)        do {} while (0)
  49 #define ENTER_INTR(x)   do {} while (0)
  50 #define LEAVE_INTR(x)   do {} while (0)
  51 #endif
  52
  53 #if  DEBUG_QLA2100
  54 #define DEBUG(x)        do {x;} while (0);
  55 #else
  56 #define DEBUG(x)        do {} while (0);
  57 #endif
  58
  59 #if defined(QL_DEBUG_LEVEL_1)
  60 #define DEBUG1(x)       do {x;} while (0);
  61 #else
  62 #define DEBUG1(x)       do {} while (0);
  63 #endif
  64
  65 #if defined(QL_DEBUG_LEVEL_2)
  66 #define DEBUG2(x)       do {x;} while (0);
  67 #define DEBUG2_3(x)     do {x;} while (0);
  68 #define DEBUG2_3_11(x)  do {x;} while (0);
  69 #define DEBUG2_9_10(x)    do {x;} while (0);
  70 #define DEBUG2_11(x)    do {x;} while (0);
  71 #define DEBUG2_13(x)    do {x;} while (0);
  72 #else
  73 #define DEBUG2(x)       do {} while (0);
  74 #endif
  75
  76 #if defined(QL_DEBUG_LEVEL_3)
  77 #define DEBUG3(x)       do {x;} while (0);
  78 #define DEBUG2_3(x)     do {x;} while (0);
  79 #define DEBUG2_3_11(x)  do {x;} while (0);
  80 #define DEBUG3_11(x)    do {x;} while (0);
  81 #else
  82 #define DEBUG3(x)       do {} while (0);
  83   #if !defined(QL_DEBUG_LEVEL_2)
  84   #define DEBUG2_3(x)   do {} while (0);
  85   #endif
  86 #endif
  87
  88 #if defined(QL_DEBUG_LEVEL_4)
  89 #define DEBUG4(x)       do {x;} while (0);
  90 #else
  91 #define DEBUG4(x)       do {} while (0);
  92 #endif
  93
  94 #if defined(QL_DEBUG_LEVEL_5)
  95 #define DEBUG5(x)          do {x;} while (0);
  96 #else
  97 #define DEBUG5(x)       do {} while (0);
  98 #endif
  99
 100 #if defined(QL_DEBUG_LEVEL_7)
 101 #define DEBUG7(x)          do {x;} while (0);
 102 #else
 103 #define DEBUG7(x)          do {} while (0);
 104 #endif
 105
 106 #if defined(QL_DEBUG_LEVEL_9)
 107 #define DEBUG9(x)       do {x;} while (0);
 108 #define DEBUG9_10(x)    do {x;} while (0);
 109 #define DEBUG2_9_10(x)  do {x;} while (0);
 110 #else
 111 #define DEBUG9(x)       do {} while (0);
 112 #endif
 113
 114 #if defined(QL_DEBUG_LEVEL_10)
 115 #define DEBUG10(x)      do {x;} while (0);
 116 #define DEBUG2_9_10(x)  do {x;} while (0);
 117 #define DEBUG9_10(x)    do {x;} while (0);
 118 #else
 119 #define DEBUG10(x)      do {} while (0);
 120   #if !defined(DEBUG2_9_10)
 121   #define DEBUG2_9_10(x)        do {} while (0);
 122   #endif
 123   #if !defined(DEBUG9_10)
 124   #define DEBUG9_10(x)  do {} while (0);
 125   #endif
 126 #endif
 127
 128 #if defined(QL_DEBUG_LEVEL_11)
 129 #define DEBUG11(x)      do{x;} while(0);
 130 #if !defined(DEBUG2_11)
 131 #define DEBUG2_11(x)    do{x;} while(0);
 132 #endif
 133 #if !defined(DEBUG2_3_11)
 134 #define DEBUG2_3_11(x)  do{x;} while(0);
 135 #endif
 136 #if !defined(DEBUG3_11)
 137 #define DEBUG3_11(x)    do{x;} while(0);
 138 #endif
 139 #else
 140 #define DEBUG11(x)      do{} while(0);
 141   #if !defined(QL_DEBUG_LEVEL_2)
 142   #define DEBUG2_11(x)  do{} while(0);
 143     #if !defined(QL_DEBUG_LEVEL_3)
 144     #define DEBUG2_3_11(x) do{} while(0);
 145     #endif
 146   #endif
 147   #if !defined(QL_DEBUG_LEVEL_3)
 148   #define DEBUG3_11(x)  do{} while(0);
 149   #endif
 150 #endif
 151
 152 #if defined(QL_DEBUG_LEVEL_12)
 153 #define DEBUG12(x)      do {x;} while (0);
 154 #else
 155 #define DEBUG12(x)      do {} while (0);
 156 #endif
 157
 158 #if defined(QL_DEBUG_LEVEL_13)
 159 #define DEBUG13(x)      do {x;} while (0)
 160 #if !defined(DEBUG2_13)
 161 #define DEBUG2_13(x)    do {x;} while(0)
 162 #endif
 163 #else
 164 #define DEBUG13(x)      do {} while (0)
 165 #if !defined(QL_DEBUG_LEVEL_2)
 166 #define DEBUG2_13(x)    do {} while(0)
 167 #endif
 168 #endif
 169
 170 #if defined(QL_DEBUG_LEVEL_14)
 171 #define DEBUG14(x)      do {x;} while (0)
 172 #else
 173 #define DEBUG14(x)      do {} while (0)
 174 #endif
 175
 176 /*
 177  * Firmware Dump structure definition
 178  */
 179 #define FW_DUMP_SIZE_128K       0xBC000
 180 #define FW_DUMP_SIZE_512K       0x2FC000
 181 #define FW_DUMP_SIZE_1M         0x5FC000
 182
 183 struct qla2300_fw_dump {
 184         uint16_t hccr;
 185         uint16_t pbiu_reg[8];
 186         uint16_t risc_host_reg[8];
 187         uint16_t mailbox_reg[32];
 188         uint16_t resp_dma_reg[32];
 189         uint16_t dma_reg[48];
 190         uint16_t risc_hdw_reg[16];
 191         uint16_t risc_gp0_reg[16];
 192         uint16_t risc_gp1_reg[16];
 193         uint16_t risc_gp2_reg[16];
 194         uint16_t risc_gp3_reg[16];
 195         uint16_t risc_gp4_reg[16];
 196         uint16_t risc_gp5_reg[16];
 197         uint16_t risc_gp6_reg[16];
 198         uint16_t risc_gp7_reg[16];
 199         uint16_t frame_buf_hdw_reg[64];
 200         uint16_t fpm_b0_reg[64];
 201         uint16_t fpm_b1_reg[64];
 202         uint16_t risc_ram[0xf800];
 203         uint16_t stack_ram[0x1000];
 204         uint16_t data_ram[1];
 205 };
 206
 207 struct qla2100_fw_dump {
 208         uint16_t hccr;
 209         uint16_t pbiu_reg[8];
 210         uint16_t mailbox_reg[32];
 211         uint16_t dma_reg[48];
 212         uint16_t risc_hdw_reg[16];
 213         uint16_t risc_gp0_reg[16];
 214         uint16_t risc_gp1_reg[16];
 215         uint16_t risc_gp2_reg[16];
 216         uint16_t risc_gp3_reg[16];
 217         uint16_t risc_gp4_reg[16];
 218         uint16_t risc_gp5_reg[16];
 219         uint16_t risc_gp6_reg[16];
 220         uint16_t risc_gp7_reg[16];
 221         uint16_t frame_buf_hdw_reg[16];
 222         uint16_t fpm_b0_reg[64];
 223         uint16_t fpm_b1_reg[64];
 224         uint16_t risc_ram[0xf000];
 225 };
 226
 227 #define FW_DUMP_SIZE_24XX       0x2B0000
 228
 229 struct qla24xx_fw_dump {
 230         uint32_t host_status;
 231         uint32_t host_reg[32];
 232         uint32_t shadow_reg[7];
 233         uint16_t mailbox_reg[32];
 234         uint32_t xseq_gp_reg[128];
 235         uint32_t xseq_0_reg[16];
 236         uint32_t xseq_1_reg[16];
 237         uint32_t rseq_gp_reg[128];
 238         uint32_t rseq_0_reg[16];
 239         uint32_t rseq_1_reg[16];
 240         uint32_t rseq_2_reg[16];
 241         uint32_t cmd_dma_reg[16];
 242         uint32_t req0_dma_reg[15];
 243         uint32_t resp0_dma_reg[15];
 244         uint32_t req1_dma_reg[15];
 245         uint32_t xmt0_dma_reg[32];
 246         uint32_t xmt1_dma_reg[32];
 247         uint32_t xmt2_dma_reg[32];
 248         uint32_t xmt3_dma_reg[32];
 249         uint32_t xmt4_dma_reg[32];
 250         uint32_t xmt_data_dma_reg[16];
 251         uint32_t rcvt0_data_dma_reg[32];
 252         uint32_t rcvt1_data_dma_reg[32];
 253         uint32_t risc_gp_reg[128];
 254         uint32_t lmc_reg[112];
 255         uint32_t fpm_hdw_reg[192];
 256         uint32_t fb_hdw_reg[176];
 257         uint32_t code_ram[0x2000];
 258         uint32_t ext_mem[1];
 259 };