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[CONNECTOR]: Initialize subsystem earlier.
[linux-2.6/verdex.git] / drivers / scsi / qla2xxx / qla_def.h
blob53508f3c4ae97392d110b65b5d4d4dd419db6bbf
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <asm/semaphore.h>
27
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_device.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <scsi/scsi_transport_fc.h>
33
34 /*
35 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
36 * but that's fine as we don't look at the last 24 ones for
37 * ISP2100 HBAs.
38 */
39 #define MAILBOX_REGISTER_COUNT_2100 8
40 #define MAILBOX_REGISTER_COUNT 32
41
42 #define QLA2200A_RISC_ROM_VER 4
43 #define FPM_2300 6
44 #define FPM_2310 7
45
46 #include "qla_settings.h"
47
48 /*
49 * Data bit definitions
50 */
51 #define BIT_0 0x1
52 #define BIT_1 0x2
53 #define BIT_2 0x4
54 #define BIT_3 0x8
55 #define BIT_4 0x10
56 #define BIT_5 0x20
57 #define BIT_6 0x40
58 #define BIT_7 0x80
59 #define BIT_8 0x100
60 #define BIT_9 0x200
61 #define BIT_10 0x400
62 #define BIT_11 0x800
63 #define BIT_12 0x1000
64 #define BIT_13 0x2000
65 #define BIT_14 0x4000
66 #define BIT_15 0x8000
67 #define BIT_16 0x10000
68 #define BIT_17 0x20000
69 #define BIT_18 0x40000
70 #define BIT_19 0x80000
71 #define BIT_20 0x100000
72 #define BIT_21 0x200000
73 #define BIT_22 0x400000
74 #define BIT_23 0x800000
75 #define BIT_24 0x1000000
76 #define BIT_25 0x2000000
77 #define BIT_26 0x4000000
78 #define BIT_27 0x8000000
79 #define BIT_28 0x10000000
80 #define BIT_29 0x20000000
81 #define BIT_30 0x40000000
82 #define BIT_31 0x80000000
83
84 #define LSB(x) ((uint8_t)(x))
85 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
86
87 #define LSW(x) ((uint16_t)(x))
88 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
89
90 #define LSD(x) ((uint32_t)((uint64_t)(x)))
91 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
92
93
94 /*
95 * I/O register
96 */
97
98 #define RD_REG_BYTE(addr) readb(addr)
99 #define RD_REG_WORD(addr) readw(addr)
100 #define RD_REG_DWORD(addr) readl(addr)
101 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
102 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
103 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
104 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
105 #define WRT_REG_WORD(addr, data) writew(data,addr)
106 #define WRT_REG_DWORD(addr, data) writel(data,addr)
107
108 /*
109 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
110 * 133Mhz slot.
111 */
112 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
113 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
114
115 /*
116 * Fibre Channel device definitions.
117 */
118 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
119 #define MAX_FIBRE_DEVICES 512
120 #define MAX_FIBRE_LUNS 0xFFFF
121 #define MAX_RSCN_COUNT 32
122 #define MAX_HOST_COUNT 16
123
124 /*
125 * Host adapter default definitions.
126 */
127 #define MAX_BUSES 1 /* We only have one bus today */
128 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
129 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
130 #define MIN_LUNS 8
131 #define MAX_LUNS MAX_FIBRE_LUNS
132 #define MAX_CMDS_PER_LUN 255
133
134 /*
135 * Fibre Channel device definitions.
136 */
137 #define SNS_LAST_LOOP_ID_2100 0xfe
138 #define SNS_LAST_LOOP_ID_2300 0x7ff
139
140 #define LAST_LOCAL_LOOP_ID 0x7d
141 #define SNS_FL_PORT 0x7e
142 #define FABRIC_CONTROLLER 0x7f
143 #define SIMPLE_NAME_SERVER 0x80
144 #define SNS_FIRST_LOOP_ID 0x81
145 #define MANAGEMENT_SERVER 0xfe
146 #define BROADCAST 0xff
147
148 /*
149 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
150 * valid range of an N-PORT id is 0 through 0x7ef.
151 */
152 #define NPH_LAST_HANDLE 0x7ef
153 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
154 #define NPH_SNS 0x7fc /* FFFFFC */
155 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
156 #define NPH_F_PORT 0x7fe /* FFFFFE */
157 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
158
159 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
160 #include "qla_fw.h"
161
162 /*
163 * Timeout timer counts in seconds
164 */
165 #define PORT_RETRY_TIME 1
166 #define LOOP_DOWN_TIMEOUT 60
167 #define LOOP_DOWN_TIME 255 /* 240 */
168 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
169
170 /* Maximum outstanding commands in ISP queues (1-65535) */
171 #define MAX_OUTSTANDING_COMMANDS 1024
172
173 /* ISP request and response entry counts (37-65535) */
174 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
175 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
176 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
177 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
178 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
179 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
180
181 /*
182 * SCSI Request Block
183 */
184 typedef struct srb {
185 struct list_head list;
186
187 struct scsi_qla_host *ha; /* HA the SP is queued on */
188 struct fc_port *fcport;
189
190 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
191
192 struct timer_list timer; /* Command timer */
193 atomic_t ref_count; /* Reference count for this structure */
194 uint16_t flags;
195
196 /* Request state */
197 uint16_t state;
198
199 /* Single transfer DMA context */
200 dma_addr_t dma_handle;
201
202 uint32_t request_sense_length;
203 uint8_t *request_sense_ptr;
204
205 /* SRB magic number */
206 uint16_t magic;
207 #define SRB_MAGIC 0x10CB
208 } srb_t;
209
210 /*
211 * SRB flag definitions
212 */
213 #define SRB_TIMEOUT BIT_0 /* Command timed out */
214 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
215 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
216 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
217
218 #define SRB_ABORTED BIT_4 /* Command aborted command already */
219 #define SRB_RETRY BIT_5 /* Command needs retrying */
220 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
221 #define SRB_FAILOVER BIT_7 /* Command in failover state */
222
223 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
224 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
225 #define SRB_IOCTL BIT_10 /* IOCTL command. */
226 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
227
228 /*
229 * SRB state definitions
230 */
231 #define SRB_FREE_STATE 0 /* returned back */
232 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
233 #define SRB_ACTIVE_STATE 2 /* in Active Array */
234 #define SRB_DONE_STATE 3 /* queued in Done Queue */
235 #define SRB_RETRY_STATE 4 /* in Retry Queue */
236 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
237 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
238 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
239 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
240 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
241
242
243 /*
244 * ISP I/O Register Set structure definitions.
245 */
246 struct device_reg_2xxx {
247 uint16_t flash_address; /* Flash BIOS address */
248 uint16_t flash_data; /* Flash BIOS data */
249 uint16_t unused_1[1]; /* Gap */
250 uint16_t ctrl_status; /* Control/Status */
251 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
252 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
253 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
254
255 uint16_t ictrl; /* Interrupt control */
256 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
257 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
258
259 uint16_t istatus; /* Interrupt status */
260 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
261
262 uint16_t semaphore; /* Semaphore */
263 uint16_t nvram; /* NVRAM register. */
264 #define NVR_DESELECT 0
265 #define NVR_BUSY BIT_15
266 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
267 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
268 #define NVR_DATA_IN BIT_3
269 #define NVR_DATA_OUT BIT_2
270 #define NVR_SELECT BIT_1
271 #define NVR_CLOCK BIT_0
272
273 union {
274 struct {
275 uint16_t mailbox0;
276 uint16_t mailbox1;
277 uint16_t mailbox2;
278 uint16_t mailbox3;
279 uint16_t mailbox4;
280 uint16_t mailbox5;
281 uint16_t mailbox6;
282 uint16_t mailbox7;
283 uint16_t unused_2[59]; /* Gap */
284 } __attribute__((packed)) isp2100;
285 struct {
286 /* Request Queue */
287 uint16_t req_q_in; /* In-Pointer */
288 uint16_t req_q_out; /* Out-Pointer */
289 /* Response Queue */
290 uint16_t rsp_q_in; /* In-Pointer */
291 uint16_t rsp_q_out; /* Out-Pointer */
292
293 /* RISC to Host Status */
294 uint32_t host_status;
295 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
296 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
297
298 /* Host to Host Semaphore */
299 uint16_t host_semaphore;
300 uint16_t unused_3[17]; /* Gap */
301 uint16_t mailbox0;
302 uint16_t mailbox1;
303 uint16_t mailbox2;
304 uint16_t mailbox3;
305 uint16_t mailbox4;
306 uint16_t mailbox5;
307 uint16_t mailbox6;
308 uint16_t mailbox7;
309 uint16_t mailbox8;
310 uint16_t mailbox9;
311 uint16_t mailbox10;
312 uint16_t mailbox11;
313 uint16_t mailbox12;
314 uint16_t mailbox13;
315 uint16_t mailbox14;
316 uint16_t mailbox15;
317 uint16_t mailbox16;
318 uint16_t mailbox17;
319 uint16_t mailbox18;
320 uint16_t mailbox19;
321 uint16_t mailbox20;
322 uint16_t mailbox21;
323 uint16_t mailbox22;
324 uint16_t mailbox23;
325 uint16_t mailbox24;
326 uint16_t mailbox25;
327 uint16_t mailbox26;
328 uint16_t mailbox27;
329 uint16_t mailbox28;
330 uint16_t mailbox29;
331 uint16_t mailbox30;
332 uint16_t mailbox31;
333 uint16_t fb_cmd;
334 uint16_t unused_4[10]; /* Gap */
335 } __attribute__((packed)) isp2300;
336 } u;
337
338 uint16_t fpm_diag_config;
339 uint16_t unused_5[0x6]; /* Gap */
340 uint16_t pcr; /* Processor Control Register. */
341 uint16_t unused_6[0x5]; /* Gap */
342 uint16_t mctr; /* Memory Configuration and Timing. */
343 uint16_t unused_7[0x3]; /* Gap */
344 uint16_t fb_cmd_2100; /* Unused on 23XX */
345 uint16_t unused_8[0x3]; /* Gap */
346 uint16_t hccr; /* Host command & control register. */
347 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
348 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
349 /* HCCR commands */
350 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
351 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
352 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
353 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
354 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
355 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
356 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
357 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
358
359 uint16_t unused_9[5]; /* Gap */
360 uint16_t gpiod; /* GPIO Data register. */
361 uint16_t gpioe; /* GPIO Enable register. */
362 #define GPIO_LED_MASK 0x00C0
363 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
364 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
365 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
366 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
367 #define GPIO_LED_ALL_OFF 0x0000
368 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
369 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
370
371 union {
372 struct {
373 uint16_t unused_10[8]; /* Gap */
374 uint16_t mailbox8;
375 uint16_t mailbox9;
376 uint16_t mailbox10;
377 uint16_t mailbox11;
378 uint16_t mailbox12;
379 uint16_t mailbox13;
380 uint16_t mailbox14;
381 uint16_t mailbox15;
382 uint16_t mailbox16;
383 uint16_t mailbox17;
384 uint16_t mailbox18;
385 uint16_t mailbox19;
386 uint16_t mailbox20;
387 uint16_t mailbox21;
388 uint16_t mailbox22;
389 uint16_t mailbox23; /* Also probe reg. */
390 } __attribute__((packed)) isp2200;
391 } u_end;
392 };
393
394 typedef union {
395 struct device_reg_2xxx isp;
396 struct device_reg_24xx isp24;
397 } device_reg_t;
398
399 #define ISP_REQ_Q_IN(ha, reg) \
400 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
401 &(reg)->u.isp2100.mailbox4 : \
402 &(reg)->u.isp2300.req_q_in)
403 #define ISP_REQ_Q_OUT(ha, reg) \
404 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
405 &(reg)->u.isp2100.mailbox4 : \
406 &(reg)->u.isp2300.req_q_out)
407 #define ISP_RSP_Q_IN(ha, reg) \
408 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
409 &(reg)->u.isp2100.mailbox5 : \
410 &(reg)->u.isp2300.rsp_q_in)
411 #define ISP_RSP_Q_OUT(ha, reg) \
412 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
413 &(reg)->u.isp2100.mailbox5 : \
414 &(reg)->u.isp2300.rsp_q_out)
415
416 #define MAILBOX_REG(ha, reg, num) \
417 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
418 (num < 8 ? \
419 &(reg)->u.isp2100.mailbox0 + (num) : \
420 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
421 &(reg)->u.isp2300.mailbox0 + (num))
422 #define RD_MAILBOX_REG(ha, reg, num) \
423 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
424 #define WRT_MAILBOX_REG(ha, reg, num, data) \
425 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
426
427 #define FB_CMD_REG(ha, reg) \
428 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
429 &(reg)->fb_cmd_2100 : \
430 &(reg)->u.isp2300.fb_cmd)
431 #define RD_FB_CMD_REG(ha, reg) \
432 RD_REG_WORD(FB_CMD_REG(ha, reg))
433 #define WRT_FB_CMD_REG(ha, reg, data) \
434 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
435
436 typedef struct {
437 uint32_t out_mb; /* outbound from driver */
438 uint32_t in_mb; /* Incoming from RISC */
439 uint16_t mb[MAILBOX_REGISTER_COUNT];
440 long buf_size;
441 void *bufp;
442 uint32_t tov;
443 uint8_t flags;
444 #define MBX_DMA_IN BIT_0
445 #define MBX_DMA_OUT BIT_1
446 #define IOCTL_CMD BIT_2
447 } mbx_cmd_t;
448
449 #define MBX_TOV_SECONDS 30
450
451 /*
452 * ISP product identification definitions in mailboxes after reset.
453 */
454 #define PROD_ID_1 0x4953
455 #define PROD_ID_2 0x0000
456 #define PROD_ID_2a 0x5020
457 #define PROD_ID_3 0x2020
458
459 /*
460 * ISP mailbox Self-Test status codes
461 */
462 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
463 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
464 #define MBS_BUSY 4 /* Busy. */
465
466 /*
467 * ISP mailbox command complete status codes
468 */
469 #define MBS_COMMAND_COMPLETE 0x4000
470 #define MBS_INVALID_COMMAND 0x4001
471 #define MBS_HOST_INTERFACE_ERROR 0x4002
472 #define MBS_TEST_FAILED 0x4003
473 #define MBS_COMMAND_ERROR 0x4005
474 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
475 #define MBS_PORT_ID_USED 0x4007
476 #define MBS_LOOP_ID_USED 0x4008
477 #define MBS_ALL_IDS_IN_USE 0x4009
478 #define MBS_NOT_LOGGED_IN 0x400A
479 #define MBS_LINK_DOWN_ERROR 0x400B
480 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
481
482 /*
483 * ISP mailbox asynchronous event status codes
484 */
485 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
486 #define MBA_RESET 0x8001 /* Reset Detected. */
487 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
488 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
489 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
490 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
491 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
492 /* occurred. */
493 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
494 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
495 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
496 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
497 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
498 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
499 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
500 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
501 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
502 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
503 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
504 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
505 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
506 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
507 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
508 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
509 /* used. */
510 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
511 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
512 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
513 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
514 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
515 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
516 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
517 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
518 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
519 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
520 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
521 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
522 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
523
524 /*
525 * Firmware options 1, 2, 3.
526 */
527 #define FO1_AE_ON_LIPF8 BIT_0
528 #define FO1_AE_ALL_LIP_RESET BIT_1
529 #define FO1_CTIO_RETRY BIT_3
530 #define FO1_DISABLE_LIP_F7_SW BIT_4
531 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
532 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
533 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
534 #define FO1_SET_EMPHASIS_SWING BIT_8
535 #define FO1_AE_AUTO_BYPASS BIT_9
536 #define FO1_ENABLE_PURE_IOCB BIT_10
537 #define FO1_AE_PLOGI_RJT BIT_11
538 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
539 #define FO1_AE_QUEUE_FULL BIT_13
540
541 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
542 #define FO2_REV_LOOPBACK BIT_1
543
544 #define FO3_ENABLE_EMERG_IOCB BIT_0
545 #define FO3_AE_RND_ERROR BIT_1
546
547 /* 24XX additional firmware options */
548 #define ADD_FO_COUNT 3
549 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
550 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
551
552 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
553
554 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
555
556 /*
557 * ISP mailbox commands
558 */
559 #define MBC_LOAD_RAM 1 /* Load RAM. */
560 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
561 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
562 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
563 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
564 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
565 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
566 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
567 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
568 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
569 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
570 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
571 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
572 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
573 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
574 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
575 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
576 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
577 #define MBC_RESET 0x18 /* Reset. */
578 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
579 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
580 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
581 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
582 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
583 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
584 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
585 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
586 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
587 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
588 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
589 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
590 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
591 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
592 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
593 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
594 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
595 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
596 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
597 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
598 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
599 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
600 /* Initialization Procedure */
601 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
602 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
603 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
604 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
605 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
606 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
607 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
608 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
609 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
610 #define MBC_LIP_RESET 0x6c /* LIP reset. */
611 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
612 /* commandd. */
613 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
614 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
615 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
616 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
617 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
618 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
619 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
620 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
621 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
622 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
623 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
624
625 /*
626 * ISP24xx mailbox commands
627 */
628 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
629 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
630 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
631 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
632 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
633 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
634 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
635 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
636 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
637 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
638 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
639 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
640
641 /* Firmware return data sizes */
642 #define FCAL_MAP_SIZE 128
643
644 /* Mailbox bit definitions for out_mb and in_mb */
645 #define MBX_31 BIT_31
646 #define MBX_30 BIT_30
647 #define MBX_29 BIT_29
648 #define MBX_28 BIT_28
649 #define MBX_27 BIT_27
650 #define MBX_26 BIT_26
651 #define MBX_25 BIT_25
652 #define MBX_24 BIT_24
653 #define MBX_23 BIT_23
654 #define MBX_22 BIT_22
655 #define MBX_21 BIT_21
656 #define MBX_20 BIT_20
657 #define MBX_19 BIT_19
658 #define MBX_18 BIT_18
659 #define MBX_17 BIT_17
660 #define MBX_16 BIT_16
661 #define MBX_15 BIT_15
662 #define MBX_14 BIT_14
663 #define MBX_13 BIT_13
664 #define MBX_12 BIT_12
665 #define MBX_11 BIT_11
666 #define MBX_10 BIT_10
667 #define MBX_9 BIT_9
668 #define MBX_8 BIT_8
669 #define MBX_7 BIT_7
670 #define MBX_6 BIT_6
671 #define MBX_5 BIT_5
672 #define MBX_4 BIT_4
673 #define MBX_3 BIT_3
674 #define MBX_2 BIT_2
675 #define MBX_1 BIT_1
676 #define MBX_0 BIT_0
677
678 /*
679 * Firmware state codes from get firmware state mailbox command
680 */
681 #define FSTATE_CONFIG_WAIT 0
682 #define FSTATE_WAIT_AL_PA 1
683 #define FSTATE_WAIT_LOGIN 2
684 #define FSTATE_READY 3
685 #define FSTATE_LOSS_OF_SYNC 4
686 #define FSTATE_ERROR 5
687 #define FSTATE_REINIT 6
688 #define FSTATE_NON_PART 7
689
690 #define FSTATE_CONFIG_CORRECT 0
691 #define FSTATE_P2P_RCV_LIP 1
692 #define FSTATE_P2P_CHOOSE_LOOP 2
693 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
694 #define FSTATE_FATAL_ERROR 4
695 #define FSTATE_LOOP_BACK_CONN 5
696
697 /*
698 * Port Database structure definition
699 * Little endian except where noted.
700 */
701 #define PORT_DATABASE_SIZE 128 /* bytes */
702 typedef struct {
703 uint8_t options;
704 uint8_t control;
705 uint8_t master_state;
706 uint8_t slave_state;
707 uint8_t reserved[2];
708 uint8_t hard_address;
709 uint8_t reserved_1;
710 uint8_t port_id[4];
711 uint8_t node_name[WWN_SIZE];
712 uint8_t port_name[WWN_SIZE];
713 uint16_t execution_throttle;
714 uint16_t execution_count;
715 uint8_t reset_count;
716 uint8_t reserved_2;
717 uint16_t resource_allocation;
718 uint16_t current_allocation;
719 uint16_t queue_head;
720 uint16_t queue_tail;
721 uint16_t transmit_execution_list_next;
722 uint16_t transmit_execution_list_previous;
723 uint16_t common_features;
724 uint16_t total_concurrent_sequences;
725 uint16_t RO_by_information_category;
726 uint8_t recipient;
727 uint8_t initiator;
728 uint16_t receive_data_size;
729 uint16_t concurrent_sequences;
730 uint16_t open_sequences_per_exchange;
731 uint16_t lun_abort_flags;
732 uint16_t lun_stop_flags;
733 uint16_t stop_queue_head;
734 uint16_t stop_queue_tail;
735 uint16_t port_retry_timer;
736 uint16_t next_sequence_id;
737 uint16_t frame_count;
738 uint16_t PRLI_payload_length;
739 uint8_t prli_svc_param_word_0[2]; /* Big endian */
740 /* Bits 15-0 of word 0 */
741 uint8_t prli_svc_param_word_3[2]; /* Big endian */
742 /* Bits 15-0 of word 3 */
743 uint16_t loop_id;
744 uint16_t extended_lun_info_list_pointer;
745 uint16_t extended_lun_stop_list_pointer;
746 } port_database_t;
747
748 /*
749 * Port database slave/master states
750 */
751 #define PD_STATE_DISCOVERY 0
752 #define PD_STATE_WAIT_DISCOVERY_ACK 1
753 #define PD_STATE_PORT_LOGIN 2
754 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
755 #define PD_STATE_PROCESS_LOGIN 4
756 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
757 #define PD_STATE_PORT_LOGGED_IN 6
758 #define PD_STATE_PORT_UNAVAILABLE 7
759 #define PD_STATE_PROCESS_LOGOUT 8
760 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
761 #define PD_STATE_PORT_LOGOUT 10
762 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
763
764
765 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
766 #define QLA_ZIO_DISABLED 0
767 #define QLA_ZIO_DEFAULT_TIMER 2
768
769 /*
770 * ISP Initialization Control Block.
771 * Little endian except where noted.
772 */
773 #define ICB_VERSION 1
774 typedef struct {
775 uint8_t version;
776 uint8_t reserved_1;
777
778 /*
779 * LSB BIT 0 = Enable Hard Loop Id
780 * LSB BIT 1 = Enable Fairness
781 * LSB BIT 2 = Enable Full-Duplex
782 * LSB BIT 3 = Enable Fast Posting
783 * LSB BIT 4 = Enable Target Mode
784 * LSB BIT 5 = Disable Initiator Mode
785 * LSB BIT 6 = Enable ADISC
786 * LSB BIT 7 = Enable Target Inquiry Data
787 *
788 * MSB BIT 0 = Enable PDBC Notify
789 * MSB BIT 1 = Non Participating LIP
790 * MSB BIT 2 = Descending Loop ID Search
791 * MSB BIT 3 = Acquire Loop ID in LIPA
792 * MSB BIT 4 = Stop PortQ on Full Status
793 * MSB BIT 5 = Full Login after LIP
794 * MSB BIT 6 = Node Name Option
795 * MSB BIT 7 = Ext IFWCB enable bit
796 */
797 uint8_t firmware_options[2];
798
799 uint16_t frame_payload_size;
800 uint16_t max_iocb_allocation;
801 uint16_t execution_throttle;
802 uint8_t retry_count;
803 uint8_t retry_delay; /* unused */
804 uint8_t port_name[WWN_SIZE]; /* Big endian. */
805 uint16_t hard_address;
806 uint8_t inquiry_data;
807 uint8_t login_timeout;
808 uint8_t node_name[WWN_SIZE]; /* Big endian. */
809
810 uint16_t request_q_outpointer;
811 uint16_t response_q_inpointer;
812 uint16_t request_q_length;
813 uint16_t response_q_length;
814 uint32_t request_q_address[2];
815 uint32_t response_q_address[2];
816
817 uint16_t lun_enables;
818 uint8_t command_resource_count;
819 uint8_t immediate_notify_resource_count;
820 uint16_t timeout;
821 uint8_t reserved_2[2];
822
823 /*
824 * LSB BIT 0 = Timer Operation mode bit 0
825 * LSB BIT 1 = Timer Operation mode bit 1
826 * LSB BIT 2 = Timer Operation mode bit 2
827 * LSB BIT 3 = Timer Operation mode bit 3
828 * LSB BIT 4 = Init Config Mode bit 0
829 * LSB BIT 5 = Init Config Mode bit 1
830 * LSB BIT 6 = Init Config Mode bit 2
831 * LSB BIT 7 = Enable Non part on LIHA failure
832 *
833 * MSB BIT 0 = Enable class 2
834 * MSB BIT 1 = Enable ACK0
835 * MSB BIT 2 =
836 * MSB BIT 3 =
837 * MSB BIT 4 = FC Tape Enable
838 * MSB BIT 5 = Enable FC Confirm
839 * MSB BIT 6 = Enable command queuing in target mode
840 * MSB BIT 7 = No Logo On Link Down
841 */
842 uint8_t add_firmware_options[2];
843
844 uint8_t response_accumulation_timer;
845 uint8_t interrupt_delay_timer;
846
847 /*
848 * LSB BIT 0 = Enable Read xfr_rdy
849 * LSB BIT 1 = Soft ID only
850 * LSB BIT 2 =
851 * LSB BIT 3 =
852 * LSB BIT 4 = FCP RSP Payload [0]
853 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
854 * LSB BIT 6 = Enable Out-of-Order frame handling
855 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
856 *
857 * MSB BIT 0 = Sbus enable - 2300
858 * MSB BIT 1 =
859 * MSB BIT 2 =
860 * MSB BIT 3 =
861 * MSB BIT 4 = LED mode
862 * MSB BIT 5 = enable 50 ohm termination
863 * MSB BIT 6 = Data Rate (2300 only)
864 * MSB BIT 7 = Data Rate (2300 only)
865 */
866 uint8_t special_options[2];
867
868 uint8_t reserved_3[26];
869 } init_cb_t;
870
871 /*
872 * Get Link Status mailbox command return buffer.
873 */
874 #define GLSO_SEND_RPS BIT_0
875 #define GLSO_USE_DID BIT_3
876
877 typedef struct {
878 uint32_t link_fail_cnt;
879 uint32_t loss_sync_cnt;
880 uint32_t loss_sig_cnt;
881 uint32_t prim_seq_err_cnt;
882 uint32_t inval_xmit_word_cnt;
883 uint32_t inval_crc_cnt;
884 } link_stat_t;
885
886 /*
887 * NVRAM Command values.
888 */
889 #define NV_START_BIT BIT_2
890 #define NV_WRITE_OP (BIT_26+BIT_24)
891 #define NV_READ_OP (BIT_26+BIT_25)
892 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
893 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
894 #define NV_DELAY_COUNT 10
895
896 /*
897 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
898 */
899 typedef struct {
900 /*
901 * NVRAM header
902 */
903 uint8_t id[4];
904 uint8_t nvram_version;
905 uint8_t reserved_0;
906
907 /*
908 * NVRAM RISC parameter block
909 */
910 uint8_t parameter_block_version;
911 uint8_t reserved_1;
912
913 /*
914 * LSB BIT 0 = Enable Hard Loop Id
915 * LSB BIT 1 = Enable Fairness
916 * LSB BIT 2 = Enable Full-Duplex
917 * LSB BIT 3 = Enable Fast Posting
918 * LSB BIT 4 = Enable Target Mode
919 * LSB BIT 5 = Disable Initiator Mode
920 * LSB BIT 6 = Enable ADISC
921 * LSB BIT 7 = Enable Target Inquiry Data
922 *
923 * MSB BIT 0 = Enable PDBC Notify
924 * MSB BIT 1 = Non Participating LIP
925 * MSB BIT 2 = Descending Loop ID Search
926 * MSB BIT 3 = Acquire Loop ID in LIPA
927 * MSB BIT 4 = Stop PortQ on Full Status
928 * MSB BIT 5 = Full Login after LIP
929 * MSB BIT 6 = Node Name Option
930 * MSB BIT 7 = Ext IFWCB enable bit
931 */
932 uint8_t firmware_options[2];
933
934 uint16_t frame_payload_size;
935 uint16_t max_iocb_allocation;
936 uint16_t execution_throttle;
937 uint8_t retry_count;
938 uint8_t retry_delay; /* unused */
939 uint8_t port_name[WWN_SIZE]; /* Big endian. */
940 uint16_t hard_address;
941 uint8_t inquiry_data;
942 uint8_t login_timeout;
943 uint8_t node_name[WWN_SIZE]; /* Big endian. */
944
945 /*
946 * LSB BIT 0 = Timer Operation mode bit 0
947 * LSB BIT 1 = Timer Operation mode bit 1
948 * LSB BIT 2 = Timer Operation mode bit 2
949 * LSB BIT 3 = Timer Operation mode bit 3
950 * LSB BIT 4 = Init Config Mode bit 0
951 * LSB BIT 5 = Init Config Mode bit 1
952 * LSB BIT 6 = Init Config Mode bit 2
953 * LSB BIT 7 = Enable Non part on LIHA failure
954 *
955 * MSB BIT 0 = Enable class 2
956 * MSB BIT 1 = Enable ACK0
957 * MSB BIT 2 =
958 * MSB BIT 3 =
959 * MSB BIT 4 = FC Tape Enable
960 * MSB BIT 5 = Enable FC Confirm
961 * MSB BIT 6 = Enable command queuing in target mode
962 * MSB BIT 7 = No Logo On Link Down
963 */
964 uint8_t add_firmware_options[2];
965
966 uint8_t response_accumulation_timer;
967 uint8_t interrupt_delay_timer;
968
969 /*
970 * LSB BIT 0 = Enable Read xfr_rdy
971 * LSB BIT 1 = Soft ID only
972 * LSB BIT 2 =
973 * LSB BIT 3 =
974 * LSB BIT 4 = FCP RSP Payload [0]
975 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
976 * LSB BIT 6 = Enable Out-of-Order frame handling
977 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
978 *
979 * MSB BIT 0 = Sbus enable - 2300
980 * MSB BIT 1 =
981 * MSB BIT 2 =
982 * MSB BIT 3 =
983 * MSB BIT 4 = LED mode
984 * MSB BIT 5 = enable 50 ohm termination
985 * MSB BIT 6 = Data Rate (2300 only)
986 * MSB BIT 7 = Data Rate (2300 only)
987 */
988 uint8_t special_options[2];
989
990 /* Reserved for expanded RISC parameter block */
991 uint8_t reserved_2[22];
992
993 /*
994 * LSB BIT 0 = Tx Sensitivity 1G bit 0
995 * LSB BIT 1 = Tx Sensitivity 1G bit 1
996 * LSB BIT 2 = Tx Sensitivity 1G bit 2
997 * LSB BIT 3 = Tx Sensitivity 1G bit 3
998 * LSB BIT 4 = Rx Sensitivity 1G bit 0
999 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1000 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1001 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1002 *
1003 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1004 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1005 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1006 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1007 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1008 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1009 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1010 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1011 *
1012 * LSB BIT 0 = Output Swing 1G bit 0
1013 * LSB BIT 1 = Output Swing 1G bit 1
1014 * LSB BIT 2 = Output Swing 1G bit 2
1015 * LSB BIT 3 = Output Emphasis 1G bit 0
1016 * LSB BIT 4 = Output Emphasis 1G bit 1
1017 * LSB BIT 5 = Output Swing 2G bit 0
1018 * LSB BIT 6 = Output Swing 2G bit 1
1019 * LSB BIT 7 = Output Swing 2G bit 2
1020 *
1021 * MSB BIT 0 = Output Emphasis 2G bit 0
1022 * MSB BIT 1 = Output Emphasis 2G bit 1
1023 * MSB BIT 2 = Output Enable
1024 * MSB BIT 3 =
1025 * MSB BIT 4 =
1026 * MSB BIT 5 =
1027 * MSB BIT 6 =
1028 * MSB BIT 7 =
1029 */
1030 uint8_t seriallink_options[4];
1031
1032 /*
1033 * NVRAM host parameter block
1034 *
1035 * LSB BIT 0 = Enable spinup delay
1036 * LSB BIT 1 = Disable BIOS
1037 * LSB BIT 2 = Enable Memory Map BIOS
1038 * LSB BIT 3 = Enable Selectable Boot
1039 * LSB BIT 4 = Disable RISC code load
1040 * LSB BIT 5 = Set cache line size 1
1041 * LSB BIT 6 = PCI Parity Disable
1042 * LSB BIT 7 = Enable extended logging
1043 *
1044 * MSB BIT 0 = Enable 64bit addressing
1045 * MSB BIT 1 = Enable lip reset
1046 * MSB BIT 2 = Enable lip full login
1047 * MSB BIT 3 = Enable target reset
1048 * MSB BIT 4 = Enable database storage
1049 * MSB BIT 5 = Enable cache flush read
1050 * MSB BIT 6 = Enable database load
1051 * MSB BIT 7 = Enable alternate WWN
1052 */
1053 uint8_t host_p[2];
1054
1055 uint8_t boot_node_name[WWN_SIZE];
1056 uint8_t boot_lun_number;
1057 uint8_t reset_delay;
1058 uint8_t port_down_retry_count;
1059 uint8_t boot_id_number;
1060 uint16_t max_luns_per_target;
1061 uint8_t fcode_boot_port_name[WWN_SIZE];
1062 uint8_t alternate_port_name[WWN_SIZE];
1063 uint8_t alternate_node_name[WWN_SIZE];
1064
1065 /*
1066 * BIT 0 = Selective Login
1067 * BIT 1 = Alt-Boot Enable
1068 * BIT 2 =
1069 * BIT 3 = Boot Order List
1070 * BIT 4 =
1071 * BIT 5 = Selective LUN
1072 * BIT 6 =
1073 * BIT 7 = unused
1074 */
1075 uint8_t efi_parameters;
1076
1077 uint8_t link_down_timeout;
1078
1079 uint8_t adapter_id[16];
1080
1081 uint8_t alt1_boot_node_name[WWN_SIZE];
1082 uint16_t alt1_boot_lun_number;
1083 uint8_t alt2_boot_node_name[WWN_SIZE];
1084 uint16_t alt2_boot_lun_number;
1085 uint8_t alt3_boot_node_name[WWN_SIZE];
1086 uint16_t alt3_boot_lun_number;
1087 uint8_t alt4_boot_node_name[WWN_SIZE];
1088 uint16_t alt4_boot_lun_number;
1089 uint8_t alt5_boot_node_name[WWN_SIZE];
1090 uint16_t alt5_boot_lun_number;
1091 uint8_t alt6_boot_node_name[WWN_SIZE];
1092 uint16_t alt6_boot_lun_number;
1093 uint8_t alt7_boot_node_name[WWN_SIZE];
1094 uint16_t alt7_boot_lun_number;
1095
1096 uint8_t reserved_3[2];
1097
1098 /* Offset 200-215 : Model Number */
1099 uint8_t model_number[16];
1100
1101 /* OEM related items */
1102 uint8_t oem_specific[16];
1103
1104 /*
1105 * NVRAM Adapter Features offset 232-239
1106 *
1107 * LSB BIT 0 = External GBIC
1108 * LSB BIT 1 = Risc RAM parity
1109 * LSB BIT 2 = Buffer Plus Module
1110 * LSB BIT 3 = Multi Chip Adapter
1111 * LSB BIT 4 = Internal connector
1112 * LSB BIT 5 =
1113 * LSB BIT 6 =
1114 * LSB BIT 7 =
1115 *
1116 * MSB BIT 0 =
1117 * MSB BIT 1 =
1118 * MSB BIT 2 =
1119 * MSB BIT 3 =
1120 * MSB BIT 4 =
1121 * MSB BIT 5 =
1122 * MSB BIT 6 =
1123 * MSB BIT 7 =
1124 */
1125 uint8_t adapter_features[2];
1126
1127 uint8_t reserved_4[16];
1128
1129 /* Subsystem vendor ID for ISP2200 */
1130 uint16_t subsystem_vendor_id_2200;
1131
1132 /* Subsystem device ID for ISP2200 */
1133 uint16_t subsystem_device_id_2200;
1134
1135 uint8_t reserved_5;
1136 uint8_t checksum;
1137 } nvram_t;
1138
1139 /*
1140 * ISP queue - response queue entry definition.
1141 */
1142 typedef struct {
1143 uint8_t data[60];
1144 uint32_t signature;
1145 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1146 } response_t;
1147
1148 typedef union {
1149 uint16_t extended;
1150 struct {
1151 uint8_t reserved;
1152 uint8_t standard;
1153 } id;
1154 } target_id_t;
1155
1156 #define SET_TARGET_ID(ha, to, from) \
1157 do { \
1158 if (HAS_EXTENDED_IDS(ha)) \
1159 to.extended = cpu_to_le16(from); \
1160 else \
1161 to.id.standard = (uint8_t)from; \
1162 } while (0)
1163
1164 /*
1165 * ISP queue - command entry structure definition.
1166 */
1167 #define COMMAND_TYPE 0x11 /* Command entry */
1168 typedef struct {
1169 uint8_t entry_type; /* Entry type. */
1170 uint8_t entry_count; /* Entry count. */
1171 uint8_t sys_define; /* System defined. */
1172 uint8_t entry_status; /* Entry Status. */
1173 uint32_t handle; /* System handle. */
1174 target_id_t target; /* SCSI ID */
1175 uint16_t lun; /* SCSI LUN */
1176 uint16_t control_flags; /* Control flags. */
1177 #define CF_WRITE BIT_6
1178 #define CF_READ BIT_5
1179 #define CF_SIMPLE_TAG BIT_3
1180 #define CF_ORDERED_TAG BIT_2
1181 #define CF_HEAD_TAG BIT_1
1182 uint16_t reserved_1;
1183 uint16_t timeout; /* Command timeout. */
1184 uint16_t dseg_count; /* Data segment count. */
1185 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1186 uint32_t byte_count; /* Total byte count. */
1187 uint32_t dseg_0_address; /* Data segment 0 address. */
1188 uint32_t dseg_0_length; /* Data segment 0 length. */
1189 uint32_t dseg_1_address; /* Data segment 1 address. */
1190 uint32_t dseg_1_length; /* Data segment 1 length. */
1191 uint32_t dseg_2_address; /* Data segment 2 address. */
1192 uint32_t dseg_2_length; /* Data segment 2 length. */
1193 } cmd_entry_t;
1194
1195 /*
1196 * ISP queue - 64-Bit addressing, command entry structure definition.
1197 */
1198 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1199 typedef struct {
1200 uint8_t entry_type; /* Entry type. */
1201 uint8_t entry_count; /* Entry count. */
1202 uint8_t sys_define; /* System defined. */
1203 uint8_t entry_status; /* Entry Status. */
1204 uint32_t handle; /* System handle. */
1205 target_id_t target; /* SCSI ID */
1206 uint16_t lun; /* SCSI LUN */
1207 uint16_t control_flags; /* Control flags. */
1208 uint16_t reserved_1;
1209 uint16_t timeout; /* Command timeout. */
1210 uint16_t dseg_count; /* Data segment count. */
1211 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1212 uint32_t byte_count; /* Total byte count. */
1213 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1214 uint32_t dseg_0_length; /* Data segment 0 length. */
1215 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1216 uint32_t dseg_1_length; /* Data segment 1 length. */
1217 } cmd_a64_entry_t, request_t;
1218
1219 /*
1220 * ISP queue - continuation entry structure definition.
1221 */
1222 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1223 typedef struct {
1224 uint8_t entry_type; /* Entry type. */
1225 uint8_t entry_count; /* Entry count. */
1226 uint8_t sys_define; /* System defined. */
1227 uint8_t entry_status; /* Entry Status. */
1228 uint32_t reserved;
1229 uint32_t dseg_0_address; /* Data segment 0 address. */
1230 uint32_t dseg_0_length; /* Data segment 0 length. */
1231 uint32_t dseg_1_address; /* Data segment 1 address. */
1232 uint32_t dseg_1_length; /* Data segment 1 length. */
1233 uint32_t dseg_2_address; /* Data segment 2 address. */
1234 uint32_t dseg_2_length; /* Data segment 2 length. */
1235 uint32_t dseg_3_address; /* Data segment 3 address. */
1236 uint32_t dseg_3_length; /* Data segment 3 length. */
1237 uint32_t dseg_4_address; /* Data segment 4 address. */
1238 uint32_t dseg_4_length; /* Data segment 4 length. */
1239 uint32_t dseg_5_address; /* Data segment 5 address. */
1240 uint32_t dseg_5_length; /* Data segment 5 length. */
1241 uint32_t dseg_6_address; /* Data segment 6 address. */
1242 uint32_t dseg_6_length; /* Data segment 6 length. */
1243 } cont_entry_t;
1244
1245 /*
1246 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1247 */
1248 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1249 typedef struct {
1250 uint8_t entry_type; /* Entry type. */
1251 uint8_t entry_count; /* Entry count. */
1252 uint8_t sys_define; /* System defined. */
1253 uint8_t entry_status; /* Entry Status. */
1254 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1255 uint32_t dseg_0_length; /* Data segment 0 length. */
1256 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1257 uint32_t dseg_1_length; /* Data segment 1 length. */
1258 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1259 uint32_t dseg_2_length; /* Data segment 2 length. */
1260 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1261 uint32_t dseg_3_length; /* Data segment 3 length. */
1262 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1263 uint32_t dseg_4_length; /* Data segment 4 length. */
1264 } cont_a64_entry_t;
1265
1266 /*
1267 * ISP queue - status entry structure definition.
1268 */
1269 #define STATUS_TYPE 0x03 /* Status entry. */
1270 typedef struct {
1271 uint8_t entry_type; /* Entry type. */
1272 uint8_t entry_count; /* Entry count. */
1273 uint8_t sys_define; /* System defined. */
1274 uint8_t entry_status; /* Entry Status. */
1275 uint32_t handle; /* System handle. */
1276 uint16_t scsi_status; /* SCSI status. */
1277 uint16_t comp_status; /* Completion status. */
1278 uint16_t state_flags; /* State flags. */
1279 uint16_t status_flags; /* Status flags. */
1280 uint16_t rsp_info_len; /* Response Info Length. */
1281 uint16_t req_sense_length; /* Request sense data length. */
1282 uint32_t residual_length; /* Residual transfer length. */
1283 uint8_t rsp_info[8]; /* FCP response information. */
1284 uint8_t req_sense_data[32]; /* Request sense data. */
1285 } sts_entry_t;
1286
1287 /*
1288 * Status entry entry status
1289 */
1290 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1291 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1292 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1293 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1294 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1295 #define RF_BUSY BIT_1 /* Busy */
1296 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1297 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1298 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1299 RF_INV_E_TYPE)
1300
1301 /*
1302 * Status entry SCSI status bit definitions.
1303 */
1304 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1305 #define SS_RESIDUAL_UNDER BIT_11
1306 #define SS_RESIDUAL_OVER BIT_10
1307 #define SS_SENSE_LEN_VALID BIT_9
1308 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1309
1310 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1311 #define SS_BUSY_CONDITION BIT_3
1312 #define SS_CONDITION_MET BIT_2
1313 #define SS_CHECK_CONDITION BIT_1
1314
1315 /*
1316 * Status entry completion status
1317 */
1318 #define CS_COMPLETE 0x0 /* No errors */
1319 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1320 #define CS_DMA 0x2 /* A DMA direction error. */
1321 #define CS_TRANSPORT 0x3 /* Transport error. */
1322 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1323 #define CS_ABORTED 0x5 /* System aborted command. */
1324 #define CS_TIMEOUT 0x6 /* Timeout error. */
1325 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1326
1327 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1328 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1329 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1330 /* (selection timeout) */
1331 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1332 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1333 #define CS_PORT_BUSY 0x2B /* Port Busy */
1334 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1335 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1336 #define CS_UNKNOWN 0x81 /* Driver defined */
1337 #define CS_RETRY 0x82 /* Driver defined */
1338 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1339
1340 /*
1341 * Status entry status flags
1342 */
1343 #define SF_ABTS_TERMINATED BIT_10
1344 #define SF_LOGOUT_SENT BIT_13
1345
1346 /*
1347 * ISP queue - status continuation entry structure definition.
1348 */
1349 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1350 typedef struct {
1351 uint8_t entry_type; /* Entry type. */
1352 uint8_t entry_count; /* Entry count. */
1353 uint8_t sys_define; /* System defined. */
1354 uint8_t entry_status; /* Entry Status. */
1355 uint8_t data[60]; /* data */
1356 } sts_cont_entry_t;
1357
1358 /*
1359 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1360 * structure definition.
1361 */
1362 #define STATUS_TYPE_21 0x21 /* Status entry. */
1363 typedef struct {
1364 uint8_t entry_type; /* Entry type. */
1365 uint8_t entry_count; /* Entry count. */
1366 uint8_t handle_count; /* Handle count. */
1367 uint8_t entry_status; /* Entry Status. */
1368 uint32_t handle[15]; /* System handles. */
1369 } sts21_entry_t;
1370
1371 /*
1372 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1373 * structure definition.
1374 */
1375 #define STATUS_TYPE_22 0x22 /* Status entry. */
1376 typedef struct {
1377 uint8_t entry_type; /* Entry type. */
1378 uint8_t entry_count; /* Entry count. */
1379 uint8_t handle_count; /* Handle count. */
1380 uint8_t entry_status; /* Entry Status. */
1381 uint16_t handle[30]; /* System handles. */
1382 } sts22_entry_t;
1383
1384 /*
1385 * ISP queue - marker entry structure definition.
1386 */
1387 #define MARKER_TYPE 0x04 /* Marker entry. */
1388 typedef struct {
1389 uint8_t entry_type; /* Entry type. */
1390 uint8_t entry_count; /* Entry count. */
1391 uint8_t handle_count; /* Handle count. */
1392 uint8_t entry_status; /* Entry Status. */
1393 uint32_t sys_define_2; /* System defined. */
1394 target_id_t target; /* SCSI ID */
1395 uint8_t modifier; /* Modifier (7-0). */
1396 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1397 #define MK_SYNC_ID 1 /* Synchronize ID */
1398 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1399 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1400 /* clear port changed, */
1401 /* use sequence number. */
1402 uint8_t reserved_1;
1403 uint16_t sequence_number; /* Sequence number of event */
1404 uint16_t lun; /* SCSI LUN */
1405 uint8_t reserved_2[48];
1406 } mrk_entry_t;
1407
1408 /*
1409 * ISP queue - Management Server entry structure definition.
1410 */
1411 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1412 typedef struct {
1413 uint8_t entry_type; /* Entry type. */
1414 uint8_t entry_count; /* Entry count. */
1415 uint8_t handle_count; /* Handle count. */
1416 uint8_t entry_status; /* Entry Status. */
1417 uint32_t handle1; /* System handle. */
1418 target_id_t loop_id;
1419 uint16_t status;
1420 uint16_t control_flags; /* Control flags. */
1421 uint16_t reserved2;
1422 uint16_t timeout;
1423 uint16_t cmd_dsd_count;
1424 uint16_t total_dsd_count;
1425 uint8_t type;
1426 uint8_t r_ctl;
1427 uint16_t rx_id;
1428 uint16_t reserved3;
1429 uint32_t handle2;
1430 uint32_t rsp_bytecount;
1431 uint32_t req_bytecount;
1432 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1433 uint32_t dseg_req_length; /* Data segment 0 length. */
1434 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1435 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1436 } ms_iocb_entry_t;
1437
1438
1439 /*
1440 * ISP queue - Mailbox Command entry structure definition.
1441 */
1442 #define MBX_IOCB_TYPE 0x39
1443 struct mbx_entry {
1444 uint8_t entry_type;
1445 uint8_t entry_count;
1446 uint8_t sys_define1;
1447 /* Use sys_define1 for source type */
1448 #define SOURCE_SCSI 0x00
1449 #define SOURCE_IP 0x01
1450 #define SOURCE_VI 0x02
1451 #define SOURCE_SCTP 0x03
1452 #define SOURCE_MP 0x04
1453 #define SOURCE_MPIOCTL 0x05
1454 #define SOURCE_ASYNC_IOCB 0x07
1455
1456 uint8_t entry_status;
1457
1458 uint32_t handle;
1459 target_id_t loop_id;
1460
1461 uint16_t status;
1462 uint16_t state_flags;
1463 uint16_t status_flags;
1464
1465 uint32_t sys_define2[2];
1466
1467 uint16_t mb0;
1468 uint16_t mb1;
1469 uint16_t mb2;
1470 uint16_t mb3;
1471 uint16_t mb6;
1472 uint16_t mb7;
1473 uint16_t mb9;
1474 uint16_t mb10;
1475 uint32_t reserved_2[2];
1476 uint8_t node_name[WWN_SIZE];
1477 uint8_t port_name[WWN_SIZE];
1478 };
1479
1480 /*
1481 * ISP request and response queue entry sizes
1482 */
1483 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1484 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1485
1486
1487 /*
1488 * 24 bit port ID type definition.
1489 */
1490 typedef union {
1491 uint32_t b24 : 24;
1492
1493 struct {
1494 uint8_t d_id[3];
1495 uint8_t rsvd_1;
1496 } r;
1497
1498 struct {
1499 uint8_t al_pa;
1500 uint8_t area;
1501 uint8_t domain;
1502 uint8_t rsvd_1;
1503 } b;
1504 } port_id_t;
1505 #define INVALID_PORT_ID 0xFFFFFF
1506
1507 /*
1508 * Switch info gathering structure.
1509 */
1510 typedef struct {
1511 port_id_t d_id;
1512 uint8_t node_name[WWN_SIZE];
1513 uint8_t port_name[WWN_SIZE];
1514 } sw_info_t;
1515
1516 /*
1517 * Inquiry command structure.
1518 */
1519 #define INQ_DATA_SIZE 36
1520
1521 /*
1522 * Inquiry mailbox IOCB packet definition.
1523 */
1524 typedef struct {
1525 union {
1526 cmd_a64_entry_t cmd;
1527 sts_entry_t rsp;
1528 struct cmd_type_7 cmd24;
1529 struct sts_entry_24xx rsp24;
1530 } p;
1531 uint8_t inq[INQ_DATA_SIZE];
1532 } inq_cmd_rsp_t;
1533
1534 /*
1535 * Report LUN command structure.
1536 */
1537 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1538
1539 typedef struct {
1540 uint32_t len;
1541 uint32_t rsrv;
1542 } rpt_hdr_t;
1543
1544 typedef struct {
1545 struct {
1546 uint8_t b : 6;
1547 uint8_t address_method : 2;
1548 } msb;
1549 uint8_t lsb;
1550 uint8_t unused[6];
1551 } rpt_lun_t;
1552
1553 typedef struct {
1554 rpt_hdr_t hdr;
1555 rpt_lun_t lst[MAX_LUNS];
1556 } rpt_lun_lst_t;
1557
1558 /*
1559 * Report Lun mailbox IOCB packet definition.
1560 */
1561 typedef struct {
1562 union {
1563 cmd_a64_entry_t cmd;
1564 sts_entry_t rsp;
1565 struct cmd_type_7 cmd24;
1566 struct sts_entry_24xx rsp24;
1567 } p;
1568 rpt_lun_lst_t list;
1569 } rpt_lun_cmd_rsp_t;
1570
1571
1572 /*
1573 * Fibre channel port type.
1574 */
1575 typedef enum {
1576 FCT_UNKNOWN,
1577 FCT_RSCN,
1578 FCT_SWITCH,
1579 FCT_BROADCAST,
1580 FCT_INITIATOR,
1581 FCT_TARGET
1582 } fc_port_type_t;
1583
1584 /*
1585 * Fibre channel port structure.
1586 */
1587 typedef struct fc_port {
1588 struct list_head list;
1589 struct scsi_qla_host *ha;
1590 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1591
1592 uint8_t node_name[WWN_SIZE];
1593 uint8_t port_name[WWN_SIZE];
1594 port_id_t d_id;
1595 uint16_t loop_id;
1596 uint16_t old_loop_id;
1597
1598 fc_port_type_t port_type;
1599
1600 atomic_t state;
1601 uint32_t flags;
1602
1603 unsigned int os_target_id;
1604
1605 uint16_t iodesc_idx_sent;
1606
1607 int port_login_retry_count;
1608 int login_retry;
1609 atomic_t port_down_timer;
1610
1611 uint8_t device_type;
1612 uint8_t unused;
1613
1614 uint8_t mp_byte; /* multi-path byte (not used) */
1615 uint8_t cur_path; /* current path id */
1616
1617 spinlock_t rport_lock;
1618 struct fc_rport *rport, *drport;
1619 u32 supported_classes;
1620 struct work_struct rport_add_work;
1621 struct work_struct rport_del_work;
1622 } fc_port_t;
1623
1624 /*
1625 * Fibre channel port/lun states.
1626 */
1627 #define FCS_UNCONFIGURED 1
1628 #define FCS_DEVICE_DEAD 2
1629 #define FCS_DEVICE_LOST 3
1630 #define FCS_ONLINE 4
1631 #define FCS_NOT_SUPPORTED 5
1632 #define FCS_FAILOVER 6
1633 #define FCS_FAILOVER_FAILED 7
1634
1635 /*
1636 * FC port flags.
1637 */
1638 #define FCF_FABRIC_DEVICE BIT_0
1639 #define FCF_LOGIN_NEEDED BIT_1
1640 #define FCF_FO_MASKED BIT_2
1641 #define FCF_FAILOVER_NEEDED BIT_3
1642 #define FCF_RESET_NEEDED BIT_4
1643 #define FCF_PERSISTENT_BOUND BIT_5
1644 #define FCF_TAPE_PRESENT BIT_6
1645 #define FCF_FARP_DONE BIT_7
1646 #define FCF_FARP_FAILED BIT_8
1647 #define FCF_FARP_REPLY_NEEDED BIT_9
1648 #define FCF_AUTH_REQ BIT_10
1649 #define FCF_SEND_AUTH_REQ BIT_11
1650 #define FCF_RECEIVE_AUTH_REQ BIT_12
1651 #define FCF_AUTH_SUCCESS BIT_13
1652 #define FCF_RLC_SUPPORT BIT_14
1653 #define FCF_CONFIG BIT_15 /* Needed? */
1654 #define FCF_RESCAN_NEEDED BIT_16
1655 #define FCF_XP_DEVICE BIT_17
1656 #define FCF_MSA_DEVICE BIT_18
1657 #define FCF_EVA_DEVICE BIT_19
1658 #define FCF_MSA_PORT_ACTIVE BIT_20
1659 #define FCF_FAILBACK_DISABLE BIT_21
1660 #define FCF_FAILOVER_DISABLE BIT_22
1661 #define FCF_DSXXX_DEVICE BIT_23
1662 #define FCF_AA_EVA_DEVICE BIT_24
1663 #define FCF_AA_MSA_DEVICE BIT_25
1664
1665 /* No loop ID flag. */
1666 #define FC_NO_LOOP_ID 0x1000
1667
1668 /*
1669 * FC-CT interface
1670 *
1671 * NOTE: All structures are big-endian in form.
1672 */
1673
1674 #define CT_REJECT_RESPONSE 0x8001
1675 #define CT_ACCEPT_RESPONSE 0x8002
1676 #define CT_REASON_CANNOT_PERFORM 0x09
1677 #define CT_EXPL_ALREADY_REGISTERED 0x10
1678
1679 #define NS_N_PORT_TYPE 0x01
1680 #define NS_NL_PORT_TYPE 0x02
1681 #define NS_NX_PORT_TYPE 0x7F
1682
1683 #define GA_NXT_CMD 0x100
1684 #define GA_NXT_REQ_SIZE (16 + 4)
1685 #define GA_NXT_RSP_SIZE (16 + 620)
1686
1687 #define GID_PT_CMD 0x1A1
1688 #define GID_PT_REQ_SIZE (16 + 4)
1689 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1690
1691 #define GPN_ID_CMD 0x112
1692 #define GPN_ID_REQ_SIZE (16 + 4)
1693 #define GPN_ID_RSP_SIZE (16 + 8)
1694
1695 #define GNN_ID_CMD 0x113
1696 #define GNN_ID_REQ_SIZE (16 + 4)
1697 #define GNN_ID_RSP_SIZE (16 + 8)
1698
1699 #define GFT_ID_CMD 0x117
1700 #define GFT_ID_REQ_SIZE (16 + 4)
1701 #define GFT_ID_RSP_SIZE (16 + 32)
1702
1703 #define RFT_ID_CMD 0x217
1704 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1705 #define RFT_ID_RSP_SIZE 16
1706
1707 #define RFF_ID_CMD 0x21F
1708 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1709 #define RFF_ID_RSP_SIZE 16
1710
1711 #define RNN_ID_CMD 0x213
1712 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1713 #define RNN_ID_RSP_SIZE 16
1714
1715 #define RSNN_NN_CMD 0x239
1716 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1717 #define RSNN_NN_RSP_SIZE 16
1718
1719 /*
1720 * HBA attribute types.
1721 */
1722 #define FDMI_HBA_ATTR_COUNT 9
1723 #define FDMI_HBA_NODE_NAME 1
1724 #define FDMI_HBA_MANUFACTURER 2
1725 #define FDMI_HBA_SERIAL_NUMBER 3
1726 #define FDMI_HBA_MODEL 4
1727 #define FDMI_HBA_MODEL_DESCRIPTION 5
1728 #define FDMI_HBA_HARDWARE_VERSION 6
1729 #define FDMI_HBA_DRIVER_VERSION 7
1730 #define FDMI_HBA_OPTION_ROM_VERSION 8
1731 #define FDMI_HBA_FIRMWARE_VERSION 9
1732 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1733 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1734
1735 struct ct_fdmi_hba_attr {
1736 uint16_t type;
1737 uint16_t len;
1738 union {
1739 uint8_t node_name[WWN_SIZE];
1740 uint8_t manufacturer[32];
1741 uint8_t serial_num[8];
1742 uint8_t model[16];
1743 uint8_t model_desc[80];
1744 uint8_t hw_version[16];
1745 uint8_t driver_version[32];
1746 uint8_t orom_version[16];
1747 uint8_t fw_version[16];
1748 uint8_t os_version[128];
1749 uint8_t max_ct_len[4];
1750 } a;
1751 };
1752
1753 struct ct_fdmi_hba_attributes {
1754 uint32_t count;
1755 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1756 };
1757
1758 /*
1759 * Port attribute types.
1760 */
1761 #define FDMI_PORT_ATTR_COUNT 5
1762 #define FDMI_PORT_FC4_TYPES 1
1763 #define FDMI_PORT_SUPPORT_SPEED 2
1764 #define FDMI_PORT_CURRENT_SPEED 3
1765 #define FDMI_PORT_MAX_FRAME_SIZE 4
1766 #define FDMI_PORT_OS_DEVICE_NAME 5
1767 #define FDMI_PORT_HOST_NAME 6
1768
1769 struct ct_fdmi_port_attr {
1770 uint16_t type;
1771 uint16_t len;
1772 union {
1773 uint8_t fc4_types[32];
1774 uint32_t sup_speed;
1775 uint32_t cur_speed;
1776 uint32_t max_frame_size;
1777 uint8_t os_dev_name[32];
1778 uint8_t host_name[32];
1779 } a;
1780 };
1781
1782 /*
1783 * Port Attribute Block.
1784 */
1785 struct ct_fdmi_port_attributes {
1786 uint32_t count;
1787 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1788 };
1789
1790 /* FDMI definitions. */
1791 #define GRHL_CMD 0x100
1792 #define GHAT_CMD 0x101
1793 #define GRPL_CMD 0x102
1794 #define GPAT_CMD 0x110
1795
1796 #define RHBA_CMD 0x200
1797 #define RHBA_RSP_SIZE 16
1798
1799 #define RHAT_CMD 0x201
1800 #define RPRT_CMD 0x210
1801
1802 #define RPA_CMD 0x211
1803 #define RPA_RSP_SIZE 16
1804
1805 #define DHBA_CMD 0x300
1806 #define DHBA_REQ_SIZE (16 + 8)
1807 #define DHBA_RSP_SIZE 16
1808
1809 #define DHAT_CMD 0x301
1810 #define DPRT_CMD 0x310
1811 #define DPA_CMD 0x311
1812
1813 /* CT command header -- request/response common fields */
1814 struct ct_cmd_hdr {
1815 uint8_t revision;
1816 uint8_t in_id[3];
1817 uint8_t gs_type;
1818 uint8_t gs_subtype;
1819 uint8_t options;
1820 uint8_t reserved;
1821 };
1822
1823 /* CT command request */
1824 struct ct_sns_req {
1825 struct ct_cmd_hdr header;
1826 uint16_t command;
1827 uint16_t max_rsp_size;
1828 uint8_t fragment_id;
1829 uint8_t reserved[3];
1830
1831 union {
1832 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1833 struct {
1834 uint8_t reserved;
1835 uint8_t port_id[3];
1836 } port_id;
1837
1838 struct {
1839 uint8_t port_type;
1840 uint8_t domain;
1841 uint8_t area;
1842 uint8_t reserved;
1843 } gid_pt;
1844
1845 struct {
1846 uint8_t reserved;
1847 uint8_t port_id[3];
1848 uint8_t fc4_types[32];
1849 } rft_id;
1850
1851 struct {
1852 uint8_t reserved;
1853 uint8_t port_id[3];
1854 uint16_t reserved2;
1855 uint8_t fc4_feature;
1856 uint8_t fc4_type;
1857 } rff_id;
1858
1859 struct {
1860 uint8_t reserved;
1861 uint8_t port_id[3];
1862 uint8_t node_name[8];
1863 } rnn_id;
1864
1865 struct {
1866 uint8_t node_name[8];
1867 uint8_t name_len;
1868 uint8_t sym_node_name[255];
1869 } rsnn_nn;
1870
1871 struct {
1872 uint8_t hba_indentifier[8];
1873 } ghat;
1874
1875 struct {
1876 uint8_t hba_identifier[8];
1877 uint32_t entry_count;
1878 uint8_t port_name[8];
1879 struct ct_fdmi_hba_attributes attrs;
1880 } rhba;
1881
1882 struct {
1883 uint8_t hba_identifier[8];
1884 struct ct_fdmi_hba_attributes attrs;
1885 } rhat;
1886
1887 struct {
1888 uint8_t port_name[8];
1889 struct ct_fdmi_port_attributes attrs;
1890 } rpa;
1891
1892 struct {
1893 uint8_t port_name[8];
1894 } dhba;
1895
1896 struct {
1897 uint8_t port_name[8];
1898 } dhat;
1899
1900 struct {
1901 uint8_t port_name[8];
1902 } dprt;
1903
1904 struct {
1905 uint8_t port_name[8];
1906 } dpa;
1907 } req;
1908 };
1909
1910 /* CT command response header */
1911 struct ct_rsp_hdr {
1912 struct ct_cmd_hdr header;
1913 uint16_t response;
1914 uint16_t residual;
1915 uint8_t fragment_id;
1916 uint8_t reason_code;
1917 uint8_t explanation_code;
1918 uint8_t vendor_unique;
1919 };
1920
1921 struct ct_sns_gid_pt_data {
1922 uint8_t control_byte;
1923 uint8_t port_id[3];
1924 };
1925
1926 struct ct_sns_rsp {
1927 struct ct_rsp_hdr header;
1928
1929 union {
1930 struct {
1931 uint8_t port_type;
1932 uint8_t port_id[3];
1933 uint8_t port_name[8];
1934 uint8_t sym_port_name_len;
1935 uint8_t sym_port_name[255];
1936 uint8_t node_name[8];
1937 uint8_t sym_node_name_len;
1938 uint8_t sym_node_name[255];
1939 uint8_t init_proc_assoc[8];
1940 uint8_t node_ip_addr[16];
1941 uint8_t class_of_service[4];
1942 uint8_t fc4_types[32];
1943 uint8_t ip_address[16];
1944 uint8_t fabric_port_name[8];
1945 uint8_t reserved;
1946 uint8_t hard_address[3];
1947 } ga_nxt;
1948
1949 struct {
1950 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1951 } gid_pt;
1952
1953 struct {
1954 uint8_t port_name[8];
1955 } gpn_id;
1956
1957 struct {
1958 uint8_t node_name[8];
1959 } gnn_id;
1960
1961 struct {
1962 uint8_t fc4_types[32];
1963 } gft_id;
1964
1965 struct {
1966 uint32_t entry_count;
1967 uint8_t port_name[8];
1968 struct ct_fdmi_hba_attributes attrs;
1969 } ghat;
1970 } rsp;
1971 };
1972
1973 struct ct_sns_pkt {
1974 union {
1975 struct ct_sns_req req;
1976 struct ct_sns_rsp rsp;
1977 } p;
1978 };
1979
1980 /*
1981 * SNS command structures -- for 2200 compatability.
1982 */
1983 #define RFT_ID_SNS_SCMD_LEN 22
1984 #define RFT_ID_SNS_CMD_SIZE 60
1985 #define RFT_ID_SNS_DATA_SIZE 16
1986
1987 #define RNN_ID_SNS_SCMD_LEN 10
1988 #define RNN_ID_SNS_CMD_SIZE 36
1989 #define RNN_ID_SNS_DATA_SIZE 16
1990
1991 #define GA_NXT_SNS_SCMD_LEN 6
1992 #define GA_NXT_SNS_CMD_SIZE 28
1993 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1994
1995 #define GID_PT_SNS_SCMD_LEN 6
1996 #define GID_PT_SNS_CMD_SIZE 28
1997 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1998
1999 #define GPN_ID_SNS_SCMD_LEN 6
2000 #define GPN_ID_SNS_CMD_SIZE 28
2001 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2002
2003 #define GNN_ID_SNS_SCMD_LEN 6
2004 #define GNN_ID_SNS_CMD_SIZE 28
2005 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2006
2007 struct sns_cmd_pkt {
2008 union {
2009 struct {
2010 uint16_t buffer_length;
2011 uint16_t reserved_1;
2012 uint32_t buffer_address[2];
2013 uint16_t subcommand_length;
2014 uint16_t reserved_2;
2015 uint16_t subcommand;
2016 uint16_t size;
2017 uint32_t reserved_3;
2018 uint8_t param[36];
2019 } cmd;
2020
2021 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2022 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2023 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2024 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2025 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2026 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2027 } p;
2028 };
2029
2030 /* IO descriptors */
2031 #define MAX_IO_DESCRIPTORS 32
2032
2033 #define ABORT_IOCB_CB 0
2034 #define ADISC_PORT_IOCB_CB 1
2035 #define LOGOUT_PORT_IOCB_CB 2
2036 #define LOGIN_PORT_IOCB_CB 3
2037 #define LAST_IOCB_CB 4
2038
2039 #define IODESC_INVALID_INDEX 0xFFFF
2040 #define IODESC_ADISC_NEEDED 0xFFFE
2041 #define IODESC_LOGIN_NEEDED 0xFFFD
2042
2043 struct io_descriptor {
2044 uint16_t used:1;
2045 uint16_t idx:11;
2046 uint16_t cb_idx:4;
2047
2048 struct timer_list timer;
2049
2050 struct scsi_qla_host *ha;
2051
2052 port_id_t d_id;
2053 fc_port_t *remote_fcport;
2054
2055 uint32_t signature;
2056 };
2057
2058 struct qla_fw_info {
2059 unsigned short addressing; /* addressing method used to load fw */
2060 #define FW_INFO_ADDR_NORMAL 0
2061 #define FW_INFO_ADDR_EXTENDED 1
2062 #define FW_INFO_ADDR_NOMORE 0xffff
2063 unsigned short *fwcode; /* pointer to FW array */
2064 unsigned short *fwlen; /* number of words in array */
2065 unsigned short *fwstart; /* start address for F/W */
2066 unsigned long *lfwstart; /* start address (long) for F/W */
2067 };
2068
2069 struct qla_board_info {
2070 char *drv_name;
2071
2072 char isp_name[8];
2073 struct qla_fw_info *fw_info;
2074 char *fw_fname;
2075 struct scsi_host_template *sht;
2076 };
2077
2078 struct fw_blob {
2079 char *name;
2080 uint32_t segs[4];
2081 const struct firmware *fw;
2082 };
2083
2084 /* Return data from MBC_GET_ID_LIST call. */
2085 struct gid_list_info {
2086 uint8_t al_pa;
2087 uint8_t area;
2088 uint8_t domain;
2089 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2090 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2091 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2092 };
2093 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2094
2095 /*
2096 * ISP operations
2097 */
2098 struct isp_operations {
2099
2100 int (*pci_config) (struct scsi_qla_host *);
2101 void (*reset_chip) (struct scsi_qla_host *);
2102 int (*chip_diag) (struct scsi_qla_host *);
2103 void (*config_rings) (struct scsi_qla_host *);
2104 void (*reset_adapter) (struct scsi_qla_host *);
2105 int (*nvram_config) (struct scsi_qla_host *);
2106 void (*update_fw_options) (struct scsi_qla_host *);
2107 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2108
2109 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2110 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2111
2112 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2113 void (*enable_intrs) (struct scsi_qla_host *);
2114 void (*disable_intrs) (struct scsi_qla_host *);
2115
2116 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2117 int (*abort_target) (struct fc_port *);
2118 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2119 uint8_t, uint8_t, uint16_t *, uint8_t);
2120 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2121 uint8_t, uint8_t);
2122
2123 uint16_t (*calc_req_entries) (uint16_t);
2124 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2125 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2126 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2127 uint32_t);
2128
2129 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2130 uint32_t, uint32_t);
2131 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2132 uint32_t);
2133
2134 void (*fw_dump) (struct scsi_qla_host *, int);
2135 void (*ascii_fw_dump) (struct scsi_qla_host *);
2136
2137 int (*beacon_on) (struct scsi_qla_host *);
2138 int (*beacon_off) (struct scsi_qla_host *);
2139 void (*beacon_blink) (struct scsi_qla_host *);
2140
2141 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2142 uint32_t, uint32_t);
2143 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2144 uint32_t);
2145 };
2146
2147 /*
2148 * Linux Host Adapter structure
2149 */
2150 typedef struct scsi_qla_host {
2151 struct list_head list;
2152
2153 /* Commonly used flags and state information. */
2154 struct Scsi_Host *host;
2155 struct pci_dev *pdev;
2156
2157 unsigned long host_no;
2158 unsigned long instance;
2159
2160 volatile struct {
2161 uint32_t init_done :1;
2162 uint32_t online :1;
2163 uint32_t mbox_int :1;
2164 uint32_t mbox_busy :1;
2165 uint32_t rscn_queue_overflow :1;
2166 uint32_t reset_active :1;
2167
2168 uint32_t management_server_logged_in :1;
2169 uint32_t process_response_queue :1;
2170
2171 uint32_t disable_risc_code_load :1;
2172 uint32_t enable_64bit_addressing :1;
2173 uint32_t enable_lip_reset :1;
2174 uint32_t enable_lip_full_login :1;
2175 uint32_t enable_target_reset :1;
2176 uint32_t enable_led_scheme :1;
2177 uint32_t msi_enabled :1;
2178 uint32_t msix_enabled :1;
2179 } flags;
2180
2181 atomic_t loop_state;
2182 #define LOOP_TIMEOUT 1
2183 #define LOOP_DOWN 2
2184 #define LOOP_UP 3
2185 #define LOOP_UPDATE 4
2186 #define LOOP_READY 5
2187 #define LOOP_DEAD 6
2188
2189 unsigned long dpc_flags;
2190 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2191 #define RESET_ACTIVE 1
2192 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2193 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2194 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2195 #define LOOP_RESYNC_ACTIVE 5
2196 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2197 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2198 #define MAILBOX_RETRY 8
2199 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2200 #define FAILOVER_EVENT_NEEDED 10
2201 #define FAILOVER_EVENT 11
2202 #define FAILOVER_NEEDED 12
2203 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2204 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2205 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2206 #define ABORT_QUEUES_NEEDED 16
2207 #define RELOGIN_NEEDED 17
2208 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2209 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2210 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2211 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2212 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2213 #define IOCTL_ERROR_RECOVERY 23
2214 #define LOOP_RESET_NEEDED 24
2215 #define BEACON_BLINK_NEEDED 25
2216 #define REGISTER_FDMI_NEEDED 26
2217 #define FCPORT_UPDATE_NEEDED 27
2218
2219 uint32_t device_flags;
2220 #define DFLG_LOCAL_DEVICES BIT_0
2221 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2222 #define DFLG_FABRIC_DEVICES BIT_2
2223 #define SWITCH_FOUND BIT_3
2224 #define DFLG_NO_CABLE BIT_4
2225
2226 uint32_t device_type;
2227 #define DT_ISP2100 BIT_0
2228 #define DT_ISP2200 BIT_1
2229 #define DT_ISP2300 BIT_2
2230 #define DT_ISP2312 BIT_3
2231 #define DT_ISP2322 BIT_4
2232 #define DT_ISP6312 BIT_5
2233 #define DT_ISP6322 BIT_6
2234 #define DT_ISP2422 BIT_7
2235 #define DT_ISP2432 BIT_8
2236 #define DT_ISP5422 BIT_9
2237 #define DT_ISP5432 BIT_10
2238 #define DT_ISP_LAST (DT_ISP5432 << 1)
2239
2240 #define DT_ZIO_SUPPORTED BIT_28
2241 #define DT_OEM_001 BIT_29
2242 #define DT_ISP2200A BIT_30
2243 #define DT_EXTENDED_IDS BIT_31
2244
2245 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2246 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2247 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2248 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2249 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2250 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2251 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2252 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2253 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2254 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2255 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2256 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2257
2258 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2259 IS_QLA6312(ha) || IS_QLA6322(ha))
2260 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2261 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2262
2263 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2264 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2265 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2266
2267 /* SRB cache. */
2268 #define SRB_MIN_REQ 128
2269 mempool_t *srb_mempool;
2270
2271 /* This spinlock is used to protect "io transactions", you must
2272 * aquire it before doing any IO to the card, eg with RD_REG*() and
2273 * WRT_REG*() for the duration of your entire commandtransaction.
2274 *
2275 * This spinlock is of lower priority than the io request lock.
2276 */
2277
2278 spinlock_t hardware_lock ____cacheline_aligned;
2279
2280 device_reg_t __iomem *iobase; /* Base I/O address */
2281 unsigned long pio_address;
2282 unsigned long pio_length;
2283 #define MIN_IOBASE_LEN 0x100
2284
2285 /* ISP ring lock, rings, and indexes */
2286 dma_addr_t request_dma; /* Physical address. */
2287 request_t *request_ring; /* Base virtual address */
2288 request_t *request_ring_ptr; /* Current address. */
2289 uint16_t req_ring_index; /* Current index. */
2290 uint16_t req_q_cnt; /* Number of available entries. */
2291 uint16_t request_q_length;
2292
2293 dma_addr_t response_dma; /* Physical address. */
2294 response_t *response_ring; /* Base virtual address */
2295 response_t *response_ring_ptr; /* Current address. */
2296 uint16_t rsp_ring_index; /* Current index. */
2297 uint16_t response_q_length;
2298
2299 struct isp_operations isp_ops;
2300
2301 /* Outstandings ISP commands. */
2302 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2303 uint32_t current_outstanding_cmd;
2304 srb_t *status_srb; /* Status continuation entry. */
2305
2306 uint16_t revision;
2307 uint8_t ports;
2308
2309 /* ISP configuration data. */
2310 uint16_t loop_id; /* Host adapter loop id */
2311 uint16_t fb_rev;
2312
2313 port_id_t d_id; /* Host adapter port id */
2314 uint16_t max_public_loop_ids;
2315 uint16_t min_external_loopid; /* First external loop Id */
2316
2317 uint16_t link_data_rate; /* F/W operating speed */
2318 #define LDR_1GB 0
2319 #define LDR_2GB 1
2320 #define LDR_4GB 3
2321 #define LDR_UNKNOWN 0xFFFF
2322
2323 uint8_t current_topology;
2324 uint8_t prev_topology;
2325 #define ISP_CFG_NL 1
2326 #define ISP_CFG_N 2
2327 #define ISP_CFG_FL 4
2328 #define ISP_CFG_F 8
2329
2330 uint8_t operating_mode; /* F/W operating mode */
2331 #define LOOP 0
2332 #define P2P 1
2333 #define LOOP_P2P 2
2334 #define P2P_LOOP 3
2335
2336 uint8_t marker_needed;
2337
2338 uint8_t interrupts_on;
2339
2340 /* HBA serial number */
2341 uint8_t serial0;
2342 uint8_t serial1;
2343 uint8_t serial2;
2344
2345 /* NVRAM configuration data */
2346 uint16_t nvram_size;
2347 uint16_t nvram_base;
2348 uint16_t vpd_size;
2349 uint16_t vpd_base;
2350
2351 uint16_t loop_reset_delay;
2352 uint8_t retry_count;
2353 uint8_t login_timeout;
2354 uint16_t r_a_tov;
2355 int port_down_retry_count;
2356 uint8_t mbx_count;
2357 uint16_t last_loop_id;
2358 uint16_t mgmt_svr_loop_id;
2359
2360 uint32_t login_retry_count;
2361
2362 /* Fibre Channel Device List. */
2363 struct list_head fcports;
2364 struct list_head rscn_fcports;
2365
2366 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2367 uint16_t iodesc_signature;
2368
2369 /* RSCN queue. */
2370 uint32_t rscn_queue[MAX_RSCN_COUNT];
2371 uint8_t rscn_in_ptr;
2372 uint8_t rscn_out_ptr;
2373
2374 /* SNS command interfaces. */
2375 ms_iocb_entry_t *ms_iocb;
2376 dma_addr_t ms_iocb_dma;
2377 struct ct_sns_pkt *ct_sns;
2378 dma_addr_t ct_sns_dma;
2379 /* SNS command interfaces for 2200. */
2380 struct sns_cmd_pkt *sns_cmd;
2381 dma_addr_t sns_cmd_dma;
2382
2383 struct task_struct *dpc_thread;
2384 uint8_t dpc_active; /* DPC routine is active */
2385
2386 /* Timeout timers. */
2387 uint8_t loop_down_abort_time; /* port down timer */
2388 atomic_t loop_down_timer; /* loop down timer */
2389 uint8_t link_down_timeout; /* link down timeout */
2390
2391 uint32_t timer_active;
2392 struct timer_list timer;
2393
2394 dma_addr_t gid_list_dma;
2395 struct gid_list_info *gid_list;
2396 int gid_list_info_size;
2397
2398 dma_addr_t rlc_rsp_dma;
2399 rpt_lun_cmd_rsp_t *rlc_rsp;
2400
2401 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2402 #define DMA_POOL_SIZE 256
2403 struct dma_pool *s_dma_pool;
2404
2405 dma_addr_t init_cb_dma;
2406 init_cb_t *init_cb;
2407 int init_cb_size;
2408
2409 dma_addr_t iodesc_pd_dma;
2410 port_database_t *iodesc_pd;
2411
2412 /* These are used by mailbox operations. */
2413 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2414
2415 mbx_cmd_t *mcp;
2416 unsigned long mbx_cmd_flags;
2417 #define MBX_INTERRUPT 1
2418 #define MBX_INTR_WAIT 2
2419 #define MBX_UPDATE_FLASH_ACTIVE 3
2420
2421 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2422
2423 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2424 struct semaphore mbx_intr_sem; /* Used for completion notification */
2425
2426 uint32_t mbx_flags;
2427 #define MBX_IN_PROGRESS BIT_0
2428 #define MBX_BUSY BIT_1 /* Got the Access */
2429 #define MBX_SLEEPING_ON_SEM BIT_2
2430 #define MBX_POLLING_FOR_COMP BIT_3
2431 #define MBX_COMPLETED BIT_4
2432 #define MBX_TIMEDOUT BIT_5
2433 #define MBX_ACCESS_TIMEDOUT BIT_6
2434
2435 mbx_cmd_t mc;
2436
2437 /* Basic firmware related information. */
2438 struct qla_board_info *brd_info;
2439 uint16_t fw_major_version;
2440 uint16_t fw_minor_version;
2441 uint16_t fw_subminor_version;
2442 uint16_t fw_attributes;
2443 uint32_t fw_memory_size;
2444 uint32_t fw_transfer_size;
2445
2446 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2447 uint8_t fw_seriallink_options[4];
2448 uint16_t fw_seriallink_options24[4];
2449
2450 /* Firmware dump information. */
2451 void *fw_dump;
2452 int fw_dump_order;
2453 int fw_dump_reading;
2454 char *fw_dump_buffer;
2455 int fw_dump_buffer_len;
2456
2457 int fw_dumped;
2458 void *fw_dump24;
2459 int fw_dump24_len;
2460
2461 uint8_t host_str[16];
2462 uint32_t pci_attr;
2463
2464 uint16_t product_id[4];
2465
2466 uint8_t model_number[16+1];
2467 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2468 char *model_desc;
2469 uint8_t adapter_id[16+1];
2470
2471 uint8_t *node_name;
2472 uint8_t *port_name;
2473 uint32_t isp_abort_cnt;
2474
2475 /* Option ROM information. */
2476 char *optrom_buffer;
2477 uint32_t optrom_size;
2478 int optrom_state;
2479 #define QLA_SWAITING 0
2480 #define QLA_SREADING 1
2481 #define QLA_SWRITING 2
2482
2483 /* Needed for BEACON */
2484 uint16_t beacon_blink_led;
2485 uint8_t beacon_color_state;
2486 #define QLA_LED_GRN_ON 0x01
2487 #define QLA_LED_YLW_ON 0x02
2488 #define QLA_LED_ABR_ON 0x04
2489 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2490 /* ISP2322: red, green, amber. */
2491
2492 uint16_t zio_mode;
2493 uint16_t zio_timer;
2494 struct fc_host_statistics fc_host_stat;
2495 } scsi_qla_host_t;
2496
2497
2498 /*
2499 * Macros to help code, maintain, etc.
2500 */
2501 #define LOOP_TRANSITION(ha) \
2502 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2503 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2504 atomic_read(&ha->loop_state) == LOOP_DOWN)
2505
2506 #define TGT_Q(ha, t) (ha->otgt[t])
2507
2508 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2509
2510 #define qla_printk(level, ha, format, arg...) \
2511 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2512
2513 /*
2514 * qla2x00 local function return status codes
2515 */
2516 #define MBS_MASK 0x3fff
2517
2518 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2519 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2520 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2521 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2522 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2523 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2524 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2525 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2526 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2527 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2528
2529 #define QLA_FUNCTION_TIMEOUT 0x100
2530 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2531 #define QLA_FUNCTION_FAILED 0x102
2532 #define QLA_MEMORY_ALLOC_FAILED 0x103
2533 #define QLA_LOCK_TIMEOUT 0x104
2534 #define QLA_ABORTED 0x105
2535 #define QLA_SUSPENDED 0x106
2536 #define QLA_BUSY 0x107
2537 #define QLA_RSCNS_HANDLED 0x108
2538 #define QLA_ALREADY_REGISTERED 0x109
2539
2540 /*
2541 * Stat info for all adpaters
2542 */
2543 struct _qla2x00stats {
2544 unsigned long mboxtout; /* mailbox timeouts */
2545 unsigned long mboxerr; /* mailbox errors */
2546 unsigned long ispAbort; /* ISP aborts */
2547 unsigned long debugNo;
2548 unsigned long loop_resync;
2549 unsigned long outarray_full;
2550 unsigned long retry_q_cnt;
2551 };
2552
2553 #define NVRAM_DELAY() udelay(10)
2554
2555 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2556
2557 /*
2558 * Flash support definitions
2559 */
2560 #define OPTROM_SIZE_2300 0x20000
2561 #define OPTROM_SIZE_2322 0x100000
2562 #define OPTROM_SIZE_24XX 0x100000
2563
2564 #include "qla_gbl.h"
2565 #include "qla_dbg.h"
2566 #include "qla_inline.h"
2567
2568 /*
2569 * String arrays
2570 */
2571 #define LINESIZE 256
2572 #define MAXARGS 26
2573
2574 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2575 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2576 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2577 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2578 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2579 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2580
2581 #endif
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