?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[CONNECTOR]: Initialize subsystem earlier.
[linux-2.6/verdex.git] / drivers / scsi / sata_sx4.c
blob4139ad4b1df065fb00d51510207c9e13dfe41332
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_sx4"
49 #define DRV_VERSION "0.8"
50
51
52 enum {
53 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
54
55 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
56 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
59
60 PDC_20621_SEQCTL = 0x400,
61 PDC_20621_SEQMASK = 0x480,
62 PDC_20621_GENERAL_CTL = 0x484,
63 PDC_20621_PAGE_SIZE = (32 * 1024),
64
65 /* chosen, not constant, values; we design our own DIMM mem map */
66 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
67 PDC_20621_DIMM_BASE = 0x00200000,
68 PDC_20621_DIMM_DATA = (64 * 1024),
69 PDC_DIMM_DATA_STEP = (256 * 1024),
70 PDC_DIMM_WINDOW_STEP = (8 * 1024),
71 PDC_DIMM_HOST_PRD = (6 * 1024),
72 PDC_DIMM_HOST_PKT = (128 * 0),
73 PDC_DIMM_HPKT_PRD = (128 * 1),
74 PDC_DIMM_ATA_PKT = (128 * 2),
75 PDC_DIMM_APKT_PRD = (128 * 3),
76 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
77 PDC_PAGE_WINDOW = 0x40,
78 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
79 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
80 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
81
82 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
83
84 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
85 (1<<23),
86
87 board_20621 = 0, /* FastTrak S150 SX4 */
88
89 PDC_RESET = (1 << 11), /* HDMA reset */
90
91 PDC_MAX_HDMA = 32,
92 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
93
94 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
95 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
96 PDC_MAX_DIMM_MODULE = 0x02,
97 PDC_I2C_CONTROL_OFFSET = 0x48,
98 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
99 PDC_DIMM0_CONTROL_OFFSET = 0x80,
100 PDC_DIMM1_CONTROL_OFFSET = 0x84,
101 PDC_SDRAM_CONTROL_OFFSET = 0x88,
102 PDC_I2C_WRITE = 0x00000000,
103 PDC_I2C_READ = 0x00000040,
104 PDC_I2C_START = 0x00000080,
105 PDC_I2C_MASK_INT = 0x00000020,
106 PDC_I2C_COMPLETE = 0x00010000,
107 PDC_I2C_NO_ACK = 0x00100000,
108 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
109 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
110 PDC_DIMM_SPD_ROW_NUM = 3,
111 PDC_DIMM_SPD_COLUMN_NUM = 4,
112 PDC_DIMM_SPD_MODULE_ROW = 5,
113 PDC_DIMM_SPD_TYPE = 11,
114 PDC_DIMM_SPD_FRESH_RATE = 12,
115 PDC_DIMM_SPD_BANK_NUM = 17,
116 PDC_DIMM_SPD_CAS_LATENCY = 18,
117 PDC_DIMM_SPD_ATTRIBUTE = 21,
118 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
119 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
120 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
121 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
122 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
123 PDC_CTL_STATUS = 0x08,
124 PDC_DIMM_WINDOW_CTLR = 0x0C,
125 PDC_TIME_CONTROL = 0x3C,
126 PDC_TIME_PERIOD = 0x40,
127 PDC_TIME_COUNTER = 0x44,
128 PDC_GENERAL_CTLR = 0x484,
129 PCI_PLL_INIT = 0x8A531824,
130 PCI_X_TCOUNT = 0xEE1E5CFF
131 };
132
133
134 struct pdc_port_priv {
135 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
136 u8 *pkt;
137 dma_addr_t pkt_dma;
138 };
139
140 struct pdc_host_priv {
141 void __iomem *dimm_mmio;
142
143 unsigned int doing_hdma;
144 unsigned int hdma_prod;
145 unsigned int hdma_cons;
146 struct {
147 struct ata_queued_cmd *qc;
148 unsigned int seq;
149 unsigned long pkt_ofs;
150 } hdma[32];
151 };
152
153
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc_port_stop(struct ata_port *ap);
160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
163 static void pdc20621_host_stop(struct ata_host_set *host_set);
164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
167 u32 device, u32 subaddr, u32 *pdata);
168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
170 #ifdef ATA_VERBOSE_DEBUG
171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
172 void *psource, u32 offset, u32 size);
173 #endif
174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
175 void *psource, u32 offset, u32 size);
176 static void pdc20621_irq_clear(struct ata_port *ap);
177 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
178
179
180 static struct scsi_host_template pdc_sata_sht = {
181 .module = THIS_MODULE,
182 .name = DRV_NAME,
183 .ioctl = ata_scsi_ioctl,
184 .queuecommand = ata_scsi_queuecmd,
185 .can_queue = ATA_DEF_QUEUE,
186 .this_id = ATA_SHT_THIS_ID,
187 .sg_tablesize = LIBATA_MAX_PRD,
188 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
189 .emulated = ATA_SHT_EMULATED,
190 .use_clustering = ATA_SHT_USE_CLUSTERING,
191 .proc_name = DRV_NAME,
192 .dma_boundary = ATA_DMA_BOUNDARY,
193 .slave_configure = ata_scsi_slave_config,
194 .bios_param = ata_std_bios_param,
195 };
196
197 static const struct ata_port_operations pdc_20621_ops = {
198 .port_disable = ata_port_disable,
199 .tf_load = pdc_tf_load_mmio,
200 .tf_read = ata_tf_read,
201 .check_status = ata_check_status,
202 .exec_command = pdc_exec_command_mmio,
203 .dev_select = ata_std_dev_select,
204 .phy_reset = pdc_20621_phy_reset,
205 .qc_prep = pdc20621_qc_prep,
206 .qc_issue = pdc20621_qc_issue_prot,
207 .eng_timeout = pdc_eng_timeout,
208 .irq_handler = pdc20621_interrupt,
209 .irq_clear = pdc20621_irq_clear,
210 .port_start = pdc_port_start,
211 .port_stop = pdc_port_stop,
212 .host_stop = pdc20621_host_stop,
213 };
214
215 static const struct ata_port_info pdc_port_info[] = {
216 /* board_20621 */
217 {
218 .sht = &pdc_sata_sht,
219 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
220 ATA_FLAG_SRST | ATA_FLAG_MMIO |
221 ATA_FLAG_NO_ATAPI,
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
225 .port_ops = &pdc_20621_ops,
226 },
227
228 };
229
230 static const struct pci_device_id pdc_sata_pci_tbl[] = {
231 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
232 board_20621 },
233 { } /* terminate list */
234 };
235
236
237 static struct pci_driver pdc_sata_pci_driver = {
238 .name = DRV_NAME,
239 .id_table = pdc_sata_pci_tbl,
240 .probe = pdc_sata_init_one,
241 .remove = ata_pci_remove_one,
242 };
243
244
245 static void pdc20621_host_stop(struct ata_host_set *host_set)
246 {
247 struct pci_dev *pdev = to_pci_dev(host_set->dev);
248 struct pdc_host_priv *hpriv = host_set->private_data;
249 void __iomem *dimm_mmio = hpriv->dimm_mmio;
250
251 pci_iounmap(pdev, dimm_mmio);
252 kfree(hpriv);
253
254 pci_iounmap(pdev, host_set->mmio_base);
255 }
256
257 static int pdc_port_start(struct ata_port *ap)
258 {
259 struct device *dev = ap->host_set->dev;
260 struct pdc_port_priv *pp;
261 int rc;
262
263 rc = ata_port_start(ap);
264 if (rc)
265 return rc;
266
267 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
268 if (!pp) {
269 rc = -ENOMEM;
270 goto err_out;
271 }
272 memset(pp, 0, sizeof(*pp));
273
274 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
275 if (!pp->pkt) {
276 rc = -ENOMEM;
277 goto err_out_kfree;
278 }
279
280 ap->private_data = pp;
281
282 return 0;
283
284 err_out_kfree:
285 kfree(pp);
286 err_out:
287 ata_port_stop(ap);
288 return rc;
289 }
290
291
292 static void pdc_port_stop(struct ata_port *ap)
293 {
294 struct device *dev = ap->host_set->dev;
295 struct pdc_port_priv *pp = ap->private_data;
296
297 ap->private_data = NULL;
298 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
299 kfree(pp);
300 ata_port_stop(ap);
301 }
302
303
304 static void pdc_20621_phy_reset (struct ata_port *ap)
305 {
306 VPRINTK("ENTER\n");
307 ap->cbl = ATA_CBL_SATA;
308 ata_port_probe(ap);
309 ata_bus_reset(ap);
310 }
311
312 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
313 unsigned int portno,
314 unsigned int total_len)
315 {
316 u32 addr;
317 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
318 u32 *buf32 = (u32 *) buf;
319
320 /* output ATA packet S/G table */
321 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
322 (PDC_DIMM_DATA_STEP * portno);
323 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
324 buf32[dw] = cpu_to_le32(addr);
325 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
326
327 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
328 PDC_20621_DIMM_BASE +
329 (PDC_DIMM_WINDOW_STEP * portno) +
330 PDC_DIMM_APKT_PRD,
331 buf32[dw], buf32[dw + 1]);
332 }
333
334 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
335 unsigned int portno,
336 unsigned int total_len)
337 {
338 u32 addr;
339 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
340 u32 *buf32 = (u32 *) buf;
341
342 /* output Host DMA packet S/G table */
343 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
344 (PDC_DIMM_DATA_STEP * portno);
345
346 buf32[dw] = cpu_to_le32(addr);
347 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
348
349 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
350 PDC_20621_DIMM_BASE +
351 (PDC_DIMM_WINDOW_STEP * portno) +
352 PDC_DIMM_HPKT_PRD,
353 buf32[dw], buf32[dw + 1]);
354 }
355
356 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
357 unsigned int devno, u8 *buf,
358 unsigned int portno)
359 {
360 unsigned int i, dw;
361 u32 *buf32 = (u32 *) buf;
362 u8 dev_reg;
363
364 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
365 (PDC_DIMM_WINDOW_STEP * portno) +
366 PDC_DIMM_APKT_PRD;
367 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
368
369 i = PDC_DIMM_ATA_PKT;
370
371 /*
372 * Set up ATA packet
373 */
374 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
375 buf[i++] = PDC_PKT_READ;
376 else if (tf->protocol == ATA_PROT_NODATA)
377 buf[i++] = PDC_PKT_NODATA;
378 else
379 buf[i++] = 0;
380 buf[i++] = 0; /* reserved */
381 buf[i++] = portno + 1; /* seq. id */
382 buf[i++] = 0xff; /* delay seq. id */
383
384 /* dimm dma S/G, and next-pkt */
385 dw = i >> 2;
386 if (tf->protocol == ATA_PROT_NODATA)
387 buf32[dw] = 0;
388 else
389 buf32[dw] = cpu_to_le32(dimm_sg);
390 buf32[dw + 1] = 0;
391 i += 8;
392
393 if (devno == 0)
394 dev_reg = ATA_DEVICE_OBS;
395 else
396 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
397
398 /* select device */
399 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
400 buf[i++] = dev_reg;
401
402 /* device control register */
403 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
404 buf[i++] = tf->ctl;
405
406 return i;
407 }
408
409 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
410 unsigned int portno)
411 {
412 unsigned int dw;
413 u32 tmp, *buf32 = (u32 *) buf;
414
415 unsigned int host_sg = PDC_20621_DIMM_BASE +
416 (PDC_DIMM_WINDOW_STEP * portno) +
417 PDC_DIMM_HOST_PRD;
418 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
419 (PDC_DIMM_WINDOW_STEP * portno) +
420 PDC_DIMM_HPKT_PRD;
421 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
422 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
423
424 dw = PDC_DIMM_HOST_PKT >> 2;
425
426 /*
427 * Set up Host DMA packet
428 */
429 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
430 tmp = PDC_PKT_READ;
431 else
432 tmp = 0;
433 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
434 tmp |= (0xff << 24); /* delay seq. id */
435 buf32[dw + 0] = cpu_to_le32(tmp);
436 buf32[dw + 1] = cpu_to_le32(host_sg);
437 buf32[dw + 2] = cpu_to_le32(dimm_sg);
438 buf32[dw + 3] = 0;
439
440 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
441 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
442 PDC_DIMM_HOST_PKT,
443 buf32[dw + 0],
444 buf32[dw + 1],
445 buf32[dw + 2],
446 buf32[dw + 3]);
447 }
448
449 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
450 {
451 struct scatterlist *sg;
452 struct ata_port *ap = qc->ap;
453 struct pdc_port_priv *pp = ap->private_data;
454 void __iomem *mmio = ap->host_set->mmio_base;
455 struct pdc_host_priv *hpriv = ap->host_set->private_data;
456 void __iomem *dimm_mmio = hpriv->dimm_mmio;
457 unsigned int portno = ap->port_no;
458 unsigned int i, idx, total_len = 0, sgt_len;
459 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
460
461 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
462
463 VPRINTK("ata%u: ENTER\n", ap->id);
464
465 /* hard-code chip #0 */
466 mmio += PDC_CHIP0_OFS;
467
468 /*
469 * Build S/G table
470 */
471 idx = 0;
472 ata_for_each_sg(sg, qc) {
473 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
474 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
475 total_len += sg_dma_len(sg);
476 }
477 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
478 sgt_len = idx * 4;
479
480 /*
481 * Build ATA, host DMA packets
482 */
483 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
484 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
485
486 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
487 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
488
489 if (qc->tf.flags & ATA_TFLAG_LBA48)
490 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
491 else
492 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
493
494 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
495
496 /* copy three S/G tables and two packets to DIMM MMIO window */
497 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
498 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
499 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
500 PDC_DIMM_HOST_PRD,
501 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
502
503 /* force host FIFO dump */
504 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
505
506 readl(dimm_mmio); /* MMIO PCI posting flush */
507
508 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
509 }
510
511 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
512 {
513 struct ata_port *ap = qc->ap;
514 struct pdc_port_priv *pp = ap->private_data;
515 void __iomem *mmio = ap->host_set->mmio_base;
516 struct pdc_host_priv *hpriv = ap->host_set->private_data;
517 void __iomem *dimm_mmio = hpriv->dimm_mmio;
518 unsigned int portno = ap->port_no;
519 unsigned int i;
520
521 VPRINTK("ata%u: ENTER\n", ap->id);
522
523 /* hard-code chip #0 */
524 mmio += PDC_CHIP0_OFS;
525
526 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
527
528 if (qc->tf.flags & ATA_TFLAG_LBA48)
529 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
530 else
531 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
532
533 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
534
535 /* copy three S/G tables and two packets to DIMM MMIO window */
536 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
537 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
538
539 /* force host FIFO dump */
540 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
541
542 readl(dimm_mmio); /* MMIO PCI posting flush */
543
544 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
545 }
546
547 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
548 {
549 switch (qc->tf.protocol) {
550 case ATA_PROT_DMA:
551 pdc20621_dma_prep(qc);
552 break;
553 case ATA_PROT_NODATA:
554 pdc20621_nodata_prep(qc);
555 break;
556 default:
557 break;
558 }
559 }
560
561 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
562 unsigned int seq,
563 u32 pkt_ofs)
564 {
565 struct ata_port *ap = qc->ap;
566 struct ata_host_set *host_set = ap->host_set;
567 void __iomem *mmio = host_set->mmio_base;
568
569 /* hard-code chip #0 */
570 mmio += PDC_CHIP0_OFS;
571
572 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
573 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
574
575 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
576 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
577 }
578
579 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
580 unsigned int seq,
581 u32 pkt_ofs)
582 {
583 struct ata_port *ap = qc->ap;
584 struct pdc_host_priv *pp = ap->host_set->private_data;
585 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
586
587 if (!pp->doing_hdma) {
588 __pdc20621_push_hdma(qc, seq, pkt_ofs);
589 pp->doing_hdma = 1;
590 return;
591 }
592
593 pp->hdma[idx].qc = qc;
594 pp->hdma[idx].seq = seq;
595 pp->hdma[idx].pkt_ofs = pkt_ofs;
596 pp->hdma_prod++;
597 }
598
599 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
600 {
601 struct ata_port *ap = qc->ap;
602 struct pdc_host_priv *pp = ap->host_set->private_data;
603 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
604
605 /* if nothing on queue, we're done */
606 if (pp->hdma_prod == pp->hdma_cons) {
607 pp->doing_hdma = 0;
608 return;
609 }
610
611 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
612 pp->hdma[idx].pkt_ofs);
613 pp->hdma_cons++;
614 }
615
616 #ifdef ATA_VERBOSE_DEBUG
617 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
618 {
619 struct ata_port *ap = qc->ap;
620 unsigned int port_no = ap->port_no;
621 struct pdc_host_priv *hpriv = ap->host_set->private_data;
622 void *dimm_mmio = hpriv->dimm_mmio;
623
624 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
625 dimm_mmio += PDC_DIMM_HOST_PKT;
626
627 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
628 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
629 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
630 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
631 }
632 #else
633 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
634 #endif /* ATA_VERBOSE_DEBUG */
635
636 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
637 {
638 struct ata_port *ap = qc->ap;
639 struct ata_host_set *host_set = ap->host_set;
640 unsigned int port_no = ap->port_no;
641 void __iomem *mmio = host_set->mmio_base;
642 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
643 u8 seq = (u8) (port_no + 1);
644 unsigned int port_ofs;
645
646 /* hard-code chip #0 */
647 mmio += PDC_CHIP0_OFS;
648
649 VPRINTK("ata%u: ENTER\n", ap->id);
650
651 wmb(); /* flush PRD, pkt writes */
652
653 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
654
655 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
656 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
657 seq += 4;
658
659 pdc20621_dump_hdma(qc);
660 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
661 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
662 port_ofs + PDC_DIMM_HOST_PKT,
663 port_ofs + PDC_DIMM_HOST_PKT,
664 seq);
665 } else {
666 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
667 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
668
669 writel(port_ofs + PDC_DIMM_ATA_PKT,
670 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
671 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
672 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
673 port_ofs + PDC_DIMM_ATA_PKT,
674 port_ofs + PDC_DIMM_ATA_PKT,
675 seq);
676 }
677 }
678
679 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
680 {
681 switch (qc->tf.protocol) {
682 case ATA_PROT_DMA:
683 case ATA_PROT_NODATA:
684 pdc20621_packet_start(qc);
685 return 0;
686
687 case ATA_PROT_ATAPI_DMA:
688 BUG();
689 break;
690
691 default:
692 break;
693 }
694
695 return ata_qc_issue_prot(qc);
696 }
697
698 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
699 struct ata_queued_cmd *qc,
700 unsigned int doing_hdma,
701 void __iomem *mmio)
702 {
703 unsigned int port_no = ap->port_no;
704 unsigned int port_ofs =
705 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
706 u8 status;
707 unsigned int handled = 0;
708
709 VPRINTK("ENTER\n");
710
711 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
712 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
713
714 /* step two - DMA from DIMM to host */
715 if (doing_hdma) {
716 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
717 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
718 /* get drive status; clear intr; complete txn */
719 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
720 ata_qc_complete(qc);
721 pdc20621_pop_hdma(qc);
722 }
723
724 /* step one - exec ATA command */
725 else {
726 u8 seq = (u8) (port_no + 1 + 4);
727 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
728 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
729
730 /* submit hdma pkt */
731 pdc20621_dump_hdma(qc);
732 pdc20621_push_hdma(qc, seq,
733 port_ofs + PDC_DIMM_HOST_PKT);
734 }
735 handled = 1;
736
737 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
738
739 /* step one - DMA from host to DIMM */
740 if (doing_hdma) {
741 u8 seq = (u8) (port_no + 1);
742 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
743 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
744
745 /* submit ata pkt */
746 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
747 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
748 writel(port_ofs + PDC_DIMM_ATA_PKT,
749 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
750 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
751 }
752
753 /* step two - execute ATA command */
754 else {
755 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
756 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
757 /* get drive status; clear intr; complete txn */
758 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
759 ata_qc_complete(qc);
760 pdc20621_pop_hdma(qc);
761 }
762 handled = 1;
763
764 /* command completion, but no data xfer */
765 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
766
767 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
768 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
769 qc->err_mask |= ac_err_mask(status);
770 ata_qc_complete(qc);
771 handled = 1;
772
773 } else {
774 ap->stats.idle_irq++;
775 }
776
777 return handled;
778 }
779
780 static void pdc20621_irq_clear(struct ata_port *ap)
781 {
782 struct ata_host_set *host_set = ap->host_set;
783 void __iomem *mmio = host_set->mmio_base;
784
785 mmio += PDC_CHIP0_OFS;
786
787 readl(mmio + PDC_20621_SEQMASK);
788 }
789
790 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
791 {
792 struct ata_host_set *host_set = dev_instance;
793 struct ata_port *ap;
794 u32 mask = 0;
795 unsigned int i, tmp, port_no;
796 unsigned int handled = 0;
797 void __iomem *mmio_base;
798
799 VPRINTK("ENTER\n");
800
801 if (!host_set || !host_set->mmio_base) {
802 VPRINTK("QUICK EXIT\n");
803 return IRQ_NONE;
804 }
805
806 mmio_base = host_set->mmio_base;
807
808 /* reading should also clear interrupts */
809 mmio_base += PDC_CHIP0_OFS;
810 mask = readl(mmio_base + PDC_20621_SEQMASK);
811 VPRINTK("mask == 0x%x\n", mask);
812
813 if (mask == 0xffffffff) {
814 VPRINTK("QUICK EXIT 2\n");
815 return IRQ_NONE;
816 }
817 mask &= 0xffff; /* only 16 tags possible */
818 if (!mask) {
819 VPRINTK("QUICK EXIT 3\n");
820 return IRQ_NONE;
821 }
822
823 spin_lock(&host_set->lock);
824
825 for (i = 1; i < 9; i++) {
826 port_no = i - 1;
827 if (port_no > 3)
828 port_no -= 4;
829 if (port_no >= host_set->n_ports)
830 ap = NULL;
831 else
832 ap = host_set->ports[port_no];
833 tmp = mask & (1 << i);
834 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
835 if (tmp && ap &&
836 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
837 struct ata_queued_cmd *qc;
838
839 qc = ata_qc_from_tag(ap, ap->active_tag);
840 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
841 handled += pdc20621_host_intr(ap, qc, (i > 4),
842 mmio_base);
843 }
844 }
845
846 spin_unlock(&host_set->lock);
847
848 VPRINTK("mask == 0x%x\n", mask);
849
850 VPRINTK("EXIT\n");
851
852 return IRQ_RETVAL(handled);
853 }
854
855 static void pdc_eng_timeout(struct ata_port *ap)
856 {
857 u8 drv_stat;
858 struct ata_host_set *host_set = ap->host_set;
859 struct ata_queued_cmd *qc;
860 unsigned long flags;
861
862 DPRINTK("ENTER\n");
863
864 spin_lock_irqsave(&host_set->lock, flags);
865
866 qc = ata_qc_from_tag(ap, ap->active_tag);
867
868 switch (qc->tf.protocol) {
869 case ATA_PROT_DMA:
870 case ATA_PROT_NODATA:
871 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
872 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
873 break;
874
875 default:
876 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
877
878 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
879 ap->id, qc->tf.command, drv_stat);
880
881 qc->err_mask |= ac_err_mask(drv_stat);
882 break;
883 }
884
885 spin_unlock_irqrestore(&host_set->lock, flags);
886 ata_eh_qc_complete(qc);
887 DPRINTK("EXIT\n");
888 }
889
890 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
891 {
892 WARN_ON (tf->protocol == ATA_PROT_DMA ||
893 tf->protocol == ATA_PROT_NODATA);
894 ata_tf_load(ap, tf);
895 }
896
897
898 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
899 {
900 WARN_ON (tf->protocol == ATA_PROT_DMA ||
901 tf->protocol == ATA_PROT_NODATA);
902 ata_exec_command(ap, tf);
903 }
904
905
906 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
907 {
908 port->cmd_addr = base;
909 port->data_addr = base;
910 port->feature_addr =
911 port->error_addr = base + 0x4;
912 port->nsect_addr = base + 0x8;
913 port->lbal_addr = base + 0xc;
914 port->lbam_addr = base + 0x10;
915 port->lbah_addr = base + 0x14;
916 port->device_addr = base + 0x18;
917 port->command_addr =
918 port->status_addr = base + 0x1c;
919 port->altstatus_addr =
920 port->ctl_addr = base + 0x38;
921 }
922
923
924 #ifdef ATA_VERBOSE_DEBUG
925 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
926 u32 offset, u32 size)
927 {
928 u32 window_size;
929 u16 idx;
930 u8 page_mask;
931 long dist;
932 void __iomem *mmio = pe->mmio_base;
933 struct pdc_host_priv *hpriv = pe->private_data;
934 void __iomem *dimm_mmio = hpriv->dimm_mmio;
935
936 /* hard-code chip #0 */
937 mmio += PDC_CHIP0_OFS;
938
939 page_mask = 0x00;
940 window_size = 0x2000 * 4; /* 32K byte uchar size */
941 idx = (u16) (offset / window_size);
942
943 writel(0x01, mmio + PDC_GENERAL_CTLR);
944 readl(mmio + PDC_GENERAL_CTLR);
945 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
946 readl(mmio + PDC_DIMM_WINDOW_CTLR);
947
948 offset -= (idx * window_size);
949 idx++;
950 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
951 (long) (window_size - offset);
952 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
953 dist);
954
955 psource += dist;
956 size -= dist;
957 for (; (long) size >= (long) window_size ;) {
958 writel(0x01, mmio + PDC_GENERAL_CTLR);
959 readl(mmio + PDC_GENERAL_CTLR);
960 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
961 readl(mmio + PDC_DIMM_WINDOW_CTLR);
962 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
963 window_size / 4);
964 psource += window_size;
965 size -= window_size;
966 idx ++;
967 }
968
969 if (size) {
970 writel(0x01, mmio + PDC_GENERAL_CTLR);
971 readl(mmio + PDC_GENERAL_CTLR);
972 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
973 readl(mmio + PDC_DIMM_WINDOW_CTLR);
974 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
975 size / 4);
976 }
977 }
978 #endif
979
980
981 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
982 u32 offset, u32 size)
983 {
984 u32 window_size;
985 u16 idx;
986 u8 page_mask;
987 long dist;
988 void __iomem *mmio = pe->mmio_base;
989 struct pdc_host_priv *hpriv = pe->private_data;
990 void __iomem *dimm_mmio = hpriv->dimm_mmio;
991
992 /* hard-code chip #0 */
993 mmio += PDC_CHIP0_OFS;
994
995 page_mask = 0x00;
996 window_size = 0x2000 * 4; /* 32K byte uchar size */
997 idx = (u16) (offset / window_size);
998
999 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1000 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1001 offset -= (idx * window_size);
1002 idx++;
1003 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1004 (long) (window_size - offset);
1005 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1006 writel(0x01, mmio + PDC_GENERAL_CTLR);
1007 readl(mmio + PDC_GENERAL_CTLR);
1008
1009 psource += dist;
1010 size -= dist;
1011 for (; (long) size >= (long) window_size ;) {
1012 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1013 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1014 memcpy_toio(dimm_mmio, psource, window_size / 4);
1015 writel(0x01, mmio + PDC_GENERAL_CTLR);
1016 readl(mmio + PDC_GENERAL_CTLR);
1017 psource += window_size;
1018 size -= window_size;
1019 idx ++;
1020 }
1021
1022 if (size) {
1023 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1024 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1025 memcpy_toio(dimm_mmio, psource, size / 4);
1026 writel(0x01, mmio + PDC_GENERAL_CTLR);
1027 readl(mmio + PDC_GENERAL_CTLR);
1028 }
1029 }
1030
1031
1032 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1033 u32 subaddr, u32 *pdata)
1034 {
1035 void __iomem *mmio = pe->mmio_base;
1036 u32 i2creg = 0;
1037 u32 status;
1038 u32 count =0;
1039
1040 /* hard-code chip #0 */
1041 mmio += PDC_CHIP0_OFS;
1042
1043 i2creg |= device << 24;
1044 i2creg |= subaddr << 16;
1045
1046 /* Set the device and subaddress */
1047 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1048 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1049
1050 /* Write Control to perform read operation, mask int */
1051 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1052 mmio + PDC_I2C_CONTROL_OFFSET);
1053
1054 for (count = 0; count <= 1000; count ++) {
1055 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1056 if (status & PDC_I2C_COMPLETE) {
1057 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1058 break;
1059 } else if (count == 1000)
1060 return 0;
1061 }
1062
1063 *pdata = (status >> 8) & 0x000000ff;
1064 return 1;
1065 }
1066
1067
1068 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1069 {
1070 u32 data=0 ;
1071 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1072 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1073 if (data == 100)
1074 return 100;
1075 } else
1076 return 0;
1077
1078 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1079 if(data <= 0x75)
1080 return 133;
1081 } else
1082 return 0;
1083
1084 return 0;
1085 }
1086
1087
1088 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1089 {
1090 u32 spd0[50];
1091 u32 data = 0;
1092 int size, i;
1093 u8 bdimmsize;
1094 void __iomem *mmio = pe->mmio_base;
1095 static const struct {
1096 unsigned int reg;
1097 unsigned int ofs;
1098 } pdc_i2c_read_data [] = {
1099 { PDC_DIMM_SPD_TYPE, 11 },
1100 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1101 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1102 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1103 { PDC_DIMM_SPD_ROW_NUM, 3 },
1104 { PDC_DIMM_SPD_BANK_NUM, 17 },
1105 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1106 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1107 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1108 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1109 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1110 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1111 };
1112
1113 /* hard-code chip #0 */
1114 mmio += PDC_CHIP0_OFS;
1115
1116 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1117 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1118 pdc_i2c_read_data[i].reg,
1119 &spd0[pdc_i2c_read_data[i].ofs]);
1120
1121 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1122 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1123 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1124 data |= (((((spd0[29] > spd0[28])
1125 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1126 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1127
1128 if (spd0[18] & 0x08)
1129 data |= ((0x03) << 14);
1130 else if (spd0[18] & 0x04)
1131 data |= ((0x02) << 14);
1132 else if (spd0[18] & 0x01)
1133 data |= ((0x01) << 14);
1134 else
1135 data |= (0 << 14);
1136
1137 /*
1138 Calculate the size of bDIMMSize (power of 2) and
1139 merge the DIMM size by program start/end address.
1140 */
1141
1142 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1143 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1144 data |= (((size / 16) - 1) << 16);
1145 data |= (0 << 23);
1146 data |= 8;
1147 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1148 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1149 return size;
1150 }
1151
1152
1153 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1154 {
1155 u32 data, spd0;
1156 int error, i;
1157 void __iomem *mmio = pe->mmio_base;
1158
1159 /* hard-code chip #0 */
1160 mmio += PDC_CHIP0_OFS;
1161
1162 /*
1163 Set To Default : DIMM Module Global Control Register (0x022259F1)
1164 DIMM Arbitration Disable (bit 20)
1165 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1166 Refresh Enable (bit 17)
1167 */
1168
1169 data = 0x022259F1;
1170 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1171 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1172
1173 /* Turn on for ECC */
1174 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1175 PDC_DIMM_SPD_TYPE, &spd0);
1176 if (spd0 == 0x02) {
1177 data |= (0x01 << 16);
1178 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1179 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1180 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1181 }
1182
1183 /* DIMM Initialization Select/Enable (bit 18/19) */
1184 data &= (~(1<<18));
1185 data |= (1<<19);
1186 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1187
1188 error = 1;
1189 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1190 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1191 if (!(data & (1<<19))) {
1192 error = 0;
1193 break;
1194 }
1195 msleep(i*100);
1196 }
1197 return error;
1198 }
1199
1200
1201 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1202 {
1203 int speed, size, length;
1204 u32 addr,spd0,pci_status;
1205 u32 tmp=0;
1206 u32 time_period=0;
1207 u32 tcount=0;
1208 u32 ticks=0;
1209 u32 clock=0;
1210 u32 fparam=0;
1211 void __iomem *mmio = pe->mmio_base;
1212
1213 /* hard-code chip #0 */
1214 mmio += PDC_CHIP0_OFS;
1215
1216 /* Initialize PLL based upon PCI Bus Frequency */
1217
1218 /* Initialize Time Period Register */
1219 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1220 time_period = readl(mmio + PDC_TIME_PERIOD);
1221 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1222
1223 /* Enable timer */
1224 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1225 readl(mmio + PDC_TIME_CONTROL);
1226
1227 /* Wait 3 seconds */
1228 msleep(3000);
1229
1230 /*
1231 When timer is enabled, counter is decreased every internal
1232 clock cycle.
1233 */
1234
1235 tcount = readl(mmio + PDC_TIME_COUNTER);
1236 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1237
1238 /*
1239 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1240 register should be >= (0xffffffff - 3x10^8).
1241 */
1242 if(tcount >= PCI_X_TCOUNT) {
1243 ticks = (time_period - tcount);
1244 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1245
1246 clock = (ticks / 300000);
1247 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1248
1249 clock = (clock * 33);
1250 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1251
1252 /* PLL F Param (bit 22:16) */
1253 fparam = (1400000 / clock) - 2;
1254 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1255
1256 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1257 pci_status = (0x8a001824 | (fparam << 16));
1258 } else
1259 pci_status = PCI_PLL_INIT;
1260
1261 /* Initialize PLL. */
1262 VPRINTK("pci_status: 0x%x\n", pci_status);
1263 writel(pci_status, mmio + PDC_CTL_STATUS);
1264 readl(mmio + PDC_CTL_STATUS);
1265
1266 /*
1267 Read SPD of DIMM by I2C interface,
1268 and program the DIMM Module Controller.
1269 */
1270 if (!(speed = pdc20621_detect_dimm(pe))) {
1271 printk(KERN_ERR "Detect Local DIMM Fail\n");
1272 return 1; /* DIMM error */
1273 }
1274 VPRINTK("Local DIMM Speed = %d\n", speed);
1275
1276 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1277 size = pdc20621_prog_dimm0(pe);
1278 VPRINTK("Local DIMM Size = %dMB\n",size);
1279
1280 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1281 if (pdc20621_prog_dimm_global(pe)) {
1282 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1283 return 1;
1284 }
1285
1286 #ifdef ATA_VERBOSE_DEBUG
1287 {
1288 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1289 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1290 '1','.','1','0',
1291 '9','8','0','3','1','6','1','2',0,0};
1292 u8 test_parttern2[40] = {0};
1293
1294 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1295 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1296
1297 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1298 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1299 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1300 test_parttern2[1], &(test_parttern2[2]));
1301 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1302 40);
1303 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1304 test_parttern2[1], &(test_parttern2[2]));
1305
1306 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1307 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1308 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1309 test_parttern2[1], &(test_parttern2[2]));
1310 }
1311 #endif
1312
1313 /* ECC initiliazation. */
1314
1315 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1316 PDC_DIMM_SPD_TYPE, &spd0);
1317 if (spd0 == 0x02) {
1318 VPRINTK("Start ECC initialization\n");
1319 addr = 0;
1320 length = size * 1024 * 1024;
1321 while (addr < length) {
1322 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1323 sizeof(u32));
1324 addr += sizeof(u32);
1325 }
1326 VPRINTK("Finish ECC initialization\n");
1327 }
1328 return 0;
1329 }
1330
1331
1332 static void pdc_20621_init(struct ata_probe_ent *pe)
1333 {
1334 u32 tmp;
1335 void __iomem *mmio = pe->mmio_base;
1336
1337 /* hard-code chip #0 */
1338 mmio += PDC_CHIP0_OFS;
1339
1340 /*
1341 * Select page 0x40 for our 32k DIMM window
1342 */
1343 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1344 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1345 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1346
1347 /*
1348 * Reset Host DMA
1349 */
1350 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1351 tmp |= PDC_RESET;
1352 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1353 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1354
1355 udelay(10);
1356
1357 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1358 tmp &= ~PDC_RESET;
1359 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1360 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1361 }
1362
1363 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1364 {
1365 static int printed_version;
1366 struct ata_probe_ent *probe_ent = NULL;
1367 unsigned long base;
1368 void __iomem *mmio_base;
1369 void __iomem *dimm_mmio = NULL;
1370 struct pdc_host_priv *hpriv = NULL;
1371 unsigned int board_idx = (unsigned int) ent->driver_data;
1372 int pci_dev_busy = 0;
1373 int rc;
1374
1375 if (!printed_version++)
1376 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1377
1378 /*
1379 * If this driver happens to only be useful on Apple's K2, then
1380 * we should check that here as it has a normal Serverworks ID
1381 */
1382 rc = pci_enable_device(pdev);
1383 if (rc)
1384 return rc;
1385
1386 rc = pci_request_regions(pdev, DRV_NAME);
1387 if (rc) {
1388 pci_dev_busy = 1;
1389 goto err_out;
1390 }
1391
1392 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1393 if (rc)
1394 goto err_out_regions;
1395 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1396 if (rc)
1397 goto err_out_regions;
1398
1399 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1400 if (probe_ent == NULL) {
1401 rc = -ENOMEM;
1402 goto err_out_regions;
1403 }
1404
1405 memset(probe_ent, 0, sizeof(*probe_ent));
1406 probe_ent->dev = pci_dev_to_dev(pdev);
1407 INIT_LIST_HEAD(&probe_ent->node);
1408
1409 mmio_base = pci_iomap(pdev, 3, 0);
1410 if (mmio_base == NULL) {
1411 rc = -ENOMEM;
1412 goto err_out_free_ent;
1413 }
1414 base = (unsigned long) mmio_base;
1415
1416 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1417 if (!hpriv) {
1418 rc = -ENOMEM;
1419 goto err_out_iounmap;
1420 }
1421 memset(hpriv, 0, sizeof(*hpriv));
1422
1423 dimm_mmio = pci_iomap(pdev, 4, 0);
1424 if (!dimm_mmio) {
1425 kfree(hpriv);
1426 rc = -ENOMEM;
1427 goto err_out_iounmap;
1428 }
1429
1430 hpriv->dimm_mmio = dimm_mmio;
1431
1432 probe_ent->sht = pdc_port_info[board_idx].sht;
1433 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1434 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1435 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1436 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1437 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1438
1439 probe_ent->irq = pdev->irq;
1440 probe_ent->irq_flags = SA_SHIRQ;
1441 probe_ent->mmio_base = mmio_base;
1442
1443 probe_ent->private_data = hpriv;
1444 base += PDC_CHIP0_OFS;
1445
1446 probe_ent->n_ports = 4;
1447 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1448 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1449 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1450 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1451
1452 pci_set_master(pdev);
1453
1454 /* initialize adapter */
1455 /* initialize local dimm */
1456 if (pdc20621_dimm_init(probe_ent)) {
1457 rc = -ENOMEM;
1458 goto err_out_iounmap_dimm;
1459 }
1460 pdc_20621_init(probe_ent);
1461
1462 /* FIXME: check ata_device_add return value */
1463 ata_device_add(probe_ent);
1464 kfree(probe_ent);
1465
1466 return 0;
1467
1468 err_out_iounmap_dimm: /* only get to this label if 20621 */
1469 kfree(hpriv);
1470 pci_iounmap(pdev, dimm_mmio);
1471 err_out_iounmap:
1472 pci_iounmap(pdev, mmio_base);
1473 err_out_free_ent:
1474 kfree(probe_ent);
1475 err_out_regions:
1476 pci_release_regions(pdev);
1477 err_out:
1478 if (!pci_dev_busy)
1479 pci_disable_device(pdev);
1480 return rc;
1481 }
1482
1483
1484 static int __init pdc_sata_init(void)
1485 {
1486 return pci_module_init(&pdc_sata_pci_driver);
1487 }
1488
1489
1490 static void __exit pdc_sata_exit(void)
1491 {
1492 pci_unregister_driver(&pdc_sata_pci_driver);
1493 }
1494
1495
1496 MODULE_AUTHOR("Jeff Garzik");
1497 MODULE_DESCRIPTION("Promise SATA low-level driver");
1498 MODULE_LICENSE("GPL");
1499 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1500 MODULE_VERSION(DRV_VERSION);
1501
1502 module_init(pdc_sata_init);
1503 module_exit(pdc_sata_exit);
Verdex Pro support