arch/arm/mach-iop13xx/irq.c

   1 /*
   2  * iop13xx IRQ handling / support functions
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/sysctl.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/irq.h>
  26 #include <asm/hardware.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/arch/irqs.h>
  29 #include <asm/arch/msi.h>
  30
  31 /* INTCTL0 CP6 R0 Page 4
  32  */
  33 static inline u32 read_intctl_0(void)
  34 {
  35         u32 val;
  36         asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
  37         return val;
  38 }
  39 static inline void write_intctl_0(u32 val)
  40 {
  41         asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
  42 }
  43
  44 /* INTCTL1 CP6 R1 Page 4
  45  */
  46 static inline u32 read_intctl_1(void)
  47 {
  48         u32 val;
  49         asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
  50         return val;
  51 }
  52 static inline void write_intctl_1(u32 val)
  53 {
  54         asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
  55 }
  56
  57 /* INTCTL2 CP6 R2 Page 4
  58  */
  59 static inline u32 read_intctl_2(void)
  60 {
  61         u32 val;
  62         asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
  63         return val;
  64 }
  65 static inline void write_intctl_2(u32 val)
  66 {
  67         asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
  68 }
  69
  70 /* INTCTL3 CP6 R3 Page 4
  71  */
  72 static inline u32 read_intctl_3(void)
  73 {
  74         u32 val;
  75         asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
  76         return val;
  77 }
  78 static inline void write_intctl_3(u32 val)
  79 {
  80         asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
  81 }
  82
  83 /* INTSTR0 CP6 R0 Page 5
  84  */
  85 static inline u32 read_intstr_0(void)
  86 {
  87         u32 val;
  88         asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
  89         return val;
  90 }
  91 static inline void write_intstr_0(u32 val)
  92 {
  93         asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
  94 }
  95
  96 /* INTSTR1 CP6 R1 Page 5
  97  */
  98 static inline u32 read_intstr_1(void)
  99 {
 100         u32 val;
 101         asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
 102         return val;
 103 }
 104 static void write_intstr_1(u32 val)
 105 {
 106         asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
 107 }
 108
 109 /* INTSTR2 CP6 R2 Page 5
 110  */
 111 static inline u32 read_intstr_2(void)
 112 {
 113         u32 val;
 114         asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
 115         return val;
 116 }
 117 static void write_intstr_2(u32 val)
 118 {
 119         asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
 120 }
 121
 122 /* INTSTR3 CP6 R3 Page 5
 123  */
 124 static inline u32 read_intstr_3(void)
 125 {
 126         u32 val;
 127         asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
 128         return val;
 129 }
 130 static void write_intstr_3(u32 val)
 131 {
 132         asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
 133 }
 134
 135 /* INTBASE CP6 R0 Page 2
 136  */
 137 static inline u32 read_intbase(void)
 138 {
 139         u32 val;
 140         asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
 141         return val;
 142 }
 143 static void write_intbase(u32 val)
 144 {
 145         asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
 146 }
 147
 148 /* INTSIZE CP6 R2 Page 2
 149  */
 150 static inline u32 read_intsize(void)
 151 {
 152         u32 val;
 153         asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
 154         return val;
 155 }
 156 static void write_intsize(u32 val)
 157 {
 158         asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
 159 }
 160
 161 /* 0 = Interrupt Masked and 1 = Interrupt not masked */
 162 static void
 163 iop13xx_irq_mask0 (unsigned int irq)
 164 {
 165         write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
 166 }
 167
 168 static void
 169 iop13xx_irq_mask1 (unsigned int irq)
 170 {
 171         write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
 172 }
 173
 174 static void
 175 iop13xx_irq_mask2 (unsigned int irq)
 176 {
 177         write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
 178 }
 179
 180 static void
 181 iop13xx_irq_mask3 (unsigned int irq)
 182 {
 183         write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
 184 }
 185
 186 static void
 187 iop13xx_irq_unmask0(unsigned int irq)
 188 {
 189         write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
 190 }
 191
 192 static void
 193 iop13xx_irq_unmask1(unsigned int irq)
 194 {
 195         write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
 196 }
 197
 198 static void
 199 iop13xx_irq_unmask2(unsigned int irq)
 200 {
 201         write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
 202 }
 203
 204 static void
 205 iop13xx_irq_unmask3(unsigned int irq)
 206 {
 207         write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
 208 }
 209
 210 static struct irq_chip iop13xx_irqchip1 = {
 211         .name   = "IOP13xx-1",
 212         .ack    = iop13xx_irq_mask0,
 213         .mask   = iop13xx_irq_mask0,
 214         .unmask = iop13xx_irq_unmask0,
 215 };
 216
 217 static struct irq_chip iop13xx_irqchip2 = {
 218         .name   = "IOP13xx-2",
 219         .ack    = iop13xx_irq_mask1,
 220         .mask   = iop13xx_irq_mask1,
 221         .unmask = iop13xx_irq_unmask1,
 222 };
 223
 224 static struct irq_chip iop13xx_irqchip3 = {
 225         .name   = "IOP13xx-3",
 226         .ack    = iop13xx_irq_mask2,
 227         .mask   = iop13xx_irq_mask2,
 228         .unmask = iop13xx_irq_unmask2,
 229 };
 230
 231 static struct irq_chip iop13xx_irqchip4 = {
 232         .name   = "IOP13xx-4",
 233         .ack    = iop13xx_irq_mask3,
 234         .mask   = iop13xx_irq_mask3,
 235         .unmask = iop13xx_irq_unmask3,
 236 };
 237
 238 extern void iop_init_cp6_handler(void);
 239
 240 void __init iop13xx_init_irq(void)
 241 {
 242         unsigned int i;
 243
 244         iop_init_cp6_handler();
 245
 246         /* disable all interrupts */
 247         write_intctl_0(0);
 248         write_intctl_1(0);
 249         write_intctl_2(0);
 250         write_intctl_3(0);
 251
 252         /* treat all as IRQ */
 253         write_intstr_0(0);
 254         write_intstr_1(0);
 255         write_intstr_2(0);
 256         write_intstr_3(0);
 257
 258         /* initialize the interrupt vector generator */
 259         write_intbase(INTBASE);
 260         write_intsize(INTSIZE_4);
 261
 262         for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
 263                 if (i < 32)
 264                         set_irq_chip(i, &iop13xx_irqchip1);
 265                 else if (i < 64)
 266                         set_irq_chip(i, &iop13xx_irqchip2);
 267                 else if (i < 96)
 268                         set_irq_chip(i, &iop13xx_irqchip3);
 269                 else
 270                         set_irq_chip(i, &iop13xx_irqchip4);
 271
 272                 set_irq_handler(i, handle_level_irq);
 273                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 274         }
 275
 276         iop13xx_msi_init();
 277 }